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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  */
  23.  
  24. #ifndef _INTEL_LRC_H_
  25. #define _INTEL_LRC_H_
  26.  
  27. #define GEN8_LR_CONTEXT_ALIGN 4096
  28. #define GEN8_CSB_ENTRIES 6
  29. #define GEN8_CSB_PTR_MASK 0x07
  30.  
  31. /* Execlists regs */
  32. #define RING_ELSP(ring)                         _MMIO((ring)->mmio_base + 0x230)
  33. #define RING_EXECLIST_STATUS_LO(ring)           _MMIO((ring)->mmio_base + 0x234)
  34. #define RING_EXECLIST_STATUS_HI(ring)           _MMIO((ring)->mmio_base + 0x234 + 4)
  35. #define RING_CONTEXT_CONTROL(ring)              _MMIO((ring)->mmio_base + 0x244)
  36. #define   CTX_CTRL_INHIBIT_SYN_CTX_SWITCH       (1 << 3)
  37. #define   CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT   (1 << 0)
  38. #define   CTX_CTRL_RS_CTX_ENABLE                (1 << 1)
  39. #define RING_CONTEXT_STATUS_BUF_LO(ring, i)     _MMIO((ring)->mmio_base + 0x370 + (i) * 8)
  40. #define RING_CONTEXT_STATUS_BUF_HI(ring, i)     _MMIO((ring)->mmio_base + 0x370 + (i) * 8 + 4)
  41. #define RING_CONTEXT_STATUS_PTR(ring)           _MMIO((ring)->mmio_base + 0x3a0)
  42.  
  43. /* Logical Rings */
  44. int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
  45. int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
  46. void intel_logical_ring_stop(struct intel_engine_cs *ring);
  47. void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
  48. int intel_logical_rings_init(struct drm_device *dev);
  49. int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
  50.  
  51. int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
  52. /**
  53.  * intel_logical_ring_advance() - advance the ringbuffer tail
  54.  * @ringbuf: Ringbuffer to advance.
  55.  *
  56.  * The tail is only updated in our logical ringbuffer struct.
  57.  */
  58. static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
  59. {
  60.         ringbuf->tail &= ringbuf->size - 1;
  61. }
  62. /**
  63.  * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
  64.  * @ringbuf: Ringbuffer to write to.
  65.  * @data: DWORD to write.
  66.  */
  67. static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
  68.                                            u32 data)
  69. {
  70.         iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
  71.         ringbuf->tail += 4;
  72. }
  73. static inline void intel_logical_ring_emit_reg(struct intel_ringbuffer *ringbuf,
  74.                                                i915_reg_t reg)
  75. {
  76.         intel_logical_ring_emit(ringbuf, i915_mmio_reg_offset(reg));
  77. }
  78.  
  79. /* Logical Ring Contexts */
  80.  
  81. /* One extra page is added before LRC for GuC as shared data */
  82. #define LRC_GUCSHR_PN   (0)
  83. #define LRC_PPHWSP_PN   (LRC_GUCSHR_PN + 1)
  84. #define LRC_STATE_PN    (LRC_PPHWSP_PN + 1)
  85.  
  86. void intel_lr_context_free(struct intel_context *ctx);
  87. int intel_lr_context_deferred_alloc(struct intel_context *ctx,
  88.                                     struct intel_engine_cs *ring);
  89. void intel_lr_context_unpin(struct drm_i915_gem_request *req);
  90. void intel_lr_context_reset(struct drm_device *dev,
  91.                         struct intel_context *ctx);
  92. uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
  93.                                      struct intel_engine_cs *ring);
  94.  
  95. /* Execlists */
  96. int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
  97. struct i915_execbuffer_params;
  98. int intel_execlists_submission(struct i915_execbuffer_params *params,
  99.                                struct drm_i915_gem_execbuffer2 *args,
  100.                                struct list_head *vmas);
  101. u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
  102.  
  103. void intel_lrc_irq_handler(struct intel_engine_cs *ring);
  104. void intel_execlists_retire_requests(struct intel_engine_cs *ring);
  105.  
  106. #endif /* _INTEL_LRC_H_ */
  107.