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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2008,2010 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23.  * DEALINGS IN THE SOFTWARE.
  24.  *
  25.  * Authors:
  26.  *      Eric Anholt <eric@anholt.net>
  27.  *      Chris Wilson <chris@chris-wilson.co.uk>
  28.  */
  29. #include <linux/i2c.h>
  30. #include <linux/i2c-algo-bit.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. struct gmbus_port {
  38.         const char *name;
  39.         int reg;
  40. };
  41.  
  42. static const struct gmbus_port gmbus_ports[] = {
  43.         { "ssc", GPIOB },
  44.         { "vga", GPIOA },
  45.         { "panel", GPIOC },
  46.         { "dpc", GPIOD },
  47.         { "dpb", GPIOE },
  48.         { "dpd", GPIOF },
  49. };
  50.  
  51. /* Intel GPIO access functions */
  52.  
  53. #define I2C_RISEFALL_TIME 10
  54.  
  55. static inline struct intel_gmbus *
  56. to_intel_gmbus(struct i2c_adapter *i2c)
  57. {
  58.         return container_of(i2c, struct intel_gmbus, adapter);
  59. }
  60.  
  61. void
  62. intel_i2c_reset(struct drm_device *dev)
  63. {
  64.         struct drm_i915_private *dev_priv = dev->dev_private;
  65.  
  66.         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
  67.         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
  68. }
  69.  
  70. static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  71. {
  72.         u32 val;
  73.  
  74.         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  75.         if (!IS_PINEVIEW(dev_priv->dev))
  76.                 return;
  77.  
  78.         val = I915_READ(DSPCLK_GATE_D);
  79.         if (enable)
  80.                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  81.         else
  82.                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  83.         I915_WRITE(DSPCLK_GATE_D, val);
  84. }
  85.  
  86. static u32 get_reserved(struct intel_gmbus *bus)
  87. {
  88.         struct drm_i915_private *dev_priv = bus->dev_priv;
  89.         struct drm_device *dev = dev_priv->dev;
  90.         u32 reserved = 0;
  91.  
  92.         /* On most chips, these bits must be preserved in software. */
  93.         if (!IS_I830(dev) && !IS_845G(dev))
  94.                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
  95.                                              (GPIO_DATA_PULLUP_DISABLE |
  96.                                               GPIO_CLOCK_PULLUP_DISABLE);
  97.  
  98.         return reserved;
  99. }
  100.  
  101. static int get_clock(void *data)
  102. {
  103.         struct intel_gmbus *bus = data;
  104.         struct drm_i915_private *dev_priv = bus->dev_priv;
  105.         u32 reserved = get_reserved(bus);
  106.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
  107.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
  108.         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
  109. }
  110.  
  111. static int get_data(void *data)
  112. {
  113.         struct intel_gmbus *bus = data;
  114.         struct drm_i915_private *dev_priv = bus->dev_priv;
  115.         u32 reserved = get_reserved(bus);
  116.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
  117.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
  118.         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
  119. }
  120.  
  121. static void set_clock(void *data, int state_high)
  122. {
  123.         struct intel_gmbus *bus = data;
  124.         struct drm_i915_private *dev_priv = bus->dev_priv;
  125.         u32 reserved = get_reserved(bus);
  126.         u32 clock_bits;
  127.  
  128.         if (state_high)
  129.                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  130.         else
  131.                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  132.                         GPIO_CLOCK_VAL_MASK;
  133.  
  134.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
  135.         POSTING_READ(bus->gpio_reg);
  136. }
  137.  
  138. static void set_data(void *data, int state_high)
  139. {
  140.         struct intel_gmbus *bus = data;
  141.         struct drm_i915_private *dev_priv = bus->dev_priv;
  142.         u32 reserved = get_reserved(bus);
  143.         u32 data_bits;
  144.  
  145.         if (state_high)
  146.                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  147.         else
  148.                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  149.                         GPIO_DATA_VAL_MASK;
  150.  
  151.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
  152.         POSTING_READ(bus->gpio_reg);
  153. }
  154.  
  155. static int
  156. intel_gpio_pre_xfer(struct i2c_adapter *adapter)
  157. {
  158.         struct intel_gmbus *bus = container_of(adapter,
  159.                                                struct intel_gmbus,
  160.                                                adapter);
  161.         struct drm_i915_private *dev_priv = bus->dev_priv;
  162.  
  163.         intel_i2c_reset(dev_priv->dev);
  164.         intel_i2c_quirk_set(dev_priv, true);
  165.         set_data(bus, 1);
  166.         set_clock(bus, 1);
  167.         udelay(I2C_RISEFALL_TIME);
  168.         return 0;
  169. }
  170.  
  171. static void
  172. intel_gpio_post_xfer(struct i2c_adapter *adapter)
  173. {
  174.         struct intel_gmbus *bus = container_of(adapter,
  175.                                                struct intel_gmbus,
  176.                                                adapter);
  177.         struct drm_i915_private *dev_priv = bus->dev_priv;
  178.  
  179.         set_data(bus, 1);
  180.         set_clock(bus, 1);
  181.         intel_i2c_quirk_set(dev_priv, false);
  182. }
  183.  
  184. static void
  185. intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
  186. {
  187.         struct drm_i915_private *dev_priv = bus->dev_priv;
  188.         struct i2c_algo_bit_data *algo;
  189.  
  190.         algo = &bus->bit_algo;
  191.  
  192.         /* -1 to map pin pair to gmbus index */
  193.         bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
  194.  
  195.         bus->adapter.algo_data = algo;
  196.         algo->setsda = set_data;
  197.         algo->setscl = set_clock;
  198.         algo->getsda = get_data;
  199.         algo->getscl = get_clock;
  200.         algo->pre_xfer = intel_gpio_pre_xfer;
  201.         algo->post_xfer = intel_gpio_post_xfer;
  202.         algo->udelay = I2C_RISEFALL_TIME;
  203.         algo->timeout = usecs_to_jiffies(2200);
  204.         algo->data = bus;
  205. }
  206.  
  207. static int
  208. gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
  209.                      u32 gmbus2_status,
  210.                      u32 gmbus4_irq_en)
  211. {
  212.         int i;
  213.         int reg_offset = dev_priv->gpio_mmio_base;
  214.         u32 gmbus2 = 0;
  215.         DEFINE_WAIT(wait);
  216.  
  217.         if (!HAS_GMBUS_IRQ(dev_priv->dev))
  218.                 gmbus4_irq_en = 0;
  219.  
  220.         /* Important: The hw handles only the first bit, so set only one! Since
  221.          * we also need to check for NAKs besides the hw ready/idle signal, we
  222.          * need to wake up periodically and check that ourselves. */
  223.         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
  224.  
  225.         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
  226.                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
  227.                                 TASK_UNINTERRUPTIBLE);
  228.  
  229.                 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
  230.                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
  231.                         break;
  232.  
  233.                 schedule_timeout(1);
  234.         }
  235.         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
  236.  
  237.         I915_WRITE(GMBUS4 + reg_offset, 0);
  238.  
  239.         if (gmbus2 & GMBUS_SATOER)
  240.                 return -ENXIO;
  241.         if (gmbus2 & gmbus2_status)
  242.                 return 0;
  243.         return -ETIMEDOUT;
  244. }
  245.  
  246. static int
  247. gmbus_wait_idle(struct drm_i915_private *dev_priv)
  248. {
  249.         int ret;
  250.         int reg_offset = dev_priv->gpio_mmio_base;
  251.  
  252. #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
  253.  
  254.         if (!HAS_GMBUS_IRQ(dev_priv->dev))
  255.                 return wait_for(C, 10);
  256.  
  257.         /* Important: The hw handles only the first bit, so set only one! */
  258.         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
  259.  
  260.         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  261.                                  msecs_to_jiffies_timeout(10));
  262.  
  263.         I915_WRITE(GMBUS4 + reg_offset, 0);
  264.  
  265.         if (ret)
  266.                 return 0;
  267.         else
  268.                 return -ETIMEDOUT;
  269. #undef C
  270. }
  271.  
  272. static int
  273. gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
  274.                 u32 gmbus1_index)
  275. {
  276.         int reg_offset = dev_priv->gpio_mmio_base;
  277.         u16 len = msg->len;
  278.         u8 *buf = msg->buf;
  279.  
  280.         I915_WRITE(GMBUS1 + reg_offset,
  281.                    gmbus1_index |
  282.                    GMBUS_CYCLE_WAIT |
  283.                    (len << GMBUS_BYTE_COUNT_SHIFT) |
  284.                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
  285.                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  286.         while (len) {
  287.                 int ret;
  288.                 u32 val, loop = 0;
  289.  
  290.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
  291.                                            GMBUS_HW_RDY_EN);
  292.                 if (ret)
  293.                         return ret;
  294.  
  295.                 val = I915_READ(GMBUS3 + reg_offset);
  296.                 do {
  297.                         *buf++ = val & 0xff;
  298.                         val >>= 8;
  299.                 } while (--len && ++loop < 4);
  300.         }
  301.  
  302.         return 0;
  303. }
  304.  
  305. static int
  306. gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
  307. {
  308.         int reg_offset = dev_priv->gpio_mmio_base;
  309.         u16 len = msg->len;
  310.         u8 *buf = msg->buf;
  311.         u32 val, loop;
  312.  
  313.         val = loop = 0;
  314.         while (len && loop < 4) {
  315.                 val |= *buf++ << (8 * loop++);
  316.                 len -= 1;
  317.         }
  318.  
  319.         I915_WRITE(GMBUS3 + reg_offset, val);
  320.         I915_WRITE(GMBUS1 + reg_offset,
  321.                    GMBUS_CYCLE_WAIT |
  322.                    (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
  323.                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
  324.                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  325.         while (len) {
  326.                 int ret;
  327.  
  328.                 val = loop = 0;
  329.                 do {
  330.                         val |= *buf++ << (8 * loop);
  331.                 } while (--len && ++loop < 4);
  332.  
  333.                 I915_WRITE(GMBUS3 + reg_offset, val);
  334.  
  335.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
  336.                                            GMBUS_HW_RDY_EN);
  337.                 if (ret)
  338.                         return ret;
  339.         }
  340.         return 0;
  341. }
  342.  
  343. /*
  344.  * The gmbus controller can combine a 1 or 2 byte write with a read that
  345.  * immediately follows it by using an "INDEX" cycle.
  346.  */
  347. static bool
  348. gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
  349. {
  350.         return (i + 1 < num &&
  351.                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
  352.                 (msgs[i + 1].flags & I2C_M_RD));
  353. }
  354.  
  355. static int
  356. gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
  357. {
  358.         int reg_offset = dev_priv->gpio_mmio_base;
  359.         u32 gmbus1_index = 0;
  360.         u32 gmbus5 = 0;
  361.         int ret;
  362.  
  363.         if (msgs[0].len == 2)
  364.                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
  365.                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
  366.         if (msgs[0].len == 1)
  367.                 gmbus1_index = GMBUS_CYCLE_INDEX |
  368.                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
  369.  
  370.         /* GMBUS5 holds 16-bit index */
  371.         if (gmbus5)
  372.                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
  373.  
  374.         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
  375.  
  376.         /* Clear GMBUS5 after each index transfer */
  377.         if (gmbus5)
  378.                 I915_WRITE(GMBUS5 + reg_offset, 0);
  379.  
  380.         return ret;
  381. }
  382.  
  383. static int
  384. gmbus_xfer(struct i2c_adapter *adapter,
  385.            struct i2c_msg *msgs,
  386.            int num)
  387. {
  388.         struct intel_gmbus *bus = container_of(adapter,
  389.                                                struct intel_gmbus,
  390.                                                adapter);
  391.         struct drm_i915_private *dev_priv = bus->dev_priv;
  392.         int i, reg_offset;
  393.         int ret = 0;
  394.  
  395.         intel_aux_display_runtime_get(dev_priv);
  396.         mutex_lock(&dev_priv->gmbus_mutex);
  397.  
  398.         if (bus->force_bit) {
  399.                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
  400.                 goto out;
  401.         }
  402.  
  403.         reg_offset = dev_priv->gpio_mmio_base;
  404.  
  405.         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
  406.  
  407.         for (i = 0; i < num; i++) {
  408.                 if (gmbus_is_index_read(msgs, i, num)) {
  409.                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
  410.                         i += 1;  /* set i to the index of the read xfer */
  411.                 } else if (msgs[i].flags & I2C_M_RD) {
  412.                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
  413.                 } else {
  414.                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
  415.                 }
  416.  
  417.                 if (ret == -ETIMEDOUT)
  418.                         goto timeout;
  419.                 if (ret == -ENXIO)
  420.                         goto clear_err;
  421.  
  422.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
  423.                                            GMBUS_HW_WAIT_EN);
  424.                 if (ret == -ENXIO)
  425.                         goto clear_err;
  426.                 if (ret)
  427.                         goto timeout;
  428.         }
  429.  
  430.         /* Generate a STOP condition on the bus. Note that gmbus can't generata
  431.          * a STOP on the very first cycle. To simplify the code we
  432.          * unconditionally generate the STOP condition with an additional gmbus
  433.          * cycle. */
  434.         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
  435.  
  436.         /* Mark the GMBUS interface as disabled after waiting for idle.
  437.          * We will re-enable it at the start of the next xfer,
  438.          * till then let it sleep.
  439.          */
  440.         if (gmbus_wait_idle(dev_priv)) {
  441.                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
  442.                          adapter->name);
  443.                 ret = -ETIMEDOUT;
  444.         }
  445.         I915_WRITE(GMBUS0 + reg_offset, 0);
  446.         ret = ret ?: i;
  447.         goto out;
  448.  
  449. clear_err:
  450.         /*
  451.          * Wait for bus to IDLE before clearing NAK.
  452.          * If we clear the NAK while bus is still active, then it will stay
  453.          * active and the next transaction may fail.
  454.          *
  455.          * If no ACK is received during the address phase of a transaction, the
  456.          * adapter must report -ENXIO. It is not clear what to return if no ACK
  457.          * is received at other times. But we have to be careful to not return
  458.          * spurious -ENXIO because that will prevent i2c and drm edid functions
  459.          * from retrying. So return -ENXIO only when gmbus properly quiescents -
  460.          * timing out seems to happen when there _is_ a ddc chip present, but
  461.          * it's slow responding and only answers on the 2nd retry.
  462.          */
  463.         ret = -ENXIO;
  464.         if (gmbus_wait_idle(dev_priv)) {
  465.                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
  466.                               adapter->name);
  467.                 ret = -ETIMEDOUT;
  468.         }
  469.  
  470.         /* Toggle the Software Clear Interrupt bit. This has the effect
  471.          * of resetting the GMBUS controller and so clearing the
  472.          * BUS_ERROR raised by the slave's NAK.
  473.          */
  474.         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
  475.         I915_WRITE(GMBUS1 + reg_offset, 0);
  476.         I915_WRITE(GMBUS0 + reg_offset, 0);
  477.  
  478.         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
  479.                          adapter->name, msgs[i].addr,
  480.                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
  481.  
  482.         goto out;
  483.  
  484. timeout:
  485.         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
  486.                  bus->adapter.name, bus->reg0 & 0xff);
  487.         I915_WRITE(GMBUS0 + reg_offset, 0);
  488.  
  489.         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  490.         bus->force_bit = 1;
  491.         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
  492.  
  493. out:
  494.         mutex_unlock(&dev_priv->gmbus_mutex);
  495.         intel_aux_display_runtime_put(dev_priv);
  496.         return ret;
  497. }
  498.  
  499. static u32 gmbus_func(struct i2c_adapter *adapter)
  500. {
  501.         return i2c_bit_algo.functionality(adapter) &
  502.                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  503.                 /* I2C_FUNC_10BIT_ADDR | */
  504.                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  505.                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  506. }
  507.  
  508. static const struct i2c_algorithm gmbus_algorithm = {
  509.         .master_xfer    = gmbus_xfer,
  510.         .functionality  = gmbus_func
  511. };
  512.  
  513. /**
  514.  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  515.  * @dev: DRM device
  516.  */
  517. int intel_setup_gmbus(struct drm_device *dev)
  518. {
  519.         struct drm_i915_private *dev_priv = dev->dev_private;
  520.         int ret, i;
  521.  
  522.         if (HAS_PCH_NOP(dev))
  523.                 return 0;
  524.         else if (HAS_PCH_SPLIT(dev))
  525.                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
  526.         else if (IS_VALLEYVIEW(dev))
  527.                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
  528.         else
  529.                 dev_priv->gpio_mmio_base = 0;
  530.  
  531.         mutex_init(&dev_priv->gmbus_mutex);
  532.         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
  533.  
  534.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  535.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  536.                 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
  537.  
  538.                 bus->adapter.owner = THIS_MODULE;
  539.                 bus->adapter.class = I2C_CLASS_DDC;
  540.                 snprintf(bus->adapter.name,
  541.                          sizeof(bus->adapter.name),
  542.                          "i915 gmbus %s",
  543.                          gmbus_ports[i].name);
  544.  
  545.                 bus->adapter.dev.parent = &dev->pdev->dev;
  546.                 bus->dev_priv = dev_priv;
  547.  
  548.                 bus->adapter.algo = &gmbus_algorithm;
  549.  
  550.                 /* By default use a conservative clock rate */
  551.                 bus->reg0 = port | GMBUS_RATE_100KHZ;
  552.  
  553.                 /* gmbus seems to be broken on i830 */
  554.                 if (IS_I830(dev))
  555.                         bus->force_bit = 1;
  556.  
  557.                 intel_gpio_setup(bus, port);
  558.  
  559.                 ret = i2c_add_adapter(&bus->adapter);
  560.                 if (ret)
  561.                         goto err;
  562.         }
  563.  
  564.         intel_i2c_reset(dev_priv->dev);
  565.  
  566.         return 0;
  567.  
  568. err:
  569.         while (--i) {
  570.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  571.                 i2c_del_adapter(&bus->adapter);
  572.         }
  573.         return ret;
  574. }
  575.  
  576. struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
  577.                                             unsigned port)
  578. {
  579.         WARN_ON(!intel_gmbus_is_port_valid(port));
  580.         /* -1 to map pin pair to gmbus index */
  581.         return (intel_gmbus_is_port_valid(port)) ?
  582.                 &dev_priv->gmbus[port - 1].adapter : NULL;
  583. }
  584.  
  585. void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  586. {
  587.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  588.  
  589.         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
  590. }
  591.  
  592. void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  593. {
  594.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  595.  
  596.         bus->force_bit += force_bit ? 1 : -1;
  597.         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
  598.                       force_bit ? "en" : "dis", adapter->name,
  599.                       bus->force_bit);
  600. }
  601.  
  602. void intel_teardown_gmbus(struct drm_device *dev)
  603. {
  604.         struct drm_i915_private *dev_priv = dev->dev_private;
  605.         int i;
  606.  
  607.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  608.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  609.                 i2c_del_adapter(&bus->adapter);
  610.         }
  611. }
  612.