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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2008,2010 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23.  * DEALINGS IN THE SOFTWARE.
  24.  *
  25.  * Authors:
  26.  *      Eric Anholt <eric@anholt.net>
  27.  *      Chris Wilson <chris@chris-wilson.co.uk>
  28.  */
  29. #include <linux/i2c.h>
  30. #include <linux/i2c-algo-bit.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. enum disp_clk {
  38.         CDCLK,
  39.         CZCLK
  40. };
  41.  
  42. struct gmbus_port {
  43.         const char *name;
  44.         int reg;
  45. };
  46.  
  47. static const struct gmbus_port gmbus_ports[] = {
  48.         { "ssc", GPIOB },
  49.         { "vga", GPIOA },
  50.         { "panel", GPIOC },
  51.         { "dpc", GPIOD },
  52.         { "dpb", GPIOE },
  53.         { "dpd", GPIOF },
  54. };
  55.  
  56. /* Intel GPIO access functions */
  57.  
  58. #define I2C_RISEFALL_TIME 10
  59.  
  60. static inline struct intel_gmbus *
  61. to_intel_gmbus(struct i2c_adapter *i2c)
  62. {
  63.         return container_of(i2c, struct intel_gmbus, adapter);
  64. }
  65.  
  66. static int get_disp_clk_div(struct drm_i915_private *dev_priv,
  67.                             enum disp_clk clk)
  68. {
  69.         u32 reg_val;
  70.         int clk_ratio;
  71.  
  72.         reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO);
  73.  
  74.         if (clk == CDCLK)
  75.                 clk_ratio =
  76.                         ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1;
  77.         else
  78.                 clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1;
  79.  
  80.         return clk_ratio;
  81. }
  82.  
  83. static void gmbus_set_freq(struct drm_i915_private *dev_priv)
  84. {
  85.         int vco, gmbus_freq = 0, cdclk_div;
  86.  
  87.         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  88.  
  89.         vco = valleyview_get_vco(dev_priv);
  90.  
  91.         /* Get the CDCLK divide ratio */
  92.         cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
  93.  
  94.         /*
  95.          * Program the gmbus_freq based on the cdclk frequency.
  96.          * BSpec erroneously claims we should aim for 4MHz, but
  97.          * in fact 1MHz is the correct frequency.
  98.          */
  99.         if (cdclk_div)
  100.                 gmbus_freq = (vco << 1) / cdclk_div;
  101.  
  102.         if (WARN_ON(gmbus_freq == 0))
  103.                 return;
  104.  
  105.         I915_WRITE(GMBUSFREQ_VLV, gmbus_freq);
  106. }
  107.  
  108. void
  109. intel_i2c_reset(struct drm_device *dev)
  110. {
  111.         struct drm_i915_private *dev_priv = dev->dev_private;
  112.  
  113.         /*
  114.          * In BIOS-less system, program the correct gmbus frequency
  115.          * before reading edid.
  116.          */
  117.         if (IS_VALLEYVIEW(dev))
  118.                 gmbus_set_freq(dev_priv);
  119.  
  120.         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
  121.         I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
  122. }
  123.  
  124. static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  125. {
  126.         u32 val;
  127.  
  128.         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  129.         if (!IS_PINEVIEW(dev_priv->dev))
  130.                 return;
  131.  
  132.         val = I915_READ(DSPCLK_GATE_D);
  133.         if (enable)
  134.                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  135.         else
  136.                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  137.         I915_WRITE(DSPCLK_GATE_D, val);
  138. }
  139.  
  140. static u32 get_reserved(struct intel_gmbus *bus)
  141. {
  142.         struct drm_i915_private *dev_priv = bus->dev_priv;
  143.         struct drm_device *dev = dev_priv->dev;
  144.         u32 reserved = 0;
  145.  
  146.         /* On most chips, these bits must be preserved in software. */
  147.         if (!IS_I830(dev) && !IS_845G(dev))
  148.                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
  149.                                              (GPIO_DATA_PULLUP_DISABLE |
  150.                                               GPIO_CLOCK_PULLUP_DISABLE);
  151.  
  152.         return reserved;
  153. }
  154.  
  155. static int get_clock(void *data)
  156. {
  157.         struct intel_gmbus *bus = data;
  158.         struct drm_i915_private *dev_priv = bus->dev_priv;
  159.         u32 reserved = get_reserved(bus);
  160.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
  161.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
  162.         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
  163. }
  164.  
  165. static int get_data(void *data)
  166. {
  167.         struct intel_gmbus *bus = data;
  168.         struct drm_i915_private *dev_priv = bus->dev_priv;
  169.         u32 reserved = get_reserved(bus);
  170.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
  171.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
  172.         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
  173. }
  174.  
  175. static void set_clock(void *data, int state_high)
  176. {
  177.         struct intel_gmbus *bus = data;
  178.         struct drm_i915_private *dev_priv = bus->dev_priv;
  179.         u32 reserved = get_reserved(bus);
  180.         u32 clock_bits;
  181.  
  182.         if (state_high)
  183.                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  184.         else
  185.                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  186.                         GPIO_CLOCK_VAL_MASK;
  187.  
  188.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
  189.         POSTING_READ(bus->gpio_reg);
  190. }
  191.  
  192. static void set_data(void *data, int state_high)
  193. {
  194.         struct intel_gmbus *bus = data;
  195.         struct drm_i915_private *dev_priv = bus->dev_priv;
  196.         u32 reserved = get_reserved(bus);
  197.         u32 data_bits;
  198.  
  199.         if (state_high)
  200.                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  201.         else
  202.                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  203.                         GPIO_DATA_VAL_MASK;
  204.  
  205.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
  206.         POSTING_READ(bus->gpio_reg);
  207. }
  208.  
  209. static int
  210. intel_gpio_pre_xfer(struct i2c_adapter *adapter)
  211. {
  212.         struct intel_gmbus *bus = container_of(adapter,
  213.                                                struct intel_gmbus,
  214.                                                adapter);
  215.         struct drm_i915_private *dev_priv = bus->dev_priv;
  216.  
  217.         intel_i2c_reset(dev_priv->dev);
  218.         intel_i2c_quirk_set(dev_priv, true);
  219.         set_data(bus, 1);
  220.         set_clock(bus, 1);
  221.         udelay(I2C_RISEFALL_TIME);
  222.         return 0;
  223. }
  224.  
  225. static void
  226. intel_gpio_post_xfer(struct i2c_adapter *adapter)
  227. {
  228.         struct intel_gmbus *bus = container_of(adapter,
  229.                                                struct intel_gmbus,
  230.                                                adapter);
  231.         struct drm_i915_private *dev_priv = bus->dev_priv;
  232.  
  233.         set_data(bus, 1);
  234.         set_clock(bus, 1);
  235.         intel_i2c_quirk_set(dev_priv, false);
  236. }
  237.  
  238. static void
  239. intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
  240. {
  241.         struct drm_i915_private *dev_priv = bus->dev_priv;
  242.         struct i2c_algo_bit_data *algo;
  243.  
  244.         algo = &bus->bit_algo;
  245.  
  246.         /* -1 to map pin pair to gmbus index */
  247.         bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
  248.  
  249.         bus->adapter.algo_data = algo;
  250.         algo->setsda = set_data;
  251.         algo->setscl = set_clock;
  252.         algo->getsda = get_data;
  253.         algo->getscl = get_clock;
  254.         algo->pre_xfer = intel_gpio_pre_xfer;
  255.         algo->post_xfer = intel_gpio_post_xfer;
  256.         algo->udelay = I2C_RISEFALL_TIME;
  257.         algo->timeout = usecs_to_jiffies(2200);
  258.         algo->data = bus;
  259. }
  260.  
  261. /*
  262.  * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
  263.  * mode. This results in spurious interrupt warnings if the legacy irq no. is
  264.  * shared with another device. The kernel then disables that interrupt source
  265.  * and so prevents the other device from working properly.
  266.  */
  267. #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
  268. static int
  269. gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
  270.                      u32 gmbus2_status,
  271.                      u32 gmbus4_irq_en)
  272. {
  273.         int i;
  274.         int reg_offset = dev_priv->gpio_mmio_base;
  275.         u32 gmbus2 = 0;
  276.         DEFINE_WAIT(wait);
  277.  
  278.         if (!HAS_GMBUS_IRQ(dev_priv->dev))
  279.                 gmbus4_irq_en = 0;
  280.  
  281.         /* Important: The hw handles only the first bit, so set only one! Since
  282.          * we also need to check for NAKs besides the hw ready/idle signal, we
  283.          * need to wake up periodically and check that ourselves. */
  284.         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
  285.  
  286.         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
  287.                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
  288.                                 TASK_UNINTERRUPTIBLE);
  289.  
  290.                 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
  291.                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
  292.                         break;
  293.  
  294.                 schedule_timeout(1);
  295.         }
  296.         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
  297.  
  298.         I915_WRITE(GMBUS4 + reg_offset, 0);
  299.  
  300.         if (gmbus2 & GMBUS_SATOER)
  301.                 return -ENXIO;
  302.         if (gmbus2 & gmbus2_status)
  303.                 return 0;
  304.         return -ETIMEDOUT;
  305. }
  306.  
  307. static int
  308. gmbus_wait_idle(struct drm_i915_private *dev_priv)
  309. {
  310.         int ret;
  311.         int reg_offset = dev_priv->gpio_mmio_base;
  312.  
  313. #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
  314.  
  315.         if (!HAS_GMBUS_IRQ(dev_priv->dev))
  316.                 return wait_for(C, 10);
  317.  
  318.         /* Important: The hw handles only the first bit, so set only one! */
  319.         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
  320.  
  321.         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  322.                                  msecs_to_jiffies_timeout(10));
  323.  
  324.         I915_WRITE(GMBUS4 + reg_offset, 0);
  325.  
  326.         if (ret)
  327.                 return 0;
  328.         else
  329.                 return -ETIMEDOUT;
  330. #undef C
  331. }
  332.  
  333. static int
  334. gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
  335.                 u32 gmbus1_index)
  336. {
  337.         int reg_offset = dev_priv->gpio_mmio_base;
  338.         u16 len = msg->len;
  339.         u8 *buf = msg->buf;
  340.  
  341.         I915_WRITE(GMBUS1 + reg_offset,
  342.                    gmbus1_index |
  343.                    GMBUS_CYCLE_WAIT |
  344.                    (len << GMBUS_BYTE_COUNT_SHIFT) |
  345.                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
  346.                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  347.         while (len) {
  348.                 int ret;
  349.                 u32 val, loop = 0;
  350.  
  351.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
  352.                                            GMBUS_HW_RDY_EN);
  353.                 if (ret)
  354.                         return ret;
  355.  
  356.                 val = I915_READ(GMBUS3 + reg_offset);
  357.                 do {
  358.                         *buf++ = val & 0xff;
  359.                         val >>= 8;
  360.                 } while (--len && ++loop < 4);
  361.         }
  362.  
  363.         return 0;
  364. }
  365.  
  366. static int
  367. gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
  368. {
  369.         int reg_offset = dev_priv->gpio_mmio_base;
  370.         u16 len = msg->len;
  371.         u8 *buf = msg->buf;
  372.         u32 val, loop;
  373.  
  374.         val = loop = 0;
  375.         while (len && loop < 4) {
  376.                 val |= *buf++ << (8 * loop++);
  377.                 len -= 1;
  378.         }
  379.  
  380.         I915_WRITE(GMBUS3 + reg_offset, val);
  381.         I915_WRITE(GMBUS1 + reg_offset,
  382.                    GMBUS_CYCLE_WAIT |
  383.                    (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
  384.                    (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
  385.                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  386.         while (len) {
  387.                 int ret;
  388.  
  389.                 val = loop = 0;
  390.                 do {
  391.                         val |= *buf++ << (8 * loop);
  392.                 } while (--len && ++loop < 4);
  393.  
  394.                 I915_WRITE(GMBUS3 + reg_offset, val);
  395.  
  396.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
  397.                                            GMBUS_HW_RDY_EN);
  398.                 if (ret)
  399.                         return ret;
  400.         }
  401.         return 0;
  402. }
  403.  
  404. /*
  405.  * The gmbus controller can combine a 1 or 2 byte write with a read that
  406.  * immediately follows it by using an "INDEX" cycle.
  407.  */
  408. static bool
  409. gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
  410. {
  411.         return (i + 1 < num &&
  412.                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
  413.                 (msgs[i + 1].flags & I2C_M_RD));
  414. }
  415.  
  416. static int
  417. gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
  418. {
  419.         int reg_offset = dev_priv->gpio_mmio_base;
  420.         u32 gmbus1_index = 0;
  421.         u32 gmbus5 = 0;
  422.         int ret;
  423.  
  424.         if (msgs[0].len == 2)
  425.                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
  426.                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
  427.         if (msgs[0].len == 1)
  428.                 gmbus1_index = GMBUS_CYCLE_INDEX |
  429.                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
  430.  
  431.         /* GMBUS5 holds 16-bit index */
  432.         if (gmbus5)
  433.                 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
  434.  
  435.         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
  436.  
  437.         /* Clear GMBUS5 after each index transfer */
  438.         if (gmbus5)
  439.                 I915_WRITE(GMBUS5 + reg_offset, 0);
  440.  
  441.         return ret;
  442. }
  443.  
  444. static int
  445. gmbus_xfer(struct i2c_adapter *adapter,
  446.            struct i2c_msg *msgs,
  447.            int num)
  448. {
  449.         struct intel_gmbus *bus = container_of(adapter,
  450.                                                struct intel_gmbus,
  451.                                                adapter);
  452.         struct drm_i915_private *dev_priv = bus->dev_priv;
  453.         int i, reg_offset;
  454.         int ret = 0;
  455.  
  456.         intel_aux_display_runtime_get(dev_priv);
  457.         mutex_lock(&dev_priv->gmbus_mutex);
  458.  
  459.         if (bus->force_bit) {
  460.                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
  461.                 goto out;
  462.         }
  463.  
  464.         reg_offset = dev_priv->gpio_mmio_base;
  465.  
  466.         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
  467.  
  468.         for (i = 0; i < num; i++) {
  469.                 if (gmbus_is_index_read(msgs, i, num)) {
  470.                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
  471.                         i += 1;  /* set i to the index of the read xfer */
  472.                 } else if (msgs[i].flags & I2C_M_RD) {
  473.                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
  474.                 } else {
  475.                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
  476.                 }
  477.  
  478.                 if (ret == -ETIMEDOUT)
  479.                         goto timeout;
  480.                 if (ret == -ENXIO)
  481.                         goto clear_err;
  482.  
  483.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
  484.                                            GMBUS_HW_WAIT_EN);
  485.                 if (ret == -ENXIO)
  486.                         goto clear_err;
  487.                 if (ret)
  488.                         goto timeout;
  489.         }
  490.  
  491.         /* Generate a STOP condition on the bus. Note that gmbus can't generata
  492.          * a STOP on the very first cycle. To simplify the code we
  493.          * unconditionally generate the STOP condition with an additional gmbus
  494.          * cycle. */
  495.         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
  496.  
  497.         /* Mark the GMBUS interface as disabled after waiting for idle.
  498.          * We will re-enable it at the start of the next xfer,
  499.          * till then let it sleep.
  500.          */
  501.         if (gmbus_wait_idle(dev_priv)) {
  502.                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
  503.                          adapter->name);
  504.                 ret = -ETIMEDOUT;
  505.         }
  506.         I915_WRITE(GMBUS0 + reg_offset, 0);
  507.         ret = ret ?: i;
  508.         goto out;
  509.  
  510. clear_err:
  511.         /*
  512.          * Wait for bus to IDLE before clearing NAK.
  513.          * If we clear the NAK while bus is still active, then it will stay
  514.          * active and the next transaction may fail.
  515.          *
  516.          * If no ACK is received during the address phase of a transaction, the
  517.          * adapter must report -ENXIO. It is not clear what to return if no ACK
  518.          * is received at other times. But we have to be careful to not return
  519.          * spurious -ENXIO because that will prevent i2c and drm edid functions
  520.          * from retrying. So return -ENXIO only when gmbus properly quiescents -
  521.          * timing out seems to happen when there _is_ a ddc chip present, but
  522.          * it's slow responding and only answers on the 2nd retry.
  523.          */
  524.         ret = -ENXIO;
  525.         if (gmbus_wait_idle(dev_priv)) {
  526.                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
  527.                               adapter->name);
  528.                 ret = -ETIMEDOUT;
  529.         }
  530.  
  531.         /* Toggle the Software Clear Interrupt bit. This has the effect
  532.          * of resetting the GMBUS controller and so clearing the
  533.          * BUS_ERROR raised by the slave's NAK.
  534.          */
  535.         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
  536.         I915_WRITE(GMBUS1 + reg_offset, 0);
  537.         I915_WRITE(GMBUS0 + reg_offset, 0);
  538.  
  539.         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
  540.                          adapter->name, msgs[i].addr,
  541.                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
  542.  
  543.         goto out;
  544.  
  545. timeout:
  546.         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
  547.                  bus->adapter.name, bus->reg0 & 0xff);
  548.         I915_WRITE(GMBUS0 + reg_offset, 0);
  549.  
  550.         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  551.         bus->force_bit = 1;
  552.         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
  553.  
  554. out:
  555.         mutex_unlock(&dev_priv->gmbus_mutex);
  556.         intel_aux_display_runtime_put(dev_priv);
  557.         return ret;
  558. }
  559.  
  560. static u32 gmbus_func(struct i2c_adapter *adapter)
  561. {
  562.         return i2c_bit_algo.functionality(adapter) &
  563.                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  564.                 /* I2C_FUNC_10BIT_ADDR | */
  565.                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  566.                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  567. }
  568.  
  569. static const struct i2c_algorithm gmbus_algorithm = {
  570.         .master_xfer    = gmbus_xfer,
  571.         .functionality  = gmbus_func
  572. };
  573.  
  574. /**
  575.  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  576.  * @dev: DRM device
  577.  */
  578. int intel_setup_gmbus(struct drm_device *dev)
  579. {
  580.         struct drm_i915_private *dev_priv = dev->dev_private;
  581.         int ret, i;
  582.  
  583.         if (HAS_PCH_NOP(dev))
  584.                 return 0;
  585.         else if (HAS_PCH_SPLIT(dev))
  586.                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
  587.         else if (IS_VALLEYVIEW(dev))
  588.                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
  589.         else
  590.                 dev_priv->gpio_mmio_base = 0;
  591.  
  592.         mutex_init(&dev_priv->gmbus_mutex);
  593.         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
  594.  
  595.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  596.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  597.                 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
  598.  
  599.                 bus->adapter.owner = THIS_MODULE;
  600.                 bus->adapter.class = I2C_CLASS_DDC;
  601.                 snprintf(bus->adapter.name,
  602.                          sizeof(bus->adapter.name),
  603.                          "i915 gmbus %s",
  604.                          gmbus_ports[i].name);
  605.  
  606.                 bus->adapter.dev.parent = &dev->pdev->dev;
  607.                 bus->dev_priv = dev_priv;
  608.  
  609.                 bus->adapter.algo = &gmbus_algorithm;
  610.  
  611.                 /* By default use a conservative clock rate */
  612.                 bus->reg0 = port | GMBUS_RATE_100KHZ;
  613.  
  614.                 /* gmbus seems to be broken on i830 */
  615.                 if (IS_I830(dev))
  616.                         bus->force_bit = 1;
  617.  
  618.                 intel_gpio_setup(bus, port);
  619.  
  620.                 ret = i2c_add_adapter(&bus->adapter);
  621.                 if (ret)
  622.                         goto err;
  623.         }
  624.  
  625.         intel_i2c_reset(dev_priv->dev);
  626.  
  627.         return 0;
  628.  
  629. err:
  630.         while (--i) {
  631.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  632.                 i2c_del_adapter(&bus->adapter);
  633.         }
  634.         return ret;
  635. }
  636.  
  637. struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
  638.                                             unsigned port)
  639. {
  640.         WARN_ON(!intel_gmbus_is_port_valid(port));
  641.         /* -1 to map pin pair to gmbus index */
  642.         return (intel_gmbus_is_port_valid(port)) ?
  643.                 &dev_priv->gmbus[port - 1].adapter : NULL;
  644. }
  645.  
  646. void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  647. {
  648.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  649.  
  650.         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
  651. }
  652.  
  653. void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  654. {
  655.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  656.  
  657.         bus->force_bit += force_bit ? 1 : -1;
  658.         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
  659.                       force_bit ? "en" : "dis", adapter->name,
  660.                       bus->force_bit);
  661. }
  662.  
  663. void intel_teardown_gmbus(struct drm_device *dev)
  664. {
  665.         struct drm_i915_private *dev_priv = dev->dev_private;
  666.         int i;
  667.  
  668.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  669.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  670.                 i2c_del_adapter(&bus->adapter);
  671.         }
  672. }
  673.