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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2008,2010 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23.  * DEALINGS IN THE SOFTWARE.
  24.  *
  25.  * Authors:
  26.  *      Eric Anholt <eric@anholt.net>
  27.  *      Chris Wilson <chris@chris-wilson.co.uk>
  28.  */
  29. #include <linux/i2c.h>
  30. #include <linux/i2c-algo-bit.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. struct gmbus_pin {
  38.         const char *name;
  39.         int reg;
  40. };
  41.  
  42. /* Map gmbus pin pairs to names and registers. */
  43. static const struct gmbus_pin gmbus_pins[] = {
  44.         [GMBUS_PIN_SSC] = { "ssc", GPIOB },
  45.         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  46.         [GMBUS_PIN_PANEL] = { "panel", GPIOC },
  47.         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  48.         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  49.         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  50. };
  51.  
  52. static const struct gmbus_pin gmbus_pins_bdw[] = {
  53.         [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
  54.         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  55.         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  56.         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  57. };
  58.  
  59. static const struct gmbus_pin gmbus_pins_skl[] = {
  60.         [GMBUS_PIN_DPC] = { "dpc", GPIOD },
  61.         [GMBUS_PIN_DPB] = { "dpb", GPIOE },
  62.         [GMBUS_PIN_DPD] = { "dpd", GPIOF },
  63. };
  64.  
  65. static const struct gmbus_pin gmbus_pins_bxt[] = {
  66.         [GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
  67.         [GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
  68.         [GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
  69. };
  70.  
  71. /* pin is expected to be valid */
  72. static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
  73.                                              unsigned int pin)
  74. {
  75.         if (IS_BROXTON(dev_priv))
  76.                 return &gmbus_pins_bxt[pin];
  77.         else if (IS_SKYLAKE(dev_priv))
  78.                 return &gmbus_pins_skl[pin];
  79.         else if (IS_BROADWELL(dev_priv))
  80.                 return &gmbus_pins_bdw[pin];
  81.         else
  82.                 return &gmbus_pins[pin];
  83. }
  84.  
  85. bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
  86.                               unsigned int pin)
  87. {
  88.         unsigned int size;
  89.  
  90.         if (IS_BROXTON(dev_priv))
  91.                 size = ARRAY_SIZE(gmbus_pins_bxt);
  92.         else if (IS_SKYLAKE(dev_priv))
  93.                 size = ARRAY_SIZE(gmbus_pins_skl);
  94.         else if (IS_BROADWELL(dev_priv))
  95.                 size = ARRAY_SIZE(gmbus_pins_bdw);
  96.         else
  97.                 size = ARRAY_SIZE(gmbus_pins);
  98.  
  99.         return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
  100. }
  101.  
  102. /* Intel GPIO access functions */
  103.  
  104. #define I2C_RISEFALL_TIME 10
  105.  
  106. static inline struct intel_gmbus *
  107. to_intel_gmbus(struct i2c_adapter *i2c)
  108. {
  109.         return container_of(i2c, struct intel_gmbus, adapter);
  110. }
  111.  
  112. void
  113. intel_i2c_reset(struct drm_device *dev)
  114. {
  115.         struct drm_i915_private *dev_priv = dev->dev_private;
  116.  
  117.         I915_WRITE(GMBUS0, 0);
  118.         I915_WRITE(GMBUS4, 0);
  119. }
  120.  
  121. static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  122. {
  123.         u32 val;
  124.  
  125.         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  126.         if (!IS_PINEVIEW(dev_priv->dev))
  127.                 return;
  128.  
  129.         val = I915_READ(DSPCLK_GATE_D);
  130.         if (enable)
  131.                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  132.         else
  133.                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  134.         I915_WRITE(DSPCLK_GATE_D, val);
  135. }
  136.  
  137. static u32 get_reserved(struct intel_gmbus *bus)
  138. {
  139.         struct drm_i915_private *dev_priv = bus->dev_priv;
  140.         struct drm_device *dev = dev_priv->dev;
  141.         u32 reserved = 0;
  142.  
  143.         /* On most chips, these bits must be preserved in software. */
  144.         if (!IS_I830(dev) && !IS_845G(dev))
  145.                 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
  146.                                              (GPIO_DATA_PULLUP_DISABLE |
  147.                                               GPIO_CLOCK_PULLUP_DISABLE);
  148.  
  149.         return reserved;
  150. }
  151.  
  152. static int get_clock(void *data)
  153. {
  154.         struct intel_gmbus *bus = data;
  155.         struct drm_i915_private *dev_priv = bus->dev_priv;
  156.         u32 reserved = get_reserved(bus);
  157.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
  158.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
  159.         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
  160. }
  161.  
  162. static int get_data(void *data)
  163. {
  164.         struct intel_gmbus *bus = data;
  165.         struct drm_i915_private *dev_priv = bus->dev_priv;
  166.         u32 reserved = get_reserved(bus);
  167.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
  168.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
  169.         return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
  170. }
  171.  
  172. static void set_clock(void *data, int state_high)
  173. {
  174.         struct intel_gmbus *bus = data;
  175.         struct drm_i915_private *dev_priv = bus->dev_priv;
  176.         u32 reserved = get_reserved(bus);
  177.         u32 clock_bits;
  178.  
  179.         if (state_high)
  180.                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  181.         else
  182.                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  183.                         GPIO_CLOCK_VAL_MASK;
  184.  
  185.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
  186.         POSTING_READ(bus->gpio_reg);
  187. }
  188.  
  189. static void set_data(void *data, int state_high)
  190. {
  191.         struct intel_gmbus *bus = data;
  192.         struct drm_i915_private *dev_priv = bus->dev_priv;
  193.         u32 reserved = get_reserved(bus);
  194.         u32 data_bits;
  195.  
  196.         if (state_high)
  197.                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  198.         else
  199.                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  200.                         GPIO_DATA_VAL_MASK;
  201.  
  202.         I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
  203.         POSTING_READ(bus->gpio_reg);
  204. }
  205.  
  206. static int
  207. intel_gpio_pre_xfer(struct i2c_adapter *adapter)
  208. {
  209.         struct intel_gmbus *bus = container_of(adapter,
  210.                                                struct intel_gmbus,
  211.                                                adapter);
  212.         struct drm_i915_private *dev_priv = bus->dev_priv;
  213.  
  214.         intel_i2c_reset(dev_priv->dev);
  215.         intel_i2c_quirk_set(dev_priv, true);
  216.         set_data(bus, 1);
  217.         set_clock(bus, 1);
  218.         udelay(I2C_RISEFALL_TIME);
  219.         return 0;
  220. }
  221.  
  222. static void
  223. intel_gpio_post_xfer(struct i2c_adapter *adapter)
  224. {
  225.         struct intel_gmbus *bus = container_of(adapter,
  226.                                                struct intel_gmbus,
  227.                                                adapter);
  228.         struct drm_i915_private *dev_priv = bus->dev_priv;
  229.  
  230.         set_data(bus, 1);
  231.         set_clock(bus, 1);
  232.         intel_i2c_quirk_set(dev_priv, false);
  233. }
  234.  
  235. static void
  236. intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
  237. {
  238.         struct drm_i915_private *dev_priv = bus->dev_priv;
  239.         struct i2c_algo_bit_data *algo;
  240.  
  241.         algo = &bus->bit_algo;
  242.  
  243.         bus->gpio_reg = dev_priv->gpio_mmio_base +
  244.                 get_gmbus_pin(dev_priv, pin)->reg;
  245.  
  246.         bus->adapter.algo_data = algo;
  247.         algo->setsda = set_data;
  248.         algo->setscl = set_clock;
  249.         algo->getsda = get_data;
  250.         algo->getscl = get_clock;
  251.         algo->pre_xfer = intel_gpio_pre_xfer;
  252.         algo->post_xfer = intel_gpio_post_xfer;
  253.         algo->udelay = I2C_RISEFALL_TIME;
  254.         algo->timeout = usecs_to_jiffies(2200);
  255.         algo->data = bus;
  256. }
  257.  
  258. static int
  259. gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
  260.                      u32 gmbus2_status,
  261.                      u32 gmbus4_irq_en)
  262. {
  263.         int i;
  264.         u32 gmbus2 = 0;
  265.         DEFINE_WAIT(wait);
  266.  
  267.         if (!HAS_GMBUS_IRQ(dev_priv->dev))
  268.                 gmbus4_irq_en = 0;
  269.  
  270.         /* Important: The hw handles only the first bit, so set only one! Since
  271.          * we also need to check for NAKs besides the hw ready/idle signal, we
  272.          * need to wake up periodically and check that ourselves. */
  273.         I915_WRITE(GMBUS4, gmbus4_irq_en);
  274.  
  275.         for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
  276.                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
  277.                                 TASK_UNINTERRUPTIBLE);
  278.  
  279.                 gmbus2 = I915_READ_NOTRACE(GMBUS2);
  280.                 if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
  281.                         break;
  282.  
  283.                 schedule_timeout(1);
  284.         }
  285.         finish_wait(&dev_priv->gmbus_wait_queue, &wait);
  286.  
  287.         I915_WRITE(GMBUS4, 0);
  288.  
  289.         if (gmbus2 & GMBUS_SATOER)
  290.                 return -ENXIO;
  291.         if (gmbus2 & gmbus2_status)
  292.                 return 0;
  293.         return -ETIMEDOUT;
  294. }
  295.  
  296. static int
  297. gmbus_wait_idle(struct drm_i915_private *dev_priv)
  298. {
  299.         int ret;
  300.  
  301. #define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
  302.  
  303.         if (!HAS_GMBUS_IRQ(dev_priv->dev))
  304.                 return wait_for(C, 10);
  305.  
  306.         /* Important: The hw handles only the first bit, so set only one! */
  307.         I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
  308.  
  309.         ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  310.                                  msecs_to_jiffies_timeout(10));
  311.  
  312.         I915_WRITE(GMBUS4, 0);
  313.  
  314.         if (ret)
  315.                 return 0;
  316.         else
  317.                 return -ETIMEDOUT;
  318. #undef C
  319. }
  320.  
  321. static int
  322. gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
  323.                       unsigned short addr, u8 *buf, unsigned int len,
  324.                       u32 gmbus1_index)
  325. {
  326.         I915_WRITE(GMBUS1,
  327.                    gmbus1_index |
  328.                    GMBUS_CYCLE_WAIT |
  329.                    (len << GMBUS_BYTE_COUNT_SHIFT) |
  330.                    (addr << GMBUS_SLAVE_ADDR_SHIFT) |
  331.                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  332.         while (len) {
  333.                 int ret;
  334.                 u32 val, loop = 0;
  335.  
  336.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
  337.                                            GMBUS_HW_RDY_EN);
  338.                 if (ret)
  339.                         return ret;
  340.  
  341.                 val = I915_READ(GMBUS3);
  342.                 do {
  343.                         *buf++ = val & 0xff;
  344.                         val >>= 8;
  345.                 } while (--len && ++loop < 4);
  346.         }
  347.  
  348.         return 0;
  349. }
  350.  
  351. static int
  352. gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
  353.                 u32 gmbus1_index)
  354. {
  355.         u8 *buf = msg->buf;
  356.         unsigned int rx_size = msg->len;
  357.         unsigned int len;
  358.         int ret;
  359.  
  360.         do {
  361.                 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
  362.  
  363.                 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
  364.                                             buf, len, gmbus1_index);
  365.                 if (ret)
  366.                         return ret;
  367.  
  368.                 rx_size -= len;
  369.                 buf += len;
  370.         } while (rx_size != 0);
  371.  
  372.         return 0;
  373. }
  374.  
  375. static int
  376. gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
  377.                        unsigned short addr, u8 *buf, unsigned int len)
  378. {
  379.         unsigned int chunk_size = len;
  380.         u32 val, loop;
  381.  
  382.         val = loop = 0;
  383.         while (len && loop < 4) {
  384.                 val |= *buf++ << (8 * loop++);
  385.                 len -= 1;
  386.         }
  387.  
  388.         I915_WRITE(GMBUS3, val);
  389.         I915_WRITE(GMBUS1,
  390.                    GMBUS_CYCLE_WAIT |
  391.                    (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
  392.                    (addr << GMBUS_SLAVE_ADDR_SHIFT) |
  393.                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  394.         while (len) {
  395.                 int ret;
  396.  
  397.                 val = loop = 0;
  398.                 do {
  399.                         val |= *buf++ << (8 * loop);
  400.                 } while (--len && ++loop < 4);
  401.  
  402.                 I915_WRITE(GMBUS3, val);
  403.  
  404.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
  405.                                            GMBUS_HW_RDY_EN);
  406.                 if (ret)
  407.                         return ret;
  408.         }
  409.  
  410.         return 0;
  411. }
  412.  
  413. static int
  414. gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
  415. {
  416.         u8 *buf = msg->buf;
  417.         unsigned int tx_size = msg->len;
  418.         unsigned int len;
  419.         int ret;
  420.  
  421.         do {
  422.                 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
  423.  
  424.                 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
  425.                 if (ret)
  426.                         return ret;
  427.  
  428.                 buf += len;
  429.                 tx_size -= len;
  430.         } while (tx_size != 0);
  431.  
  432.         return 0;
  433. }
  434.  
  435. /*
  436.  * The gmbus controller can combine a 1 or 2 byte write with a read that
  437.  * immediately follows it by using an "INDEX" cycle.
  438.  */
  439. static bool
  440. gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
  441. {
  442.         return (i + 1 < num &&
  443.                 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
  444.                 (msgs[i + 1].flags & I2C_M_RD));
  445. }
  446.  
  447. static int
  448. gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
  449. {
  450.         u32 gmbus1_index = 0;
  451.         u32 gmbus5 = 0;
  452.         int ret;
  453.  
  454.         if (msgs[0].len == 2)
  455.                 gmbus5 = GMBUS_2BYTE_INDEX_EN |
  456.                          msgs[0].buf[1] | (msgs[0].buf[0] << 8);
  457.         if (msgs[0].len == 1)
  458.                 gmbus1_index = GMBUS_CYCLE_INDEX |
  459.                                (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
  460.  
  461.         /* GMBUS5 holds 16-bit index */
  462.         if (gmbus5)
  463.                 I915_WRITE(GMBUS5, gmbus5);
  464.  
  465.         ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
  466.  
  467.         /* Clear GMBUS5 after each index transfer */
  468.         if (gmbus5)
  469.                 I915_WRITE(GMBUS5, 0);
  470.  
  471.         return ret;
  472. }
  473.  
  474. static int
  475. gmbus_xfer(struct i2c_adapter *adapter,
  476.            struct i2c_msg *msgs,
  477.            int num)
  478. {
  479.         struct intel_gmbus *bus = container_of(adapter,
  480.                                                struct intel_gmbus,
  481.                                                adapter);
  482.         struct drm_i915_private *dev_priv = bus->dev_priv;
  483.         int i = 0, inc, try = 0;
  484.         int ret = 0;
  485.  
  486.         intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
  487.         mutex_lock(&dev_priv->gmbus_mutex);
  488.  
  489.         if (bus->force_bit) {
  490.                 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
  491.                 goto out;
  492.         }
  493.  
  494. retry:
  495.         I915_WRITE(GMBUS0, bus->reg0);
  496.  
  497.         for (; i < num; i += inc) {
  498.                 inc = 1;
  499.                 if (gmbus_is_index_read(msgs, i, num)) {
  500.                         ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
  501.                         inc = 2; /* an index read is two msgs */
  502.                 } else if (msgs[i].flags & I2C_M_RD) {
  503.                         ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
  504.                 } else {
  505.                         ret = gmbus_xfer_write(dev_priv, &msgs[i]);
  506.                 }
  507.  
  508.                 if (ret == -ETIMEDOUT)
  509.                         goto timeout;
  510.                 if (ret == -ENXIO)
  511.                         goto clear_err;
  512.  
  513.                 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
  514.                                            GMBUS_HW_WAIT_EN);
  515.                 if (ret == -ENXIO)
  516.                         goto clear_err;
  517.                 if (ret)
  518.                         goto timeout;
  519.         }
  520.  
  521.         /* Generate a STOP condition on the bus. Note that gmbus can't generata
  522.          * a STOP on the very first cycle. To simplify the code we
  523.          * unconditionally generate the STOP condition with an additional gmbus
  524.          * cycle. */
  525.         I915_WRITE(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
  526.  
  527.         /* Mark the GMBUS interface as disabled after waiting for idle.
  528.          * We will re-enable it at the start of the next xfer,
  529.          * till then let it sleep.
  530.          */
  531.         if (gmbus_wait_idle(dev_priv)) {
  532.                 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
  533.                          adapter->name);
  534.                 ret = -ETIMEDOUT;
  535.         }
  536.         I915_WRITE(GMBUS0, 0);
  537.         ret = ret ?: i;
  538.         goto out;
  539.  
  540. clear_err:
  541.         /*
  542.          * Wait for bus to IDLE before clearing NAK.
  543.          * If we clear the NAK while bus is still active, then it will stay
  544.          * active and the next transaction may fail.
  545.          *
  546.          * If no ACK is received during the address phase of a transaction, the
  547.          * adapter must report -ENXIO. It is not clear what to return if no ACK
  548.          * is received at other times. But we have to be careful to not return
  549.          * spurious -ENXIO because that will prevent i2c and drm edid functions
  550.          * from retrying. So return -ENXIO only when gmbus properly quiescents -
  551.          * timing out seems to happen when there _is_ a ddc chip present, but
  552.          * it's slow responding and only answers on the 2nd retry.
  553.          */
  554.         ret = -ENXIO;
  555.         if (gmbus_wait_idle(dev_priv)) {
  556.                 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
  557.                               adapter->name);
  558.                 ret = -ETIMEDOUT;
  559.         }
  560.  
  561.         /* Toggle the Software Clear Interrupt bit. This has the effect
  562.          * of resetting the GMBUS controller and so clearing the
  563.          * BUS_ERROR raised by the slave's NAK.
  564.          */
  565.         I915_WRITE(GMBUS1, GMBUS_SW_CLR_INT);
  566.         I915_WRITE(GMBUS1, 0);
  567.         I915_WRITE(GMBUS0, 0);
  568.  
  569.         DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
  570.                          adapter->name, msgs[i].addr,
  571.                          (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
  572.  
  573.         /*
  574.          * Passive adapters sometimes NAK the first probe. Retry the first
  575.          * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
  576.          * has retries internally. See also the retry loop in
  577.          * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
  578.          */
  579.         if (ret == -ENXIO && i == 0 && try++ == 0) {
  580.                 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
  581.                               adapter->name);
  582.                 goto retry;
  583.         }
  584.  
  585.         goto out;
  586.  
  587. timeout:
  588.         DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
  589.                  bus->adapter.name, bus->reg0 & 0xff);
  590.         I915_WRITE(GMBUS0, 0);
  591.  
  592.         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  593.         bus->force_bit = 1;
  594.         ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
  595.  
  596. out:
  597.         mutex_unlock(&dev_priv->gmbus_mutex);
  598.  
  599.         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
  600.  
  601.         return ret;
  602. }
  603.  
  604. static u32 gmbus_func(struct i2c_adapter *adapter)
  605. {
  606.         return i2c_bit_algo.functionality(adapter) &
  607.                 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  608.                 /* I2C_FUNC_10BIT_ADDR | */
  609.                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  610.                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  611. }
  612.  
  613. static const struct i2c_algorithm gmbus_algorithm = {
  614.         .master_xfer    = gmbus_xfer,
  615.         .functionality  = gmbus_func
  616. };
  617.  
  618. /**
  619.  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  620.  * @dev: DRM device
  621.  */
  622. int intel_setup_gmbus(struct drm_device *dev)
  623. {
  624.         struct drm_i915_private *dev_priv = dev->dev_private;
  625.         struct intel_gmbus *bus;
  626.         unsigned int pin;
  627.         int ret;
  628.  
  629.         if (HAS_PCH_NOP(dev))
  630.                 return 0;
  631.         else if (HAS_PCH_SPLIT(dev))
  632.                 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
  633.         else if (IS_VALLEYVIEW(dev))
  634.                 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
  635.         else
  636.                 dev_priv->gpio_mmio_base = 0;
  637.  
  638.         mutex_init(&dev_priv->gmbus_mutex);
  639.         init_waitqueue_head(&dev_priv->gmbus_wait_queue);
  640.  
  641.         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
  642.                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
  643.                         continue;
  644.  
  645.                 bus = &dev_priv->gmbus[pin];
  646.  
  647.                 bus->adapter.owner = THIS_MODULE;
  648.                 bus->adapter.class = I2C_CLASS_DDC;
  649.                 snprintf(bus->adapter.name,
  650.                          sizeof(bus->adapter.name),
  651.                          "i915 gmbus %s",
  652.                          get_gmbus_pin(dev_priv, pin)->name);
  653.  
  654.                 bus->adapter.dev.parent = &dev->pdev->dev;
  655.                 bus->dev_priv = dev_priv;
  656.  
  657.                 bus->adapter.algo = &gmbus_algorithm;
  658.  
  659.                 /* By default use a conservative clock rate */
  660.                 bus->reg0 = pin | GMBUS_RATE_100KHZ;
  661.  
  662.                 /* gmbus seems to be broken on i830 */
  663.                 if (IS_I830(dev))
  664.                         bus->force_bit = 1;
  665.  
  666.                 intel_gpio_setup(bus, pin);
  667.  
  668.                 ret = i2c_add_adapter(&bus->adapter);
  669.                 if (ret)
  670.                         goto err;
  671.         }
  672.  
  673.         intel_i2c_reset(dev_priv->dev);
  674.  
  675.         return 0;
  676.  
  677. err:
  678.         while (--pin) {
  679.                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
  680.                         continue;
  681.  
  682.                 bus = &dev_priv->gmbus[pin];
  683.                 i2c_del_adapter(&bus->adapter);
  684.         }
  685.         return ret;
  686. }
  687.  
  688. struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
  689.                                             unsigned int pin)
  690. {
  691.         if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
  692.                 return NULL;
  693.  
  694.         return &dev_priv->gmbus[pin].adapter;
  695. }
  696.  
  697. void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  698. {
  699.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  700.  
  701.         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
  702. }
  703.  
  704. void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  705. {
  706.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  707.  
  708.         bus->force_bit += force_bit ? 1 : -1;
  709.         DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
  710.                       force_bit ? "en" : "dis", adapter->name,
  711.                       bus->force_bit);
  712. }
  713.  
  714. void intel_teardown_gmbus(struct drm_device *dev)
  715. {
  716.         struct drm_i915_private *dev_priv = dev->dev_private;
  717.         struct intel_gmbus *bus;
  718.         unsigned int pin;
  719.  
  720.         for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
  721.                 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
  722.                         continue;
  723.  
  724.                 bus = &dev_priv->gmbus[pin];
  725.                 i2c_del_adapter(&bus->adapter);
  726.         }
  727. }
  728.