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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2008,2010 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23.  * DEALINGS IN THE SOFTWARE.
  24.  *
  25.  * Authors:
  26.  *      Eric Anholt <eric@anholt.net>
  27.  *      Chris Wilson <chris@chris-wilson.co.uk>
  28.  */
  29. #include <linux/i2c.h>
  30. #include <linux/i2c-algo-bit.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "intel_drv.h"
  34. //#include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include <syscall.h>
  37.  
  38. #define MSEC_PER_SEC    1000L
  39. #define USEC_PER_MSEC   1000L
  40. #define NSEC_PER_USEC   1000L
  41. #define NSEC_PER_MSEC   1000000L
  42. #define USEC_PER_SEC    1000000L
  43. #define NSEC_PER_SEC    1000000000L
  44. #define FSEC_PER_SEC    1000000000000000L
  45.  
  46. #define HZ_TO_MSEC_MUL32 0xA0000000
  47. #define HZ_TO_MSEC_ADJ32 0x0
  48. #define HZ_TO_MSEC_SHR32 28
  49. #define HZ_TO_MSEC_MUL64 0xA000000000000000
  50. #define HZ_TO_MSEC_ADJ64 0x0
  51. #define HZ_TO_MSEC_SHR64 60
  52. #define MSEC_TO_HZ_MUL32 0xCCCCCCCD
  53. #define MSEC_TO_HZ_ADJ32 0x733333333
  54. #define MSEC_TO_HZ_SHR32 35
  55. #define MSEC_TO_HZ_MUL64 0xCCCCCCCCCCCCCCCD
  56. #define MSEC_TO_HZ_ADJ64 0x73333333333333333
  57. #define MSEC_TO_HZ_SHR64 67
  58. #define HZ_TO_MSEC_NUM 10
  59. #define HZ_TO_MSEC_DEN 1
  60. #define MSEC_TO_HZ_NUM 1
  61. #define MSEC_TO_HZ_DEN 10
  62.  
  63. #define HZ_TO_USEC_MUL32 0x9C400000
  64. #define HZ_TO_USEC_ADJ32 0x0
  65. #define HZ_TO_USEC_SHR32 18
  66. #define HZ_TO_USEC_MUL64 0x9C40000000000000
  67. #define HZ_TO_USEC_ADJ64 0x0
  68. #define HZ_TO_USEC_SHR64 50
  69. #define USEC_TO_HZ_MUL32 0xD1B71759
  70. #define USEC_TO_HZ_ADJ32 0x1FFF2E48E8A7
  71. #define USEC_TO_HZ_SHR32 45
  72. #define USEC_TO_HZ_MUL64 0xD1B71758E219652C
  73. #define USEC_TO_HZ_ADJ64 0x1FFF2E48E8A71DE69AD4
  74. #define USEC_TO_HZ_SHR64 77
  75. #define HZ_TO_USEC_NUM 10000
  76. #define HZ_TO_USEC_DEN 1
  77. #define USEC_TO_HZ_NUM 1
  78. #define USEC_TO_HZ_DEN 10000
  79.  
  80. unsigned int inline jiffies_to_usecs(const unsigned long j)
  81. {
  82. #if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ)
  83.         return (USEC_PER_SEC / HZ) * j;
  84. #elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
  85.         return (j + (HZ / USEC_PER_SEC) - 1)/(HZ / USEC_PER_SEC);
  86. #else
  87. # if BITS_PER_LONG == 32
  88.         return (HZ_TO_USEC_MUL32 * j) >> HZ_TO_USEC_SHR32;
  89. # else
  90.         return (j * HZ_TO_USEC_NUM) / HZ_TO_USEC_DEN;
  91. # endif
  92. #endif
  93. }
  94.  
  95. /*
  96. * When we convert to jiffies then we interpret incoming values
  97. * the following way:
  98. *
  99. * - negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET)
  100. *
  101. * - 'too large' values [that would result in larger than
  102. *   MAX_JIFFY_OFFSET values] mean 'infinite timeout' too.
  103. *
  104. * - all other values are converted to jiffies by either multiplying
  105. *   the input value by a factor or dividing it with a factor
  106. *
  107. * We must also be careful about 32-bit overflows.
  108. */
  109. unsigned long msecs_to_jiffies(const unsigned int m)
  110. {
  111.         /*
  112.          * Negative value, means infinite timeout:
  113.          */
  114.         if ((int)m < 0)
  115.                 return MAX_JIFFY_OFFSET;
  116.  
  117. #if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)
  118.         /*
  119.          * HZ is equal to or smaller than 1000, and 1000 is a nice
  120.          * round multiple of HZ, divide with the factor between them,
  121.          * but round upwards:
  122.          */
  123.         return (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);
  124. #elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
  125.         /*
  126.          * HZ is larger than 1000, and HZ is a nice round multiple of
  127.          * 1000 - simply multiply with the factor between them.
  128.          *
  129.          * But first make sure the multiplication result cannot
  130.          * overflow:
  131.          */
  132.         if (m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
  133.                 return MAX_JIFFY_OFFSET;
  134.  
  135.         return m * (HZ / MSEC_PER_SEC);
  136. #else
  137.         /*
  138.          * Generic case - multiply, round and divide. But first
  139.          * check that if we are doing a net multiplication, that
  140.          * we wouldn't overflow:
  141.          */
  142.         if (HZ > MSEC_PER_SEC && m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
  143.                 return MAX_JIFFY_OFFSET;
  144.  
  145.         return (MSEC_TO_HZ_MUL32 * m + MSEC_TO_HZ_ADJ32)
  146.                 >> MSEC_TO_HZ_SHR32;
  147. #endif
  148. }
  149.  
  150. unsigned long usecs_to_jiffies(const unsigned int u)
  151. {
  152.         if (u > jiffies_to_usecs(MAX_JIFFY_OFFSET))
  153.                 return MAX_JIFFY_OFFSET;
  154. #if HZ <= USEC_PER_SEC && !(USEC_PER_SEC % HZ)
  155.         return (u + (USEC_PER_SEC / HZ) - 1) / (USEC_PER_SEC / HZ);
  156. #elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
  157.         return u * (HZ / USEC_PER_SEC);
  158. #else
  159.         return (USEC_TO_HZ_MUL32 * u + USEC_TO_HZ_ADJ32)
  160.                 >> USEC_TO_HZ_SHR32;
  161. #endif
  162. }
  163.  
  164.  
  165.  
  166. /* Intel GPIO access functions */
  167.  
  168. #define I2C_RISEFALL_TIME 20
  169.  
  170. static inline struct intel_gmbus *
  171. to_intel_gmbus(struct i2c_adapter *i2c)
  172. {
  173.         return container_of(i2c, struct intel_gmbus, adapter);
  174. }
  175.  
  176. struct intel_gpio {
  177.         struct i2c_adapter adapter;
  178.         struct i2c_algo_bit_data algo;
  179.         struct drm_i915_private *dev_priv;
  180.         u32 reg;
  181. };
  182.  
  183. void
  184. intel_i2c_reset(struct drm_device *dev)
  185. {
  186.         struct drm_i915_private *dev_priv = dev->dev_private;
  187.         if (HAS_PCH_SPLIT(dev))
  188.                 I915_WRITE(PCH_GMBUS0, 0);
  189.         else
  190.                 I915_WRITE(GMBUS0, 0);
  191. }
  192.  
  193. static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
  194. {
  195.         u32 val;
  196.  
  197.         /* When using bit bashing for I2C, this bit needs to be set to 1 */
  198.         if (!IS_PINEVIEW(dev_priv->dev))
  199.                 return;
  200.  
  201.         val = I915_READ(DSPCLK_GATE_D);
  202.         if (enable)
  203.                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
  204.         else
  205.                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
  206.         I915_WRITE(DSPCLK_GATE_D, val);
  207. }
  208.  
  209. static u32 get_reserved(struct intel_gpio *gpio)
  210. {
  211.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  212.         struct drm_device *dev = dev_priv->dev;
  213.         u32 reserved = 0;
  214.  
  215.         /* On most chips, these bits must be preserved in software. */
  216.         if (!IS_I830(dev) && !IS_845G(dev))
  217.                 reserved = I915_READ_NOTRACE(gpio->reg) &
  218.                                              (GPIO_DATA_PULLUP_DISABLE |
  219.                                               GPIO_CLOCK_PULLUP_DISABLE);
  220.  
  221.         return reserved;
  222. }
  223.  
  224. static int get_clock(void *data)
  225. {
  226.         struct intel_gpio *gpio = data;
  227.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  228.         u32 reserved = get_reserved(gpio);
  229.         I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
  230.         I915_WRITE_NOTRACE(gpio->reg, reserved);
  231.         return (I915_READ_NOTRACE(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
  232. }
  233.  
  234. static int get_data(void *data)
  235. {
  236.         struct intel_gpio *gpio = data;
  237.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  238.         u32 reserved = get_reserved(gpio);
  239.         I915_WRITE_NOTRACE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
  240.         I915_WRITE_NOTRACE(gpio->reg, reserved);
  241.         return (I915_READ_NOTRACE(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
  242. }
  243.  
  244. static void set_clock(void *data, int state_high)
  245. {
  246.         struct intel_gpio *gpio = data;
  247.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  248.         u32 reserved = get_reserved(gpio);
  249.         u32 clock_bits;
  250.  
  251.         if (state_high)
  252.                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
  253.         else
  254.                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
  255.                         GPIO_CLOCK_VAL_MASK;
  256.  
  257.         I915_WRITE_NOTRACE(gpio->reg, reserved | clock_bits);
  258.         POSTING_READ(gpio->reg);
  259. }
  260.  
  261. static void set_data(void *data, int state_high)
  262. {
  263.         struct intel_gpio *gpio = data;
  264.         struct drm_i915_private *dev_priv = gpio->dev_priv;
  265.         u32 reserved = get_reserved(gpio);
  266.         u32 data_bits;
  267.  
  268.         if (state_high)
  269.                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
  270.         else
  271.                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
  272.                         GPIO_DATA_VAL_MASK;
  273.  
  274.         I915_WRITE_NOTRACE(gpio->reg, reserved | data_bits);
  275.         POSTING_READ(gpio->reg);
  276. }
  277.  
  278. static struct i2c_adapter *
  279. intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin)
  280. {
  281.         static const int map_pin_to_reg[] = {
  282.                 0,
  283.                 GPIOB,
  284.                 GPIOA,
  285.                 GPIOC,
  286.                 GPIOD,
  287.                 GPIOE,
  288.                 0,
  289.                 GPIOF,
  290.         };
  291.         struct intel_gpio *gpio;
  292.     ENTER();
  293.         if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
  294.                 return NULL;
  295.  
  296.         gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
  297.         if (gpio == NULL)
  298.                 return NULL;
  299.  
  300.         gpio->reg = map_pin_to_reg[pin];
  301.         if (HAS_PCH_SPLIT(dev_priv->dev))
  302.                 gpio->reg += PCH_GPIOA - GPIOA;
  303.         gpio->dev_priv = dev_priv;
  304.  
  305.         snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
  306.                  "i915 GPIO%c", "?BACDE?F"[pin]);
  307. //   gpio->adapter.owner = THIS_MODULE;
  308.         gpio->adapter.algo_data = &gpio->algo;
  309.         gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
  310.         gpio->algo.setsda = set_data;
  311.         gpio->algo.setscl = set_clock;
  312.         gpio->algo.getsda = get_data;
  313.         gpio->algo.getscl = get_clock;
  314.         gpio->algo.udelay = I2C_RISEFALL_TIME;
  315.         gpio->algo.timeout = usecs_to_jiffies(2200);
  316.         gpio->algo.data = gpio;
  317.  
  318.     if (i2c_bit_add_bus(&gpio->adapter))
  319.        goto out_free;
  320.     LEAVE();
  321.         return &gpio->adapter;
  322.  
  323. out_free:
  324.         kfree(gpio);
  325.         return NULL;
  326. }
  327.  
  328. static int
  329. intel_i2c_quirk_xfer(struct drm_i915_private *dev_priv,
  330.                      struct i2c_adapter *adapter,
  331.                      struct i2c_msg *msgs,
  332.                      int num)
  333. {
  334.         struct intel_gpio *gpio = container_of(adapter,
  335.                                                struct intel_gpio,
  336.                                                adapter);
  337.         int ret;
  338.  
  339.         intel_i2c_reset(dev_priv->dev);
  340.  
  341.         intel_i2c_quirk_set(dev_priv, true);
  342.         set_data(gpio, 1);
  343.         set_clock(gpio, 1);
  344.         udelay(I2C_RISEFALL_TIME);
  345.  
  346.         ret = adapter->algo->master_xfer(adapter, msgs, num);
  347.  
  348.         set_data(gpio, 1);
  349.         set_clock(gpio, 1);
  350.         intel_i2c_quirk_set(dev_priv, false);
  351.  
  352.         return ret;
  353. }
  354.  
  355. static int
  356. gmbus_xfer(struct i2c_adapter *adapter,
  357.            struct i2c_msg *msgs,
  358.            int num)
  359. {
  360.         struct intel_gmbus *bus = container_of(adapter,
  361.                                                struct intel_gmbus,
  362.                                                adapter);
  363.         struct drm_i915_private *dev_priv = adapter->algo_data;
  364.         int i, reg_offset;
  365.  
  366.         if (bus->force_bit)
  367.                 return intel_i2c_quirk_xfer(dev_priv,
  368.                                             bus->force_bit, msgs, num);
  369.  
  370.         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
  371.  
  372.         I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
  373.  
  374.         for (i = 0; i < num; i++) {
  375.                 u16 len = msgs[i].len;
  376.                 u8 *buf = msgs[i].buf;
  377.  
  378.                 if (msgs[i].flags & I2C_M_RD) {
  379.                         I915_WRITE(GMBUS1 + reg_offset,
  380.                                    GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
  381.                                    (len << GMBUS_BYTE_COUNT_SHIFT) |
  382.                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  383.                                    GMBUS_SLAVE_READ | GMBUS_SW_RDY);
  384.                         POSTING_READ(GMBUS2+reg_offset);
  385.                         do {
  386.                                 u32 val, loop = 0;
  387.  
  388.                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  389.                                         goto timeout;
  390.                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  391.                                         goto clear_err;
  392.  
  393.                                 val = I915_READ(GMBUS3 + reg_offset);
  394.                                 do {
  395.                                         *buf++ = val & 0xff;
  396.                                         val >>= 8;
  397.                                 } while (--len && ++loop < 4);
  398.                         } while (len);
  399.                 } else {
  400.                         u32 val, loop;
  401.  
  402.                         val = loop = 0;
  403.                         do {
  404.                                 val |= *buf++ << (8 * loop);
  405.                         } while (--len && ++loop < 4);
  406.  
  407.                         I915_WRITE(GMBUS3 + reg_offset, val);
  408.                         I915_WRITE(GMBUS1 + reg_offset,
  409.                                    (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
  410.                                    (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
  411.                                    (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
  412.                                    GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
  413.                         POSTING_READ(GMBUS2+reg_offset);
  414.  
  415.                         while (len) {
  416.                                 if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
  417.                                         goto timeout;
  418.                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  419.                                         goto clear_err;
  420.  
  421.                                 val = loop = 0;
  422.                                 do {
  423.                                         val |= *buf++ << (8 * loop);
  424.                                 } while (--len && ++loop < 4);
  425.  
  426.                                 I915_WRITE(GMBUS3 + reg_offset, val);
  427.                                 POSTING_READ(GMBUS2+reg_offset);
  428.                         }
  429.                 }
  430.  
  431.                 if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
  432.                         goto timeout;
  433.                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
  434.                         goto clear_err;
  435.         }
  436.  
  437.         goto done;
  438.  
  439. clear_err:
  440.         /* Toggle the Software Clear Interrupt bit. This has the effect
  441.          * of resetting the GMBUS controller and so clearing the
  442.          * BUS_ERROR raised by the slave's NAK.
  443.          */
  444.         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
  445.         I915_WRITE(GMBUS1 + reg_offset, 0);
  446.  
  447. done:
  448.         /* Mark the GMBUS interface as disabled. We will re-enable it at the
  449.          * start of the next xfer, till then let it sleep.
  450.          */
  451.         I915_WRITE(GMBUS0 + reg_offset, 0);
  452.         return i;
  453.  
  454. timeout:
  455.         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
  456.                  bus->reg0 & 0xff, bus->adapter.name);
  457.         I915_WRITE(GMBUS0 + reg_offset, 0);
  458.  
  459.         /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
  460.         bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
  461.         if (!bus->force_bit)
  462.                 return -ENOMEM;
  463.  
  464.         return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
  465. }
  466.  
  467. static u32 gmbus_func(struct i2c_adapter *adapter)
  468. {
  469.         struct intel_gmbus *bus = container_of(adapter,
  470.                                                struct intel_gmbus,
  471.                                                adapter);
  472.  
  473.         if (bus->force_bit)
  474.                 bus->force_bit->algo->functionality(bus->force_bit);
  475.  
  476.         return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
  477.                 /* I2C_FUNC_10BIT_ADDR | */
  478.                 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
  479.                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
  480. }
  481.  
  482. static const struct i2c_algorithm gmbus_algorithm = {
  483.         .master_xfer    = gmbus_xfer,
  484.         .functionality  = gmbus_func
  485. };
  486.  
  487. /**
  488.  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
  489.  * @dev: DRM device
  490.  */
  491. int intel_setup_gmbus(struct drm_device *dev)
  492. {
  493.         static const char *names[GMBUS_NUM_PORTS] = {
  494.                 "disabled",
  495.                 "ssc",
  496.                 "vga",
  497.                 "panel",
  498.                 "dpc",
  499.                 "dpb",
  500.                 "reserved",
  501.                 "dpd",
  502.         };
  503.         struct drm_i915_private *dev_priv = dev->dev_private;
  504.         int ret, i;
  505.     ENTER();
  506.         dev_priv->gmbus = kcalloc(sizeof(struct intel_gmbus), GMBUS_NUM_PORTS,
  507.                                   GFP_KERNEL);
  508.         if (dev_priv->gmbus == NULL)
  509.                 return -ENOMEM;
  510.  
  511.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  512.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  513.  
  514. //       bus->adapter.owner = THIS_MODULE;
  515.                 bus->adapter.class = I2C_CLASS_DDC;
  516.                 snprintf(bus->adapter.name,
  517.                          sizeof(bus->adapter.name),
  518.                          "i915 gmbus %s",
  519.                          names[i]);
  520.  
  521.                 bus->adapter.dev.parent = &dev->pdev->dev;
  522.                 bus->adapter.algo_data  = dev_priv;
  523.  
  524.                 bus->adapter.algo = &gmbus_algorithm;
  525. //       ret = i2c_add_adapter(&bus->adapter);
  526. //       if (ret)
  527. //           goto err;
  528.  
  529.                 /* By default use a conservative clock rate */
  530.                 bus->reg0 = i | GMBUS_RATE_100KHZ;
  531.  
  532.                 /* XXX force bit banging until GMBUS is fully debugged */
  533.                 bus->force_bit = intel_gpio_create(dev_priv, i);
  534.         }
  535.  
  536.         intel_i2c_reset(dev_priv->dev);
  537.     LEAVE();
  538.         return 0;
  539.  
  540. err:
  541. //   while (--i) {
  542. //       struct intel_gmbus *bus = &dev_priv->gmbus[i];
  543. //       i2c_del_adapter(&bus->adapter);
  544. //   }
  545.         kfree(dev_priv->gmbus);
  546.         dev_priv->gmbus = NULL;
  547.         return ret;
  548. }
  549.  
  550. void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
  551. {
  552.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  553.  
  554.         /* speed:
  555.          * 0x0 = 100 KHz
  556.          * 0x1 = 50 KHz
  557.          * 0x2 = 400 KHz
  558.          * 0x3 = 1000 Khz
  559.          */
  560.         bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
  561. }
  562.  
  563. void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
  564. {
  565.         struct intel_gmbus *bus = to_intel_gmbus(adapter);
  566.  
  567.         if (force_bit) {
  568.                 if (bus->force_bit == NULL) {
  569.                         struct drm_i915_private *dev_priv = adapter->algo_data;
  570.                         bus->force_bit = intel_gpio_create(dev_priv,
  571.                                                            bus->reg0 & 0xff);
  572.                 }
  573.         } else {
  574.                 if (bus->force_bit) {
  575. //           i2c_del_adapter(bus->force_bit);
  576.                         kfree(bus->force_bit);
  577.                         bus->force_bit = NULL;
  578.                 }
  579.         }
  580. }
  581.  
  582. void intel_teardown_gmbus(struct drm_device *dev)
  583. {
  584.         struct drm_i915_private *dev_priv = dev->dev_private;
  585.         int i;
  586.  
  587.         if (dev_priv->gmbus == NULL)
  588.                 return;
  589.  
  590.         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
  591.                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
  592.                 if (bus->force_bit) {
  593. //           i2c_del_adapter(bus->force_bit);
  594.                         kfree(bus->force_bit);
  595.                 }
  596. //       i2c_del_adapter(&bus->adapter);
  597.         }
  598.  
  599.         kfree(dev_priv->gmbus);
  600.         dev_priv->gmbus = NULL;
  601. }
  602.