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  1. /*
  2.  * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2009 Intel Corporation
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the next
  13.  * paragraph) shall be included in all copies or substantial portions of the
  14.  * Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *      Eric Anholt <eric@anholt.net>
  26.  *      Jesse Barnes <jesse.barnes@intel.com>
  27.  */
  28.  
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38.  
  39. static void
  40. assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  41. {
  42.         struct drm_device *dev = intel_hdmi->base.base.dev;
  43.         struct drm_i915_private *dev_priv = dev->dev_private;
  44.         uint32_t enabled_bits;
  45.  
  46.         enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  47.  
  48.         WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
  49.              "HDMI port enabled, expecting disabled\n");
  50. }
  51.  
  52. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  53. {
  54.         return container_of(encoder, struct intel_hdmi, base.base);
  55. }
  56.  
  57. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  58. {
  59.         return container_of(intel_attached_encoder(connector),
  60.                             struct intel_hdmi, base);
  61. }
  62.  
  63. void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  64. {
  65.         uint8_t *data = (uint8_t *)frame;
  66.         uint8_t sum = 0;
  67.         unsigned i;
  68.  
  69.         frame->checksum = 0;
  70.         frame->ecc = 0;
  71.  
  72.         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  73.                 sum += data[i];
  74.  
  75.         frame->checksum = 0x100 - sum;
  76. }
  77.  
  78. static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  79. {
  80.         switch (frame->type) {
  81.         case DIP_TYPE_AVI:
  82.                 return VIDEO_DIP_SELECT_AVI;
  83.         case DIP_TYPE_SPD:
  84.                 return VIDEO_DIP_SELECT_SPD;
  85.         default:
  86.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  87.                 return 0;
  88.         }
  89. }
  90.  
  91. static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  92. {
  93.         switch (frame->type) {
  94.         case DIP_TYPE_AVI:
  95.                 return VIDEO_DIP_ENABLE_AVI;
  96.         case DIP_TYPE_SPD:
  97.                 return VIDEO_DIP_ENABLE_SPD;
  98.         default:
  99.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  100.                 return 0;
  101.         }
  102. }
  103.  
  104. static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
  105. {
  106.         switch (frame->type) {
  107.         case DIP_TYPE_AVI:
  108.                 return VIDEO_DIP_ENABLE_AVI_HSW;
  109.         case DIP_TYPE_SPD:
  110.                 return VIDEO_DIP_ENABLE_SPD_HSW;
  111.         default:
  112.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  113.                 return 0;
  114.         }
  115. }
  116.  
  117. static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
  118. {
  119.         switch (frame->type) {
  120.         case DIP_TYPE_AVI:
  121.                 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
  122.         case DIP_TYPE_SPD:
  123.                 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
  124.         default:
  125.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  126.                 return 0;
  127.         }
  128. }
  129.  
  130. static void g4x_write_infoframe(struct drm_encoder *encoder,
  131.                                  struct dip_infoframe *frame)
  132. {
  133.         uint32_t *data = (uint32_t *)frame;
  134.         struct drm_device *dev = encoder->dev;
  135.         struct drm_i915_private *dev_priv = dev->dev_private;
  136.         u32 val = I915_READ(VIDEO_DIP_CTL);
  137.         unsigned i, len = DIP_HEADER_SIZE + frame->len;
  138.  
  139.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  140.  
  141.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  142.         val |= g4x_infoframe_index(frame);
  143.  
  144.         val &= ~g4x_infoframe_enable(frame);
  145.  
  146.         I915_WRITE(VIDEO_DIP_CTL, val);
  147.  
  148.         mmiowb();
  149.         for (i = 0; i < len; i += 4) {
  150.                 I915_WRITE(VIDEO_DIP_DATA, *data);
  151.                 data++;
  152.         }
  153.         /* Write every possible data byte to force correct ECC calculation. */
  154.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  155.                 I915_WRITE(VIDEO_DIP_DATA, 0);
  156.         mmiowb();
  157.  
  158.         val |= g4x_infoframe_enable(frame);
  159.         val &= ~VIDEO_DIP_FREQ_MASK;
  160.         val |= VIDEO_DIP_FREQ_VSYNC;
  161.  
  162.         I915_WRITE(VIDEO_DIP_CTL, val);
  163.         POSTING_READ(VIDEO_DIP_CTL);
  164. }
  165.  
  166. static void ibx_write_infoframe(struct drm_encoder *encoder,
  167.                                      struct dip_infoframe *frame)
  168. {
  169.         uint32_t *data = (uint32_t *)frame;
  170.         struct drm_device *dev = encoder->dev;
  171.         struct drm_i915_private *dev_priv = dev->dev_private;
  172.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  173.         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  174.         unsigned i, len = DIP_HEADER_SIZE + frame->len;
  175.         u32 val = I915_READ(reg);
  176.  
  177.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  178.  
  179.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  180.         val |= g4x_infoframe_index(frame);
  181.  
  182.         val &= ~g4x_infoframe_enable(frame);
  183.  
  184.         I915_WRITE(reg, val);
  185.  
  186.         mmiowb();
  187.         for (i = 0; i < len; i += 4) {
  188.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  189.                 data++;
  190.         }
  191.         /* Write every possible data byte to force correct ECC calculation. */
  192.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  193.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  194.         mmiowb();
  195.  
  196.         val |= g4x_infoframe_enable(frame);
  197.         val &= ~VIDEO_DIP_FREQ_MASK;
  198.         val |= VIDEO_DIP_FREQ_VSYNC;
  199.  
  200.         I915_WRITE(reg, val);
  201.         POSTING_READ(reg);
  202. }
  203.  
  204. static void cpt_write_infoframe(struct drm_encoder *encoder,
  205.                                 struct dip_infoframe *frame)
  206. {
  207.         uint32_t *data = (uint32_t *)frame;
  208.         struct drm_device *dev = encoder->dev;
  209.         struct drm_i915_private *dev_priv = dev->dev_private;
  210.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  211.         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  212.         unsigned i, len = DIP_HEADER_SIZE + frame->len;
  213.         u32 val = I915_READ(reg);
  214.  
  215.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  216.  
  217.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  218.         val |= g4x_infoframe_index(frame);
  219.  
  220.         /* The DIP control register spec says that we need to update the AVI
  221.          * infoframe without clearing its enable bit */
  222.         if (frame->type != DIP_TYPE_AVI)
  223.                 val &= ~g4x_infoframe_enable(frame);
  224.  
  225.         I915_WRITE(reg, val);
  226.  
  227.         mmiowb();
  228.         for (i = 0; i < len; i += 4) {
  229.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  230.                 data++;
  231.         }
  232.         /* Write every possible data byte to force correct ECC calculation. */
  233.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  234.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  235.         mmiowb();
  236.  
  237.         val |= g4x_infoframe_enable(frame);
  238.         val &= ~VIDEO_DIP_FREQ_MASK;
  239.         val |= VIDEO_DIP_FREQ_VSYNC;
  240.  
  241.         I915_WRITE(reg, val);
  242.         POSTING_READ(reg);
  243. }
  244.  
  245. static void vlv_write_infoframe(struct drm_encoder *encoder,
  246.                                      struct dip_infoframe *frame)
  247. {
  248.         uint32_t *data = (uint32_t *)frame;
  249.         struct drm_device *dev = encoder->dev;
  250.         struct drm_i915_private *dev_priv = dev->dev_private;
  251.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  252.         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  253.         unsigned i, len = DIP_HEADER_SIZE + frame->len;
  254.         u32 val = I915_READ(reg);
  255.  
  256.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  257.  
  258.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  259.         val |= g4x_infoframe_index(frame);
  260.  
  261.         val &= ~g4x_infoframe_enable(frame);
  262.  
  263.         I915_WRITE(reg, val);
  264.  
  265.         mmiowb();
  266.         for (i = 0; i < len; i += 4) {
  267.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  268.                 data++;
  269.         }
  270.         /* Write every possible data byte to force correct ECC calculation. */
  271.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  272.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  273.         mmiowb();
  274.  
  275.         val |= g4x_infoframe_enable(frame);
  276.         val &= ~VIDEO_DIP_FREQ_MASK;
  277.         val |= VIDEO_DIP_FREQ_VSYNC;
  278.  
  279.         I915_WRITE(reg, val);
  280.         POSTING_READ(reg);
  281. }
  282.  
  283. static void hsw_write_infoframe(struct drm_encoder *encoder,
  284.                                 struct dip_infoframe *frame)
  285. {
  286.         uint32_t *data = (uint32_t *)frame;
  287.         struct drm_device *dev = encoder->dev;
  288.         struct drm_i915_private *dev_priv = dev->dev_private;
  289.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  290.         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  291.         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
  292.         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
  293.         u32 val = I915_READ(ctl_reg);
  294.  
  295.         if (data_reg == 0)
  296.                 return;
  297.  
  298.         val &= ~hsw_infoframe_enable(frame);
  299.         I915_WRITE(ctl_reg, val);
  300.  
  301.         mmiowb();
  302.         for (i = 0; i < len; i += 4) {
  303.                 I915_WRITE(data_reg + i, *data);
  304.                 data++;
  305.         }
  306.         /* Write every possible data byte to force correct ECC calculation. */
  307.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  308.                 I915_WRITE(data_reg + i, 0);
  309.         mmiowb();
  310.  
  311.         val |= hsw_infoframe_enable(frame);
  312.         I915_WRITE(ctl_reg, val);
  313.         POSTING_READ(ctl_reg);
  314. }
  315.  
  316. static void intel_set_infoframe(struct drm_encoder *encoder,
  317.                                 struct dip_infoframe *frame)
  318. {
  319.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  320.  
  321.         intel_dip_infoframe_csum(frame);
  322.         intel_hdmi->write_infoframe(encoder, frame);
  323. }
  324.  
  325. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  326.                                          struct drm_display_mode *adjusted_mode)
  327. {
  328.         struct dip_infoframe avi_if = {
  329.                 .type = DIP_TYPE_AVI,
  330.                 .ver = DIP_VERSION_AVI,
  331.                 .len = DIP_LEN_AVI,
  332.         };
  333.  
  334.         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  335.                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
  336.  
  337.         intel_set_infoframe(encoder, &avi_if);
  338. }
  339.  
  340. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  341. {
  342.         struct dip_infoframe spd_if;
  343.  
  344.         memset(&spd_if, 0, sizeof(spd_if));
  345.         spd_if.type = DIP_TYPE_SPD;
  346.         spd_if.ver = DIP_VERSION_SPD;
  347.         spd_if.len = DIP_LEN_SPD;
  348.         strcpy(spd_if.body.spd.vn, "Intel");
  349.         strcpy(spd_if.body.spd.pd, "Integrated gfx");
  350.         spd_if.body.spd.sdi = DIP_SPD_PC;
  351.  
  352.         intel_set_infoframe(encoder, &spd_if);
  353. }
  354.  
  355. static void g4x_set_infoframes(struct drm_encoder *encoder,
  356.                                struct drm_display_mode *adjusted_mode)
  357. {
  358.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  359.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  360.         u32 reg = VIDEO_DIP_CTL;
  361.         u32 val = I915_READ(reg);
  362.         u32 port;
  363.  
  364.         assert_hdmi_port_disabled(intel_hdmi);
  365.  
  366.         /* If the registers were not initialized yet, they might be zeroes,
  367.          * which means we're selecting the AVI DIP and we're setting its
  368.          * frequency to once. This seems to really confuse the HW and make
  369.          * things stop working (the register spec says the AVI always needs to
  370.          * be sent every VSync). So here we avoid writing to the register more
  371.          * than we need and also explicitly select the AVI DIP and explicitly
  372.          * set its frequency to every VSync. Avoiding to write it twice seems to
  373.          * be enough to solve the problem, but being defensive shouldn't hurt us
  374.          * either. */
  375.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  376.  
  377.         if (!intel_hdmi->has_hdmi_sink) {
  378.                 if (!(val & VIDEO_DIP_ENABLE))
  379.                         return;
  380.                 val &= ~VIDEO_DIP_ENABLE;
  381.                 I915_WRITE(reg, val);
  382.                 POSTING_READ(reg);
  383.                 return;
  384.         }
  385.  
  386.         switch (intel_hdmi->sdvox_reg) {
  387.         case SDVOB:
  388.                 port = VIDEO_DIP_PORT_B;
  389.                 break;
  390.         case SDVOC:
  391.                 port = VIDEO_DIP_PORT_C;
  392.                 break;
  393.         default:
  394.                 BUG();
  395.                 return;
  396.         }
  397.  
  398.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  399.                 if (val & VIDEO_DIP_ENABLE) {
  400.                         val &= ~VIDEO_DIP_ENABLE;
  401.                         I915_WRITE(reg, val);
  402.                         POSTING_READ(reg);
  403.                 }
  404.                 val &= ~VIDEO_DIP_PORT_MASK;
  405.                 val |= port;
  406.         }
  407.  
  408.         val |= VIDEO_DIP_ENABLE;
  409.         val &= ~VIDEO_DIP_ENABLE_VENDOR;
  410.  
  411.         I915_WRITE(reg, val);
  412.         POSTING_READ(reg);
  413.  
  414.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  415.         intel_hdmi_set_spd_infoframe(encoder);
  416. }
  417.  
  418. static void ibx_set_infoframes(struct drm_encoder *encoder,
  419.                                struct drm_display_mode *adjusted_mode)
  420. {
  421.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  422.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  423.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  424.         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  425.         u32 val = I915_READ(reg);
  426.         u32 port;
  427.  
  428.         assert_hdmi_port_disabled(intel_hdmi);
  429.  
  430.         /* See the big comment in g4x_set_infoframes() */
  431.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  432.  
  433.         if (!intel_hdmi->has_hdmi_sink) {
  434.                 if (!(val & VIDEO_DIP_ENABLE))
  435.                         return;
  436.                 val &= ~VIDEO_DIP_ENABLE;
  437.                 I915_WRITE(reg, val);
  438.                 POSTING_READ(reg);
  439.                 return;
  440.         }
  441.  
  442.         switch (intel_hdmi->sdvox_reg) {
  443.         case HDMIB:
  444.                 port = VIDEO_DIP_PORT_B;
  445.                 break;
  446.         case HDMIC:
  447.                 port = VIDEO_DIP_PORT_C;
  448.                 break;
  449.         case HDMID:
  450.                 port = VIDEO_DIP_PORT_D;
  451.                 break;
  452.         default:
  453.                 BUG();
  454.                 return;
  455.         }
  456.  
  457.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  458.                 if (val & VIDEO_DIP_ENABLE) {
  459.                         val &= ~VIDEO_DIP_ENABLE;
  460.                         I915_WRITE(reg, val);
  461.                         POSTING_READ(reg);
  462.                 }
  463.                 val &= ~VIDEO_DIP_PORT_MASK;
  464.                 val |= port;
  465.         }
  466.  
  467.         val |= VIDEO_DIP_ENABLE;
  468.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  469.                  VIDEO_DIP_ENABLE_GCP);
  470.  
  471.         I915_WRITE(reg, val);
  472.         POSTING_READ(reg);
  473.  
  474.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  475.         intel_hdmi_set_spd_infoframe(encoder);
  476. }
  477.  
  478. static void cpt_set_infoframes(struct drm_encoder *encoder,
  479.                                struct drm_display_mode *adjusted_mode)
  480. {
  481.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  482.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  483.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  484.         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  485.         u32 val = I915_READ(reg);
  486.  
  487.         assert_hdmi_port_disabled(intel_hdmi);
  488.  
  489.         /* See the big comment in g4x_set_infoframes() */
  490.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  491.  
  492.         if (!intel_hdmi->has_hdmi_sink) {
  493.                 if (!(val & VIDEO_DIP_ENABLE))
  494.                         return;
  495.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
  496.                 I915_WRITE(reg, val);
  497.                 POSTING_READ(reg);
  498.                 return;
  499.         }
  500.  
  501.         /* Set both together, unset both together: see the spec. */
  502.         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  503.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  504.                  VIDEO_DIP_ENABLE_GCP);
  505.  
  506.         I915_WRITE(reg, val);
  507.         POSTING_READ(reg);
  508.  
  509.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  510.         intel_hdmi_set_spd_infoframe(encoder);
  511. }
  512.  
  513. static void vlv_set_infoframes(struct drm_encoder *encoder,
  514.                                struct drm_display_mode *adjusted_mode)
  515. {
  516.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  517.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  518.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  519.         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  520.         u32 val = I915_READ(reg);
  521.  
  522.         assert_hdmi_port_disabled(intel_hdmi);
  523.  
  524.         /* See the big comment in g4x_set_infoframes() */
  525.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  526.  
  527.         if (!intel_hdmi->has_hdmi_sink) {
  528.                 if (!(val & VIDEO_DIP_ENABLE))
  529.                         return;
  530.                 val &= ~VIDEO_DIP_ENABLE;
  531.                 I915_WRITE(reg, val);
  532.                 POSTING_READ(reg);
  533.                 return;
  534.         }
  535.  
  536.         val |= VIDEO_DIP_ENABLE;
  537.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  538.                  VIDEO_DIP_ENABLE_GCP);
  539.  
  540.         I915_WRITE(reg, val);
  541.         POSTING_READ(reg);
  542.  
  543.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  544.         intel_hdmi_set_spd_infoframe(encoder);
  545. }
  546.  
  547. static void hsw_set_infoframes(struct drm_encoder *encoder,
  548.                                struct drm_display_mode *adjusted_mode)
  549. {
  550.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  551.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  552.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  553.         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  554.         u32 val = I915_READ(reg);
  555.  
  556.         assert_hdmi_port_disabled(intel_hdmi);
  557.  
  558.         if (!intel_hdmi->has_hdmi_sink) {
  559.                 I915_WRITE(reg, 0);
  560.                 POSTING_READ(reg);
  561.                 return;
  562.         }
  563.  
  564.         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
  565.                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
  566.  
  567.         I915_WRITE(reg, val);
  568.         POSTING_READ(reg);
  569.  
  570.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  571.         intel_hdmi_set_spd_infoframe(encoder);
  572. }
  573.  
  574. static void intel_hdmi_mode_set(struct drm_encoder *encoder,
  575.                                 struct drm_display_mode *mode,
  576.                                 struct drm_display_mode *adjusted_mode)
  577. {
  578.         struct drm_device *dev = encoder->dev;
  579.         struct drm_i915_private *dev_priv = dev->dev_private;
  580.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  581.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  582.         u32 sdvox;
  583.  
  584.         sdvox = SDVO_ENCODING_HDMI;
  585.         if (!HAS_PCH_SPLIT(dev))
  586.                 sdvox |= intel_hdmi->color_range;
  587.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  588.                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  589.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  590.                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  591.  
  592.         if (intel_crtc->bpp > 24)
  593.                 sdvox |= COLOR_FORMAT_12bpc;
  594.         else
  595.                 sdvox |= COLOR_FORMAT_8bpc;
  596.  
  597.         /* Required on CPT */
  598.         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  599.                 sdvox |= HDMI_MODE_SELECT;
  600.  
  601.         if (intel_hdmi->has_audio) {
  602.                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  603.                                  pipe_name(intel_crtc->pipe));
  604.                 sdvox |= SDVO_AUDIO_ENABLE;
  605.                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
  606.                 intel_write_eld(encoder, adjusted_mode);
  607.         }
  608.  
  609.                 if (HAS_PCH_CPT(dev))
  610.                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  611.         else if (intel_crtc->pipe == PIPE_B)
  612.                         sdvox |= SDVO_PIPE_B_SELECT;
  613.  
  614.         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
  615.         POSTING_READ(intel_hdmi->sdvox_reg);
  616.  
  617.         intel_hdmi->set_infoframes(encoder, adjusted_mode);
  618. }
  619.  
  620. static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  621.                                     enum pipe *pipe)
  622. {
  623.         struct drm_device *dev = encoder->base.dev;
  624.         struct drm_i915_private *dev_priv = dev->dev_private;
  625.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  626.         u32 tmp;
  627.  
  628.         tmp = I915_READ(intel_hdmi->sdvox_reg);
  629.  
  630.         if (!(tmp & SDVO_ENABLE))
  631.                 return false;
  632.  
  633.         if (HAS_PCH_CPT(dev))
  634.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  635.         else
  636.                 *pipe = PORT_TO_PIPE(tmp);
  637.  
  638.         return true;
  639. }
  640.  
  641. static void intel_enable_hdmi(struct intel_encoder *encoder)
  642. {
  643.         struct drm_device *dev = encoder->base.dev;
  644.         struct drm_i915_private *dev_priv = dev->dev_private;
  645.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  646.         u32 temp;
  647.         u32 enable_bits = SDVO_ENABLE;
  648.  
  649.         if (intel_hdmi->has_audio)
  650.                 enable_bits |= SDVO_AUDIO_ENABLE;
  651.  
  652.         temp = I915_READ(intel_hdmi->sdvox_reg);
  653.  
  654.         /* HW workaround for IBX, we need to move the port to transcoder A
  655.          * before disabling it. */
  656.         if (HAS_PCH_IBX(dev)) {
  657.                 struct drm_crtc *crtc = encoder->base.crtc;
  658.                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  659.  
  660.                 /* Restore the transcoder select bit. */
  661.                 if (pipe == PIPE_B)
  662.                         enable_bits |= SDVO_PIPE_B_SELECT;
  663.         }
  664.  
  665.         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  666.          * we do this anyway which shows more stable in testing.
  667.          */
  668.         if (HAS_PCH_SPLIT(dev)) {
  669.                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  670.                 POSTING_READ(intel_hdmi->sdvox_reg);
  671.         }
  672.  
  673.         temp |= enable_bits;
  674.  
  675.         I915_WRITE(intel_hdmi->sdvox_reg, temp);
  676.         POSTING_READ(intel_hdmi->sdvox_reg);
  677.  
  678.         /* HW workaround, need to write this twice for issue that may result
  679.          * in first write getting masked.
  680.          */
  681.         if (HAS_PCH_SPLIT(dev)) {
  682.                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
  683.                 POSTING_READ(intel_hdmi->sdvox_reg);
  684.         }
  685. }
  686.  
  687. static void intel_disable_hdmi(struct intel_encoder *encoder)
  688. {
  689.         struct drm_device *dev = encoder->base.dev;
  690.         struct drm_i915_private *dev_priv = dev->dev_private;
  691.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  692.         u32 temp;
  693.         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
  694.  
  695.         temp = I915_READ(intel_hdmi->sdvox_reg);
  696.  
  697.         /* HW workaround for IBX, we need to move the port to transcoder A
  698.          * before disabling it. */
  699.         if (HAS_PCH_IBX(dev)) {
  700.                 struct drm_crtc *crtc = encoder->base.crtc;
  701.                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  702.  
  703.                         if (temp & SDVO_PIPE_B_SELECT) {
  704.                                 temp &= ~SDVO_PIPE_B_SELECT;
  705.                                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
  706.                                 POSTING_READ(intel_hdmi->sdvox_reg);
  707.  
  708.                                 /* Again we need to write this twice. */
  709.                                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
  710.                                 POSTING_READ(intel_hdmi->sdvox_reg);
  711.  
  712.                                 /* Transcoder selection bits only update
  713.                                  * effectively on vblank. */
  714.                                 if (crtc)
  715.                                         intel_wait_for_vblank(dev, pipe);
  716.                                 else
  717.                                         msleep(50);
  718.                         }
  719.         }
  720.  
  721.         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  722.          * we do this anyway which shows more stable in testing.
  723.          */
  724.         if (HAS_PCH_SPLIT(dev)) {
  725.                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  726.                 POSTING_READ(intel_hdmi->sdvox_reg);
  727.         }
  728.  
  729.                 temp &= ~enable_bits;
  730.  
  731.         I915_WRITE(intel_hdmi->sdvox_reg, temp);
  732.         POSTING_READ(intel_hdmi->sdvox_reg);
  733.  
  734.         /* HW workaround, need to write this twice for issue that may result
  735.          * in first write getting masked.
  736.          */
  737.         if (HAS_PCH_SPLIT(dev)) {
  738.                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
  739.                 POSTING_READ(intel_hdmi->sdvox_reg);
  740.         }
  741. }
  742.  
  743. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  744.                                  struct drm_display_mode *mode)
  745. {
  746.         if (mode->clock > 165000)
  747.                 return MODE_CLOCK_HIGH;
  748.         if (mode->clock < 20000)
  749.                 return MODE_CLOCK_LOW;
  750.  
  751.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  752.                 return MODE_NO_DBLESCAN;
  753.  
  754.         return MODE_OK;
  755. }
  756.  
  757. static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  758.                                   const struct drm_display_mode *mode,
  759.                                   struct drm_display_mode *adjusted_mode)
  760. {
  761.         return true;
  762. }
  763.  
  764. static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
  765. {
  766.         struct drm_device *dev = intel_hdmi->base.base.dev;
  767.         struct drm_i915_private *dev_priv = dev->dev_private;
  768.         uint32_t bit;
  769.  
  770.         switch (intel_hdmi->sdvox_reg) {
  771.         case SDVOB:
  772.                 bit = HDMIB_HOTPLUG_LIVE_STATUS;
  773.                 break;
  774.         case SDVOC:
  775.                 bit = HDMIC_HOTPLUG_LIVE_STATUS;
  776.                 break;
  777.         default:
  778.                 bit = 0;
  779.                 break;
  780.         }
  781.  
  782.         return I915_READ(PORT_HOTPLUG_STAT) & bit;
  783. }
  784.  
  785. static enum drm_connector_status
  786. intel_hdmi_detect(struct drm_connector *connector, bool force)
  787. {
  788.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  789.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  790.         struct edid *edid;
  791.         enum drm_connector_status status = connector_status_disconnected;
  792.  
  793.         if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
  794.                 return status;
  795.  
  796.         intel_hdmi->has_hdmi_sink = false;
  797.         intel_hdmi->has_audio = false;
  798.         edid = drm_get_edid(connector,
  799.                             intel_gmbus_get_adapter(dev_priv,
  800.                                                     intel_hdmi->ddc_bus));
  801.  
  802.         if (edid) {
  803.                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  804.                         status = connector_status_connected;
  805.                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  806.                                 intel_hdmi->has_hdmi_sink =
  807.                                                 drm_detect_hdmi_monitor(edid);
  808.                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  809.                 }
  810.                 kfree(edid);
  811.         }
  812.  
  813.         if (status == connector_status_connected) {
  814.                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  815.                         intel_hdmi->has_audio =
  816.                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
  817.         }
  818.  
  819.         return status;
  820. }
  821.  
  822. static int intel_hdmi_get_modes(struct drm_connector *connector)
  823. {
  824.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  825.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  826.  
  827.         /* We should parse the EDID data and find out if it's an HDMI sink so
  828.          * we can send audio to it.
  829.          */
  830.  
  831.         return intel_ddc_get_modes(connector,
  832.                                    intel_gmbus_get_adapter(dev_priv,
  833.                                                            intel_hdmi->ddc_bus));
  834. }
  835.  
  836. static bool
  837. intel_hdmi_detect_audio(struct drm_connector *connector)
  838. {
  839.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  840.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  841.         struct edid *edid;
  842.         bool has_audio = false;
  843.  
  844.         edid = drm_get_edid(connector,
  845.                             intel_gmbus_get_adapter(dev_priv,
  846.                                                     intel_hdmi->ddc_bus));
  847.         if (edid) {
  848.                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
  849.                         has_audio = drm_detect_monitor_audio(edid);
  850.                 kfree(edid);
  851.         }
  852.  
  853.         return has_audio;
  854. }
  855.  
  856. static int
  857. intel_hdmi_set_property(struct drm_connector *connector,
  858.                       struct drm_property *property,
  859.                       uint64_t val)
  860. {
  861.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  862.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  863.         int ret;
  864.  
  865.         ret = drm_connector_property_set_value(connector, property, val);
  866.         if (ret)
  867.                 return ret;
  868. #if 0
  869.         if (property == dev_priv->force_audio_property) {
  870.                 enum hdmi_force_audio i = val;
  871.                 bool has_audio;
  872.  
  873.                 if (i == intel_hdmi->force_audio)
  874.                         return 0;
  875.  
  876.                 intel_hdmi->force_audio = i;
  877.  
  878.                 if (i == HDMI_AUDIO_AUTO)
  879.                         has_audio = intel_hdmi_detect_audio(connector);
  880.                 else
  881.                         has_audio = (i == HDMI_AUDIO_ON);
  882.  
  883.                 if (i == HDMI_AUDIO_OFF_DVI)
  884.                         intel_hdmi->has_hdmi_sink = 0;
  885.  
  886.                 intel_hdmi->has_audio = has_audio;
  887.                 goto done;
  888.         }
  889. #endif
  890.  
  891.         if (property == dev_priv->broadcast_rgb_property) {
  892.                 if (val == !!intel_hdmi->color_range)
  893.                         return 0;
  894.  
  895.                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  896.                 goto done;
  897.         }
  898.  
  899.         return -EINVAL;
  900.  
  901. done:
  902.         if (intel_hdmi->base.base.crtc) {
  903.                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
  904.                 intel_set_mode(crtc, &crtc->mode,
  905.                                crtc->x, crtc->y, crtc->fb);
  906.         }
  907.  
  908.         return 0;
  909. }
  910.  
  911. static void intel_hdmi_destroy(struct drm_connector *connector)
  912. {
  913.         drm_sysfs_connector_remove(connector);
  914.         drm_connector_cleanup(connector);
  915.         kfree(connector);
  916. }
  917.  
  918. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
  919.         .mode_fixup = intel_hdmi_mode_fixup,
  920.         .mode_set = intel_ddi_mode_set,
  921.         .disable = intel_encoder_noop,
  922. };
  923.  
  924. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
  925.         .mode_fixup = intel_hdmi_mode_fixup,
  926.         .mode_set = intel_hdmi_mode_set,
  927.         .disable = intel_encoder_noop,
  928. };
  929.  
  930. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  931.         .dpms = intel_connector_dpms,
  932.         .detect = intel_hdmi_detect,
  933.         .fill_modes = drm_helper_probe_single_connector_modes,
  934.         .set_property = intel_hdmi_set_property,
  935.         .destroy = intel_hdmi_destroy,
  936. };
  937.  
  938. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  939.         .get_modes = intel_hdmi_get_modes,
  940.         .mode_valid = intel_hdmi_mode_valid,
  941.         .best_encoder = intel_best_encoder,
  942. };
  943.  
  944. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  945.         .destroy = intel_encoder_destroy,
  946. };
  947.  
  948. static void
  949. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  950. {
  951.         intel_attach_force_audio_property(connector);
  952.         intel_attach_broadcast_rgb_property(connector);
  953. }
  954.  
  955. void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
  956. {
  957.         struct drm_i915_private *dev_priv = dev->dev_private;
  958.         struct drm_connector *connector;
  959.         struct intel_encoder *intel_encoder;
  960.         struct intel_connector *intel_connector;
  961.         struct intel_hdmi *intel_hdmi;
  962.  
  963.         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
  964.         if (!intel_hdmi)
  965.                 return;
  966.  
  967.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  968.         if (!intel_connector) {
  969.                 kfree(intel_hdmi);
  970.                 return;
  971.         }
  972.  
  973.         intel_encoder = &intel_hdmi->base;
  974.         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  975.                          DRM_MODE_ENCODER_TMDS);
  976.  
  977.         connector = &intel_connector->base;
  978.         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  979.                            DRM_MODE_CONNECTOR_HDMIA);
  980.         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  981.  
  982.         intel_encoder->type = INTEL_OUTPUT_HDMI;
  983.  
  984.         connector->polled = DRM_CONNECTOR_POLL_HPD;
  985.         connector->interlace_allowed = 1;
  986.         connector->doublescan_allowed = 0;
  987.         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  988.  
  989.         intel_encoder->cloneable = false;
  990.  
  991.         intel_hdmi->ddi_port = port;
  992.         switch (port) {
  993.         case PORT_B:
  994.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  995.                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  996.                 break;
  997.         case PORT_C:
  998.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  999.                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  1000.                 break;
  1001.         case PORT_D:
  1002.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  1003.                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
  1004.                 break;
  1005.         case PORT_A:
  1006.                 /* Internal port only for eDP. */
  1007.         default:
  1008.                 BUG();
  1009.         }
  1010.  
  1011.         intel_hdmi->sdvox_reg = sdvox_reg;
  1012.  
  1013.         if (!HAS_PCH_SPLIT(dev)) {
  1014.                 intel_hdmi->write_infoframe = g4x_write_infoframe;
  1015.                 intel_hdmi->set_infoframes = g4x_set_infoframes;
  1016.         } else if (IS_VALLEYVIEW(dev)) {
  1017.                 intel_hdmi->write_infoframe = vlv_write_infoframe;
  1018.                 intel_hdmi->set_infoframes = vlv_set_infoframes;
  1019.         } else if (IS_HASWELL(dev)) {
  1020.                 intel_hdmi->write_infoframe = hsw_write_infoframe;
  1021.                 intel_hdmi->set_infoframes = hsw_set_infoframes;
  1022.         } else if (HAS_PCH_IBX(dev)) {
  1023.                 intel_hdmi->write_infoframe = ibx_write_infoframe;
  1024.                 intel_hdmi->set_infoframes = ibx_set_infoframes;
  1025.         } else {
  1026.                 intel_hdmi->write_infoframe = cpt_write_infoframe;
  1027.                 intel_hdmi->set_infoframes = cpt_set_infoframes;
  1028.         }
  1029.  
  1030.         if (IS_HASWELL(dev)) {
  1031.                 intel_encoder->enable = intel_enable_ddi;
  1032.                 intel_encoder->disable = intel_disable_ddi;
  1033.                 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
  1034.                 drm_encoder_helper_add(&intel_encoder->base,
  1035.                                        &intel_hdmi_helper_funcs_hsw);
  1036.         } else {
  1037.                 intel_encoder->enable = intel_enable_hdmi;
  1038.                 intel_encoder->disable = intel_disable_hdmi;
  1039.                 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
  1040.                 drm_encoder_helper_add(&intel_encoder->base,
  1041.                                        &intel_hdmi_helper_funcs);
  1042.         }
  1043.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  1044.  
  1045.  
  1046.         intel_hdmi_add_properties(intel_hdmi, connector);
  1047.  
  1048.         intel_connector_attach_encoder(intel_connector, intel_encoder);
  1049.         drm_sysfs_connector_add(connector);
  1050.  
  1051.         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  1052.          * 0xd.  Failure to do so will result in spurious interrupts being
  1053.          * generated on the port when a cable is not attached.
  1054.          */
  1055.         if (IS_G4X(dev) && !IS_GM45(dev)) {
  1056.                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  1057.                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  1058.         }
  1059. }
  1060.