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  1. /*
  2.  * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2009 Intel Corporation
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the next
  13.  * paragraph) shall be included in all copies or substantial portions of the
  14.  * Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *      Eric Anholt <eric@anholt.net>
  26.  *      Jesse Barnes <jesse.barnes@intel.com>
  27.  */
  28.  
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. //#include <linux/delay.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "intel_drv.h"
  37. #include "i915_drm.h"
  38. #include "i915_drv.h"
  39.  
  40. struct intel_hdmi {
  41.         struct intel_encoder base;
  42.         u32 sdvox_reg;
  43.         int ddc_bus;
  44.         uint32_t color_range;
  45.         bool has_hdmi_sink;
  46.         bool has_audio;
  47.         int force_audio;
  48.         void (*write_infoframe)(struct drm_encoder *encoder,
  49.                                 struct dip_infoframe *frame);
  50. };
  51.  
  52. static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  53. {
  54.         return container_of(encoder, struct intel_hdmi, base.base);
  55. }
  56.  
  57. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  58. {
  59.         return container_of(intel_attached_encoder(connector),
  60.                             struct intel_hdmi, base);
  61. }
  62.  
  63. void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  64. {
  65.         uint8_t *data = (uint8_t *)frame;
  66.         uint8_t sum = 0;
  67.         unsigned i;
  68.  
  69.         frame->checksum = 0;
  70.         frame->ecc = 0;
  71.  
  72.         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  73.                 sum += data[i];
  74.  
  75.         frame->checksum = 0x100 - sum;
  76. }
  77.  
  78. static u32 intel_infoframe_index(struct dip_infoframe *frame)
  79. {
  80.         u32 flags = 0;
  81.  
  82.         switch (frame->type) {
  83.         case DIP_TYPE_AVI:
  84.                 flags |= VIDEO_DIP_SELECT_AVI;
  85.                 break;
  86.         case DIP_TYPE_SPD:
  87.                 flags |= VIDEO_DIP_SELECT_SPD;
  88.                 break;
  89.         default:
  90.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  91.                 break;
  92.         }
  93.  
  94.         return flags;
  95. }
  96.  
  97. static u32 intel_infoframe_flags(struct dip_infoframe *frame)
  98. {
  99.         u32 flags = 0;
  100.  
  101.         switch (frame->type) {
  102.         case DIP_TYPE_AVI:
  103.                 flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
  104.                 break;
  105.         case DIP_TYPE_SPD:
  106.                 flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC;
  107.                 break;
  108.         default:
  109.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  110.                 break;
  111.         }
  112.  
  113.         return flags;
  114. }
  115.  
  116. static void i9xx_write_infoframe(struct drm_encoder *encoder,
  117.                                  struct dip_infoframe *frame)
  118. {
  119.         uint32_t *data = (uint32_t *)frame;
  120.         struct drm_device *dev = encoder->dev;
  121.         struct drm_i915_private *dev_priv = dev->dev_private;
  122.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  123.         u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
  124.         unsigned i, len = DIP_HEADER_SIZE + frame->len;
  125.  
  126.  
  127.         /* XXX first guess at handling video port, is this corrent? */
  128.         if (intel_hdmi->sdvox_reg == SDVOB)
  129.                 port = VIDEO_DIP_PORT_B;
  130.         else if (intel_hdmi->sdvox_reg == SDVOC)
  131.                 port = VIDEO_DIP_PORT_C;
  132.         else
  133.                 return;
  134.  
  135.         flags = intel_infoframe_index(frame);
  136.  
  137.         val &= ~VIDEO_DIP_SELECT_MASK;
  138.  
  139.         I915_WRITE(VIDEO_DIP_CTL, val | port | flags);
  140.  
  141.         for (i = 0; i < len; i += 4) {
  142.                 I915_WRITE(VIDEO_DIP_DATA, *data);
  143.                 data++;
  144.         }
  145.  
  146.         flags |= intel_infoframe_flags(frame);
  147.  
  148.         I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
  149. }
  150.  
  151. static void ironlake_write_infoframe(struct drm_encoder *encoder,
  152.                                      struct dip_infoframe *frame)
  153. {
  154.         uint32_t *data = (uint32_t *)frame;
  155.         struct drm_device *dev = encoder->dev;
  156.         struct drm_i915_private *dev_priv = dev->dev_private;
  157.         struct drm_crtc *crtc = encoder->crtc;
  158.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  159.         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  160.         unsigned i, len = DIP_HEADER_SIZE + frame->len;
  161.         u32 flags, val = I915_READ(reg);
  162.  
  163.         intel_wait_for_vblank(dev, intel_crtc->pipe);
  164.  
  165.         flags = intel_infoframe_index(frame);
  166.  
  167.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  168.  
  169.         I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
  170.  
  171.         for (i = 0; i < len; i += 4) {
  172.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  173.                 data++;
  174.         }
  175.  
  176.         flags |= intel_infoframe_flags(frame);
  177.  
  178.         I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
  179. }
  180. static void intel_set_infoframe(struct drm_encoder *encoder,
  181.                                 struct dip_infoframe *frame)
  182. {
  183.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  184.  
  185.         if (!intel_hdmi->has_hdmi_sink)
  186.                 return;
  187.  
  188.         intel_dip_infoframe_csum(frame);
  189.         intel_hdmi->write_infoframe(encoder, frame);
  190. }
  191.  
  192. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
  193. {
  194.         struct dip_infoframe avi_if = {
  195.                 .type = DIP_TYPE_AVI,
  196.                 .ver = DIP_VERSION_AVI,
  197.                 .len = DIP_LEN_AVI,
  198.         };
  199.  
  200.         intel_set_infoframe(encoder, &avi_if);
  201. }
  202.  
  203. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  204. {
  205.         struct dip_infoframe spd_if;
  206.  
  207.         memset(&spd_if, 0, sizeof(spd_if));
  208.         spd_if.type = DIP_TYPE_SPD;
  209.         spd_if.ver = DIP_VERSION_SPD;
  210.         spd_if.len = DIP_LEN_SPD;
  211.         strcpy(spd_if.body.spd.vn, "Intel");
  212.         strcpy(spd_if.body.spd.pd, "Integrated gfx");
  213.         spd_if.body.spd.sdi = DIP_SPD_PC;
  214.  
  215.         intel_set_infoframe(encoder, &spd_if);
  216. }
  217.  
  218. static void intel_hdmi_mode_set(struct drm_encoder *encoder,
  219.                                 struct drm_display_mode *mode,
  220.                                 struct drm_display_mode *adjusted_mode)
  221. {
  222.         struct drm_device *dev = encoder->dev;
  223.         struct drm_i915_private *dev_priv = dev->dev_private;
  224.         struct drm_crtc *crtc = encoder->crtc;
  225.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  226.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  227.         u32 sdvox;
  228.  
  229.         sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
  230.         if (!HAS_PCH_SPLIT(dev))
  231.                 sdvox |= intel_hdmi->color_range;
  232.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  233.                 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  234.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  235.                 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  236.  
  237.         if (intel_crtc->bpp > 24)
  238.                 sdvox |= COLOR_FORMAT_12bpc;
  239.         else
  240.                 sdvox |= COLOR_FORMAT_8bpc;
  241.  
  242.         /* Required on CPT */
  243.         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  244.                 sdvox |= HDMI_MODE_SELECT;
  245.  
  246.         if (intel_hdmi->has_audio) {
  247.                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  248.                                  pipe_name(intel_crtc->pipe));
  249.                 sdvox |= SDVO_AUDIO_ENABLE;
  250.                 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
  251.                 intel_write_eld(encoder, adjusted_mode);
  252.         }
  253.  
  254.                 if (HAS_PCH_CPT(dev))
  255.                 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  256.         else if (intel_crtc->pipe == 1)
  257.                         sdvox |= SDVO_PIPE_B_SELECT;
  258.  
  259.         I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
  260.         POSTING_READ(intel_hdmi->sdvox_reg);
  261.  
  262.         intel_hdmi_set_avi_infoframe(encoder);
  263.         intel_hdmi_set_spd_infoframe(encoder);
  264. }
  265.  
  266. static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
  267. {
  268.         struct drm_device *dev = encoder->dev;
  269.         struct drm_i915_private *dev_priv = dev->dev_private;
  270.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  271.         u32 temp;
  272.         u32 enable_bits = SDVO_ENABLE;
  273.  
  274.         if (intel_hdmi->has_audio)
  275.                 enable_bits |= SDVO_AUDIO_ENABLE;
  276.  
  277.         temp = I915_READ(intel_hdmi->sdvox_reg);
  278.  
  279.         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  280.          * we do this anyway which shows more stable in testing.
  281.          */
  282.         if (HAS_PCH_SPLIT(dev)) {
  283.                 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  284.                 POSTING_READ(intel_hdmi->sdvox_reg);
  285.         }
  286.  
  287.         if (mode != DRM_MODE_DPMS_ON) {
  288.                 temp &= ~enable_bits;
  289.         } else {
  290.                 temp |= enable_bits;
  291.         }
  292.  
  293.         I915_WRITE(intel_hdmi->sdvox_reg, temp);
  294.         POSTING_READ(intel_hdmi->sdvox_reg);
  295.  
  296.         /* HW workaround, need to write this twice for issue that may result
  297.          * in first write getting masked.
  298.          */
  299.         if (HAS_PCH_SPLIT(dev)) {
  300.                 I915_WRITE(intel_hdmi->sdvox_reg, temp);
  301.                 POSTING_READ(intel_hdmi->sdvox_reg);
  302.         }
  303. }
  304.  
  305. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  306.                                  struct drm_display_mode *mode)
  307. {
  308.         if (mode->clock > 165000)
  309.                 return MODE_CLOCK_HIGH;
  310.         if (mode->clock < 20000)
  311.                 return MODE_CLOCK_LOW;
  312.  
  313.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  314.                 return MODE_NO_DBLESCAN;
  315.  
  316.         return MODE_OK;
  317. }
  318.  
  319. static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  320.                                   struct drm_display_mode *mode,
  321.                                   struct drm_display_mode *adjusted_mode)
  322. {
  323.         return true;
  324. }
  325.  
  326. static enum drm_connector_status
  327. intel_hdmi_detect(struct drm_connector *connector, bool force)
  328. {
  329.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  330.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  331.         struct edid *edid;
  332.         enum drm_connector_status status = connector_status_disconnected;
  333.  
  334.         intel_hdmi->has_hdmi_sink = false;
  335.         intel_hdmi->has_audio = false;
  336.         edid = drm_get_edid(connector,
  337.                             &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
  338.  
  339.         if (edid) {
  340.                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  341.                         status = connector_status_connected;
  342.                         intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
  343.                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  344.                 }
  345.                 connector->display_info.raw_edid = NULL;
  346.                 kfree(edid);
  347.         }
  348.  
  349.         if (status == connector_status_connected) {
  350.                 if (intel_hdmi->force_audio)
  351.                         intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
  352.         }
  353.  
  354.         return status;
  355. }
  356.  
  357. static int intel_hdmi_get_modes(struct drm_connector *connector)
  358. {
  359.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  360.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  361.  
  362.         /* We should parse the EDID data and find out if it's an HDMI sink so
  363.          * we can send audio to it.
  364.          */
  365.  
  366.         return intel_ddc_get_modes(connector,
  367.                                    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
  368. }
  369.  
  370. static bool
  371. intel_hdmi_detect_audio(struct drm_connector *connector)
  372. {
  373.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  374.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  375.         struct edid *edid;
  376.         bool has_audio = false;
  377.  
  378.         edid = drm_get_edid(connector,
  379.                             &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
  380.         if (edid) {
  381.                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
  382.                         has_audio = drm_detect_monitor_audio(edid);
  383.  
  384.                 connector->display_info.raw_edid = NULL;
  385.                 kfree(edid);
  386.         }
  387.  
  388.         return has_audio;
  389. }
  390.  
  391. static int
  392. intel_hdmi_set_property(struct drm_connector *connector,
  393.                       struct drm_property *property,
  394.                       uint64_t val)
  395. {
  396.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  397.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  398.         int ret;
  399.  
  400.         ret = drm_connector_property_set_value(connector, property, val);
  401.         if (ret)
  402.                 return ret;
  403. #if 0
  404.         if (property == dev_priv->force_audio_property) {
  405.                 int i = val;
  406.                 bool has_audio;
  407.  
  408.                 if (i == intel_hdmi->force_audio)
  409.                         return 0;
  410.  
  411.                 intel_hdmi->force_audio = i;
  412.  
  413.                 if (i == 0)
  414.                         has_audio = intel_hdmi_detect_audio(connector);
  415.                 else
  416.                         has_audio = i > 0;
  417.  
  418.                 if (has_audio == intel_hdmi->has_audio)
  419.                         return 0;
  420.  
  421.                 intel_hdmi->has_audio = has_audio;
  422.                 goto done;
  423.         }
  424.  
  425.         if (property == dev_priv->broadcast_rgb_property) {
  426.                 if (val == !!intel_hdmi->color_range)
  427.                         return 0;
  428.  
  429.                 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  430.                 goto done;
  431.         }
  432. #endif
  433.         return -EINVAL;
  434.  
  435. done:
  436.         if (intel_hdmi->base.base.crtc) {
  437.                 struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
  438.                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
  439.                                          crtc->x, crtc->y,
  440.                                          crtc->fb);
  441.         }
  442.  
  443.         return 0;
  444. }
  445.  
  446. static void intel_hdmi_destroy(struct drm_connector *connector)
  447. {
  448.         drm_sysfs_connector_remove(connector);
  449.         drm_connector_cleanup(connector);
  450.         kfree(connector);
  451. }
  452.  
  453. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
  454.         .dpms = intel_hdmi_dpms,
  455.         .mode_fixup = intel_hdmi_mode_fixup,
  456.         .prepare = intel_encoder_prepare,
  457.         .mode_set = intel_hdmi_mode_set,
  458.         .commit = intel_encoder_commit,
  459. };
  460.  
  461. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  462.         .dpms = drm_helper_connector_dpms,
  463.         .detect = intel_hdmi_detect,
  464.         .fill_modes = drm_helper_probe_single_connector_modes,
  465.         .set_property = intel_hdmi_set_property,
  466.         .destroy = intel_hdmi_destroy,
  467. };
  468.  
  469. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  470.         .get_modes = intel_hdmi_get_modes,
  471.         .mode_valid = intel_hdmi_mode_valid,
  472.         .best_encoder = intel_best_encoder,
  473. };
  474.  
  475. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  476.         .destroy = intel_encoder_destroy,
  477. };
  478.  
  479. static void
  480. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  481. {
  482.         intel_attach_force_audio_property(connector);
  483.         intel_attach_broadcast_rgb_property(connector);
  484. }
  485.  
  486. void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
  487. {
  488.         struct drm_i915_private *dev_priv = dev->dev_private;
  489.         struct drm_connector *connector;
  490.         struct intel_encoder *intel_encoder;
  491.         struct intel_connector *intel_connector;
  492.         struct intel_hdmi *intel_hdmi;
  493.         int i;
  494.  
  495.         intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
  496.         if (!intel_hdmi)
  497.                 return;
  498.  
  499.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  500.         if (!intel_connector) {
  501.                 kfree(intel_hdmi);
  502.                 return;
  503.         }
  504.  
  505.         intel_encoder = &intel_hdmi->base;
  506.         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  507.                          DRM_MODE_ENCODER_TMDS);
  508.  
  509.         connector = &intel_connector->base;
  510.         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  511.                            DRM_MODE_CONNECTOR_HDMIA);
  512.         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  513.  
  514.         intel_encoder->type = INTEL_OUTPUT_HDMI;
  515.  
  516.         connector->polled = DRM_CONNECTOR_POLL_HPD;
  517.         connector->interlace_allowed = 0;
  518.         connector->doublescan_allowed = 0;
  519.         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  520.  
  521.         /* Set up the DDC bus. */
  522.         if (sdvox_reg == SDVOB) {
  523.                 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
  524.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  525.                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  526.         } else if (sdvox_reg == SDVOC) {
  527.                 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
  528.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  529.                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  530.         } else if (sdvox_reg == HDMIB) {
  531.                 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
  532.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  533.                 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  534.         } else if (sdvox_reg == HDMIC) {
  535.                 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
  536.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  537.                 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  538.         } else if (sdvox_reg == HDMID) {
  539.                 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
  540.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  541.                 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
  542.         }
  543.  
  544.         intel_hdmi->sdvox_reg = sdvox_reg;
  545.  
  546.         if (!HAS_PCH_SPLIT(dev)) {
  547.                 intel_hdmi->write_infoframe = i9xx_write_infoframe;
  548.                 I915_WRITE(VIDEO_DIP_CTL, 0);
  549.         } else {
  550.                 intel_hdmi->write_infoframe = ironlake_write_infoframe;
  551.                 for_each_pipe(i)
  552.                         I915_WRITE(TVIDEO_DIP_CTL(i), 0);
  553.         }
  554.  
  555.         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
  556.  
  557.         intel_hdmi_add_properties(intel_hdmi, connector);
  558.  
  559.         intel_connector_attach_encoder(intel_connector, intel_encoder);
  560.         drm_sysfs_connector_add(connector);
  561.  
  562.         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  563.          * 0xd.  Failure to do so will result in spurious interrupts being
  564.          * generated on the port when a cable is not attached.
  565.          */
  566.         if (IS_G4X(dev) && !IS_GM45(dev)) {
  567.                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  568.                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  569.         }
  570. }
  571.