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  1. /*
  2.  * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright © 2006-2009 Intel Corporation
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the next
  13.  * paragraph) shall be included in all copies or substantial portions of the
  14.  * Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22.  * DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *      Eric Anholt <eric@anholt.net>
  26.  *      Jesse Barnes <jesse.barnes@intel.com>
  27.  */
  28.  
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <linux/hdmi.h>
  33. #include <drm/drmP.h>
  34. #include <drm/drm_crtc.h>
  35. #include <drm/drm_edid.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39.  
  40. static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41. {
  42.         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43. }
  44.  
  45. static void
  46. assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47. {
  48.         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49.         struct drm_i915_private *dev_priv = dev->dev_private;
  50.         uint32_t enabled_bits;
  51.  
  52.         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53.  
  54.         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55.              "HDMI port enabled, expecting disabled\n");
  56. }
  57.  
  58. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59. {
  60.         struct intel_digital_port *intel_dig_port =
  61.                 container_of(encoder, struct intel_digital_port, base.base);
  62.         return &intel_dig_port->hdmi;
  63. }
  64.  
  65. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66. {
  67.         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68. }
  69.  
  70. static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71. {
  72.         switch (type) {
  73.         case HDMI_INFOFRAME_TYPE_AVI:
  74.                 return VIDEO_DIP_SELECT_AVI;
  75.         case HDMI_INFOFRAME_TYPE_SPD:
  76.                 return VIDEO_DIP_SELECT_SPD;
  77.         case HDMI_INFOFRAME_TYPE_VENDOR:
  78.                 return VIDEO_DIP_SELECT_VENDOR;
  79.         default:
  80.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81.                 return 0;
  82.         }
  83. }
  84.  
  85. static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86. {
  87.         switch (type) {
  88.         case HDMI_INFOFRAME_TYPE_AVI:
  89.                 return VIDEO_DIP_ENABLE_AVI;
  90.         case HDMI_INFOFRAME_TYPE_SPD:
  91.                 return VIDEO_DIP_ENABLE_SPD;
  92.         case HDMI_INFOFRAME_TYPE_VENDOR:
  93.                 return VIDEO_DIP_ENABLE_VENDOR;
  94.         default:
  95.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96.                 return 0;
  97.         }
  98. }
  99.  
  100. static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
  101. {
  102.         switch (type) {
  103.         case HDMI_INFOFRAME_TYPE_AVI:
  104.                 return VIDEO_DIP_ENABLE_AVI_HSW;
  105.         case HDMI_INFOFRAME_TYPE_SPD:
  106.                 return VIDEO_DIP_ENABLE_SPD_HSW;
  107.         case HDMI_INFOFRAME_TYPE_VENDOR:
  108.                 return VIDEO_DIP_ENABLE_VS_HSW;
  109.         default:
  110.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  111.                 return 0;
  112.         }
  113. }
  114.  
  115. static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
  116.                                   enum transcoder cpu_transcoder)
  117. {
  118.         switch (type) {
  119.         case HDMI_INFOFRAME_TYPE_AVI:
  120.                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
  121.         case HDMI_INFOFRAME_TYPE_SPD:
  122.                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
  123.         case HDMI_INFOFRAME_TYPE_VENDOR:
  124.                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
  125.         default:
  126.                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  127.                 return 0;
  128.         }
  129. }
  130.  
  131. static void g4x_write_infoframe(struct drm_encoder *encoder,
  132.                                 enum hdmi_infoframe_type type,
  133.                                 const uint8_t *frame, ssize_t len)
  134. {
  135.         uint32_t *data = (uint32_t *)frame;
  136.         struct drm_device *dev = encoder->dev;
  137.         struct drm_i915_private *dev_priv = dev->dev_private;
  138.         u32 val = I915_READ(VIDEO_DIP_CTL);
  139.         int i;
  140.  
  141.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  142.  
  143.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  144.         val |= g4x_infoframe_index(type);
  145.  
  146.         val &= ~g4x_infoframe_enable(type);
  147.  
  148.         I915_WRITE(VIDEO_DIP_CTL, val);
  149.  
  150.         mmiowb();
  151.         for (i = 0; i < len; i += 4) {
  152.                 I915_WRITE(VIDEO_DIP_DATA, *data);
  153.                 data++;
  154.         }
  155.         /* Write every possible data byte to force correct ECC calculation. */
  156.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  157.                 I915_WRITE(VIDEO_DIP_DATA, 0);
  158.         mmiowb();
  159.  
  160.         val |= g4x_infoframe_enable(type);
  161.         val &= ~VIDEO_DIP_FREQ_MASK;
  162.         val |= VIDEO_DIP_FREQ_VSYNC;
  163.  
  164.         I915_WRITE(VIDEO_DIP_CTL, val);
  165.         POSTING_READ(VIDEO_DIP_CTL);
  166. }
  167.  
  168. static void ibx_write_infoframe(struct drm_encoder *encoder,
  169.                                 enum hdmi_infoframe_type type,
  170.                                 const uint8_t *frame, ssize_t len)
  171. {
  172.         uint32_t *data = (uint32_t *)frame;
  173.         struct drm_device *dev = encoder->dev;
  174.         struct drm_i915_private *dev_priv = dev->dev_private;
  175.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  176.         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  177.         u32 val = I915_READ(reg);
  178.  
  179.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  180.  
  181.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  182.         val |= g4x_infoframe_index(type);
  183.  
  184.         val &= ~g4x_infoframe_enable(type);
  185.  
  186.         I915_WRITE(reg, val);
  187.  
  188.         mmiowb();
  189.         for (i = 0; i < len; i += 4) {
  190.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  191.                 data++;
  192.         }
  193.         /* Write every possible data byte to force correct ECC calculation. */
  194.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  195.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  196.         mmiowb();
  197.  
  198.         val |= g4x_infoframe_enable(type);
  199.         val &= ~VIDEO_DIP_FREQ_MASK;
  200.         val |= VIDEO_DIP_FREQ_VSYNC;
  201.  
  202.         I915_WRITE(reg, val);
  203.         POSTING_READ(reg);
  204. }
  205.  
  206. static void cpt_write_infoframe(struct drm_encoder *encoder,
  207.                                 enum hdmi_infoframe_type type,
  208.                                 const uint8_t *frame, ssize_t len)
  209. {
  210.         uint32_t *data = (uint32_t *)frame;
  211.         struct drm_device *dev = encoder->dev;
  212.         struct drm_i915_private *dev_priv = dev->dev_private;
  213.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  214.         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  215.         u32 val = I915_READ(reg);
  216.  
  217.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  218.  
  219.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  220.         val |= g4x_infoframe_index(type);
  221.  
  222.         /* The DIP control register spec says that we need to update the AVI
  223.          * infoframe without clearing its enable bit */
  224.         if (type != HDMI_INFOFRAME_TYPE_AVI)
  225.                 val &= ~g4x_infoframe_enable(type);
  226.  
  227.         I915_WRITE(reg, val);
  228.  
  229.         mmiowb();
  230.         for (i = 0; i < len; i += 4) {
  231.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  232.                 data++;
  233.         }
  234.         /* Write every possible data byte to force correct ECC calculation. */
  235.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  236.                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  237.         mmiowb();
  238.  
  239.         val |= g4x_infoframe_enable(type);
  240.         val &= ~VIDEO_DIP_FREQ_MASK;
  241.         val |= VIDEO_DIP_FREQ_VSYNC;
  242.  
  243.         I915_WRITE(reg, val);
  244.         POSTING_READ(reg);
  245. }
  246.  
  247. static void vlv_write_infoframe(struct drm_encoder *encoder,
  248.                                 enum hdmi_infoframe_type type,
  249.                                 const uint8_t *frame, ssize_t len)
  250. {
  251.         uint32_t *data = (uint32_t *)frame;
  252.         struct drm_device *dev = encoder->dev;
  253.         struct drm_i915_private *dev_priv = dev->dev_private;
  254.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  255.         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  256.         u32 val = I915_READ(reg);
  257.  
  258.         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  259.  
  260.         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  261.         val |= g4x_infoframe_index(type);
  262.  
  263.         val &= ~g4x_infoframe_enable(type);
  264.  
  265.         I915_WRITE(reg, val);
  266.  
  267.         mmiowb();
  268.         for (i = 0; i < len; i += 4) {
  269.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  270.                 data++;
  271.         }
  272.         /* Write every possible data byte to force correct ECC calculation. */
  273.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  274.                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  275.         mmiowb();
  276.  
  277.         val |= g4x_infoframe_enable(type);
  278.         val &= ~VIDEO_DIP_FREQ_MASK;
  279.         val |= VIDEO_DIP_FREQ_VSYNC;
  280.  
  281.         I915_WRITE(reg, val);
  282.         POSTING_READ(reg);
  283. }
  284.  
  285. static void hsw_write_infoframe(struct drm_encoder *encoder,
  286.                                 enum hdmi_infoframe_type type,
  287.                                 const uint8_t *frame, ssize_t len)
  288. {
  289.         uint32_t *data = (uint32_t *)frame;
  290.         struct drm_device *dev = encoder->dev;
  291.         struct drm_i915_private *dev_priv = dev->dev_private;
  292.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  293.         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
  294.         u32 data_reg;
  295.         int i;
  296.         u32 val = I915_READ(ctl_reg);
  297.  
  298.         data_reg = hsw_infoframe_data_reg(type,
  299.                                           intel_crtc->config.cpu_transcoder);
  300.         if (data_reg == 0)
  301.                 return;
  302.  
  303.         val &= ~hsw_infoframe_enable(type);
  304.         I915_WRITE(ctl_reg, val);
  305.  
  306.         mmiowb();
  307.         for (i = 0; i < len; i += 4) {
  308.                 I915_WRITE(data_reg + i, *data);
  309.                 data++;
  310.         }
  311.         /* Write every possible data byte to force correct ECC calculation. */
  312.         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  313.                 I915_WRITE(data_reg + i, 0);
  314.         mmiowb();
  315.  
  316.         val |= hsw_infoframe_enable(type);
  317.         I915_WRITE(ctl_reg, val);
  318.         POSTING_READ(ctl_reg);
  319. }
  320.  
  321. /*
  322.  * The data we write to the DIP data buffer registers is 1 byte bigger than the
  323.  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
  324.  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
  325.  * used for both technologies.
  326.  *
  327.  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
  328.  * DW1:       DB3       | DB2 | DB1 | DB0
  329.  * DW2:       DB7       | DB6 | DB5 | DB4
  330.  * DW3: ...
  331.  *
  332.  * (HB is Header Byte, DB is Data Byte)
  333.  *
  334.  * The hdmi pack() functions don't know about that hardware specific hole so we
  335.  * trick them by giving an offset into the buffer and moving back the header
  336.  * bytes by one.
  337.  */
  338. static void intel_write_infoframe(struct drm_encoder *encoder,
  339.                                   union hdmi_infoframe *frame)
  340. {
  341.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  342.         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
  343.         ssize_t len;
  344.  
  345.         /* see comment above for the reason for this offset */
  346.         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
  347.         if (len < 0)
  348.                 return;
  349.  
  350.         /* Insert the 'hole' (see big comment above) at position 3 */
  351.         buffer[0] = buffer[1];
  352.         buffer[1] = buffer[2];
  353.         buffer[2] = buffer[3];
  354.         buffer[3] = 0;
  355.         len++;
  356.  
  357.         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
  358. }
  359.  
  360. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  361.                                          struct drm_display_mode *adjusted_mode)
  362. {
  363.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  364.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  365.         union hdmi_infoframe frame;
  366.         int ret;
  367.  
  368.         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
  369.                                                        adjusted_mode);
  370.         if (ret < 0) {
  371.                 DRM_ERROR("couldn't fill AVI infoframe\n");
  372.                 return;
  373.         }
  374.  
  375.         if (intel_hdmi->rgb_quant_range_selectable) {
  376.                 if (intel_crtc->config.limited_color_range)
  377.                         frame.avi.quantization_range =
  378.                                 HDMI_QUANTIZATION_RANGE_LIMITED;
  379.                 else
  380.                         frame.avi.quantization_range =
  381.                                 HDMI_QUANTIZATION_RANGE_FULL;
  382.         }
  383.  
  384.         intel_write_infoframe(encoder, &frame);
  385. }
  386.  
  387. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  388. {
  389.         union hdmi_infoframe frame;
  390.         int ret;
  391.  
  392.         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
  393.         if (ret < 0) {
  394.                 DRM_ERROR("couldn't fill SPD infoframe\n");
  395.                 return;
  396.         }
  397.  
  398.         frame.spd.sdi = HDMI_SPD_SDI_PC;
  399.  
  400.         intel_write_infoframe(encoder, &frame);
  401. }
  402.  
  403. static void
  404. intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
  405.                               struct drm_display_mode *adjusted_mode)
  406. {
  407.         union hdmi_infoframe frame;
  408.         int ret;
  409.  
  410.         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
  411.                                                           adjusted_mode);
  412.         if (ret < 0)
  413.                 return;
  414.  
  415.         intel_write_infoframe(encoder, &frame);
  416. }
  417.  
  418. static void g4x_set_infoframes(struct drm_encoder *encoder,
  419.                                struct drm_display_mode *adjusted_mode)
  420. {
  421.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  422.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  423.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  424.         u32 reg = VIDEO_DIP_CTL;
  425.         u32 val = I915_READ(reg);
  426.         u32 port;
  427.  
  428.         assert_hdmi_port_disabled(intel_hdmi);
  429.  
  430.         /* If the registers were not initialized yet, they might be zeroes,
  431.          * which means we're selecting the AVI DIP and we're setting its
  432.          * frequency to once. This seems to really confuse the HW and make
  433.          * things stop working (the register spec says the AVI always needs to
  434.          * be sent every VSync). So here we avoid writing to the register more
  435.          * than we need and also explicitly select the AVI DIP and explicitly
  436.          * set its frequency to every VSync. Avoiding to write it twice seems to
  437.          * be enough to solve the problem, but being defensive shouldn't hurt us
  438.          * either. */
  439.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  440.  
  441.         if (!intel_hdmi->has_hdmi_sink) {
  442.                 if (!(val & VIDEO_DIP_ENABLE))
  443.                         return;
  444.                 val &= ~VIDEO_DIP_ENABLE;
  445.                 I915_WRITE(reg, val);
  446.                 POSTING_READ(reg);
  447.                 return;
  448.         }
  449.  
  450.         switch (intel_dig_port->port) {
  451.         case PORT_B:
  452.                 port = VIDEO_DIP_PORT_B;
  453.                 break;
  454.         case PORT_C:
  455.                 port = VIDEO_DIP_PORT_C;
  456.                 break;
  457.         default:
  458.                 BUG();
  459.                 return;
  460.         }
  461.  
  462.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  463.                 if (val & VIDEO_DIP_ENABLE) {
  464.                         val &= ~VIDEO_DIP_ENABLE;
  465.                         I915_WRITE(reg, val);
  466.                         POSTING_READ(reg);
  467.                 }
  468.                 val &= ~VIDEO_DIP_PORT_MASK;
  469.                 val |= port;
  470.         }
  471.  
  472.         val |= VIDEO_DIP_ENABLE;
  473.         val &= ~VIDEO_DIP_ENABLE_VENDOR;
  474.  
  475.         I915_WRITE(reg, val);
  476.         POSTING_READ(reg);
  477.  
  478.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  479.         intel_hdmi_set_spd_infoframe(encoder);
  480.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  481. }
  482.  
  483. static void ibx_set_infoframes(struct drm_encoder *encoder,
  484.                                struct drm_display_mode *adjusted_mode)
  485. {
  486.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  487.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  488.         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  489.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  490.         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  491.         u32 val = I915_READ(reg);
  492.         u32 port;
  493.  
  494.         assert_hdmi_port_disabled(intel_hdmi);
  495.  
  496.         /* See the big comment in g4x_set_infoframes() */
  497.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  498.  
  499.         if (!intel_hdmi->has_hdmi_sink) {
  500.                 if (!(val & VIDEO_DIP_ENABLE))
  501.                         return;
  502.                 val &= ~VIDEO_DIP_ENABLE;
  503.                 I915_WRITE(reg, val);
  504.                 POSTING_READ(reg);
  505.                 return;
  506.         }
  507.  
  508.         switch (intel_dig_port->port) {
  509.         case PORT_B:
  510.                 port = VIDEO_DIP_PORT_B;
  511.                 break;
  512.         case PORT_C:
  513.                 port = VIDEO_DIP_PORT_C;
  514.                 break;
  515.         case PORT_D:
  516.                 port = VIDEO_DIP_PORT_D;
  517.                 break;
  518.         default:
  519.                 BUG();
  520.                 return;
  521.         }
  522.  
  523.         if (port != (val & VIDEO_DIP_PORT_MASK)) {
  524.                 if (val & VIDEO_DIP_ENABLE) {
  525.                         val &= ~VIDEO_DIP_ENABLE;
  526.                         I915_WRITE(reg, val);
  527.                         POSTING_READ(reg);
  528.                 }
  529.                 val &= ~VIDEO_DIP_PORT_MASK;
  530.                 val |= port;
  531.         }
  532.  
  533.         val |= VIDEO_DIP_ENABLE;
  534.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  535.                  VIDEO_DIP_ENABLE_GCP);
  536.  
  537.         I915_WRITE(reg, val);
  538.         POSTING_READ(reg);
  539.  
  540.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  541.         intel_hdmi_set_spd_infoframe(encoder);
  542.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  543. }
  544.  
  545. static void cpt_set_infoframes(struct drm_encoder *encoder,
  546.                                struct drm_display_mode *adjusted_mode)
  547. {
  548.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  549.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  550.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  551.         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  552.         u32 val = I915_READ(reg);
  553.  
  554.         assert_hdmi_port_disabled(intel_hdmi);
  555.  
  556.         /* See the big comment in g4x_set_infoframes() */
  557.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  558.  
  559.         if (!intel_hdmi->has_hdmi_sink) {
  560.                 if (!(val & VIDEO_DIP_ENABLE))
  561.                         return;
  562.                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
  563.                 I915_WRITE(reg, val);
  564.                 POSTING_READ(reg);
  565.                 return;
  566.         }
  567.  
  568.         /* Set both together, unset both together: see the spec. */
  569.         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  570.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  571.                  VIDEO_DIP_ENABLE_GCP);
  572.  
  573.         I915_WRITE(reg, val);
  574.         POSTING_READ(reg);
  575.  
  576.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  577.         intel_hdmi_set_spd_infoframe(encoder);
  578.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  579. }
  580.  
  581. static void vlv_set_infoframes(struct drm_encoder *encoder,
  582.                                struct drm_display_mode *adjusted_mode)
  583. {
  584.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  585.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  586.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  587.         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  588.         u32 val = I915_READ(reg);
  589.  
  590.         assert_hdmi_port_disabled(intel_hdmi);
  591.  
  592.         /* See the big comment in g4x_set_infoframes() */
  593.         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  594.  
  595.         if (!intel_hdmi->has_hdmi_sink) {
  596.                 if (!(val & VIDEO_DIP_ENABLE))
  597.                         return;
  598.                 val &= ~VIDEO_DIP_ENABLE;
  599.                 I915_WRITE(reg, val);
  600.                 POSTING_READ(reg);
  601.                 return;
  602.         }
  603.  
  604.         val |= VIDEO_DIP_ENABLE;
  605.         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  606.                  VIDEO_DIP_ENABLE_GCP);
  607.  
  608.         I915_WRITE(reg, val);
  609.         POSTING_READ(reg);
  610.  
  611.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  612.         intel_hdmi_set_spd_infoframe(encoder);
  613.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  614. }
  615.  
  616. static void hsw_set_infoframes(struct drm_encoder *encoder,
  617.                                struct drm_display_mode *adjusted_mode)
  618. {
  619.         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  620.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  621.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  622.         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
  623.         u32 val = I915_READ(reg);
  624.  
  625.         assert_hdmi_port_disabled(intel_hdmi);
  626.  
  627.         if (!intel_hdmi->has_hdmi_sink) {
  628.                 I915_WRITE(reg, 0);
  629.                 POSTING_READ(reg);
  630.                 return;
  631.         }
  632.  
  633.         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
  634.                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
  635.  
  636.         I915_WRITE(reg, val);
  637.         POSTING_READ(reg);
  638.  
  639.         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  640.         intel_hdmi_set_spd_infoframe(encoder);
  641.         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
  642. }
  643.  
  644. static void intel_hdmi_mode_set(struct intel_encoder *encoder)
  645. {
  646.         struct drm_device *dev = encoder->base.dev;
  647.         struct drm_i915_private *dev_priv = dev->dev_private;
  648.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  649.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  650.         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  651.         u32 hdmi_val;
  652.  
  653.         hdmi_val = SDVO_ENCODING_HDMI;
  654.         if (!HAS_PCH_SPLIT(dev))
  655.                 hdmi_val |= intel_hdmi->color_range;
  656.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  657.                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  658.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  659.                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  660.  
  661.         if (crtc->config.pipe_bpp > 24)
  662.                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  663.         else
  664.                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  665.  
  666.         /* Required on CPT */
  667.         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  668.                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
  669.  
  670.         if (intel_hdmi->has_audio) {
  671.                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  672.                                  pipe_name(crtc->pipe));
  673.                 hdmi_val |= SDVO_AUDIO_ENABLE;
  674.                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
  675.                 intel_write_eld(&encoder->base, adjusted_mode);
  676.         }
  677.  
  678.                 if (HAS_PCH_CPT(dev))
  679.                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
  680.         else
  681.                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
  682.  
  683.         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
  684.         POSTING_READ(intel_hdmi->hdmi_reg);
  685.  
  686.         intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
  687. }
  688.  
  689. static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  690.                                     enum pipe *pipe)
  691. {
  692.         struct drm_device *dev = encoder->base.dev;
  693.         struct drm_i915_private *dev_priv = dev->dev_private;
  694.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  695.         u32 tmp;
  696.  
  697.         tmp = I915_READ(intel_hdmi->hdmi_reg);
  698.  
  699.         if (!(tmp & SDVO_ENABLE))
  700.                 return false;
  701.  
  702.         if (HAS_PCH_CPT(dev))
  703.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  704.         else
  705.                 *pipe = PORT_TO_PIPE(tmp);
  706.  
  707.         return true;
  708. }
  709.  
  710. static void intel_hdmi_get_config(struct intel_encoder *encoder,
  711.                                   struct intel_crtc_config *pipe_config)
  712. {
  713.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  714.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  715.         u32 tmp, flags = 0;
  716.  
  717.         tmp = I915_READ(intel_hdmi->hdmi_reg);
  718.  
  719.         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  720.                 flags |= DRM_MODE_FLAG_PHSYNC;
  721.         else
  722.                 flags |= DRM_MODE_FLAG_NHSYNC;
  723.  
  724.         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  725.                 flags |= DRM_MODE_FLAG_PVSYNC;
  726.         else
  727.                 flags |= DRM_MODE_FLAG_NVSYNC;
  728.  
  729.         pipe_config->adjusted_mode.flags |= flags;
  730. }
  731.  
  732. static void intel_enable_hdmi(struct intel_encoder *encoder)
  733. {
  734.         struct drm_device *dev = encoder->base.dev;
  735.         struct drm_i915_private *dev_priv = dev->dev_private;
  736.         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  737.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  738.         u32 temp;
  739.         u32 enable_bits = SDVO_ENABLE;
  740.  
  741.         if (intel_hdmi->has_audio)
  742.                 enable_bits |= SDVO_AUDIO_ENABLE;
  743.  
  744.         temp = I915_READ(intel_hdmi->hdmi_reg);
  745.  
  746.         /* HW workaround for IBX, we need to move the port to transcoder A
  747.          * before disabling it, so restore the transcoder select bit here. */
  748.         if (HAS_PCH_IBX(dev))
  749.                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
  750.  
  751.         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  752.          * we do this anyway which shows more stable in testing.
  753.          */
  754.         if (HAS_PCH_SPLIT(dev)) {
  755.                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
  756.                 POSTING_READ(intel_hdmi->hdmi_reg);
  757.         }
  758.  
  759.         temp |= enable_bits;
  760.  
  761.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  762.         POSTING_READ(intel_hdmi->hdmi_reg);
  763.  
  764.         /* HW workaround, need to write this twice for issue that may result
  765.          * in first write getting masked.
  766.          */
  767.         if (HAS_PCH_SPLIT(dev)) {
  768.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  769.                 POSTING_READ(intel_hdmi->hdmi_reg);
  770.         }
  771. }
  772.  
  773. static void vlv_enable_hdmi(struct intel_encoder *encoder)
  774. {
  775. }
  776.  
  777. static void intel_disable_hdmi(struct intel_encoder *encoder)
  778. {
  779.         struct drm_device *dev = encoder->base.dev;
  780.         struct drm_i915_private *dev_priv = dev->dev_private;
  781.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  782.         u32 temp;
  783.         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
  784.  
  785.         temp = I915_READ(intel_hdmi->hdmi_reg);
  786.  
  787.         /* HW workaround for IBX, we need to move the port to transcoder A
  788.          * before disabling it. */
  789.         if (HAS_PCH_IBX(dev)) {
  790.                 struct drm_crtc *crtc = encoder->base.crtc;
  791.                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  792.  
  793.                         if (temp & SDVO_PIPE_B_SELECT) {
  794.                                 temp &= ~SDVO_PIPE_B_SELECT;
  795.                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  796.                         POSTING_READ(intel_hdmi->hdmi_reg);
  797.  
  798.                                 /* Again we need to write this twice. */
  799.                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  800.                         POSTING_READ(intel_hdmi->hdmi_reg);
  801.  
  802.                                 /* Transcoder selection bits only update
  803.                                  * effectively on vblank. */
  804.                                 if (crtc)
  805.                                         intel_wait_for_vblank(dev, pipe);
  806.                                 else
  807.                                         msleep(50);
  808.                         }
  809.         }
  810.  
  811.         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  812.          * we do this anyway which shows more stable in testing.
  813.          */
  814.         if (HAS_PCH_SPLIT(dev)) {
  815.                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
  816.                 POSTING_READ(intel_hdmi->hdmi_reg);
  817.         }
  818.  
  819.                 temp &= ~enable_bits;
  820.  
  821.         I915_WRITE(intel_hdmi->hdmi_reg, temp);
  822.         POSTING_READ(intel_hdmi->hdmi_reg);
  823.  
  824.         /* HW workaround, need to write this twice for issue that may result
  825.          * in first write getting masked.
  826.          */
  827.         if (HAS_PCH_SPLIT(dev)) {
  828.                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
  829.                 POSTING_READ(intel_hdmi->hdmi_reg);
  830.         }
  831. }
  832.  
  833. static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
  834. {
  835.         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  836.  
  837.         if (IS_G4X(dev))
  838.                 return 165000;
  839.         else if (IS_HASWELL(dev))
  840.                 return 300000;
  841.         else
  842.                 return 225000;
  843. }
  844.  
  845. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  846.                                  struct drm_display_mode *mode)
  847. {
  848.         if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
  849.                 return MODE_CLOCK_HIGH;
  850.         if (mode->clock < 20000)
  851.                 return MODE_CLOCK_LOW;
  852.  
  853.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  854.                 return MODE_NO_DBLESCAN;
  855.  
  856.         return MODE_OK;
  857. }
  858.  
  859. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  860.                                struct intel_crtc_config *pipe_config)
  861. {
  862.         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  863.         struct drm_device *dev = encoder->base.dev;
  864.         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  865.         int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
  866.         int portclock_limit = hdmi_portclock_limit(intel_hdmi);
  867.         int desired_bpp;
  868.  
  869.         if (intel_hdmi->color_range_auto) {
  870.                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
  871.                 if (intel_hdmi->has_hdmi_sink &&
  872.                     drm_match_cea_mode(adjusted_mode) > 1)
  873.                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
  874.                 else
  875.                         intel_hdmi->color_range = 0;
  876.         }
  877.  
  878.         if (intel_hdmi->color_range)
  879.                 pipe_config->limited_color_range = true;
  880.  
  881.         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
  882.                 pipe_config->has_pch_encoder = true;
  883.  
  884.         /*
  885.          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  886.          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
  887.          * outputs. We also need to check that the higher clock still fits
  888.          * within limits.
  889.          */
  890.         if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
  891.             && HAS_PCH_SPLIT(dev)) {
  892.                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
  893.                 desired_bpp = 12*3;
  894.  
  895.                 /* Need to adjust the port link by 1.5x for 12bpc. */
  896.                 pipe_config->port_clock = clock_12bpc;
  897.         } else {
  898.                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
  899.                 desired_bpp = 8*3;
  900.         }
  901.  
  902.         if (!pipe_config->bw_constrained) {
  903.                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
  904.                 pipe_config->pipe_bpp = desired_bpp;
  905.         }
  906.  
  907.         if (adjusted_mode->clock > portclock_limit) {
  908.                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
  909.                 return false;
  910.         }
  911.  
  912.         return true;
  913. }
  914.  
  915. static enum drm_connector_status
  916. intel_hdmi_detect(struct drm_connector *connector, bool force)
  917. {
  918.         struct drm_device *dev = connector->dev;
  919.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  920.         struct intel_digital_port *intel_dig_port =
  921.                 hdmi_to_dig_port(intel_hdmi);
  922.         struct intel_encoder *intel_encoder = &intel_dig_port->base;
  923.         struct drm_i915_private *dev_priv = dev->dev_private;
  924.         struct edid *edid;
  925.         enum drm_connector_status status = connector_status_disconnected;
  926.  
  927.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  928.                       connector->base.id, drm_get_connector_name(connector));
  929.  
  930.         intel_hdmi->has_hdmi_sink = false;
  931.         intel_hdmi->has_audio = false;
  932.         intel_hdmi->rgb_quant_range_selectable = false;
  933.         edid = drm_get_edid(connector,
  934.                             intel_gmbus_get_adapter(dev_priv,
  935.                                                     intel_hdmi->ddc_bus));
  936.  
  937.         if (edid) {
  938.                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  939.                         status = connector_status_connected;
  940.                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  941.                                 intel_hdmi->has_hdmi_sink =
  942.                                                 drm_detect_hdmi_monitor(edid);
  943.                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  944.                         intel_hdmi->rgb_quant_range_selectable =
  945.                                 drm_rgb_quant_range_selectable(edid);
  946.                 }
  947.                 kfree(edid);
  948.         }
  949.  
  950.         if (status == connector_status_connected) {
  951.                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  952.                         intel_hdmi->has_audio =
  953.                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
  954.                 intel_encoder->type = INTEL_OUTPUT_HDMI;
  955.         }
  956.  
  957.         return status;
  958. }
  959.  
  960. static int intel_hdmi_get_modes(struct drm_connector *connector)
  961. {
  962.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  963.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  964.  
  965.         /* We should parse the EDID data and find out if it's an HDMI sink so
  966.          * we can send audio to it.
  967.          */
  968.  
  969.         return intel_ddc_get_modes(connector,
  970.                                    intel_gmbus_get_adapter(dev_priv,
  971.                                                            intel_hdmi->ddc_bus));
  972. }
  973.  
  974. static bool
  975. intel_hdmi_detect_audio(struct drm_connector *connector)
  976. {
  977.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  978.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  979.         struct edid *edid;
  980.         bool has_audio = false;
  981.  
  982.         edid = drm_get_edid(connector,
  983.                             intel_gmbus_get_adapter(dev_priv,
  984.                                                     intel_hdmi->ddc_bus));
  985.         if (edid) {
  986.                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
  987.                         has_audio = drm_detect_monitor_audio(edid);
  988.                 kfree(edid);
  989.         }
  990.  
  991.         return has_audio;
  992. }
  993.  
  994. static int
  995. intel_hdmi_set_property(struct drm_connector *connector,
  996.                       struct drm_property *property,
  997.                       uint64_t val)
  998. {
  999.         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  1000.         struct intel_digital_port *intel_dig_port =
  1001.                 hdmi_to_dig_port(intel_hdmi);
  1002.         struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1003.         int ret;
  1004.  
  1005.         ret = drm_object_property_set_value(&connector->base, property, val);
  1006.         if (ret)
  1007.                 return ret;
  1008.  
  1009.         if (property == dev_priv->force_audio_property) {
  1010.                 enum hdmi_force_audio i = val;
  1011.                 bool has_audio;
  1012.  
  1013.                 if (i == intel_hdmi->force_audio)
  1014.                         return 0;
  1015.  
  1016.                 intel_hdmi->force_audio = i;
  1017.  
  1018.                 if (i == HDMI_AUDIO_AUTO)
  1019.                         has_audio = intel_hdmi_detect_audio(connector);
  1020.                 else
  1021.                         has_audio = (i == HDMI_AUDIO_ON);
  1022.  
  1023.                 if (i == HDMI_AUDIO_OFF_DVI)
  1024.                         intel_hdmi->has_hdmi_sink = 0;
  1025.  
  1026.                 intel_hdmi->has_audio = has_audio;
  1027.                 goto done;
  1028.         }
  1029.  
  1030.         if (property == dev_priv->broadcast_rgb_property) {
  1031.                 bool old_auto = intel_hdmi->color_range_auto;
  1032.                 uint32_t old_range = intel_hdmi->color_range;
  1033.  
  1034.                 switch (val) {
  1035.                 case INTEL_BROADCAST_RGB_AUTO:
  1036.                         intel_hdmi->color_range_auto = true;
  1037.                         break;
  1038.                 case INTEL_BROADCAST_RGB_FULL:
  1039.                         intel_hdmi->color_range_auto = false;
  1040.                         intel_hdmi->color_range = 0;
  1041.                         break;
  1042.                 case INTEL_BROADCAST_RGB_LIMITED:
  1043.                         intel_hdmi->color_range_auto = false;
  1044.                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
  1045.                         break;
  1046.                 default:
  1047.                         return -EINVAL;
  1048.                 }
  1049.  
  1050.                 if (old_auto == intel_hdmi->color_range_auto &&
  1051.                     old_range == intel_hdmi->color_range)
  1052.                         return 0;
  1053.  
  1054.                 goto done;
  1055.         }
  1056.  
  1057.         return -EINVAL;
  1058.  
  1059. done:
  1060.         if (intel_dig_port->base.base.crtc)
  1061.                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
  1062.  
  1063.         return 0;
  1064. }
  1065.  
  1066. static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
  1067. {
  1068.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1069.         struct drm_device *dev = encoder->base.dev;
  1070.         struct drm_i915_private *dev_priv = dev->dev_private;
  1071.         struct intel_crtc *intel_crtc =
  1072.                 to_intel_crtc(encoder->base.crtc);
  1073.         int port = vlv_dport_to_channel(dport);
  1074.         int pipe = intel_crtc->pipe;
  1075.         u32 val;
  1076.  
  1077.         if (!IS_VALLEYVIEW(dev))
  1078.                 return;
  1079.  
  1080.         /* Enable clock channels for this port */
  1081.         mutex_lock(&dev_priv->dpio_lock);
  1082.         val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
  1083.         val = 0;
  1084.         if (pipe)
  1085.                 val |= (1<<21);
  1086.         else
  1087.                 val &= ~(1<<21);
  1088.         val |= 0x001000c4;
  1089.         vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
  1090.  
  1091.         /* HDMI 1.0V-2dB */
  1092.         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
  1093.         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
  1094.                          0x2b245f5f);
  1095.         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
  1096.                          0x5578b83a);
  1097.         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
  1098.                          0x0c782040);
  1099.         vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
  1100.                          0x2b247878);
  1101.         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
  1102.         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
  1103.                          0x00002000);
  1104.         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
  1105.                          DPIO_TX_OCALINIT_EN);
  1106.  
  1107.         /* Program lane clock */
  1108.         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
  1109.                          0x00760018);
  1110.         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
  1111.                          0x00400888);
  1112.         mutex_unlock(&dev_priv->dpio_lock);
  1113.  
  1114.         intel_enable_hdmi(encoder);
  1115.  
  1116.         vlv_wait_port_ready(dev_priv, port);
  1117. }
  1118.  
  1119. static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
  1120. {
  1121.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1122.         struct drm_device *dev = encoder->base.dev;
  1123.         struct drm_i915_private *dev_priv = dev->dev_private;
  1124.         int port = vlv_dport_to_channel(dport);
  1125.  
  1126.         if (!IS_VALLEYVIEW(dev))
  1127.                 return;
  1128.  
  1129.         /* Program Tx lane resets to default */
  1130.         mutex_lock(&dev_priv->dpio_lock);
  1131.         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
  1132.                          DPIO_PCS_TX_LANE2_RESET |
  1133.                          DPIO_PCS_TX_LANE1_RESET);
  1134.         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
  1135.                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
  1136.                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
  1137.                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
  1138.                          DPIO_PCS_CLK_SOFT_RESET);
  1139.  
  1140.         /* Fix up inter-pair skew failure */
  1141.         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
  1142.         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
  1143.         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
  1144.  
  1145.         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
  1146.                          0x00002000);
  1147.         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
  1148.                          DPIO_TX_OCALINIT_EN);
  1149.         mutex_unlock(&dev_priv->dpio_lock);
  1150. }
  1151.  
  1152. static void intel_hdmi_post_disable(struct intel_encoder *encoder)
  1153. {
  1154.         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1155.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1156.         int port = vlv_dport_to_channel(dport);
  1157.  
  1158.         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
  1159.         mutex_lock(&dev_priv->dpio_lock);
  1160.         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
  1161.         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
  1162.         mutex_unlock(&dev_priv->dpio_lock);
  1163. }
  1164.  
  1165. static void intel_hdmi_destroy(struct drm_connector *connector)
  1166. {
  1167.         drm_sysfs_connector_remove(connector);
  1168.         drm_connector_cleanup(connector);
  1169.         kfree(connector);
  1170. }
  1171.  
  1172. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  1173.         .dpms = intel_connector_dpms,
  1174.         .detect = intel_hdmi_detect,
  1175.         .fill_modes = drm_helper_probe_single_connector_modes,
  1176.         .set_property = intel_hdmi_set_property,
  1177.         .destroy = intel_hdmi_destroy,
  1178. };
  1179.  
  1180. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  1181.         .get_modes = intel_hdmi_get_modes,
  1182.         .mode_valid = intel_hdmi_mode_valid,
  1183.         .best_encoder = intel_best_encoder,
  1184. };
  1185.  
  1186. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  1187.         .destroy = intel_encoder_destroy,
  1188. };
  1189.  
  1190. static void
  1191. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  1192. {
  1193.         intel_attach_force_audio_property(connector);
  1194.         intel_attach_broadcast_rgb_property(connector);
  1195.         intel_hdmi->color_range_auto = true;
  1196. }
  1197.  
  1198. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  1199.                                struct intel_connector *intel_connector)
  1200. {
  1201.         struct drm_connector *connector = &intel_connector->base;
  1202.         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  1203.         struct intel_encoder *intel_encoder = &intel_dig_port->base;
  1204.         struct drm_device *dev = intel_encoder->base.dev;
  1205.         struct drm_i915_private *dev_priv = dev->dev_private;
  1206.         enum port port = intel_dig_port->port;
  1207.  
  1208.         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  1209.                            DRM_MODE_CONNECTOR_HDMIA);
  1210.         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  1211.  
  1212.         connector->interlace_allowed = 1;
  1213.         connector->doublescan_allowed = 0;
  1214.  
  1215.         switch (port) {
  1216.         case PORT_B:
  1217.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  1218.                 intel_encoder->hpd_pin = HPD_PORT_B;
  1219.                 break;
  1220.         case PORT_C:
  1221.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  1222.                 intel_encoder->hpd_pin = HPD_PORT_C;
  1223.                 break;
  1224.         case PORT_D:
  1225.                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  1226.                 intel_encoder->hpd_pin = HPD_PORT_D;
  1227.                 break;
  1228.         case PORT_A:
  1229.                 intel_encoder->hpd_pin = HPD_PORT_A;
  1230.                 /* Internal port only for eDP. */
  1231.         default:
  1232.                 BUG();
  1233.         }
  1234.  
  1235.         if (IS_VALLEYVIEW(dev)) {
  1236.                 intel_hdmi->write_infoframe = vlv_write_infoframe;
  1237.                 intel_hdmi->set_infoframes = vlv_set_infoframes;
  1238.         } else if (!HAS_PCH_SPLIT(dev)) {
  1239.                 intel_hdmi->write_infoframe = g4x_write_infoframe;
  1240.                 intel_hdmi->set_infoframes = g4x_set_infoframes;
  1241.         } else if (HAS_DDI(dev)) {
  1242.                 intel_hdmi->write_infoframe = hsw_write_infoframe;
  1243.                 intel_hdmi->set_infoframes = hsw_set_infoframes;
  1244.         } else if (HAS_PCH_IBX(dev)) {
  1245.                 intel_hdmi->write_infoframe = ibx_write_infoframe;
  1246.                 intel_hdmi->set_infoframes = ibx_set_infoframes;
  1247.         } else {
  1248.                 intel_hdmi->write_infoframe = cpt_write_infoframe;
  1249.                 intel_hdmi->set_infoframes = cpt_set_infoframes;
  1250.         }
  1251.  
  1252.         if (HAS_DDI(dev))
  1253.                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  1254.         else
  1255.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  1256.  
  1257.         intel_hdmi_add_properties(intel_hdmi, connector);
  1258.  
  1259.         intel_connector_attach_encoder(intel_connector, intel_encoder);
  1260.         drm_sysfs_connector_add(connector);
  1261.  
  1262.         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  1263.          * 0xd.  Failure to do so will result in spurious interrupts being
  1264.          * generated on the port when a cable is not attached.
  1265.          */
  1266.         if (IS_G4X(dev) && !IS_GM45(dev)) {
  1267.                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  1268.                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  1269.         }
  1270. }
  1271.  
  1272. void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
  1273. {
  1274.         struct intel_digital_port *intel_dig_port;
  1275.         struct intel_encoder *intel_encoder;
  1276.         struct intel_connector *intel_connector;
  1277.  
  1278.         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
  1279.         if (!intel_dig_port)
  1280.                 return;
  1281.  
  1282.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  1283.         if (!intel_connector) {
  1284.                 kfree(intel_dig_port);
  1285.                 return;
  1286.         }
  1287.  
  1288.         intel_encoder = &intel_dig_port->base;
  1289.  
  1290.         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  1291.                          DRM_MODE_ENCODER_TMDS);
  1292.  
  1293.         intel_encoder->compute_config = intel_hdmi_compute_config;
  1294.         intel_encoder->mode_set = intel_hdmi_mode_set;
  1295.         intel_encoder->disable = intel_disable_hdmi;
  1296.         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
  1297.         intel_encoder->get_config = intel_hdmi_get_config;
  1298.         if (IS_VALLEYVIEW(dev)) {
  1299.                 intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
  1300.                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
  1301.                 intel_encoder->enable = vlv_enable_hdmi;
  1302.                 intel_encoder->post_disable = intel_hdmi_post_disable;
  1303.         } else {
  1304.                 intel_encoder->enable = intel_enable_hdmi;
  1305.         }
  1306.  
  1307.         intel_encoder->type = INTEL_OUTPUT_HDMI;
  1308.         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1309.         intel_encoder->cloneable = false;
  1310.  
  1311.         intel_dig_port->port = port;
  1312.         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
  1313.         intel_dig_port->dp.output_reg = 0;
  1314.  
  1315.         intel_hdmi_init_connector(intel_dig_port, intel_connector);
  1316. }
  1317.