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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Vinit Azad <vinit.azad@intel.com>
  25.  *    Ben Widawsky <ben@bwidawsk.net>
  26.  *    Dave Gordon <david.s.gordon@intel.com>
  27.  *    Alex Dai <yu.dai@intel.com>
  28.  */
  29. #include <linux/firmware.h>
  30. #include "intel_drv.h"
  31. #include "i915_drv.h"
  32. #include "intel_guc.h"
  33.  
  34. /**
  35.  * DOC: GuC
  36.  *
  37.  * intel_guc:
  38.  * Top level structure of guc. It handles firmware loading and manages client
  39.  * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy
  40.  * ExecList submission.
  41.  *
  42.  * Firmware versioning:
  43.  * The firmware build process will generate a version header file with major and
  44.  * minor version defined. The versions are built into CSS header of firmware.
  45.  * i915 kernel driver set the minimal firmware version required per platform.
  46.  * The firmware installation package will install (symbolic link) proper version
  47.  * of firmware.
  48.  *
  49.  * GuC address space:
  50.  * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
  51.  * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is
  52.  * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
  53.  * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.
  54.  *
  55.  * Firmware log:
  56.  * Firmware log is enabled by setting i915.guc_log_level to non-negative level.
  57.  * Log data is printed out via reading debugfs i915_guc_log_dump. Reading from
  58.  * i915_guc_load_status will print out firmware loading status and scratch
  59.  * registers value.
  60.  *
  61.  */
  62.  
  63. #define I915_SKL_GUC_UCODE "i915/skl_guc_ver4.bin"
  64. MODULE_FIRMWARE(I915_SKL_GUC_UCODE);
  65.  
  66. /* User-friendly representation of an enum */
  67. const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status)
  68. {
  69.         switch (status) {
  70.         case GUC_FIRMWARE_FAIL:
  71.                 return "FAIL";
  72.         case GUC_FIRMWARE_NONE:
  73.                 return "NONE";
  74.         case GUC_FIRMWARE_PENDING:
  75.                 return "PENDING";
  76.         case GUC_FIRMWARE_SUCCESS:
  77.                 return "SUCCESS";
  78.         default:
  79.                 return "UNKNOWN!";
  80.         }
  81. };
  82.  
  83. static void direct_interrupts_to_host(struct drm_i915_private *dev_priv)
  84. {
  85.         struct intel_engine_cs *ring;
  86.         int i, irqs;
  87.  
  88.         /* tell all command streamers NOT to forward interrupts and vblank to GuC */
  89.         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
  90.         irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
  91.         for_each_ring(ring, dev_priv, i)
  92.                 I915_WRITE(RING_MODE_GEN7(ring), irqs);
  93.  
  94.         /* route all GT interrupts to the host */
  95.         I915_WRITE(GUC_BCS_RCS_IER, 0);
  96.         I915_WRITE(GUC_VCS2_VCS1_IER, 0);
  97.         I915_WRITE(GUC_WD_VECS_IER, 0);
  98. }
  99.  
  100. static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv)
  101. {
  102.         struct intel_engine_cs *ring;
  103.         int i, irqs;
  104.  
  105.         /* tell all command streamers to forward interrupts and vblank to GuC */
  106.         irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_ALWAYS);
  107.         irqs |= _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
  108.         for_each_ring(ring, dev_priv, i)
  109.                 I915_WRITE(RING_MODE_GEN7(ring), irqs);
  110.  
  111.         /* route USER_INTERRUPT to Host, all others are sent to GuC. */
  112.         irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
  113.                GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
  114.         /* These three registers have the same bit definitions */
  115.         I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
  116.         I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
  117.         I915_WRITE(GUC_WD_VECS_IER, ~irqs);
  118. }
  119.  
  120. static u32 get_gttype(struct drm_i915_private *dev_priv)
  121. {
  122.         /* XXX: GT type based on PCI device ID? field seems unused by fw */
  123.         return 0;
  124. }
  125.  
  126. static u32 get_core_family(struct drm_i915_private *dev_priv)
  127. {
  128.         switch (INTEL_INFO(dev_priv)->gen) {
  129.         case 9:
  130.                 return GFXCORE_FAMILY_GEN9;
  131.  
  132.         default:
  133.                 DRM_ERROR("GUC: unsupported core family\n");
  134.                 return GFXCORE_FAMILY_UNKNOWN;
  135.         }
  136. }
  137.  
  138. static void set_guc_init_params(struct drm_i915_private *dev_priv)
  139. {
  140.         struct intel_guc *guc = &dev_priv->guc;
  141.         u32 params[GUC_CTL_MAX_DWORDS];
  142.         int i;
  143.  
  144.         memset(&params, 0, sizeof(params));
  145.  
  146.         params[GUC_CTL_DEVICE_INFO] |=
  147.                 (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
  148.                 (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
  149.  
  150.         /*
  151.          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
  152.          * second. This ARAR is calculated by:
  153.          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
  154.          */
  155.         params[GUC_CTL_ARAT_HIGH] = 0;
  156.         params[GUC_CTL_ARAT_LOW] = 100000000;
  157.  
  158.         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
  159.  
  160.         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
  161.                         GUC_CTL_VCS2_ENABLED;
  162.  
  163.         if (i915.guc_log_level >= 0) {
  164.                 params[GUC_CTL_LOG_PARAMS] = guc->log_flags;
  165.                 params[GUC_CTL_DEBUG] =
  166.                         i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
  167.         }
  168.  
  169.         /* If GuC submission is enabled, set up additional parameters here */
  170.         if (i915.enable_guc_submission) {
  171.                 u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj);
  172.                 u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16;
  173.  
  174.                 pgs >>= PAGE_SHIFT;
  175.                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
  176.                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
  177.  
  178.                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
  179.  
  180.                 /* Unmask this bit to enable the GuC's internal scheduler */
  181.                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
  182.         }
  183.  
  184.         I915_WRITE(SOFT_SCRATCH(0), 0);
  185.  
  186.         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
  187.                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
  188. }
  189.  
  190. /*
  191.  * Read the GuC status register (GUC_STATUS) and store it in the
  192.  * specified location; then return a boolean indicating whether
  193.  * the value matches either of two values representing completion
  194.  * of the GuC boot process.
  195.  *
  196.  * This is used for polling the GuC status in a wait_for_atomic()
  197.  * loop below.
  198.  */
  199. static inline bool guc_ucode_response(struct drm_i915_private *dev_priv,
  200.                                       u32 *status)
  201. {
  202.         u32 val = I915_READ(GUC_STATUS);
  203.         u32 uk_val = val & GS_UKERNEL_MASK;
  204.         *status = val;
  205.         return (uk_val == GS_UKERNEL_READY ||
  206.                 ((val & GS_MIA_CORE_STATE) && uk_val == GS_UKERNEL_LAPIC_DONE));
  207. }
  208.  
  209. /*
  210.  * Transfer the firmware image to RAM for execution by the microcontroller.
  211.  *
  212.  * GuC Firmware layout:
  213.  * +-------------------------------+  ----
  214.  * |          CSS header           |  128B
  215.  * | contains major/minor version  |
  216.  * +-------------------------------+  ----
  217.  * |             uCode             |
  218.  * +-------------------------------+  ----
  219.  * |         RSA signature         |  256B
  220.  * +-------------------------------+  ----
  221.  *
  222.  * Architecturally, the DMA engine is bidirectional, and can potentially even
  223.  * transfer between GTT locations. This functionality is left out of the API
  224.  * for now as there is no need for it.
  225.  *
  226.  * Note that GuC needs the CSS header plus uKernel code to be copied by the
  227.  * DMA engine in one operation, whereas the RSA signature is loaded via MMIO.
  228.  */
  229.  
  230. #define UOS_CSS_HEADER_OFFSET           0
  231. #define UOS_VER_MINOR_OFFSET            0x44
  232. #define UOS_VER_MAJOR_OFFSET            0x46
  233. #define UOS_CSS_HEADER_SIZE             0x80
  234. #define UOS_RSA_SIG_SIZE                0x100
  235.  
  236. static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
  237. {
  238.         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
  239.         struct drm_i915_gem_object *fw_obj = guc_fw->guc_fw_obj;
  240.         unsigned long offset;
  241.         struct sg_table *sg = fw_obj->pages;
  242.         u32 status, ucode_size, rsa[UOS_RSA_SIG_SIZE / sizeof(u32)];
  243.         int i, ret = 0;
  244.  
  245.         /* uCode size, also is where RSA signature starts */
  246.         offset = ucode_size = guc_fw->guc_fw_size - UOS_RSA_SIG_SIZE;
  247.         I915_WRITE(DMA_COPY_SIZE, ucode_size);
  248.  
  249.         /* Copy RSA signature from the fw image to HW for verification */
  250.         sg_pcopy_to_buffer(sg->sgl, sg->nents, rsa, UOS_RSA_SIG_SIZE, offset);
  251.         for (i = 0; i < UOS_RSA_SIG_SIZE / sizeof(u32); i++)
  252.                 I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
  253.  
  254.         /* Set the source address for the new blob */
  255.         offset = i915_gem_obj_ggtt_offset(fw_obj);
  256.         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
  257.         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
  258.  
  259.         /*
  260.          * Set the DMA destination. Current uCode expects the code to be
  261.          * loaded at 8k; locations below this are used for the stack.
  262.          */
  263.         I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
  264.         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
  265.  
  266.         /* Finally start the DMA */
  267.         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
  268.  
  269.         /*
  270.          * Spin-wait for the DMA to complete & the GuC to start up.
  271.          * NB: Docs recommend not using the interrupt for completion.
  272.          * Measurements indicate this should take no more than 20ms, so a
  273.          * timeout here indicates that the GuC has failed and is unusable.
  274.          * (Higher levels of the driver will attempt to fall back to
  275.          * execlist mode if this happens.)
  276.          */
  277.         ret = wait_for_atomic(guc_ucode_response(dev_priv, &status), 100);
  278.  
  279.         DRM_DEBUG_DRIVER("DMA status 0x%x, GuC status 0x%x\n",
  280.                         I915_READ(DMA_CTRL), status);
  281.  
  282.         if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
  283.                 DRM_ERROR("GuC firmware signature verification failed\n");
  284.                 ret = -ENOEXEC;
  285.         }
  286.  
  287.         DRM_DEBUG_DRIVER("returning %d\n", ret);
  288.  
  289.         return ret;
  290. }
  291.  
  292. /*
  293.  * Load the GuC firmware blob into the MinuteIA.
  294.  */
  295. static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
  296. {
  297.         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
  298.         struct drm_device *dev = dev_priv->dev;
  299.         int ret;
  300.  
  301.         ret = i915_gem_object_set_to_gtt_domain(guc_fw->guc_fw_obj, false);
  302.         if (ret) {
  303.                 DRM_DEBUG_DRIVER("set-domain failed %d\n", ret);
  304.                 return ret;
  305.         }
  306.  
  307.         ret = i915_gem_obj_ggtt_pin(guc_fw->guc_fw_obj, 0, 0);
  308.         if (ret) {
  309.                 DRM_DEBUG_DRIVER("pin failed %d\n", ret);
  310.                 return ret;
  311.         }
  312.  
  313.         /* Invalidate GuC TLB to let GuC take the latest updates to GTT. */
  314.         I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
  315.  
  316.         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  317.  
  318.         /* init WOPCM */
  319.         I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
  320.         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
  321.  
  322.         /* Enable MIA caching. GuC clock gating is disabled. */
  323.         I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
  324.  
  325.         /* WaDisableMinuteIaClockGating:skl,bxt */
  326.         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
  327.             (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) {
  328.                 I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
  329.                                               ~GUC_ENABLE_MIA_CLOCK_GATING));
  330.         }
  331.  
  332.         /* WaC6DisallowByGfxPause*/
  333.         I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
  334.  
  335.         if (IS_BROXTON(dev))
  336.                 I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
  337.         else
  338.                 I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
  339.  
  340.         if (IS_GEN9(dev)) {
  341.                 /* DOP Clock Gating Enable for GuC clocks */
  342.                 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
  343.                                             I915_READ(GEN7_MISCCPCTL)));
  344.  
  345.                 /* allows for 5us before GT can go to RC6 */
  346.                 I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
  347.         }
  348.  
  349.         set_guc_init_params(dev_priv);
  350.  
  351.         ret = guc_ucode_xfer_dma(dev_priv);
  352.  
  353.         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  354.  
  355.         /*
  356.          * We keep the object pages for reuse during resume. But we can unpin it
  357.          * now that DMA has completed, so it doesn't continue to take up space.
  358.          */
  359.         i915_gem_object_ggtt_unpin(guc_fw->guc_fw_obj);
  360.  
  361.         return ret;
  362. }
  363.  
  364. /**
  365.  * intel_guc_ucode_load() - load GuC uCode into the device
  366.  * @dev:        drm device
  367.  *
  368.  * Called from gem_init_hw() during driver loading and also after a GPU reset.
  369.  *
  370.  * The firmware image should have already been fetched into memory by the
  371.  * earlier call to intel_guc_ucode_init(), so here we need only check that
  372.  * is succeeded, and then transfer the image to the h/w.
  373.  *
  374.  * Return:      non-zero code on error
  375.  */
  376. int intel_guc_ucode_load(struct drm_device *dev)
  377. {
  378.         struct drm_i915_private *dev_priv = dev->dev_private;
  379.         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
  380.         int err = 0;
  381.  
  382.         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
  383.                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
  384.                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
  385.  
  386.         direct_interrupts_to_host(dev_priv);
  387.  
  388.         if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_NONE)
  389.                 return 0;
  390.  
  391.         if (guc_fw->guc_fw_fetch_status == GUC_FIRMWARE_SUCCESS &&
  392.             guc_fw->guc_fw_load_status == GUC_FIRMWARE_FAIL)
  393.                 return -ENOEXEC;
  394.  
  395.         guc_fw->guc_fw_load_status = GUC_FIRMWARE_PENDING;
  396.  
  397.         DRM_DEBUG_DRIVER("GuC fw fetch status %s\n",
  398.                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
  399.  
  400.         switch (guc_fw->guc_fw_fetch_status) {
  401.         case GUC_FIRMWARE_FAIL:
  402.                 /* something went wrong :( */
  403.                 err = -EIO;
  404.                 goto fail;
  405.  
  406.         case GUC_FIRMWARE_NONE:
  407.         case GUC_FIRMWARE_PENDING:
  408.         default:
  409.                 /* "can't happen" */
  410.                 WARN_ONCE(1, "GuC fw %s invalid guc_fw_fetch_status %s [%d]\n",
  411.                         guc_fw->guc_fw_path,
  412.                         intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
  413.                         guc_fw->guc_fw_fetch_status);
  414.                 err = -ENXIO;
  415.                 goto fail;
  416.  
  417.         case GUC_FIRMWARE_SUCCESS:
  418.                 break;
  419.         }
  420.  
  421.         err = i915_guc_submission_init(dev);
  422.         if (err)
  423.                 goto fail;
  424.  
  425.         err = guc_ucode_xfer(dev_priv);
  426.         if (err)
  427.                 goto fail;
  428.  
  429.         guc_fw->guc_fw_load_status = GUC_FIRMWARE_SUCCESS;
  430.  
  431.         DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
  432.                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status),
  433.                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
  434.  
  435.         if (i915.enable_guc_submission) {
  436.                 /* The execbuf_client will be recreated. Release it first. */
  437.                 i915_guc_submission_disable(dev);
  438.  
  439.                 err = i915_guc_submission_enable(dev);
  440.                 if (err)
  441.                         goto fail;
  442.                 direct_interrupts_to_guc(dev_priv);
  443.         }
  444.  
  445.         return 0;
  446.  
  447. fail:
  448.         if (guc_fw->guc_fw_load_status == GUC_FIRMWARE_PENDING)
  449.                 guc_fw->guc_fw_load_status = GUC_FIRMWARE_FAIL;
  450.  
  451.         direct_interrupts_to_host(dev_priv);
  452.         i915_guc_submission_disable(dev);
  453.  
  454.         return err;
  455. }
  456.  
  457. static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
  458. {
  459.         struct drm_i915_gem_object *obj;
  460.         const struct firmware *fw;
  461.         const u8 *css_header;
  462.         const size_t minsize = UOS_CSS_HEADER_SIZE + UOS_RSA_SIG_SIZE;
  463.         const size_t maxsize = GUC_WOPCM_SIZE_VALUE + UOS_RSA_SIG_SIZE
  464.                         - 0x8000; /* 32k reserved (8K stack + 24k context) */
  465.         int err;
  466.  
  467.         DRM_DEBUG_DRIVER("before requesting firmware: GuC fw fetch status %s\n",
  468.                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
  469.  
  470.         err = request_firmware(&fw, guc_fw->guc_fw_path, &dev->pdev->dev);
  471.         if (err)
  472.                 goto fail;
  473.         if (!fw)
  474.                 goto fail;
  475.  
  476.         DRM_DEBUG_DRIVER("fetch GuC fw from %s succeeded, fw %p\n",
  477.                 guc_fw->guc_fw_path, fw);
  478.         DRM_DEBUG_DRIVER("firmware file size %zu (minimum %zu, maximum %zu)\n",
  479.                 fw->size, minsize, maxsize);
  480.  
  481.         /* Check the size of the blob befoe examining buffer contents */
  482.         if (fw->size < minsize || fw->size > maxsize)
  483.                 goto fail;
  484.  
  485.         /*
  486.          * The GuC firmware image has the version number embedded at a well-known
  487.          * offset within the firmware blob; note that major / minor version are
  488.          * TWO bytes each (i.e. u16), although all pointers and offsets are defined
  489.          * in terms of bytes (u8).
  490.          */
  491.         css_header = fw->data + UOS_CSS_HEADER_OFFSET;
  492.         guc_fw->guc_fw_major_found = *(u16 *)(css_header + UOS_VER_MAJOR_OFFSET);
  493.         guc_fw->guc_fw_minor_found = *(u16 *)(css_header + UOS_VER_MINOR_OFFSET);
  494.  
  495.         if (guc_fw->guc_fw_major_found != guc_fw->guc_fw_major_wanted ||
  496.             guc_fw->guc_fw_minor_found < guc_fw->guc_fw_minor_wanted) {
  497.                 DRM_ERROR("GuC firmware version %d.%d, required %d.%d\n",
  498.                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
  499.                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
  500.                 err = -ENOEXEC;
  501.                 goto fail;
  502.         }
  503.  
  504.         DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n",
  505.                         guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found,
  506.                         guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
  507.  
  508.         mutex_lock(&dev->struct_mutex);
  509.         obj = i915_gem_object_create_from_data(dev, fw->data, fw->size);
  510.         mutex_unlock(&dev->struct_mutex);
  511.         if (IS_ERR_OR_NULL(obj)) {
  512.                 err = obj ? PTR_ERR(obj) : -ENOMEM;
  513.                 goto fail;
  514.         }
  515.  
  516.         guc_fw->guc_fw_obj = obj;
  517.         guc_fw->guc_fw_size = fw->size;
  518.  
  519.         DRM_DEBUG_DRIVER("GuC fw fetch status SUCCESS, obj %p\n",
  520.                         guc_fw->guc_fw_obj);
  521.  
  522.         release_firmware(fw);
  523.         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_SUCCESS;
  524.         return;
  525.  
  526. fail:
  527.         DRM_DEBUG_DRIVER("GuC fw fetch status FAIL; err %d, fw %p, obj %p\n",
  528.                 err, fw, guc_fw->guc_fw_obj);
  529.         DRM_ERROR("Failed to fetch GuC firmware from %s (error %d)\n",
  530.                   guc_fw->guc_fw_path, err);
  531.  
  532.         obj = guc_fw->guc_fw_obj;
  533.         if (obj)
  534.                 drm_gem_object_unreference(&obj->base);
  535.         guc_fw->guc_fw_obj = NULL;
  536.  
  537.         release_firmware(fw);           /* OK even if fw is NULL */
  538.         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
  539. }
  540.  
  541. /**
  542.  * intel_guc_ucode_init() - define parameters and fetch firmware
  543.  * @dev:        drm device
  544.  *
  545.  * Called early during driver load, but after GEM is initialised.
  546.  *
  547.  * The firmware will be transferred to the GuC's memory later,
  548.  * when intel_guc_ucode_load() is called.
  549.  */
  550. void intel_guc_ucode_init(struct drm_device *dev)
  551. {
  552.         struct drm_i915_private *dev_priv = dev->dev_private;
  553.         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
  554.         const char *fw_path;
  555.  
  556.         if (!HAS_GUC_SCHED(dev))
  557.                 i915.enable_guc_submission = false;
  558.  
  559.         if (!HAS_GUC_UCODE(dev)) {
  560.                 fw_path = NULL;
  561.         } else if (IS_SKYLAKE(dev)) {
  562.                 fw_path = I915_SKL_GUC_UCODE;
  563.                 guc_fw->guc_fw_major_wanted = 4;
  564.                 guc_fw->guc_fw_minor_wanted = 3;
  565.         } else {
  566.                 i915.enable_guc_submission = false;
  567.                 fw_path = "";   /* unknown device */
  568.         }
  569.  
  570.         guc_fw->guc_dev = dev;
  571.         guc_fw->guc_fw_path = fw_path;
  572.         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
  573.         guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE;
  574.  
  575.         if (fw_path == NULL)
  576.                 return;
  577.  
  578.         if (*fw_path == '\0') {
  579.                 DRM_ERROR("No GuC firmware known for this platform\n");
  580.                 guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_FAIL;
  581.                 return;
  582.         }
  583.  
  584.         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_PENDING;
  585.         DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
  586.         guc_fw_fetch(dev, guc_fw);
  587.         /* status must now be FAIL or SUCCESS */
  588. }
  589.  
  590. /**
  591.  * intel_guc_ucode_fini() - clean up all allocated resources
  592.  * @dev:        drm device
  593.  */
  594. void intel_guc_ucode_fini(struct drm_device *dev)
  595. {
  596.         struct drm_i915_private *dev_priv = dev->dev_private;
  597.         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
  598.  
  599.         direct_interrupts_to_host(dev_priv);
  600.         i915_guc_submission_fini(dev);
  601.  
  602.         mutex_lock(&dev->struct_mutex);
  603.         if (guc_fw->guc_fw_obj)
  604.                 drm_gem_object_unreference(&guc_fw->guc_fw_obj->base);
  605.         guc_fw->guc_fw_obj = NULL;
  606.         mutex_unlock(&dev->struct_mutex);
  607.  
  608.         guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE;
  609. }
  610.