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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/async.h>
  29. #include <linux/i2c.h>
  30. #include <linux/hdmi.h>
  31. #include <drm/i915_drm.h>
  32. #include "i915_drv.h"
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_crtc_helper.h>
  35. #include <drm/drm_fb_helper.h>
  36. #include <drm/drm_dp_dual_mode_helper.h>
  37. #include <drm/drm_dp_mst_helper.h>
  38. #include <drm/drm_rect.h>
  39. #include <drm/drm_atomic.h>
  40.  
  41. /**
  42.  * _wait_for - magic (register) wait macro
  43.  *
  44.  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45.  * contexts. Note that it's important that we check the condition again after
  46.  * having timed out, since the timeout could be due to preemption or similar and
  47.  * we've never had a chance to check the condition before the timeout.
  48.  */
  49. #define _wait_for(COND, MS, W) ({ \
  50.         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  51.         int ret__ = 0;                                                  \
  52.         while (!(COND)) {                                               \
  53.                 if (time_after(jiffies, timeout__)) {                   \
  54.                         if (!(COND))                                    \
  55.                                 ret__ = -ETIMEDOUT;                     \
  56.                         break;                                          \
  57.                 }                                                       \
  58.                 if (W )  {                              \
  59.          msleep(W); \
  60.                 } else {                                                \
  61.                         cpu_relax();                                    \
  62.                 }                                                       \
  63.         }                                                               \
  64.         ret__;                                                          \
  65. })
  66.  
  67. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  68. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  69. #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  70.                                                DIV_ROUND_UP((US), 1000), 0)
  71.  
  72. #define KHz(x) (1000 * (x))
  73. #define MHz(x) KHz(1000 * (x))
  74.  
  75. /*
  76.  * Display related stuff
  77.  */
  78.  
  79. /* store information about an Ixxx DVO */
  80. /* The i830->i865 use multiple DVOs with multiple i2cs */
  81. /* the i915, i945 have a single sDVO i2c bus - which is different */
  82. #define MAX_OUTPUTS 6
  83. /* maximum connectors per crtcs in the mode set */
  84.  
  85. /* Maximum cursor sizes */
  86. #define GEN2_CURSOR_WIDTH 64
  87. #define GEN2_CURSOR_HEIGHT 64
  88. #define MAX_CURSOR_WIDTH 256
  89. #define MAX_CURSOR_HEIGHT 256
  90.  
  91. #define INTEL_I2C_BUS_DVO 1
  92. #define INTEL_I2C_BUS_SDVO 2
  93.  
  94. /* these are outputs from the chip - integrated only
  95.    external chips are via DVO or SDVO output */
  96. enum intel_output_type {
  97.         INTEL_OUTPUT_UNUSED = 0,
  98.         INTEL_OUTPUT_ANALOG = 1,
  99.         INTEL_OUTPUT_DVO = 2,
  100.         INTEL_OUTPUT_SDVO = 3,
  101.         INTEL_OUTPUT_LVDS = 4,
  102.         INTEL_OUTPUT_TVOUT = 5,
  103.         INTEL_OUTPUT_HDMI = 6,
  104.         INTEL_OUTPUT_DISPLAYPORT = 7,
  105.         INTEL_OUTPUT_EDP = 8,
  106.         INTEL_OUTPUT_DSI = 9,
  107.         INTEL_OUTPUT_UNKNOWN = 10,
  108.         INTEL_OUTPUT_DP_MST = 11,
  109. };
  110.  
  111. #define INTEL_DVO_CHIP_NONE 0
  112. #define INTEL_DVO_CHIP_LVDS 1
  113. #define INTEL_DVO_CHIP_TMDS 2
  114. #define INTEL_DVO_CHIP_TVOUT 4
  115.  
  116. #define INTEL_DSI_VIDEO_MODE    0
  117. #define INTEL_DSI_COMMAND_MODE  1
  118.  
  119. struct intel_framebuffer {
  120.         struct drm_framebuffer base;
  121.         struct drm_i915_gem_object *obj;
  122.         void   *private; /*Kolibri */
  123. };
  124.  
  125. struct intel_fbdev {
  126.         struct drm_fb_helper helper;
  127.         struct intel_framebuffer *fb;
  128.         int preferred_bpp;
  129. };
  130.  
  131. struct intel_encoder {
  132.         struct drm_encoder base;
  133.  
  134.         enum intel_output_type type;
  135.         unsigned int cloneable;
  136.         void (*hot_plug)(struct intel_encoder *);
  137.         bool (*compute_config)(struct intel_encoder *,
  138.                                struct intel_crtc_state *);
  139.         void (*pre_pll_enable)(struct intel_encoder *);
  140.         void (*pre_enable)(struct intel_encoder *);
  141.         void (*enable)(struct intel_encoder *);
  142.         void (*mode_set)(struct intel_encoder *intel_encoder);
  143.         void (*disable)(struct intel_encoder *);
  144.         void (*post_disable)(struct intel_encoder *);
  145.         void (*post_pll_disable)(struct intel_encoder *);
  146.         /* Read out the current hw state of this connector, returning true if
  147.          * the encoder is active. If the encoder is enabled it also set the pipe
  148.          * it is connected to in the pipe parameter. */
  149.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  150.         /* Reconstructs the equivalent mode flags for the current hardware
  151.          * state. This must be called _after_ display->get_pipe_config has
  152.          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
  153.          * be set correctly before calling this function. */
  154.         void (*get_config)(struct intel_encoder *,
  155.                            struct intel_crtc_state *pipe_config);
  156.         /*
  157.          * Called during system suspend after all pending requests for the
  158.          * encoder are flushed (for example for DP AUX transactions) and
  159.          * device interrupts are disabled.
  160.          */
  161.         void (*suspend)(struct intel_encoder *);
  162.         int crtc_mask;
  163.         enum hpd_pin hpd_pin;
  164. };
  165.  
  166. struct intel_panel {
  167.         struct drm_display_mode *fixed_mode;
  168.         struct drm_display_mode *downclock_mode;
  169.         int fitting_mode;
  170.  
  171.         /* backlight */
  172.         struct {
  173.                 bool present;
  174.                 u32 level;
  175.                 u32 min;
  176.                 u32 max;
  177.                 bool enabled;
  178.                 bool combination_mode;  /* gen 2/4 only */
  179.                 bool active_low_pwm;
  180.  
  181.                 /* PWM chip */
  182.                 bool util_pin_active_low;       /* bxt+ */
  183.                 u8 controller;          /* bxt+ only */
  184.                 struct pwm_device *pwm;
  185.  
  186.                 struct backlight_device *device;
  187.  
  188.                 /* Connector and platform specific backlight functions */
  189.                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
  190.                 uint32_t (*get)(struct intel_connector *connector);
  191.                 void (*set)(struct intel_connector *connector, uint32_t level);
  192.                 void (*disable)(struct intel_connector *connector);
  193.                 void (*enable)(struct intel_connector *connector);
  194.                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
  195.                                       uint32_t hz);
  196.                 void (*power)(struct intel_connector *, bool enable);
  197.         } backlight;
  198. };
  199.  
  200. struct intel_connector {
  201.         struct drm_connector base;
  202.         /*
  203.          * The fixed encoder this connector is connected to.
  204.          */
  205.         struct intel_encoder *encoder;
  206.  
  207.         /* Reads out the current hw, returning true if the connector is enabled
  208.          * and active (i.e. dpms ON state). */
  209.         bool (*get_hw_state)(struct intel_connector *);
  210.  
  211.         /*
  212.          * Removes all interfaces through which the connector is accessible
  213.          * - like sysfs, debugfs entries -, so that no new operations can be
  214.          * started on the connector. Also makes sure all currently pending
  215.          * operations finish before returing.
  216.          */
  217.         void (*unregister)(struct intel_connector *);
  218.  
  219.         /* Panel info for eDP and LVDS */
  220.         struct intel_panel panel;
  221.  
  222.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  223.         struct edid *edid;
  224.         struct edid *detect_edid;
  225.  
  226.         /* since POLL and HPD connectors may use the same HPD line keep the native
  227.            state of connector->polled in case hotplug storm detection changes it */
  228.         u8 polled;
  229.  
  230.         void *port; /* store this opaque as its illegal to dereference it */
  231.  
  232.         struct intel_dp *mst_port;
  233. };
  234.  
  235. typedef struct dpll {
  236.         /* given values */
  237.         int n;
  238.         int m1, m2;
  239.         int p1, p2;
  240.         /* derived values */
  241.         int     dot;
  242.         int     vco;
  243.         int     m;
  244.         int     p;
  245. } intel_clock_t;
  246.  
  247. struct intel_atomic_state {
  248.         struct drm_atomic_state base;
  249.  
  250.         unsigned int cdclk;
  251.  
  252.         /*
  253.          * Calculated device cdclk, can be different from cdclk
  254.          * only when all crtc's are DPMS off.
  255.          */
  256.         unsigned int dev_cdclk;
  257.  
  258.         bool dpll_set, modeset;
  259.  
  260.         unsigned int active_crtcs;
  261.         unsigned int min_pixclk[I915_MAX_PIPES];
  262.  
  263.         struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
  264.         struct intel_wm_config wm_config;
  265. };
  266.  
  267. struct intel_plane_state {
  268.         struct drm_plane_state base;
  269.         struct drm_rect src;
  270.         struct drm_rect dst;
  271.         struct drm_rect clip;
  272.         bool visible;
  273.  
  274.         /*
  275.          * scaler_id
  276.          *    = -1 : not using a scaler
  277.          *    >=  0 : using a scalers
  278.          *
  279.          * plane requiring a scaler:
  280.          *   - During check_plane, its bit is set in
  281.          *     crtc_state->scaler_state.scaler_users by calling helper function
  282.          *     update_scaler_plane.
  283.          *   - scaler_id indicates the scaler it got assigned.
  284.          *
  285.          * plane doesn't require a scaler:
  286.          *   - this can happen when scaling is no more required or plane simply
  287.          *     got disabled.
  288.          *   - During check_plane, corresponding bit is reset in
  289.          *     crtc_state->scaler_state.scaler_users by calling helper function
  290.          *     update_scaler_plane.
  291.          */
  292.         int scaler_id;
  293.  
  294.         struct drm_intel_sprite_colorkey ckey;
  295.  
  296.         /* async flip related structures */
  297.         struct drm_i915_gem_request *wait_req;
  298. };
  299.  
  300. struct intel_initial_plane_config {
  301.         struct intel_framebuffer *fb;
  302.         unsigned int tiling;
  303.         int size;
  304.         u32 base;
  305. };
  306.  
  307. #define SKL_MIN_SRC_W 8
  308. #define SKL_MAX_SRC_W 4096
  309. #define SKL_MIN_SRC_H 8
  310. #define SKL_MAX_SRC_H 4096
  311. #define SKL_MIN_DST_W 8
  312. #define SKL_MAX_DST_W 4096
  313. #define SKL_MIN_DST_H 8
  314. #define SKL_MAX_DST_H 4096
  315.  
  316. struct intel_scaler {
  317.         int in_use;
  318.         uint32_t mode;
  319. };
  320.  
  321. struct intel_crtc_scaler_state {
  322. #define SKL_NUM_SCALERS 2
  323.         struct intel_scaler scalers[SKL_NUM_SCALERS];
  324.  
  325.         /*
  326.          * scaler_users: keeps track of users requesting scalers on this crtc.
  327.          *
  328.          *     If a bit is set, a user is using a scaler.
  329.          *     Here user can be a plane or crtc as defined below:
  330.          *       bits 0-30 - plane (bit position is index from drm_plane_index)
  331.          *       bit 31    - crtc
  332.          *
  333.          * Instead of creating a new index to cover planes and crtc, using
  334.          * existing drm_plane_index for planes which is well less than 31
  335.          * planes and bit 31 for crtc. This should be fine to cover all
  336.          * our platforms.
  337.          *
  338.          * intel_atomic_setup_scalers will setup available scalers to users
  339.          * requesting scalers. It will gracefully fail if request exceeds
  340.          * avilability.
  341.          */
  342. #define SKL_CRTC_INDEX 31
  343.         unsigned scaler_users;
  344.  
  345.         /* scaler used by crtc for panel fitting purpose */
  346.         int scaler_id;
  347. };
  348.  
  349. /* drm_mode->private_flags */
  350. #define I915_MODE_FLAG_INHERITED 1
  351.  
  352. struct intel_pipe_wm {
  353.         struct intel_wm_level wm[5];
  354.         uint32_t linetime;
  355.         bool fbc_wm_enabled;
  356.         bool pipe_enabled;
  357.         bool sprites_enabled;
  358.         bool sprites_scaled;
  359. };
  360.  
  361. struct skl_pipe_wm {
  362.         struct skl_wm_level wm[8];
  363.         struct skl_wm_level trans_wm;
  364.         uint32_t linetime;
  365. };
  366.  
  367. struct intel_crtc_state {
  368.         struct drm_crtc_state base;
  369.  
  370.         /**
  371.          * quirks - bitfield with hw state readout quirks
  372.          *
  373.          * For various reasons the hw state readout code might not be able to
  374.          * completely faithfully read out the current state. These cases are
  375.          * tracked with quirk flags so that fastboot and state checker can act
  376.          * accordingly.
  377.          */
  378. #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
  379.         unsigned long quirks;
  380.  
  381.         bool update_pipe; /* can a fast modeset be performed? */
  382.         bool disable_cxsr;
  383.         bool update_wm_pre, update_wm_post; /* watermarks are updated */
  384.         bool fb_changed; /* fb on any of the planes is changed */
  385.  
  386.         /* Pipe source size (ie. panel fitter input size)
  387.          * All planes will be positioned inside this space,
  388.          * and get clipped at the edges. */
  389.         int pipe_src_w, pipe_src_h;
  390.  
  391.         /* Whether to set up the PCH/FDI. Note that we never allow sharing
  392.          * between pch encoders and cpu encoders. */
  393.         bool has_pch_encoder;
  394.  
  395.         /* Are we sending infoframes on the attached port */
  396.         bool has_infoframe;
  397.  
  398.         /* CPU Transcoder for the pipe. Currently this can only differ from the
  399.          * pipe on Haswell (where we have a special eDP transcoder). */
  400.         enum transcoder cpu_transcoder;
  401.  
  402.         /*
  403.          * Use reduced/limited/broadcast rbg range, compressing from the full
  404.          * range fed into the crtcs.
  405.          */
  406.         bool limited_color_range;
  407.  
  408.         /* DP has a bunch of special case unfortunately, so mark the pipe
  409.          * accordingly. */
  410.         bool has_dp_encoder;
  411.  
  412.         /* DSI has special cases */
  413.         bool has_dsi_encoder;
  414.  
  415.         /* Whether we should send NULL infoframes. Required for audio. */
  416.         bool has_hdmi_sink;
  417.  
  418.         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
  419.          * has_dp_encoder is set. */
  420.         bool has_audio;
  421.  
  422.         /*
  423.          * Enable dithering, used when the selected pipe bpp doesn't match the
  424.          * plane bpp.
  425.          */
  426.         bool dither;
  427.  
  428.         /* Controls for the clock computation, to override various stages. */
  429.         bool clock_set;
  430.  
  431.         /* SDVO TV has a bunch of special case. To make multifunction encoders
  432.          * work correctly, we need to track this at runtime.*/
  433.         bool sdvo_tv_clock;
  434.  
  435.         /*
  436.          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
  437.          * required. This is set in the 2nd loop of calling encoder's
  438.          * ->compute_config if the first pick doesn't work out.
  439.          */
  440.         bool bw_constrained;
  441.  
  442.         /* Settings for the intel dpll used on pretty much everything but
  443.          * haswell. */
  444.         struct dpll dpll;
  445.  
  446.         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
  447.         enum intel_dpll_id shared_dpll;
  448.  
  449.         /*
  450.          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
  451.          * - enum skl_dpll on SKL
  452.          */
  453.         uint32_t ddi_pll_sel;
  454.  
  455.         /* Actual register state of the dpll, for shared dpll cross-checking. */
  456.         struct intel_dpll_hw_state dpll_hw_state;
  457.  
  458.         int pipe_bpp;
  459.         struct intel_link_m_n dp_m_n;
  460.  
  461.         /* m2_n2 for eDP downclock */
  462.         struct intel_link_m_n dp_m2_n2;
  463.         bool has_drrs;
  464.  
  465.         /*
  466.          * Frequence the dpll for the port should run at. Differs from the
  467.          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
  468.          * already multiplied by pixel_multiplier.
  469.          */
  470.         int port_clock;
  471.  
  472.         /* Used by SDVO (and if we ever fix it, HDMI). */
  473.         unsigned pixel_multiplier;
  474.  
  475.         uint8_t lane_count;
  476.  
  477.         /* Panel fitter controls for gen2-gen4 + VLV */
  478.         struct {
  479.                 u32 control;
  480.                 u32 pgm_ratios;
  481.                 u32 lvds_border_bits;
  482.         } gmch_pfit;
  483.  
  484.         /* Panel fitter placement and size for Ironlake+ */
  485.         struct {
  486.                 u32 pos;
  487.                 u32 size;
  488.                 bool enabled;
  489.                 bool force_thru;
  490.         } pch_pfit;
  491.  
  492.         /* FDI configuration, only valid if has_pch_encoder is set. */
  493.         int fdi_lanes;
  494.         struct intel_link_m_n fdi_m_n;
  495.  
  496.         bool ips_enabled;
  497.  
  498.         bool enable_fbc;
  499.  
  500.         bool double_wide;
  501.  
  502.         bool dp_encoder_is_mst;
  503.         int pbn;
  504.  
  505.         struct intel_crtc_scaler_state scaler_state;
  506.  
  507.         /* w/a for waiting 2 vblanks during crtc enable */
  508.         enum pipe hsw_workaround_pipe;
  509.  
  510.         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
  511.         bool disable_lp_wm;
  512.  
  513.         struct {
  514.                 /*
  515.                  * optimal watermarks, programmed post-vblank when this state
  516.                  * is committed
  517.                  */
  518.                 union {
  519.                         struct intel_pipe_wm ilk;
  520.                         struct skl_pipe_wm skl;
  521.                 } optimal;
  522.         } wm;
  523. };
  524.  
  525. struct vlv_wm_state {
  526.         struct vlv_pipe_wm wm[3];
  527.         struct vlv_sr_wm sr[3];
  528.         uint8_t num_active_planes;
  529.         uint8_t num_levels;
  530.         uint8_t level;
  531.         bool cxsr;
  532. };
  533.  
  534. struct intel_mmio_flip {
  535.         struct work_struct work;
  536.         struct drm_i915_private *i915;
  537.         struct drm_i915_gem_request *req;
  538.         struct intel_crtc *crtc;
  539.         unsigned int rotation;
  540. };
  541.  
  542. /*
  543.  * Tracking of operations that need to be performed at the beginning/end of an
  544.  * atomic commit, outside the atomic section where interrupts are disabled.
  545.  * These are generally operations that grab mutexes or might otherwise sleep
  546.  * and thus can't be run with interrupts disabled.
  547.  */
  548. struct intel_crtc_atomic_commit {
  549.         /* Sleepable operations to perform before commit */
  550.  
  551.         /* Sleepable operations to perform after commit */
  552.         unsigned fb_bits;
  553.         bool post_enable_primary;
  554.  
  555.         /* Sleepable operations to perform before and after commit */
  556.         bool update_fbc;
  557. };
  558.  
  559. struct intel_crtc {
  560.         struct drm_crtc base;
  561.         enum pipe pipe;
  562.         enum plane plane;
  563.         u8 lut_r[256], lut_g[256], lut_b[256];
  564.         /*
  565.          * Whether the crtc and the connected output pipeline is active. Implies
  566.          * that crtc->enabled is set, i.e. the current mode configuration has
  567.          * some outputs connected to this crtc.
  568.          */
  569.         bool active;
  570.         unsigned long enabled_power_domains;
  571.         bool lowfreq_avail;
  572.         struct intel_overlay *overlay;
  573.         struct intel_unpin_work *unpin_work;
  574.  
  575.         atomic_t unpin_work_count;
  576.  
  577.         /* Display surface base address adjustement for pageflips. Note that on
  578.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  579.          * handled in the hw itself (with the TILEOFF register). */
  580.         u32 dspaddr_offset;
  581.         int adjusted_x;
  582.         int adjusted_y;
  583.  
  584.         uint32_t cursor_addr;
  585.         uint32_t cursor_cntl;
  586.         uint32_t cursor_size;
  587.         uint32_t cursor_base;
  588.  
  589.         struct intel_crtc_state *config;
  590.  
  591.         /* reset counter value when the last flip was submitted */
  592.         unsigned int reset_counter;
  593.  
  594.         /* Access to these should be protected by dev_priv->irq_lock. */
  595.         bool cpu_fifo_underrun_disabled;
  596.         bool pch_fifo_underrun_disabled;
  597.  
  598.         /* per-pipe watermark state */
  599.         struct {
  600.                 /* watermarks currently being used  */
  601.                 union {
  602.                         struct intel_pipe_wm ilk;
  603.                         struct skl_pipe_wm skl;
  604.                 } active;
  605.                 /* allow CxSR on this pipe */
  606.                 bool cxsr_allowed;
  607.         } wm;
  608.  
  609.         int scanline_offset;
  610.  
  611.         struct {
  612.                 unsigned start_vbl_count;
  613.                 ktime_t start_vbl_time;
  614.                 int min_vbl, max_vbl;
  615.                 int scanline_start;
  616.         } debug;
  617.  
  618.         struct intel_crtc_atomic_commit atomic;
  619.  
  620.         /* scalers available on this crtc */
  621.         int num_scalers;
  622.  
  623.         struct vlv_wm_state wm_state;
  624. };
  625.  
  626. struct intel_plane_wm_parameters {
  627.         uint32_t horiz_pixels;
  628.         uint32_t vert_pixels;
  629.         /*
  630.          *   For packed pixel formats:
  631.          *     bytes_per_pixel - holds bytes per pixel
  632.          *   For planar pixel formats:
  633.          *     bytes_per_pixel - holds bytes per pixel for uv-plane
  634.          *     y_bytes_per_pixel - holds bytes per pixel for y-plane
  635.          */
  636.         uint8_t bytes_per_pixel;
  637.         uint8_t y_bytes_per_pixel;
  638.         bool enabled;
  639.         bool scaled;
  640.         u64 tiling;
  641.         unsigned int rotation;
  642.         uint16_t fifo_size;
  643. };
  644.  
  645. struct intel_plane {
  646.         struct drm_plane base;
  647.         int plane;
  648.         enum pipe pipe;
  649.         bool can_scale;
  650.         int max_downscale;
  651.         uint32_t frontbuffer_bit;
  652.  
  653.         /* Since we need to change the watermarks before/after
  654.          * enabling/disabling the planes, we need to store the parameters here
  655.          * as the other pieces of the struct may not reflect the values we want
  656.          * for the watermark calculations. Currently only Haswell uses this.
  657.          */
  658.         struct intel_plane_wm_parameters wm;
  659.  
  660.         /*
  661.          * NOTE: Do not place new plane state fields here (e.g., when adding
  662.          * new plane properties).  New runtime state should now be placed in
  663.          * the intel_plane_state structure and accessed via plane_state.
  664.          */
  665.  
  666.         void (*update_plane)(struct drm_plane *plane,
  667.                              const struct intel_crtc_state *crtc_state,
  668.                              const struct intel_plane_state *plane_state);
  669.         void (*disable_plane)(struct drm_plane *plane,
  670.                               struct drm_crtc *crtc);
  671.         int (*check_plane)(struct drm_plane *plane,
  672.                            struct intel_crtc_state *crtc_state,
  673.                            struct intel_plane_state *state);
  674. };
  675.  
  676. struct intel_watermark_params {
  677.         unsigned long fifo_size;
  678.         unsigned long max_wm;
  679.         unsigned long default_wm;
  680.         unsigned long guard_size;
  681.         unsigned long cacheline_size;
  682. };
  683.  
  684. struct cxsr_latency {
  685.         int is_desktop;
  686.         int is_ddr3;
  687.         unsigned long fsb_freq;
  688.         unsigned long mem_freq;
  689.         unsigned long display_sr;
  690.         unsigned long display_hpll_disable;
  691.         unsigned long cursor_sr;
  692.         unsigned long cursor_hpll_disable;
  693. };
  694.  
  695. #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
  696. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  697. #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
  698. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  699. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  700. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  701. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  702. #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
  703. #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
  704.  
  705. struct intel_hdmi {
  706.         i915_reg_t hdmi_reg;
  707.         int ddc_bus;
  708.         struct {
  709.                 enum drm_dp_dual_mode_type type;
  710.                 int max_tmds_clock;
  711.         } dp_dual_mode;
  712.         bool limited_color_range;
  713.         bool color_range_auto;
  714.         bool has_hdmi_sink;
  715.         bool has_audio;
  716.         enum hdmi_force_audio force_audio;
  717.         bool rgb_quant_range_selectable;
  718.         enum hdmi_picture_aspect aspect_ratio;
  719.         struct intel_connector *attached_connector;
  720.         void (*write_infoframe)(struct drm_encoder *encoder,
  721.                                 enum hdmi_infoframe_type type,
  722.                                 const void *frame, ssize_t len);
  723.         void (*set_infoframes)(struct drm_encoder *encoder,
  724.                                bool enable,
  725.                                const struct drm_display_mode *adjusted_mode);
  726.         bool (*infoframe_enabled)(struct drm_encoder *encoder,
  727.                                   const struct intel_crtc_state *pipe_config);
  728. };
  729.  
  730. struct intel_dp_mst_encoder;
  731. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  732.  
  733. /*
  734.  * enum link_m_n_set:
  735.  *      When platform provides two set of M_N registers for dp, we can
  736.  *      program them and switch between them incase of DRRS.
  737.  *      But When only one such register is provided, we have to program the
  738.  *      required divider value on that registers itself based on the DRRS state.
  739.  *
  740.  * M1_N1        : Program dp_m_n on M1_N1 registers
  741.  *                        dp_m2_n2 on M2_N2 registers (If supported)
  742.  *
  743.  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
  744.  *                        M2_N2 registers are not supported
  745.  */
  746.  
  747. enum link_m_n_set {
  748.         /* Sets the m1_n1 and m2_n2 */
  749.         M1_N1 = 0,
  750.         M2_N2
  751. };
  752.  
  753. struct intel_dp {
  754.         i915_reg_t output_reg;
  755.         i915_reg_t aux_ch_ctl_reg;
  756.         i915_reg_t aux_ch_data_reg[5];
  757.         uint32_t DP;
  758.         int link_rate;
  759.         uint8_t lane_count;
  760.         bool has_audio;
  761.         enum hdmi_force_audio force_audio;
  762.         bool limited_color_range;
  763.         bool color_range_auto;
  764.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  765.         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
  766.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  767.         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
  768.         uint8_t num_sink_rates;
  769.         int sink_rates[DP_MAX_SUPPORTED_RATES];
  770.         struct drm_dp_aux aux;
  771.         uint8_t train_set[4];
  772.         int panel_power_up_delay;
  773.         int panel_power_down_delay;
  774.         int panel_power_cycle_delay;
  775.         int backlight_on_delay;
  776.         int backlight_off_delay;
  777.         struct delayed_work panel_vdd_work;
  778.         bool want_panel_vdd;
  779.         unsigned long last_power_on;
  780.         unsigned long last_backlight_off;
  781.         ktime_t panel_power_off_time;
  782.  
  783.         struct notifier_block edp_notifier;
  784.  
  785.         /*
  786.          * Pipe whose power sequencer is currently locked into
  787.          * this port. Only relevant on VLV/CHV.
  788.          */
  789.         enum pipe pps_pipe;
  790.         struct edp_power_seq pps_delays;
  791.  
  792.         bool can_mst; /* this port supports mst */
  793.         bool is_mst;
  794.         int active_mst_links;
  795.         /* connector directly attached - won't be use for modeset in mst world */
  796.         struct intel_connector *attached_connector;
  797.  
  798.         /* mst connector list */
  799.         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
  800.         struct drm_dp_mst_topology_mgr mst_mgr;
  801.  
  802.         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
  803.         /*
  804.          * This function returns the value we have to program the AUX_CTL
  805.          * register with to kick off an AUX transaction.
  806.          */
  807.         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
  808.                                      bool has_aux_irq,
  809.                                      int send_bytes,
  810.                                      uint32_t aux_clock_divider);
  811.  
  812.         /* This is called before a link training is starterd */
  813.         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
  814.  
  815.         /* Displayport compliance testing */
  816.         unsigned long compliance_test_type;
  817.         unsigned long compliance_test_data;
  818.         bool compliance_test_active;
  819. };
  820.  
  821. struct intel_digital_port {
  822.         struct intel_encoder base;
  823.         enum port port;
  824.         u32 saved_port_bits;
  825.         struct intel_dp dp;
  826.         struct intel_hdmi hdmi;
  827.         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
  828.         bool release_cl2_override;
  829.         uint8_t max_lanes;
  830.         /* for communication with audio component; protected by av_mutex */
  831.         const struct drm_connector *audio_connector;
  832. };
  833.  
  834. struct intel_dp_mst_encoder {
  835.         struct intel_encoder base;
  836.         enum pipe pipe;
  837.         struct intel_digital_port *primary;
  838.         void *port; /* store this opaque as its illegal to dereference it */
  839. };
  840.  
  841. static inline enum dpio_channel
  842. vlv_dport_to_channel(struct intel_digital_port *dport)
  843. {
  844.         switch (dport->port) {
  845.         case PORT_B:
  846.         case PORT_D:
  847.                 return DPIO_CH0;
  848.         case PORT_C:
  849.                 return DPIO_CH1;
  850.         default:
  851.                 BUG();
  852.         }
  853. }
  854.  
  855. static inline enum dpio_phy
  856. vlv_dport_to_phy(struct intel_digital_port *dport)
  857. {
  858.         switch (dport->port) {
  859.         case PORT_B:
  860.         case PORT_C:
  861.                 return DPIO_PHY0;
  862.         case PORT_D:
  863.                 return DPIO_PHY1;
  864.         default:
  865.                 BUG();
  866.         }
  867. }
  868.  
  869. static inline enum dpio_channel
  870. vlv_pipe_to_channel(enum pipe pipe)
  871. {
  872.         switch (pipe) {
  873.         case PIPE_A:
  874.         case PIPE_C:
  875.                 return DPIO_CH0;
  876.         case PIPE_B:
  877.                 return DPIO_CH1;
  878.         default:
  879.                 BUG();
  880.         }
  881. }
  882.  
  883. static inline struct drm_crtc *
  884. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  885. {
  886.         struct drm_i915_private *dev_priv = dev->dev_private;
  887.         return dev_priv->pipe_to_crtc_mapping[pipe];
  888. }
  889.  
  890. static inline struct drm_crtc *
  891. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  892. {
  893.         struct drm_i915_private *dev_priv = dev->dev_private;
  894.         return dev_priv->plane_to_crtc_mapping[plane];
  895. }
  896.  
  897. struct intel_unpin_work {
  898.         struct work_struct work;
  899.         struct drm_crtc *crtc;
  900.         struct drm_framebuffer *old_fb;
  901.         struct drm_i915_gem_object *pending_flip_obj;
  902.         struct drm_pending_vblank_event *event;
  903.         atomic_t pending;
  904. #define INTEL_FLIP_INACTIVE     0
  905. #define INTEL_FLIP_PENDING      1
  906. #define INTEL_FLIP_COMPLETE     2
  907.         u32 flip_count;
  908.         u32 gtt_offset;
  909.         struct drm_i915_gem_request *flip_queued_req;
  910.         u32 flip_queued_vblank;
  911.         u32 flip_ready_vblank;
  912.         bool enable_stall_check;
  913. };
  914.  
  915. struct intel_load_detect_pipe {
  916.         struct drm_atomic_state *restore_state;
  917. };
  918.  
  919. static inline struct intel_encoder *
  920. intel_attached_encoder(struct drm_connector *connector)
  921. {
  922.         return to_intel_connector(connector)->encoder;
  923. }
  924.  
  925. static inline struct intel_digital_port *
  926. enc_to_dig_port(struct drm_encoder *encoder)
  927. {
  928.         return container_of(encoder, struct intel_digital_port, base.base);
  929. }
  930.  
  931. static inline struct intel_dp_mst_encoder *
  932. enc_to_mst(struct drm_encoder *encoder)
  933. {
  934.         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
  935. }
  936.  
  937. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  938. {
  939.         return &enc_to_dig_port(encoder)->dp;
  940. }
  941.  
  942. static inline struct intel_digital_port *
  943. dp_to_dig_port(struct intel_dp *intel_dp)
  944. {
  945.         return container_of(intel_dp, struct intel_digital_port, dp);
  946. }
  947.  
  948. static inline struct intel_digital_port *
  949. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  950. {
  951.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  952. }
  953.  
  954. /*
  955.  * Returns the number of planes for this pipe, ie the number of sprites + 1
  956.  * (primary plane). This doesn't count the cursor plane then.
  957.  */
  958. static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
  959. {
  960.         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
  961. }
  962.  
  963. /* intel_fifo_underrun.c */
  964. bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  965.                                            enum pipe pipe, bool enable);
  966. bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
  967.                                            enum transcoder pch_transcoder,
  968.                                            bool enable);
  969. void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
  970.                                          enum pipe pipe);
  971. void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
  972.                                          enum transcoder pch_transcoder);
  973. void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
  974. void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
  975.  
  976. /* i915_irq.c */
  977. void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  978. void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  979. void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  980. void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  981. void gen6_reset_rps_interrupts(struct drm_device *dev);
  982. void gen6_enable_rps_interrupts(struct drm_device *dev);
  983. void gen6_disable_rps_interrupts(struct drm_device *dev);
  984. u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
  985. void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
  986. void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
  987. static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
  988. {
  989.         /*
  990.          * We only use drm_irq_uninstall() at unload and VT switch, so
  991.          * this is the only thing we need to check.
  992.          */
  993.         return dev_priv->pm.irqs_enabled;
  994. }
  995.  
  996. int intel_get_crtc_scanline(struct intel_crtc *crtc);
  997. void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
  998.                                      unsigned int pipe_mask);
  999. void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
  1000.                                      unsigned int pipe_mask);
  1001.  
  1002. /* intel_crt.c */
  1003. void intel_crt_init(struct drm_device *dev);
  1004.  
  1005.  
  1006. /* intel_ddi.c */
  1007. void intel_ddi_clk_select(struct intel_encoder *encoder,
  1008.                           const struct intel_crtc_state *pipe_config);
  1009. void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
  1010. void hsw_fdi_link_train(struct drm_crtc *crtc);
  1011. void intel_ddi_init(struct drm_device *dev, enum port port);
  1012. enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
  1013. bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
  1014. void intel_ddi_pll_init(struct drm_device *dev);
  1015. void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  1016. void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  1017.                                        enum transcoder cpu_transcoder);
  1018. void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  1019. void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  1020. bool intel_ddi_pll_select(struct intel_crtc *crtc,
  1021.                           struct intel_crtc_state *crtc_state);
  1022. void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  1023. void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
  1024. bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  1025. void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  1026. void intel_ddi_get_config(struct intel_encoder *encoder,
  1027.                           struct intel_crtc_state *pipe_config);
  1028. struct intel_encoder *
  1029. intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
  1030.  
  1031. void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
  1032. void intel_ddi_clock_get(struct intel_encoder *encoder,
  1033.                          struct intel_crtc_state *pipe_config);
  1034. void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
  1035. uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
  1036.  
  1037. /* intel_frontbuffer.c */
  1038. void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
  1039.                              enum fb_op_origin origin);
  1040. void intel_frontbuffer_flip_prepare(struct drm_device *dev,
  1041.                                     unsigned frontbuffer_bits);
  1042. void intel_frontbuffer_flip_complete(struct drm_device *dev,
  1043.                                      unsigned frontbuffer_bits);
  1044. void intel_frontbuffer_flip(struct drm_device *dev,
  1045.                             unsigned frontbuffer_bits);
  1046. unsigned int intel_fb_align_height(struct drm_device *dev,
  1047.                                    unsigned int height,
  1048.                                    uint32_t pixel_format,
  1049.                                    uint64_t fb_format_modifier);
  1050. void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
  1051.                         enum fb_op_origin origin);
  1052. u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
  1053.                               uint64_t fb_modifier, uint32_t pixel_format);
  1054.  
  1055. /* intel_audio.c */
  1056. void intel_init_audio(struct drm_device *dev);
  1057. void intel_audio_codec_enable(struct intel_encoder *encoder);
  1058. void intel_audio_codec_disable(struct intel_encoder *encoder);
  1059. void i915_audio_component_init(struct drm_i915_private *dev_priv);
  1060. void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
  1061.  
  1062. /* intel_display.c */
  1063. extern const struct drm_plane_funcs intel_plane_funcs;
  1064. bool intel_has_pending_fb_unpin(struct drm_device *dev);
  1065. int intel_pch_rawclk(struct drm_device *dev);
  1066. int intel_hrawclk(struct drm_device *dev);
  1067. void intel_mark_busy(struct drm_device *dev);
  1068. void intel_mark_idle(struct drm_device *dev);
  1069. void intel_crtc_restore_mode(struct drm_crtc *crtc);
  1070. int intel_display_suspend(struct drm_device *dev);
  1071. void intel_encoder_destroy(struct drm_encoder *encoder);
  1072. int intel_connector_init(struct intel_connector *);
  1073. struct intel_connector *intel_connector_alloc(void);
  1074. bool intel_connector_get_hw_state(struct intel_connector *connector);
  1075. void intel_connector_attach_encoder(struct intel_connector *connector,
  1076.                                     struct intel_encoder *encoder);
  1077. struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  1078. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  1079.                                              struct drm_crtc *crtc);
  1080. enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
  1081. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  1082.                                 struct drm_file *file_priv);
  1083. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  1084.                                              enum pipe pipe);
  1085. bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
  1086. static inline void
  1087. intel_wait_for_vblank(struct drm_device *dev, int pipe)
  1088. {
  1089.         drm_wait_one_vblank(dev, pipe);
  1090. }
  1091. static inline void
  1092. intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
  1093. {
  1094.         const struct intel_crtc *crtc =
  1095.                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
  1096.  
  1097.         if (crtc->active)
  1098.                 intel_wait_for_vblank(dev, pipe);
  1099. }
  1100. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  1101. void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  1102.                          struct intel_digital_port *dport,
  1103.                          unsigned int expected_mask);
  1104. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  1105.                                 struct drm_display_mode *mode,
  1106.                                 struct intel_load_detect_pipe *old,
  1107.                                 struct drm_modeset_acquire_ctx *ctx);
  1108. void intel_release_load_detect_pipe(struct drm_connector *connector,
  1109.                                     struct intel_load_detect_pipe *old,
  1110.                                     struct drm_modeset_acquire_ctx *ctx);
  1111. int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
  1112.                                struct drm_framebuffer *fb,
  1113.                                const struct drm_plane_state *plane_state);
  1114. struct drm_framebuffer *
  1115. __intel_framebuffer_create(struct drm_device *dev,
  1116.                            struct drm_mode_fb_cmd2 *mode_cmd,
  1117.                            struct drm_i915_gem_object *obj);
  1118. void intel_prepare_page_flip(struct drm_device *dev, int plane);
  1119. void intel_finish_page_flip(struct drm_device *dev, int pipe);
  1120. void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  1121. void intel_check_page_flip(struct drm_device *dev, int pipe);
  1122. int intel_prepare_plane_fb(struct drm_plane *plane,
  1123.                            const struct drm_plane_state *new_state);
  1124. void intel_cleanup_plane_fb(struct drm_plane *plane,
  1125.                             const struct drm_plane_state *old_state);
  1126. int intel_plane_atomic_get_property(struct drm_plane *plane,
  1127.                                     const struct drm_plane_state *state,
  1128.                                     struct drm_property *property,
  1129.                                     uint64_t *val);
  1130. int intel_plane_atomic_set_property(struct drm_plane *plane,
  1131.                                     struct drm_plane_state *state,
  1132.                                     struct drm_property *property,
  1133.                                     uint64_t val);
  1134. int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
  1135.                                     struct drm_plane_state *plane_state);
  1136.  
  1137. unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
  1138.                                uint64_t fb_modifier, unsigned int cpp);
  1139.  
  1140. static inline bool
  1141. intel_rotation_90_or_270(unsigned int rotation)
  1142. {
  1143.         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
  1144. }
  1145.  
  1146. void intel_create_rotation_property(struct drm_device *dev,
  1147.                                         struct intel_plane *plane);
  1148.  
  1149. /* shared dpll functions */
  1150. struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
  1151. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  1152.                         struct intel_shared_dpll *pll,
  1153.                         bool state);
  1154. #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
  1155. #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
  1156. struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
  1157.                                                 struct intel_crtc_state *state);
  1158.  
  1159. int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
  1160.                      const struct dpll *dpll);
  1161. void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
  1162.  
  1163. /* modesetting asserts */
  1164. void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1165.                            enum pipe pipe);
  1166. void assert_pll(struct drm_i915_private *dev_priv,
  1167.                 enum pipe pipe, bool state);
  1168. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  1169. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  1170. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  1171.                        enum pipe pipe, bool state);
  1172. #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
  1173. #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
  1174. void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
  1175. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  1176. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  1177. u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
  1178.                               int *x, int *y,
  1179.                               uint64_t fb_modifier,
  1180.                               unsigned int cpp,
  1181.                               unsigned int pitch);
  1182. void intel_prepare_reset(struct drm_device *dev);
  1183. void intel_finish_reset(struct drm_device *dev);
  1184. void hsw_enable_pc8(struct drm_i915_private *dev_priv);
  1185. void hsw_disable_pc8(struct drm_i915_private *dev_priv);
  1186. void broxton_init_cdclk(struct drm_device *dev);
  1187. void broxton_uninit_cdclk(struct drm_device *dev);
  1188. void broxton_ddi_phy_init(struct drm_device *dev);
  1189. void broxton_ddi_phy_uninit(struct drm_device *dev);
  1190. void bxt_enable_dc9(struct drm_i915_private *dev_priv);
  1191. void bxt_disable_dc9(struct drm_i915_private *dev_priv);
  1192. void skl_init_cdclk(struct drm_i915_private *dev_priv);
  1193. int skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
  1194. void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
  1195. void skl_enable_dc6(struct drm_i915_private *dev_priv);
  1196. void skl_disable_dc6(struct drm_i915_private *dev_priv);
  1197. void intel_dp_get_m_n(struct intel_crtc *crtc,
  1198.                       struct intel_crtc_state *pipe_config);
  1199. void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
  1200. int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
  1201. void
  1202. ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
  1203.                                 int dotclock);
  1204. bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
  1205.                         intel_clock_t *best_clock);
  1206. int chv_calc_dpll_params(int refclk, intel_clock_t *pll_clock);
  1207.  
  1208. bool intel_crtc_active(struct drm_crtc *crtc);
  1209. void hsw_enable_ips(struct intel_crtc *crtc);
  1210. void hsw_disable_ips(struct intel_crtc *crtc);
  1211. enum intel_display_power_domain
  1212. intel_display_port_power_domain(struct intel_encoder *intel_encoder);
  1213. enum intel_display_power_domain
  1214. intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
  1215. void intel_mode_from_pipe_config(struct drm_display_mode *mode,
  1216.                                  struct intel_crtc_state *pipe_config);
  1217.  
  1218. int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
  1219. int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
  1220.  
  1221. u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
  1222.                            struct drm_i915_gem_object *obj,
  1223.                            unsigned int plane);
  1224.  
  1225. u32 skl_plane_ctl_format(uint32_t pixel_format);
  1226. u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
  1227. u32 skl_plane_ctl_rotation(unsigned int rotation);
  1228.  
  1229. /* intel_csr.c */
  1230. void intel_csr_ucode_init(struct drm_i915_private *);
  1231. bool intel_csr_load_program(struct drm_i915_private *);
  1232. void intel_csr_ucode_fini(struct drm_i915_private *);
  1233.  
  1234. /* intel_dp.c */
  1235. void intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
  1236. bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  1237.                              struct intel_connector *intel_connector);
  1238. void intel_dp_set_link_params(struct intel_dp *intel_dp,
  1239.                               const struct intel_crtc_state *pipe_config);
  1240. void intel_dp_start_link_train(struct intel_dp *intel_dp);
  1241. void intel_dp_stop_link_train(struct intel_dp *intel_dp);
  1242. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  1243. void intel_dp_encoder_reset(struct drm_encoder *encoder);
  1244. void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
  1245. void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  1246. int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
  1247. bool intel_dp_compute_config(struct intel_encoder *encoder,
  1248.                              struct intel_crtc_state *pipe_config);
  1249. bool intel_dp_is_edp(struct drm_device *dev, enum port port);
  1250. enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
  1251.                                   bool long_hpd);
  1252. void intel_edp_backlight_on(struct intel_dp *intel_dp);
  1253. void intel_edp_backlight_off(struct intel_dp *intel_dp);
  1254. void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
  1255. void intel_edp_panel_on(struct intel_dp *intel_dp);
  1256. void intel_edp_panel_off(struct intel_dp *intel_dp);
  1257. void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
  1258. void intel_dp_mst_suspend(struct drm_device *dev);
  1259. void intel_dp_mst_resume(struct drm_device *dev);
  1260. int intel_dp_max_link_rate(struct intel_dp *intel_dp);
  1261. int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
  1262. void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
  1263. void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
  1264. uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
  1265. void intel_plane_destroy(struct drm_plane *plane);
  1266. void intel_edp_drrs_enable(struct intel_dp *intel_dp);
  1267. void intel_edp_drrs_disable(struct intel_dp *intel_dp);
  1268. void intel_edp_drrs_invalidate(struct drm_device *dev,
  1269.                 unsigned frontbuffer_bits);
  1270. void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
  1271. bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
  1272.                                          struct intel_digital_port *port);
  1273. void hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config);
  1274.  
  1275. void
  1276. intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
  1277.                                        uint8_t dp_train_pat);
  1278. void
  1279. intel_dp_set_signal_levels(struct intel_dp *intel_dp);
  1280. void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
  1281. uint8_t
  1282. intel_dp_voltage_max(struct intel_dp *intel_dp);
  1283. uint8_t
  1284. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
  1285. void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
  1286.                            uint8_t *link_bw, uint8_t *rate_select);
  1287. bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
  1288. bool
  1289. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
  1290.  
  1291. /* intel_dp_mst.c */
  1292. int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
  1293. void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
  1294. /* intel_dsi.c */
  1295. void intel_dsi_init(struct drm_device *dev);
  1296.  
  1297.  
  1298. /* intel_dvo.c */
  1299. void intel_dvo_init(struct drm_device *dev);
  1300.  
  1301.  
  1302. /* legacy fbdev emulation in intel_fbdev.c */
  1303. #ifdef CONFIG_DRM_FBDEV_EMULATION
  1304. extern int intel_fbdev_init(struct drm_device *dev);
  1305. extern void intel_fbdev_initial_config_async(struct drm_device *dev);
  1306. extern void intel_fbdev_fini(struct drm_device *dev);
  1307. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
  1308. extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
  1309. extern void intel_fbdev_restore_mode(struct drm_device *dev);
  1310. #else
  1311. static inline int intel_fbdev_init(struct drm_device *dev)
  1312. {
  1313.         return 0;
  1314. }
  1315.  
  1316. static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
  1317. {
  1318. }
  1319.  
  1320. static inline void intel_fbdev_fini(struct drm_device *dev)
  1321. {
  1322. }
  1323.  
  1324. static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
  1325. {
  1326. }
  1327.  
  1328. static inline void intel_fbdev_restore_mode(struct drm_device *dev)
  1329. {
  1330. }
  1331. #endif
  1332.  
  1333. /* intel_fbc.c */
  1334. void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
  1335.                            struct drm_atomic_state *state);
  1336. bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
  1337. void intel_fbc_pre_update(struct intel_crtc *crtc);
  1338. void intel_fbc_post_update(struct intel_crtc *crtc);
  1339. void intel_fbc_init(struct drm_i915_private *dev_priv);
  1340. void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
  1341. void intel_fbc_enable(struct intel_crtc *crtc);
  1342. void intel_fbc_disable(struct intel_crtc *crtc);
  1343. void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
  1344. void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
  1345.                           unsigned int frontbuffer_bits,
  1346.                           enum fb_op_origin origin);
  1347. void intel_fbc_flush(struct drm_i915_private *dev_priv,
  1348.                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
  1349. void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
  1350.  
  1351. /* intel_hdmi.c */
  1352. void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
  1353. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  1354.                                struct intel_connector *intel_connector);
  1355. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  1356. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  1357.                                struct intel_crtc_state *pipe_config);
  1358. void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
  1359.  
  1360.  
  1361. /* intel_lvds.c */
  1362. void intel_lvds_init(struct drm_device *dev);
  1363. bool intel_is_dual_link_lvds(struct drm_device *dev);
  1364.  
  1365.  
  1366. /* intel_modes.c */
  1367. int intel_connector_update_modes(struct drm_connector *connector,
  1368.                                  struct edid *edid);
  1369. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  1370. void intel_attach_force_audio_property(struct drm_connector *connector);
  1371. void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  1372. void intel_attach_aspect_ratio_property(struct drm_connector *connector);
  1373.  
  1374.  
  1375. /* intel_overlay.c */
  1376. void intel_setup_overlay(struct drm_device *dev);
  1377. void intel_cleanup_overlay(struct drm_device *dev);
  1378. int intel_overlay_switch_off(struct intel_overlay *overlay);
  1379. int intel_overlay_put_image(struct drm_device *dev, void *data,
  1380.                             struct drm_file *file_priv);
  1381. int intel_overlay_attrs(struct drm_device *dev, void *data,
  1382.                         struct drm_file *file_priv);
  1383. void intel_overlay_reset(struct drm_i915_private *dev_priv);
  1384.  
  1385.  
  1386. /* intel_panel.c */
  1387. int intel_panel_init(struct intel_panel *panel,
  1388.                      struct drm_display_mode *fixed_mode,
  1389.                      struct drm_display_mode *downclock_mode);
  1390. void intel_panel_fini(struct intel_panel *panel);
  1391. void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  1392.                             struct drm_display_mode *adjusted_mode);
  1393. void intel_pch_panel_fitting(struct intel_crtc *crtc,
  1394.                              struct intel_crtc_state *pipe_config,
  1395.                              int fitting_mode);
  1396. void intel_gmch_panel_fitting(struct intel_crtc *crtc,
  1397.                               struct intel_crtc_state *pipe_config,
  1398.                               int fitting_mode);
  1399. void intel_panel_set_backlight_acpi(struct intel_connector *connector,
  1400.                                     u32 level, u32 max);
  1401. int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
  1402. void intel_panel_enable_backlight(struct intel_connector *connector);
  1403. void intel_panel_disable_backlight(struct intel_connector *connector);
  1404. void intel_panel_destroy_backlight(struct drm_connector *connector);
  1405. enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  1406. extern struct drm_display_mode *intel_find_panel_downclock(
  1407.                                 struct drm_device *dev,
  1408.                                 struct drm_display_mode *fixed_mode,
  1409.                                 struct drm_connector *connector);
  1410. void intel_backlight_register(struct drm_device *dev);
  1411. void intel_backlight_unregister(struct drm_device *dev);
  1412.  
  1413.  
  1414. /* intel_psr.c */
  1415. void intel_psr_enable(struct intel_dp *intel_dp);
  1416. void intel_psr_disable(struct intel_dp *intel_dp);
  1417. void intel_psr_invalidate(struct drm_device *dev,
  1418.                           unsigned frontbuffer_bits);
  1419. void intel_psr_flush(struct drm_device *dev,
  1420.                      unsigned frontbuffer_bits,
  1421.                      enum fb_op_origin origin);
  1422. void intel_psr_init(struct drm_device *dev);
  1423. void intel_psr_single_frame_update(struct drm_device *dev,
  1424.                                    unsigned frontbuffer_bits);
  1425.  
  1426. /* intel_runtime_pm.c */
  1427. int intel_power_domains_init(struct drm_i915_private *);
  1428. void intel_power_domains_fini(struct drm_i915_private *);
  1429. void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
  1430. void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
  1431. void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv);
  1432. void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv);
  1433. void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
  1434. const char *
  1435. intel_display_power_domain_str(enum intel_display_power_domain domain);
  1436.  
  1437. bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  1438.                                     enum intel_display_power_domain domain);
  1439. bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  1440.                                       enum intel_display_power_domain domain);
  1441. void intel_display_power_get(struct drm_i915_private *dev_priv,
  1442.                              enum intel_display_power_domain domain);
  1443. bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
  1444.                                         enum intel_display_power_domain domain);
  1445. void intel_display_power_put(struct drm_i915_private *dev_priv,
  1446.                              enum intel_display_power_domain domain);
  1447.  
  1448. static inline void
  1449. assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
  1450. {
  1451.         WARN_ONCE(dev_priv->pm.suspended,
  1452.                   "Device suspended during HW access\n");
  1453. }
  1454.  
  1455. static inline void
  1456. assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
  1457. {
  1458.         assert_rpm_device_not_suspended(dev_priv);
  1459.         /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
  1460.          * too much noise. */
  1461.         if (!atomic_read(&dev_priv->pm.wakeref_count))
  1462.                 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
  1463. }
  1464.  
  1465. static inline int
  1466. assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
  1467. {
  1468.         int seq = atomic_read(&dev_priv->pm.atomic_seq);
  1469.  
  1470.         assert_rpm_wakelock_held(dev_priv);
  1471.  
  1472.         return seq;
  1473. }
  1474.  
  1475. static inline void
  1476. assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
  1477. {
  1478.         WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
  1479.                   "HW access outside of RPM atomic section\n");
  1480. }
  1481.  
  1482. /**
  1483.  * disable_rpm_wakeref_asserts - disable the RPM assert checks
  1484.  * @dev_priv: i915 device instance
  1485.  *
  1486.  * This function disable asserts that check if we hold an RPM wakelock
  1487.  * reference, while keeping the device-not-suspended checks still enabled.
  1488.  * It's meant to be used only in special circumstances where our rule about
  1489.  * the wakelock refcount wrt. the device power state doesn't hold. According
  1490.  * to this rule at any point where we access the HW or want to keep the HW in
  1491.  * an active state we must hold an RPM wakelock reference acquired via one of
  1492.  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
  1493.  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
  1494.  * forcewake release timer, and the GPU RPS and hangcheck works. All other
  1495.  * users should avoid using this function.
  1496.  *
  1497.  * Any calls to this function must have a symmetric call to
  1498.  * enable_rpm_wakeref_asserts().
  1499.  */
  1500. static inline void
  1501. disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
  1502. {
  1503.         atomic_inc(&dev_priv->pm.wakeref_count);
  1504. }
  1505.  
  1506. /**
  1507.  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
  1508.  * @dev_priv: i915 device instance
  1509.  *
  1510.  * This function re-enables the RPM assert checks after disabling them with
  1511.  * disable_rpm_wakeref_asserts. It's meant to be used only in special
  1512.  * circumstances otherwise its use should be avoided.
  1513.  *
  1514.  * Any calls to this function must have a symmetric call to
  1515.  * disable_rpm_wakeref_asserts().
  1516.  */
  1517. static inline void
  1518. enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
  1519. {
  1520.         atomic_dec(&dev_priv->pm.wakeref_count);
  1521. }
  1522.  
  1523. /* TODO: convert users of these to rely instead on proper RPM refcounting */
  1524. #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)   \
  1525.         disable_rpm_wakeref_asserts(dev_priv)
  1526.  
  1527. #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)    \
  1528.         enable_rpm_wakeref_asserts(dev_priv)
  1529.  
  1530. void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
  1531. bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
  1532. void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
  1533. void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
  1534.  
  1535. void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
  1536.  
  1537. void chv_phy_powergate_lanes(struct intel_encoder *encoder,
  1538.                              bool override, unsigned int mask);
  1539. bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
  1540.                           enum dpio_channel ch, bool override);
  1541.  
  1542.  
  1543. /* intel_pm.c */
  1544. void intel_init_clock_gating(struct drm_device *dev);
  1545. void intel_suspend_hw(struct drm_device *dev);
  1546. int ilk_wm_max_level(const struct drm_device *dev);
  1547. void intel_update_watermarks(struct drm_crtc *crtc);
  1548. void intel_init_pm(struct drm_device *dev);
  1549. void intel_pm_setup(struct drm_device *dev);
  1550. void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  1551. void intel_gpu_ips_teardown(void);
  1552. void intel_init_gt_powersave(struct drm_device *dev);
  1553. void intel_cleanup_gt_powersave(struct drm_device *dev);
  1554. void intel_enable_gt_powersave(struct drm_device *dev);
  1555. void intel_disable_gt_powersave(struct drm_device *dev);
  1556. void intel_suspend_gt_powersave(struct drm_device *dev);
  1557. void intel_reset_gt_powersave(struct drm_device *dev);
  1558. void gen6_update_ring_freq(struct drm_device *dev);
  1559. void gen6_rps_busy(struct drm_i915_private *dev_priv);
  1560. void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
  1561. void gen6_rps_idle(struct drm_i915_private *dev_priv);
  1562. void gen6_rps_boost(struct drm_i915_private *dev_priv,
  1563.                     struct intel_rps_client *rps,
  1564.                     unsigned long submitted);
  1565. void intel_queue_rps_boost_for_request(struct drm_device *dev,
  1566.                                        struct drm_i915_gem_request *req);
  1567. void vlv_wm_get_hw_state(struct drm_device *dev);
  1568. void ilk_wm_get_hw_state(struct drm_device *dev);
  1569. void skl_wm_get_hw_state(struct drm_device *dev);
  1570. void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  1571.                           struct skl_ddb_allocation *ddb /* out */);
  1572. uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
  1573. int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6);
  1574.  
  1575. /* intel_sdvo.c */
  1576. bool intel_sdvo_init(struct drm_device *dev,
  1577.                      i915_reg_t reg, enum port port);
  1578.  
  1579.  
  1580. /* intel_sprite.c */
  1581. int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  1582. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  1583.                               struct drm_file *file_priv);
  1584. void intel_pipe_update_start(struct intel_crtc *crtc);
  1585. void intel_pipe_update_end(struct intel_crtc *crtc);
  1586.  
  1587. /* intel_tv.c */
  1588. void intel_tv_init(struct drm_device *dev);
  1589.  
  1590. /* intel_atomic.c */
  1591. int intel_connector_atomic_get_property(struct drm_connector *connector,
  1592.                                         const struct drm_connector_state *state,
  1593.                                         struct drm_property *property,
  1594.                                         uint64_t *val);
  1595. struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
  1596. void intel_crtc_destroy_state(struct drm_crtc *crtc,
  1597.                                struct drm_crtc_state *state);
  1598. struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
  1599. void intel_atomic_state_clear(struct drm_atomic_state *);
  1600. struct intel_shared_dpll_config *
  1601. intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
  1602.  
  1603. static inline struct intel_crtc_state *
  1604. intel_atomic_get_crtc_state(struct drm_atomic_state *state,
  1605.                             struct intel_crtc *crtc)
  1606. {
  1607.         struct drm_crtc_state *crtc_state;
  1608.         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
  1609.         if (IS_ERR(crtc_state))
  1610.                 return ERR_CAST(crtc_state);
  1611.  
  1612.         return to_intel_crtc_state(crtc_state);
  1613. }
  1614. int intel_atomic_setup_scalers(struct drm_device *dev,
  1615.         struct intel_crtc *intel_crtc,
  1616.         struct intel_crtc_state *crtc_state);
  1617.  
  1618. /* intel_atomic_plane.c */
  1619. struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
  1620. struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
  1621. void intel_plane_destroy_state(struct drm_plane *plane,
  1622.                                struct drm_plane_state *state);
  1623. extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
  1624.  
  1625. int drm_core_init(void);
  1626. void set_fake_framebuffer();
  1627. int kolibri_framebuffer_init(void *param);
  1628. void shmem_file_delete(struct file *filep);
  1629. void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
  1630. int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
  1631.             struct drm_driver *driver);
  1632. #define synchronize_irq(x)
  1633.  
  1634. #endif /* __INTEL_DRV_H__ */
  1635.