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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/i2c.h>
  29. #include <linux/hdmi.h>
  30. #include <drm/i915_drm.h>
  31. #include "i915_drv.h"
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_crtc_helper.h>
  34. #include <drm/drm_fb_helper.h>
  35. #include <drm/drm_dp_helper.h>
  36.  
  37. #define KBUILD_MODNAME "i915.dll"
  38.  
  39.  
  40. #define cpu_relax()     asm volatile("rep; nop")
  41.  
  42. /**
  43.  * _wait_for - magic (register) wait macro
  44.  *
  45.  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46.  * contexts. Note that it's important that we check the condition again after
  47.  * having timed out, since the timeout could be due to preemption or similar and
  48.  * we've never had a chance to check the condition before the timeout.
  49.  */
  50. #define _wait_for(COND, MS, W) ({ \
  51.     unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS);  \
  52.         int ret__ = 0;                                                  \
  53.         while (!(COND)) {                                               \
  54.         if (time_after(GetTimerTicks(), timeout__)) {          \
  55.                         if (!(COND))                                    \
  56.                         ret__ = -ETIMEDOUT;                             \
  57.                         break;                                          \
  58.                 }                                                       \
  59.                 if (W )  {                              \
  60.          msleep(W); \
  61.                 } else {                                                \
  62.                         cpu_relax();                                    \
  63.                 }                                                       \
  64.         }                                                               \
  65.         ret__;                                                          \
  66. })
  67.  
  68. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70. #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71.                                                DIV_ROUND_UP((US), 1000), 0)
  72.  
  73. #define KHz(x) (1000 * (x))
  74. #define MHz(x) KHz(1000 * (x))
  75.  
  76. /*
  77.  * Display related stuff
  78.  */
  79.  
  80. /* store information about an Ixxx DVO */
  81. /* The i830->i865 use multiple DVOs with multiple i2cs */
  82. /* the i915, i945 have a single sDVO i2c bus - which is different */
  83. #define MAX_OUTPUTS 6
  84. /* maximum connectors per crtcs in the mode set */
  85.  
  86. #define INTEL_I2C_BUS_DVO 1
  87. #define INTEL_I2C_BUS_SDVO 2
  88.  
  89. /* these are outputs from the chip - integrated only
  90.    external chips are via DVO or SDVO output */
  91. #define INTEL_OUTPUT_UNUSED 0
  92. #define INTEL_OUTPUT_ANALOG 1
  93. #define INTEL_OUTPUT_DVO 2
  94. #define INTEL_OUTPUT_SDVO 3
  95. #define INTEL_OUTPUT_LVDS 4
  96. #define INTEL_OUTPUT_TVOUT 5
  97. #define INTEL_OUTPUT_HDMI 6
  98. #define INTEL_OUTPUT_DISPLAYPORT 7
  99. #define INTEL_OUTPUT_EDP 8
  100. #define INTEL_OUTPUT_DSI 9
  101. #define INTEL_OUTPUT_UNKNOWN 10
  102.  
  103. #define INTEL_DVO_CHIP_NONE 0
  104. #define INTEL_DVO_CHIP_LVDS 1
  105. #define INTEL_DVO_CHIP_TMDS 2
  106. #define INTEL_DVO_CHIP_TVOUT 4
  107.  
  108. #define INTEL_DSI_COMMAND_MODE  0
  109. #define INTEL_DSI_VIDEO_MODE    1
  110.  
  111. struct intel_framebuffer {
  112.         struct drm_framebuffer base;
  113.         struct drm_i915_gem_object *obj;
  114. };
  115.  
  116. struct intel_fbdev {
  117.         struct drm_fb_helper helper;
  118.         struct intel_framebuffer ifb;
  119.         struct list_head fbdev_list;
  120.         struct drm_display_mode *our_mode;
  121. };
  122.  
  123. struct intel_encoder {
  124.         struct drm_encoder base;
  125.         /*
  126.          * The new crtc this encoder will be driven from. Only differs from
  127.          * base->crtc while a modeset is in progress.
  128.          */
  129.         struct intel_crtc *new_crtc;
  130.  
  131.         int type;
  132.         /*
  133.          * Intel hw has only one MUX where encoders could be clone, hence a
  134.          * simple flag is enough to compute the possible_clones mask.
  135.          */
  136.         bool cloneable;
  137.         bool connectors_active;
  138.         void (*hot_plug)(struct intel_encoder *);
  139.         bool (*compute_config)(struct intel_encoder *,
  140.                                struct intel_crtc_config *);
  141.         void (*pre_pll_enable)(struct intel_encoder *);
  142.         void (*pre_enable)(struct intel_encoder *);
  143.         void (*enable)(struct intel_encoder *);
  144.         void (*mode_set)(struct intel_encoder *intel_encoder);
  145.         void (*disable)(struct intel_encoder *);
  146.         void (*post_disable)(struct intel_encoder *);
  147.         /* Read out the current hw state of this connector, returning true if
  148.          * the encoder is active. If the encoder is enabled it also set the pipe
  149.          * it is connected to in the pipe parameter. */
  150.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  151.         /* Reconstructs the equivalent mode flags for the current hardware
  152.          * state. This must be called _after_ display->get_pipe_config has
  153.          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
  154.          * be set correctly before calling this function. */
  155.         void (*get_config)(struct intel_encoder *,
  156.                            struct intel_crtc_config *pipe_config);
  157.         int crtc_mask;
  158.         enum hpd_pin hpd_pin;
  159. };
  160.  
  161. struct intel_panel {
  162.         struct drm_display_mode *fixed_mode;
  163.         struct drm_display_mode *downclock_mode;
  164.         int fitting_mode;
  165.  
  166.         /* backlight */
  167.         struct {
  168.                 bool present;
  169.                 u32 level;
  170.                 u32 max;
  171.                 bool enabled;
  172.                 bool combination_mode;  /* gen 2/4 only */
  173.                 bool active_low_pwm;
  174.                 struct backlight_device *device;
  175.         } backlight;
  176. };
  177.  
  178. struct intel_connector {
  179.         struct drm_connector base;
  180.         /*
  181.          * The fixed encoder this connector is connected to.
  182.          */
  183.         struct intel_encoder *encoder;
  184.  
  185.         /*
  186.          * The new encoder this connector will be driven. Only differs from
  187.          * encoder while a modeset is in progress.
  188.          */
  189.         struct intel_encoder *new_encoder;
  190.  
  191.         /* Reads out the current hw, returning true if the connector is enabled
  192.          * and active (i.e. dpms ON state). */
  193.         bool (*get_hw_state)(struct intel_connector *);
  194.  
  195.         /* Panel info for eDP and LVDS */
  196.         struct intel_panel panel;
  197.  
  198.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  199.         struct edid *edid;
  200.  
  201.         /* since POLL and HPD connectors may use the same HPD line keep the native
  202.            state of connector->polled in case hotplug storm detection changes it */
  203.         u8 polled;
  204. };
  205.  
  206. typedef struct dpll {
  207.         /* given values */
  208.         int n;
  209.         int m1, m2;
  210.         int p1, p2;
  211.         /* derived values */
  212.         int     dot;
  213.         int     vco;
  214.         int     m;
  215.         int     p;
  216. } intel_clock_t;
  217.  
  218. struct intel_crtc_config {
  219.         /**
  220.          * quirks - bitfield with hw state readout quirks
  221.          *
  222.          * For various reasons the hw state readout code might not be able to
  223.          * completely faithfully read out the current state. These cases are
  224.          * tracked with quirk flags so that fastboot and state checker can act
  225.          * accordingly.
  226.          */
  227. #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
  228.         unsigned long quirks;
  229.  
  230.         /* User requested mode, only valid as a starting point to
  231.          * compute adjusted_mode, except in the case of (S)DVO where
  232.          * it's also for the output timings of the (S)DVO chip.
  233.          * adjusted_mode will then correspond to the S(DVO) chip's
  234.          * preferred input timings. */
  235.         struct drm_display_mode requested_mode;
  236.         /* Actual pipe timings ie. what we program into the pipe timing
  237.          * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
  238.         struct drm_display_mode adjusted_mode;
  239.  
  240.         /* Pipe source size (ie. panel fitter input size)
  241.          * All planes will be positioned inside this space,
  242.          * and get clipped at the edges. */
  243.         int pipe_src_w, pipe_src_h;
  244.  
  245.         /* Whether to set up the PCH/FDI. Note that we never allow sharing
  246.          * between pch encoders and cpu encoders. */
  247.         bool has_pch_encoder;
  248.  
  249.         /* CPU Transcoder for the pipe. Currently this can only differ from the
  250.          * pipe on Haswell (where we have a special eDP transcoder). */
  251.         enum transcoder cpu_transcoder;
  252.  
  253.         /*
  254.          * Use reduced/limited/broadcast rbg range, compressing from the full
  255.          * range fed into the crtcs.
  256.          */
  257.         bool limited_color_range;
  258.  
  259.         /* DP has a bunch of special case unfortunately, so mark the pipe
  260.          * accordingly. */
  261.         bool has_dp_encoder;
  262.  
  263.         /*
  264.          * Enable dithering, used when the selected pipe bpp doesn't match the
  265.          * plane bpp.
  266.          */
  267.         bool dither;
  268.  
  269.         /* Controls for the clock computation, to override various stages. */
  270.         bool clock_set;
  271.  
  272.         /* SDVO TV has a bunch of special case. To make multifunction encoders
  273.          * work correctly, we need to track this at runtime.*/
  274.         bool sdvo_tv_clock;
  275.  
  276.         /*
  277.          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
  278.          * required. This is set in the 2nd loop of calling encoder's
  279.          * ->compute_config if the first pick doesn't work out.
  280.          */
  281.         bool bw_constrained;
  282.  
  283.         /* Settings for the intel dpll used on pretty much everything but
  284.          * haswell. */
  285.         struct dpll dpll;
  286.  
  287.         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
  288.         enum intel_dpll_id shared_dpll;
  289.  
  290.         /* Actual register state of the dpll, for shared dpll cross-checking. */
  291.         struct intel_dpll_hw_state dpll_hw_state;
  292.  
  293.         int pipe_bpp;
  294.         struct intel_link_m_n dp_m_n;
  295.  
  296.         /*
  297.          * Frequence the dpll for the port should run at. Differs from the
  298.          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
  299.          * already multiplied by pixel_multiplier.
  300.          */
  301.         int port_clock;
  302.  
  303.         /* Used by SDVO (and if we ever fix it, HDMI). */
  304.         unsigned pixel_multiplier;
  305.  
  306.         /* Panel fitter controls for gen2-gen4 + VLV */
  307.         struct {
  308.                 u32 control;
  309.                 u32 pgm_ratios;
  310.                 u32 lvds_border_bits;
  311.         } gmch_pfit;
  312.  
  313.         /* Panel fitter placement and size for Ironlake+ */
  314.         struct {
  315.                 u32 pos;
  316.                 u32 size;
  317.                 bool enabled;
  318.         } pch_pfit;
  319.  
  320.         /* FDI configuration, only valid if has_pch_encoder is set. */
  321.         int fdi_lanes;
  322.         struct intel_link_m_n fdi_m_n;
  323.  
  324.         bool ips_enabled;
  325.  
  326.         bool double_wide;
  327. };
  328.  
  329. struct intel_pipe_wm {
  330.         struct intel_wm_level wm[5];
  331.         uint32_t linetime;
  332.         bool fbc_wm_enabled;
  333. };
  334.  
  335. struct intel_crtc {
  336.         struct drm_crtc base;
  337.         enum pipe pipe;
  338.         enum plane plane;
  339.         u8 lut_r[256], lut_g[256], lut_b[256];
  340.         /*
  341.          * Whether the crtc and the connected output pipeline is active. Implies
  342.          * that crtc->enabled is set, i.e. the current mode configuration has
  343.          * some outputs connected to this crtc.
  344.          */
  345.         bool active;
  346.         unsigned long enabled_power_domains;
  347.         bool eld_vld;
  348.         bool primary_enabled; /* is the primary plane (partially) visible? */
  349.         bool lowfreq_avail;
  350.         struct intel_overlay *overlay;
  351.         struct intel_unpin_work *unpin_work;
  352.  
  353.         atomic_t unpin_work_count;
  354.  
  355.         /* Display surface base address adjustement for pageflips. Note that on
  356.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  357.          * handled in the hw itself (with the TILEOFF register). */
  358.         unsigned long dspaddr_offset;
  359.  
  360.         struct drm_i915_gem_object *cursor_bo;
  361.         uint32_t cursor_addr;
  362.         int16_t cursor_x, cursor_y;
  363.         int16_t cursor_width, cursor_height;
  364.         bool cursor_visible;
  365.  
  366.         struct intel_crtc_config config;
  367.  
  368.         uint32_t ddi_pll_sel;
  369.  
  370.         /* reset counter value when the last flip was submitted */
  371.         unsigned int reset_counter;
  372.  
  373.         /* Access to these should be protected by dev_priv->irq_lock. */
  374.         bool cpu_fifo_underrun_disabled;
  375.         bool pch_fifo_underrun_disabled;
  376.  
  377.         /* per-pipe watermark state */
  378.         struct {
  379.                 /* watermarks currently being used  */
  380.                 struct intel_pipe_wm active;
  381.         } wm;
  382. };
  383.  
  384. struct intel_plane_wm_parameters {
  385.         uint32_t horiz_pixels;
  386.         uint8_t bytes_per_pixel;
  387.         bool enabled;
  388.         bool scaled;
  389. };
  390.  
  391. struct intel_plane {
  392.         struct drm_plane base;
  393.         int plane;
  394.         enum pipe pipe;
  395.         struct drm_i915_gem_object *obj;
  396.         bool can_scale;
  397.         int max_downscale;
  398.         u32 lut_r[1024], lut_g[1024], lut_b[1024];
  399.         int crtc_x, crtc_y;
  400.         unsigned int crtc_w, crtc_h;
  401.         uint32_t src_x, src_y;
  402.         uint32_t src_w, src_h;
  403.  
  404.         /* Since we need to change the watermarks before/after
  405.          * enabling/disabling the planes, we need to store the parameters here
  406.          * as the other pieces of the struct may not reflect the values we want
  407.          * for the watermark calculations. Currently only Haswell uses this.
  408.          */
  409.         struct intel_plane_wm_parameters wm;
  410.  
  411.         void (*update_plane)(struct drm_plane *plane,
  412.                              struct drm_crtc *crtc,
  413.                              struct drm_framebuffer *fb,
  414.                              struct drm_i915_gem_object *obj,
  415.                              int crtc_x, int crtc_y,
  416.                              unsigned int crtc_w, unsigned int crtc_h,
  417.                              uint32_t x, uint32_t y,
  418.                              uint32_t src_w, uint32_t src_h);
  419.         void (*disable_plane)(struct drm_plane *plane,
  420.                               struct drm_crtc *crtc);
  421.         int (*update_colorkey)(struct drm_plane *plane,
  422.                                struct drm_intel_sprite_colorkey *key);
  423.         void (*get_colorkey)(struct drm_plane *plane,
  424.                              struct drm_intel_sprite_colorkey *key);
  425. };
  426.  
  427. struct intel_watermark_params {
  428.         unsigned long fifo_size;
  429.         unsigned long max_wm;
  430.         unsigned long default_wm;
  431.         unsigned long guard_size;
  432.         unsigned long cacheline_size;
  433. };
  434.  
  435. struct cxsr_latency {
  436.         int is_desktop;
  437.         int is_ddr3;
  438.         unsigned long fsb_freq;
  439.         unsigned long mem_freq;
  440.         unsigned long display_sr;
  441.         unsigned long display_hpll_disable;
  442.         unsigned long cursor_sr;
  443.         unsigned long cursor_hpll_disable;
  444. };
  445.  
  446. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  447. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  448. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  449. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  450. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  451.  
  452. struct intel_hdmi {
  453.         u32 hdmi_reg;
  454.         int ddc_bus;
  455.         uint32_t color_range;
  456.         bool color_range_auto;
  457.         bool has_hdmi_sink;
  458.         bool has_audio;
  459.         enum hdmi_force_audio force_audio;
  460.         bool rgb_quant_range_selectable;
  461.         void (*write_infoframe)(struct drm_encoder *encoder,
  462.                                 enum hdmi_infoframe_type type,
  463.                                 const void *frame, ssize_t len);
  464.         void (*set_infoframes)(struct drm_encoder *encoder,
  465.                                struct drm_display_mode *adjusted_mode);
  466. };
  467.  
  468. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  469.  
  470. struct intel_dp {
  471.         uint32_t output_reg;
  472.         uint32_t aux_ch_ctl_reg;
  473.         uint32_t DP;
  474.         bool has_audio;
  475.         enum hdmi_force_audio force_audio;
  476.         uint32_t color_range;
  477.         bool color_range_auto;
  478.         uint8_t link_bw;
  479.         uint8_t lane_count;
  480.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  481.         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
  482.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  483.         struct i2c_adapter adapter;
  484.         struct i2c_algo_dp_aux_data algo;
  485.         uint8_t train_set[4];
  486.         int panel_power_up_delay;
  487.         int panel_power_down_delay;
  488.         int panel_power_cycle_delay;
  489.         int backlight_on_delay;
  490.         int backlight_off_delay;
  491.         struct delayed_work panel_vdd_work;
  492.         bool want_panel_vdd;
  493.         bool psr_setup_done;
  494.         struct intel_connector *attached_connector;
  495. };
  496.  
  497. struct intel_digital_port {
  498.         struct intel_encoder base;
  499.         enum port port;
  500.         u32 saved_port_bits;
  501.         struct intel_dp dp;
  502.         struct intel_hdmi hdmi;
  503. };
  504.  
  505. static inline int
  506. vlv_dport_to_channel(struct intel_digital_port *dport)
  507. {
  508.         switch (dport->port) {
  509.         case PORT_B:
  510.                 return DPIO_CH0;
  511.         case PORT_C:
  512.                 return DPIO_CH1;
  513.         default:
  514.                 BUG();
  515.         }
  516. }
  517.  
  518. static inline struct drm_crtc *
  519. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  520. {
  521.         struct drm_i915_private *dev_priv = dev->dev_private;
  522.         return dev_priv->pipe_to_crtc_mapping[pipe];
  523. }
  524.  
  525. static inline struct drm_crtc *
  526. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  527. {
  528.         struct drm_i915_private *dev_priv = dev->dev_private;
  529.         return dev_priv->plane_to_crtc_mapping[plane];
  530. }
  531.  
  532. struct intel_unpin_work {
  533.         struct work_struct work;
  534.         struct drm_crtc *crtc;
  535.         struct drm_i915_gem_object *old_fb_obj;
  536.         struct drm_i915_gem_object *pending_flip_obj;
  537.         struct drm_pending_vblank_event *event;
  538.         atomic_t pending;
  539. #define INTEL_FLIP_INACTIVE     0
  540. #define INTEL_FLIP_PENDING      1
  541. #define INTEL_FLIP_COMPLETE     2
  542.         bool enable_stall_check;
  543. };
  544.  
  545. struct intel_set_config {
  546.         struct drm_encoder **save_connector_encoders;
  547.         struct drm_crtc **save_encoder_crtcs;
  548.  
  549.         bool fb_changed;
  550.         bool mode_changed;
  551. };
  552.  
  553. struct intel_load_detect_pipe {
  554.         struct drm_framebuffer *release_fb;
  555.         bool load_detect_temp;
  556.         int dpms_mode;
  557. };
  558.  
  559. static inline struct intel_encoder *
  560. intel_attached_encoder(struct drm_connector *connector)
  561. {
  562.         return to_intel_connector(connector)->encoder;
  563. }
  564.  
  565. static inline struct intel_digital_port *
  566. enc_to_dig_port(struct drm_encoder *encoder)
  567. {
  568.         return container_of(encoder, struct intel_digital_port, base.base);
  569. }
  570.  
  571. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  572. {
  573.         return &enc_to_dig_port(encoder)->dp;
  574. }
  575.  
  576. static inline struct intel_digital_port *
  577. dp_to_dig_port(struct intel_dp *intel_dp)
  578. {
  579.         return container_of(intel_dp, struct intel_digital_port, dp);
  580. }
  581.  
  582. static inline struct intel_digital_port *
  583. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  584. {
  585.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  586. }
  587.  
  588.  
  589. /* i915_irq.c */
  590. bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
  591.                                            enum pipe pipe, bool enable);
  592. bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
  593.                                            enum transcoder pch_transcoder,
  594.                                            bool enable);
  595. void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  596. void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  597. void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  598. void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  599. void hsw_pc8_disable_interrupts(struct drm_device *dev);
  600. void hsw_pc8_restore_interrupts(struct drm_device *dev);
  601.  
  602.  
  603. /* intel_crt.c */
  604. void intel_crt_init(struct drm_device *dev);
  605.  
  606.  
  607. /* intel_ddi.c */
  608. void intel_prepare_ddi(struct drm_device *dev);
  609. void hsw_fdi_link_train(struct drm_crtc *crtc);
  610. void intel_ddi_init(struct drm_device *dev, enum port port);
  611. enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
  612. bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
  613. int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  614. void intel_ddi_pll_init(struct drm_device *dev);
  615. void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  616. void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  617.                                        enum transcoder cpu_transcoder);
  618. void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  619. void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  620. void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
  621. bool intel_ddi_pll_select(struct intel_crtc *crtc);
  622. void intel_ddi_pll_enable(struct intel_crtc *crtc);
  623. void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
  624. void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  625. void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  626. bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  627. void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  628. void intel_ddi_get_config(struct intel_encoder *encoder,
  629.                           struct intel_crtc_config *pipe_config);
  630.  
  631.  
  632. /* intel_display.c */
  633. const char *intel_output_name(int output);
  634. bool intel_has_pending_fb_unpin(struct drm_device *dev);
  635. int intel_pch_rawclk(struct drm_device *dev);
  636. void intel_mark_busy(struct drm_device *dev);
  637. void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  638.                         struct intel_ring_buffer *ring);
  639. void intel_mark_idle(struct drm_device *dev);
  640. void intel_crtc_restore_mode(struct drm_crtc *crtc);
  641. void intel_crtc_update_dpms(struct drm_crtc *crtc);
  642. void intel_encoder_destroy(struct drm_encoder *encoder);
  643. void intel_connector_dpms(struct drm_connector *, int mode);
  644. bool intel_connector_get_hw_state(struct intel_connector *connector);
  645. void intel_modeset_check_state(struct drm_device *dev);
  646. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  647.                                 struct intel_digital_port *port);
  648. void intel_connector_attach_encoder(struct intel_connector *connector,
  649.                                            struct intel_encoder *encoder);
  650. struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  651. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  652.                                                     struct drm_crtc *crtc);
  653. enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
  654. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  655.                                 struct drm_file *file_priv);
  656. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  657.                              enum pipe pipe);
  658. void intel_wait_for_vblank(struct drm_device *dev, int pipe);
  659. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
  660. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  661. void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  662.                          struct intel_digital_port *dport);
  663. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  664.                                        struct drm_display_mode *mode,
  665.                                        struct intel_load_detect_pipe *old);
  666. void intel_release_load_detect_pipe(struct drm_connector *connector,
  667.                                            struct intel_load_detect_pipe *old);
  668. int intel_pin_and_fence_fb_obj(struct drm_device *dev,
  669.                                       struct drm_i915_gem_object *obj,
  670.                                       struct intel_ring_buffer *pipelined);
  671. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  672. int intel_framebuffer_init(struct drm_device *dev,
  673.                                   struct intel_framebuffer *ifb,
  674.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  675.                                   struct drm_i915_gem_object *obj);
  676. void intel_framebuffer_fini(struct intel_framebuffer *fb);
  677. void intel_prepare_page_flip(struct drm_device *dev, int plane);
  678. void intel_finish_page_flip(struct drm_device *dev, int pipe);
  679. void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  680. struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
  681. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  682.                         struct intel_shared_dpll *pll,
  683.                         bool state);
  684. #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
  685. #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
  686. void assert_pll(struct drm_i915_private *dev_priv,
  687.                 enum pipe pipe, bool state);
  688. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  689. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  690. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  691.                        enum pipe pipe, bool state);
  692. #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
  693. #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
  694. void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
  695. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  696. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  697. void intel_write_eld(struct drm_encoder *encoder,
  698.                             struct drm_display_mode *mode);
  699. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  700.                                                     unsigned int tiling_mode,
  701.                                                       unsigned int bpp,
  702.                                                       unsigned int pitch);
  703. void intel_display_handle_reset(struct drm_device *dev);
  704. void hsw_enable_pc8_work(struct work_struct *__work);
  705. void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
  706. void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
  707. void intel_dp_get_m_n(struct intel_crtc *crtc,
  708.                       struct intel_crtc_config *pipe_config);
  709. int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
  710. void
  711. ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
  712.                                 int dotclock);
  713. bool intel_crtc_active(struct drm_crtc *crtc);
  714. void hsw_enable_ips(struct intel_crtc *crtc);
  715. void hsw_disable_ips(struct intel_crtc *crtc);
  716. void intel_display_set_init_power(struct drm_device *dev, bool enable);
  717. int valleyview_get_vco(struct drm_i915_private *dev_priv);
  718.  
  719. /* intel_dp.c */
  720. void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
  721. bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  722.                              struct intel_connector *intel_connector);
  723. void intel_dp_start_link_train(struct intel_dp *intel_dp);
  724. void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  725. void intel_dp_stop_link_train(struct intel_dp *intel_dp);
  726. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  727. void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  728. void intel_dp_check_link_status(struct intel_dp *intel_dp);
  729. bool intel_dp_compute_config(struct intel_encoder *encoder,
  730.                              struct intel_crtc_config *pipe_config);
  731. bool intel_dp_is_edp(struct drm_device *dev, enum port port);
  732. void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
  733. void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
  734. void ironlake_edp_panel_on(struct intel_dp *intel_dp);
  735. void ironlake_edp_panel_off(struct intel_dp *intel_dp);
  736. void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  737. void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  738. void intel_edp_psr_enable(struct intel_dp *intel_dp);
  739. void intel_edp_psr_disable(struct intel_dp *intel_dp);
  740. void intel_edp_psr_update(struct drm_device *dev);
  741.  
  742.  
  743. /* intel_dsi.c */
  744. bool intel_dsi_init(struct drm_device *dev);
  745.  
  746.  
  747. /* intel_dvo.c */
  748. void intel_dvo_init(struct drm_device *dev);
  749.  
  750.  
  751. /* legacy fbdev emulation in intel_fbdev.c */
  752. #ifdef CONFIG_DRM_I915_FBDEV
  753. extern int intel_fbdev_init(struct drm_device *dev);
  754. extern void intel_fbdev_initial_config(struct drm_device *dev);
  755. extern void intel_fbdev_fini(struct drm_device *dev);
  756. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
  757. extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
  758. extern void intel_fbdev_restore_mode(struct drm_device *dev);
  759. #else
  760. static inline int intel_fbdev_init(struct drm_device *dev)
  761. {
  762.         return 0;
  763. }
  764.  
  765. static inline void intel_fbdev_initial_config(struct drm_device *dev)
  766. {
  767. }
  768.  
  769. static inline void intel_fbdev_fini(struct drm_device *dev)
  770. {
  771. }
  772.  
  773. static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state)
  774. {
  775. }
  776.  
  777. static inline void intel_fbdev_restore_mode(struct drm_device *dev)
  778. {
  779. }
  780. #endif
  781.  
  782. /* intel_hdmi.c */
  783. void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
  784. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  785.                                struct intel_connector *intel_connector);
  786. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  787. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  788.                                struct intel_crtc_config *pipe_config);
  789.  
  790.  
  791. /* intel_lvds.c */
  792. void intel_lvds_init(struct drm_device *dev);
  793. bool intel_is_dual_link_lvds(struct drm_device *dev);
  794.  
  795.  
  796. /* intel_modes.c */
  797. int intel_connector_update_modes(struct drm_connector *connector,
  798.                                  struct edid *edid);
  799. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  800. void intel_attach_force_audio_property(struct drm_connector *connector);
  801. void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  802.  
  803.  
  804. /* intel_overlay.c */
  805. void intel_setup_overlay(struct drm_device *dev);
  806. void intel_cleanup_overlay(struct drm_device *dev);
  807. int intel_overlay_switch_off(struct intel_overlay *overlay);
  808. int intel_overlay_put_image(struct drm_device *dev, void *data,
  809.                                      struct drm_file *file_priv);
  810. int intel_overlay_attrs(struct drm_device *dev, void *data,
  811.                                      struct drm_file *file_priv);
  812.  
  813.  
  814. /* intel_panel.c */
  815. int intel_panel_init(struct intel_panel *panel,
  816.                      struct drm_display_mode *fixed_mode);
  817. void intel_panel_fini(struct intel_panel *panel);
  818. void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  819.                             struct drm_display_mode *adjusted_mode);
  820. void intel_pch_panel_fitting(struct intel_crtc *crtc,
  821.                              struct intel_crtc_config *pipe_config,
  822.                              int fitting_mode);
  823. void intel_gmch_panel_fitting(struct intel_crtc *crtc,
  824.                               struct intel_crtc_config *pipe_config,
  825.                               int fitting_mode);
  826. void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
  827.                                u32 max);
  828. int intel_panel_setup_backlight(struct drm_connector *connector);
  829. void intel_panel_enable_backlight(struct intel_connector *connector);
  830. void intel_panel_disable_backlight(struct intel_connector *connector);
  831. void intel_panel_destroy_backlight(struct drm_connector *connector);
  832. void intel_panel_init_backlight_funcs(struct drm_device *dev);
  833. enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  834. extern struct drm_display_mode *intel_find_panel_downclock(
  835.                                 struct drm_device *dev,
  836.                                 struct drm_display_mode *fixed_mode,
  837.                                 struct drm_connector *connector);
  838.  
  839. /* intel_pm.c */
  840. void intel_init_clock_gating(struct drm_device *dev);
  841. void intel_suspend_hw(struct drm_device *dev);
  842. void intel_update_watermarks(struct drm_crtc *crtc);
  843. void intel_update_sprite_watermarks(struct drm_plane *plane,
  844.                                     struct drm_crtc *crtc,
  845.                                     uint32_t sprite_width, int pixel_size,
  846.                                     bool enabled, bool scaled);
  847. void intel_init_pm(struct drm_device *dev);
  848. void intel_pm_setup(struct drm_device *dev);
  849. bool intel_fbc_enabled(struct drm_device *dev);
  850. void intel_update_fbc(struct drm_device *dev);
  851. void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  852. void intel_gpu_ips_teardown(void);
  853. int intel_power_domains_init(struct drm_device *dev);
  854. void intel_power_domains_remove(struct drm_device *dev);
  855. bool intel_display_power_enabled(struct drm_device *dev,
  856.                                  enum intel_display_power_domain domain);
  857. bool intel_display_power_enabled_sw(struct drm_device *dev,
  858.                                     enum intel_display_power_domain domain);
  859. void intel_display_power_get(struct drm_device *dev,
  860.                              enum intel_display_power_domain domain);
  861. void intel_display_power_put(struct drm_device *dev,
  862.                                         enum intel_display_power_domain domain);
  863. void intel_power_domains_init_hw(struct drm_device *dev);
  864. void intel_set_power_well(struct drm_device *dev, bool enable);
  865. void intel_enable_gt_powersave(struct drm_device *dev);
  866. void intel_disable_gt_powersave(struct drm_device *dev);
  867. void ironlake_teardown_rc6(struct drm_device *dev);
  868. void gen6_update_ring_freq(struct drm_device *dev);
  869. void gen6_rps_idle(struct drm_i915_private *dev_priv);
  870. void gen6_rps_boost(struct drm_i915_private *dev_priv);
  871. void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
  872. void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
  873. void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
  874. void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
  875. void intel_init_runtime_pm(struct drm_i915_private *dev_priv);
  876. void intel_fini_runtime_pm(struct drm_i915_private *dev_priv);
  877. void ilk_wm_get_hw_state(struct drm_device *dev);
  878.  
  879.  
  880. /* intel_sdvo.c */
  881. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
  882.  
  883.  
  884. /* intel_sprite.c */
  885. int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  886. void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
  887.                                enum plane plane);
  888. void intel_plane_restore(struct drm_plane *plane);
  889. void intel_plane_disable(struct drm_plane *plane);
  890. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  891.                               struct drm_file *file_priv);
  892. int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  893.                               struct drm_file *file_priv);
  894.  
  895.  
  896. /* intel_tv.c */
  897. void intel_tv_init(struct drm_device *dev);
  898.  
  899. #endif /* __INTEL_DRV_H__ */
  900.