Subversion Repositories Kolibri OS

Rev

Rev 3482 | Rev 4104 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/i2c.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_fb_helper.h>
  34. #include <drm/drm_dp_helper.h>
  35.  
  36. #define KBUILD_MODNAME "i915.dll"
  37.  
  38.  
  39. #define cpu_relax()     asm volatile("rep; nop")
  40.  
  41. /**
  42.  * _wait_for - magic (register) wait macro
  43.  *
  44.  * Does the right thing for modeset paths when run under kdgb or similar atomic
  45.  * contexts. Note that it's important that we check the condition again after
  46.  * having timed out, since the timeout could be due to preemption or similar and
  47.  * we've never had a chance to check the condition before the timeout.
  48.  */
  49. #define _wait_for(COND, MS, W) ({ \
  50.     unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS);  \
  51.         int ret__ = 0;                                                  \
  52.         while (!(COND)) {                                               \
  53.         if (time_after(GetTimerTicks(), timeout__)) {          \
  54.                         if (!(COND))                                    \
  55.                         ret__ = -ETIMEDOUT;                             \
  56.                         break;                                          \
  57.                 }                                                       \
  58.                 if (W )  {                              \
  59.          msleep(W); \
  60.                 } else {                                                \
  61.                         cpu_relax();                                    \
  62.                 }                                                       \
  63.         }                                                               \
  64.         ret__;                                                          \
  65. })
  66.  
  67. #define wait_for_atomic_us(COND, US) ({ \
  68.         unsigned long timeout__ = GetTimerTicks() + usecs_to_jiffies(US);       \
  69.         int ret__ = 0;                                                  \
  70.         while (!(COND)) {                                               \
  71.                 if (time_after(GetTimerTicks(), timeout__)) {                   \
  72.                         ret__ = -ETIMEDOUT;                             \
  73.                         break;                                          \
  74.                 }                                                       \
  75.                 cpu_relax();                                            \
  76.         }                                                               \
  77.         ret__;                                                          \
  78. })
  79.  
  80. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  81. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  82.  
  83. #define MSLEEP(x) do { \
  84.         if (in_dbg_master()) \
  85.                 mdelay(x); \
  86.         else \
  87.                 msleep(x); \
  88. } while(0)
  89.  
  90. #define KHz(x) (1000*x)
  91. #define MHz(x) KHz(1000*x)
  92.  
  93. /*
  94.  * Display related stuff
  95.  */
  96.  
  97. /* store information about an Ixxx DVO */
  98. /* The i830->i865 use multiple DVOs with multiple i2cs */
  99. /* the i915, i945 have a single sDVO i2c bus - which is different */
  100. #define MAX_OUTPUTS 6
  101. /* maximum connectors per crtcs in the mode set */
  102. #define INTELFB_CONN_LIMIT 4
  103.  
  104. #define INTEL_I2C_BUS_DVO 1
  105. #define INTEL_I2C_BUS_SDVO 2
  106.  
  107. /* these are outputs from the chip - integrated only
  108.    external chips are via DVO or SDVO output */
  109. #define INTEL_OUTPUT_UNUSED 0
  110. #define INTEL_OUTPUT_ANALOG 1
  111. #define INTEL_OUTPUT_DVO 2
  112. #define INTEL_OUTPUT_SDVO 3
  113. #define INTEL_OUTPUT_LVDS 4
  114. #define INTEL_OUTPUT_TVOUT 5
  115. #define INTEL_OUTPUT_HDMI 6
  116. #define INTEL_OUTPUT_DISPLAYPORT 7
  117. #define INTEL_OUTPUT_EDP 8
  118. #define INTEL_OUTPUT_UNKNOWN 9
  119.  
  120. #define INTEL_DVO_CHIP_NONE 0
  121. #define INTEL_DVO_CHIP_LVDS 1
  122. #define INTEL_DVO_CHIP_TMDS 2
  123. #define INTEL_DVO_CHIP_TVOUT 4
  124.  
  125. struct intel_framebuffer {
  126.         struct drm_framebuffer base;
  127.         struct drm_i915_gem_object *obj;
  128. };
  129.  
  130. struct intel_fbdev {
  131.         struct drm_fb_helper helper;
  132.         struct intel_framebuffer ifb;
  133.         struct list_head fbdev_list;
  134.         struct drm_display_mode *our_mode;
  135. };
  136.  
  137. struct intel_encoder {
  138.         struct drm_encoder base;
  139.         /*
  140.          * The new crtc this encoder will be driven from. Only differs from
  141.          * base->crtc while a modeset is in progress.
  142.          */
  143.         struct intel_crtc *new_crtc;
  144.  
  145.         int type;
  146.         bool needs_tv_clock;
  147.         /*
  148.          * Intel hw has only one MUX where encoders could be clone, hence a
  149.          * simple flag is enough to compute the possible_clones mask.
  150.          */
  151.         bool cloneable;
  152.         bool connectors_active;
  153.         void (*hot_plug)(struct intel_encoder *);
  154.         bool (*compute_config)(struct intel_encoder *,
  155.                                struct intel_crtc_config *);
  156.         void (*pre_pll_enable)(struct intel_encoder *);
  157.         void (*pre_enable)(struct intel_encoder *);
  158.         void (*enable)(struct intel_encoder *);
  159.         void (*mode_set)(struct intel_encoder *intel_encoder);
  160.         void (*disable)(struct intel_encoder *);
  161.         void (*post_disable)(struct intel_encoder *);
  162.         /* Read out the current hw state of this connector, returning true if
  163.          * the encoder is active. If the encoder is enabled it also set the pipe
  164.          * it is connected to in the pipe parameter. */
  165.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  166.         int crtc_mask;
  167.         enum hpd_pin hpd_pin;
  168. };
  169.  
  170. struct intel_panel {
  171.         struct drm_display_mode *fixed_mode;
  172.         int fitting_mode;
  173. };
  174.  
  175. struct intel_connector {
  176.         struct drm_connector base;
  177.         /*
  178.          * The fixed encoder this connector is connected to.
  179.          */
  180.         struct intel_encoder *encoder;
  181.  
  182.         /*
  183.          * The new encoder this connector will be driven. Only differs from
  184.          * encoder while a modeset is in progress.
  185.          */
  186.         struct intel_encoder *new_encoder;
  187.  
  188.         /* Reads out the current hw, returning true if the connector is enabled
  189.          * and active (i.e. dpms ON state). */
  190.         bool (*get_hw_state)(struct intel_connector *);
  191.  
  192.         /* Panel info for eDP and LVDS */
  193.         struct intel_panel panel;
  194.  
  195.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  196.         struct edid *edid;
  197.  
  198.         /* since POLL and HPD connectors may use the same HPD line keep the native
  199.            state of connector->polled in case hotplug storm detection changes it */
  200.         u8 polled;
  201. };
  202.  
  203. struct intel_crtc_config {
  204.         struct drm_display_mode requested_mode;
  205.         struct drm_display_mode adjusted_mode;
  206.         /* This flag must be set by the encoder's compute_config callback if it
  207.          * changes the crtc timings in the mode to prevent the crtc fixup from
  208.          * overwriting them.  Currently only lvds needs that. */
  209.         bool timings_set;
  210.         /* Whether to set up the PCH/FDI. Note that we never allow sharing
  211.          * between pch encoders and cpu encoders. */
  212.         bool has_pch_encoder;
  213.  
  214.         /* CPU Transcoder for the pipe. Currently this can only differ from the
  215.          * pipe on Haswell (where we have a special eDP transcoder). */
  216.         enum transcoder cpu_transcoder;
  217.  
  218.         /*
  219.          * Use reduced/limited/broadcast rbg range, compressing from the full
  220.          * range fed into the crtcs.
  221.          */
  222.         bool limited_color_range;
  223.  
  224.         /* DP has a bunch of special case unfortunately, so mark the pipe
  225.          * accordingly. */
  226.         bool has_dp_encoder;
  227.         bool dither;
  228.  
  229.         /* Controls for the clock computation, to override various stages. */
  230.         bool clock_set;
  231.  
  232.         /* Settings for the intel dpll used on pretty much everything but
  233.          * haswell. */
  234.         struct dpll {
  235.                 unsigned n;
  236.                 unsigned m1, m2;
  237.                 unsigned p1, p2;
  238.         } dpll;
  239.  
  240.         int pipe_bpp;
  241.         struct intel_link_m_n dp_m_n;
  242.         /**
  243.          * This is currently used by DP and HDMI encoders since those can have a
  244.          * target pixel clock != the port link clock (which is currently stored
  245.          * in adjusted_mode->clock).
  246.          */
  247.         int pixel_target_clock;
  248.         /* Used by SDVO (and if we ever fix it, HDMI). */
  249.         unsigned pixel_multiplier;
  250. };
  251.  
  252. struct intel_crtc {
  253.         struct drm_crtc base;
  254.         enum pipe pipe;
  255.         enum plane plane;
  256.         u8 lut_r[256], lut_g[256], lut_b[256];
  257.         /*
  258.          * Whether the crtc and the connected output pipeline is active. Implies
  259.          * that crtc->enabled is set, i.e. the current mode configuration has
  260.          * some outputs connected to this crtc.
  261.          */
  262.         bool active;
  263.         bool eld_vld;
  264.         bool primary_disabled; /* is the crtc obscured by a plane? */
  265.         bool lowfreq_avail;
  266.         struct intel_overlay *overlay;
  267.         struct intel_unpin_work *unpin_work;
  268.         int fdi_lanes;
  269.  
  270.         atomic_t unpin_work_count;
  271.  
  272.         /* Display surface base address adjustement for pageflips. Note that on
  273.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  274.          * handled in the hw itself (with the TILEOFF register). */
  275.         unsigned long dspaddr_offset;
  276.  
  277.         struct drm_i915_gem_object *cursor_bo;
  278.         uint32_t cursor_addr;
  279.         int16_t cursor_x, cursor_y;
  280.         int16_t cursor_width, cursor_height;
  281.         bool cursor_visible;
  282.  
  283.         struct intel_crtc_config config;
  284.  
  285.         /* We can share PLLs across outputs if the timings match */
  286.         struct intel_pch_pll *pch_pll;
  287.         uint32_t ddi_pll_sel;
  288.  
  289.         /* reset counter value when the last flip was submitted */
  290.         unsigned int reset_counter;
  291. };
  292.  
  293. struct intel_plane {
  294.         struct drm_plane base;
  295.         int plane;
  296.         enum pipe pipe;
  297.         struct drm_i915_gem_object *obj;
  298.         bool can_scale;
  299.         int max_downscale;
  300.         u32 lut_r[1024], lut_g[1024], lut_b[1024];
  301.         int crtc_x, crtc_y;
  302.         unsigned int crtc_w, crtc_h;
  303.         uint32_t src_x, src_y;
  304.         uint32_t src_w, src_h;
  305.         void (*update_plane)(struct drm_plane *plane,
  306.                              struct drm_framebuffer *fb,
  307.                              struct drm_i915_gem_object *obj,
  308.                              int crtc_x, int crtc_y,
  309.                              unsigned int crtc_w, unsigned int crtc_h,
  310.                              uint32_t x, uint32_t y,
  311.                              uint32_t src_w, uint32_t src_h);
  312.         void (*disable_plane)(struct drm_plane *plane);
  313.         int (*update_colorkey)(struct drm_plane *plane,
  314.                                struct drm_intel_sprite_colorkey *key);
  315.         void (*get_colorkey)(struct drm_plane *plane,
  316.                              struct drm_intel_sprite_colorkey *key);
  317. };
  318.  
  319. struct intel_watermark_params {
  320.         unsigned long fifo_size;
  321.         unsigned long max_wm;
  322.         unsigned long default_wm;
  323.         unsigned long guard_size;
  324.         unsigned long cacheline_size;
  325. };
  326.  
  327. struct cxsr_latency {
  328.         int is_desktop;
  329.         int is_ddr3;
  330.         unsigned long fsb_freq;
  331.         unsigned long mem_freq;
  332.         unsigned long display_sr;
  333.         unsigned long display_hpll_disable;
  334.         unsigned long cursor_sr;
  335.         unsigned long cursor_hpll_disable;
  336. };
  337.  
  338. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  339. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  340. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  341. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  342. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  343.  
  344. #define DIP_HEADER_SIZE 5
  345.  
  346. #define DIP_TYPE_AVI    0x82
  347. #define DIP_VERSION_AVI 0x2
  348. #define DIP_LEN_AVI     13
  349. #define DIP_AVI_PR_1    0
  350. #define DIP_AVI_PR_2    1
  351. #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
  352. #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
  353. #define DIP_AVI_RGB_QUANT_RANGE_FULL    (2 << 2)
  354.  
  355. #define DIP_TYPE_SPD    0x83
  356. #define DIP_VERSION_SPD 0x1
  357. #define DIP_LEN_SPD     25
  358. #define DIP_SPD_UNKNOWN 0
  359. #define DIP_SPD_DSTB    0x1
  360. #define DIP_SPD_DVDP    0x2
  361. #define DIP_SPD_DVHS    0x3
  362. #define DIP_SPD_HDDVR   0x4
  363. #define DIP_SPD_DVC     0x5
  364. #define DIP_SPD_DSC     0x6
  365. #define DIP_SPD_VCD     0x7
  366. #define DIP_SPD_GAME    0x8
  367. #define DIP_SPD_PC      0x9
  368. #define DIP_SPD_BD      0xa
  369. #define DIP_SPD_SCD     0xb
  370.  
  371. struct dip_infoframe {
  372.         uint8_t type;           /* HB0 */
  373.         uint8_t ver;            /* HB1 */
  374.         uint8_t len;            /* HB2 - body len, not including checksum */
  375.         uint8_t ecc;            /* Header ECC */
  376.         uint8_t checksum;       /* PB0 */
  377.         union {
  378.                 struct {
  379.                         /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
  380.                         uint8_t Y_A_B_S;
  381.                         /* PB2 - C 7:6, M 5:4, R 3:0 */
  382.                         uint8_t C_M_R;
  383.                         /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
  384.                         uint8_t ITC_EC_Q_SC;
  385.                         /* PB4 - VIC 6:0 */
  386.                         uint8_t VIC;
  387.                         /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
  388.                         uint8_t YQ_CN_PR;
  389.                         /* PB6 to PB13 */
  390.                         uint16_t top_bar_end;
  391.                         uint16_t bottom_bar_start;
  392.                         uint16_t left_bar_end;
  393.                         uint16_t right_bar_start;
  394.                 } __attribute__ ((packed)) avi;
  395.                 struct {
  396.                         uint8_t vn[8];
  397.                         uint8_t pd[16];
  398.                         uint8_t sdi;
  399.                 } __attribute__ ((packed)) spd;
  400.                 uint8_t payload[27];
  401.         } __attribute__ ((packed)) body;
  402. } __attribute__((packed));
  403.  
  404. struct intel_hdmi {
  405.         u32 hdmi_reg;
  406.         int ddc_bus;
  407.         uint32_t color_range;
  408.         bool color_range_auto;
  409.         bool has_hdmi_sink;
  410.         bool has_audio;
  411.         enum hdmi_force_audio force_audio;
  412.         bool rgb_quant_range_selectable;
  413.         void (*write_infoframe)(struct drm_encoder *encoder,
  414.                                 struct dip_infoframe *frame);
  415.         void (*set_infoframes)(struct drm_encoder *encoder,
  416.                                struct drm_display_mode *adjusted_mode);
  417. };
  418.  
  419. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  420. #define DP_LINK_CONFIGURATION_SIZE      9
  421.  
  422. struct intel_dp {
  423.         uint32_t output_reg;
  424.         uint32_t aux_ch_ctl_reg;
  425.         uint32_t DP;
  426.         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  427.         bool has_audio;
  428.         enum hdmi_force_audio force_audio;
  429.         uint32_t color_range;
  430.         bool color_range_auto;
  431.         uint8_t link_bw;
  432.         uint8_t lane_count;
  433.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  434.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  435.         struct i2c_adapter adapter;
  436.         struct i2c_algo_dp_aux_data algo;
  437.         bool is_pch_edp;
  438.         uint8_t train_set[4];
  439.         int panel_power_up_delay;
  440.         int panel_power_down_delay;
  441.         int panel_power_cycle_delay;
  442.         int backlight_on_delay;
  443.         int backlight_off_delay;
  444.         struct delayed_work panel_vdd_work;
  445.         bool want_panel_vdd;
  446.         struct intel_connector *attached_connector;
  447. };
  448.  
  449. struct intel_digital_port {
  450.         struct intel_encoder base;
  451.         enum port port;
  452.         u32 port_reversal;
  453.         struct intel_dp dp;
  454.         struct intel_hdmi hdmi;
  455. };
  456.  
  457. static inline struct drm_crtc *
  458. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  459. {
  460.         struct drm_i915_private *dev_priv = dev->dev_private;
  461.         return dev_priv->pipe_to_crtc_mapping[pipe];
  462. }
  463.  
  464. static inline struct drm_crtc *
  465. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  466. {
  467.         struct drm_i915_private *dev_priv = dev->dev_private;
  468.         return dev_priv->plane_to_crtc_mapping[plane];
  469. }
  470.  
  471. struct intel_unpin_work {
  472.         struct work_struct work;
  473.         struct drm_crtc *crtc;
  474.         struct drm_i915_gem_object *old_fb_obj;
  475.         struct drm_i915_gem_object *pending_flip_obj;
  476.         struct drm_pending_vblank_event *event;
  477.         atomic_t pending;
  478. #define INTEL_FLIP_INACTIVE     0
  479. #define INTEL_FLIP_PENDING      1
  480. #define INTEL_FLIP_COMPLETE     2
  481.         bool enable_stall_check;
  482. };
  483.  
  484. struct intel_fbc_work {
  485.         struct delayed_work work;
  486.         struct drm_crtc *crtc;
  487.         struct drm_framebuffer *fb;
  488.         int interval;
  489. };
  490.  
  491. int intel_pch_rawclk(struct drm_device *dev);
  492.  
  493. int intel_connector_update_modes(struct drm_connector *connector,
  494.                                 struct edid *edid);
  495. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  496.  
  497. extern void intel_attach_force_audio_property(struct drm_connector *connector);
  498. extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  499.  
  500. extern void intel_crt_init(struct drm_device *dev);
  501. extern void intel_hdmi_init(struct drm_device *dev,
  502.                             int hdmi_reg, enum port port);
  503. extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  504.                                       struct intel_connector *intel_connector);
  505. extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  506. extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  507.                                       struct intel_crtc_config *pipe_config);
  508. extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
  509. extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
  510.                             bool is_sdvob);
  511. extern void intel_dvo_init(struct drm_device *dev);
  512. extern void intel_tv_init(struct drm_device *dev);
  513. extern void intel_mark_busy(struct drm_device *dev);
  514. extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
  515. extern void intel_mark_idle(struct drm_device *dev);
  516. extern bool intel_lvds_init(struct drm_device *dev);
  517. extern bool intel_is_dual_link_lvds(struct drm_device *dev);
  518. extern void intel_dp_init(struct drm_device *dev, int output_reg,
  519.                           enum port port);
  520. extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  521.                                     struct intel_connector *intel_connector);
  522. extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
  523. extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
  524. extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  525. extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
  526. extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  527. extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  528. extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
  529. extern bool intel_dp_compute_config(struct intel_encoder *encoder,
  530.                                     struct intel_crtc_config *pipe_config);
  531. extern bool intel_dpd_is_edp(struct drm_device *dev);
  532. extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
  533. extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
  534. extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
  535. extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
  536. extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  537. extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  538. extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
  539. extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  540. extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  541.                                       enum plane plane);
  542.  
  543. /* intel_panel.c */
  544. extern int intel_panel_init(struct intel_panel *panel,
  545.                             struct drm_display_mode *fixed_mode);
  546. extern void intel_panel_fini(struct intel_panel *panel);
  547.  
  548. extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  549.                                    struct drm_display_mode *adjusted_mode);
  550. extern void intel_pch_panel_fitting(struct drm_device *dev,
  551.                                     int fitting_mode,
  552.                                     const struct drm_display_mode *mode,
  553.                                     struct drm_display_mode *adjusted_mode);
  554. extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
  555. extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
  556. extern int intel_panel_setup_backlight(struct drm_connector *connector);
  557. extern void intel_panel_enable_backlight(struct drm_device *dev,
  558.                                          enum pipe pipe);
  559. extern void intel_panel_disable_backlight(struct drm_device *dev);
  560. extern void intel_panel_destroy_backlight(struct drm_device *dev);
  561. extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  562.  
  563. struct intel_set_config {
  564.         struct drm_encoder **save_connector_encoders;
  565.         struct drm_crtc **save_encoder_crtcs;
  566.  
  567.         bool fb_changed;
  568.         bool mode_changed;
  569. };
  570.  
  571. extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  572.                            int x, int y, struct drm_framebuffer *old_fb);
  573. extern void intel_modeset_disable(struct drm_device *dev);
  574. extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
  575. extern void intel_crtc_load_lut(struct drm_crtc *crtc);
  576. extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
  577. extern void intel_encoder_destroy(struct drm_encoder *encoder);
  578. extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
  579. extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
  580. extern void intel_connector_dpms(struct drm_connector *, int mode);
  581. extern bool intel_connector_get_hw_state(struct intel_connector *connector);
  582. extern void intel_modeset_check_state(struct drm_device *dev);
  583. extern void intel_plane_restore(struct drm_plane *plane);
  584.  
  585.  
  586. static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
  587. {
  588.         return to_intel_connector(connector)->encoder;
  589. }
  590.  
  591. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  592. {
  593.         struct intel_digital_port *intel_dig_port =
  594.                 container_of(encoder, struct intel_digital_port, base.base);
  595.         return &intel_dig_port->dp;
  596. }
  597.  
  598. static inline struct intel_digital_port *
  599. enc_to_dig_port(struct drm_encoder *encoder)
  600. {
  601.         return container_of(encoder, struct intel_digital_port, base.base);
  602. }
  603.  
  604. static inline struct intel_digital_port *
  605. dp_to_dig_port(struct intel_dp *intel_dp)
  606. {
  607.         return container_of(intel_dp, struct intel_digital_port, dp);
  608. }
  609.  
  610. static inline struct intel_digital_port *
  611. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  612. {
  613.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  614. }
  615.  
  616. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  617.                                 struct intel_digital_port *port);
  618.  
  619. extern void intel_connector_attach_encoder(struct intel_connector *connector,
  620.                                            struct intel_encoder *encoder);
  621. extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  622.  
  623. extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  624.                                                     struct drm_crtc *crtc);
  625. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  626.                                 struct drm_file *file_priv);
  627. extern enum transcoder
  628. intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  629.                              enum pipe pipe);
  630. extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
  631. extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
  632. extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  633.  
  634. struct intel_load_detect_pipe {
  635.         struct drm_framebuffer *release_fb;
  636.         bool load_detect_temp;
  637.         int dpms_mode;
  638. };
  639. extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
  640.                                        struct drm_display_mode *mode,
  641.                                        struct intel_load_detect_pipe *old);
  642. extern void intel_release_load_detect_pipe(struct drm_connector *connector,
  643.                                            struct intel_load_detect_pipe *old);
  644.  
  645. extern void intelfb_restore(void);
  646. extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  647.                                     u16 blue, int regno);
  648. extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  649.                                     u16 *blue, int regno);
  650. extern void intel_enable_clock_gating(struct drm_device *dev);
  651.  
  652. extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
  653.                                       struct drm_i915_gem_object *obj,
  654.                                       struct intel_ring_buffer *pipelined);
  655. extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  656.  
  657. extern int intel_framebuffer_init(struct drm_device *dev,
  658.                                   struct intel_framebuffer *ifb,
  659.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  660.                                   struct drm_i915_gem_object *obj);
  661. extern int intel_fbdev_init(struct drm_device *dev);
  662. extern void intel_fbdev_initial_config(struct drm_device *dev);
  663. extern void intel_fbdev_fini(struct drm_device *dev);
  664. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
  665. extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
  666. extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
  667. extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  668.  
  669. extern void intel_setup_overlay(struct drm_device *dev);
  670. extern void intel_cleanup_overlay(struct drm_device *dev);
  671. extern int intel_overlay_switch_off(struct intel_overlay *overlay);
  672. extern int intel_overlay_put_image(struct drm_device *dev, void *data,
  673.                                    struct drm_file *file_priv);
  674. extern int intel_overlay_attrs(struct drm_device *dev, void *data,
  675.                                struct drm_file *file_priv);
  676.  
  677. extern void intel_fb_output_poll_changed(struct drm_device *dev);
  678. extern void intel_fb_restore_mode(struct drm_device *dev);
  679.  
  680. extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  681.                         bool state);
  682. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  683. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  684.  
  685. extern void intel_init_clock_gating(struct drm_device *dev);
  686. extern void intel_write_eld(struct drm_encoder *encoder,
  687.                             struct drm_display_mode *mode);
  688. extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
  689. extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  690.                                          struct intel_link_m_n *m_n);
  691. extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  692.                                          struct intel_link_m_n *m_n);
  693. extern void intel_prepare_ddi(struct drm_device *dev);
  694. extern void hsw_fdi_link_train(struct drm_crtc *crtc);
  695. extern void intel_ddi_init(struct drm_device *dev, enum port port);
  696.  
  697. /* For use by IVB LP watermark workaround in intel_sprite.c */
  698. extern void intel_update_watermarks(struct drm_device *dev);
  699. extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  700.                                            uint32_t sprite_width,
  701.                                            int pixel_size);
  702. extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
  703.                          struct drm_display_mode *mode);
  704.  
  705. extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  706.                                                     unsigned int tiling_mode,
  707.                                                       unsigned int bpp,
  708.                                                       unsigned int pitch);
  709.  
  710. extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  711.                                      struct drm_file *file_priv);
  712. extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  713.                                      struct drm_file *file_priv);
  714.  
  715. extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
  716.  
  717. /* Power-related functions, located in intel_pm.c */
  718. extern void intel_init_pm(struct drm_device *dev);
  719. /* FBC */
  720. extern bool intel_fbc_enabled(struct drm_device *dev);
  721. extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
  722. extern void intel_update_fbc(struct drm_device *dev);
  723. /* IPS */
  724. extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  725. extern void intel_gpu_ips_teardown(void);
  726.  
  727. extern bool intel_using_power_well(struct drm_device *dev);
  728. extern void intel_init_power_well(struct drm_device *dev);
  729. extern void intel_set_power_well(struct drm_device *dev, bool enable);
  730. extern void intel_enable_gt_powersave(struct drm_device *dev);
  731. extern void intel_disable_gt_powersave(struct drm_device *dev);
  732. extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
  733. extern void ironlake_teardown_rc6(struct drm_device *dev);
  734.  
  735. extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  736.                                    enum pipe *pipe);
  737. extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  738. extern void intel_ddi_pll_init(struct drm_device *dev);
  739. extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  740. extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  741.                                               enum transcoder cpu_transcoder);
  742. extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  743. extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  744. extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
  745. extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
  746. extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
  747. extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  748. extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  749. extern bool
  750. intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  751. extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  752.  
  753. extern void intel_display_handle_reset(struct drm_device *dev);
  754.  
  755. #endif /* __INTEL_DRV_H__ */
  756.