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  1. /*
  2.  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  3.  * Copyright (c) 2007-2008 Intel Corporation
  4.  *   Jesse Barnes <jesse.barnes@intel.com>
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23.  * IN THE SOFTWARE.
  24.  */
  25. #ifndef __INTEL_DRV_H__
  26. #define __INTEL_DRV_H__
  27.  
  28. #include <linux/i2c.h>
  29. #include <linux/hdmi.h>
  30. #include <drm/i915_drm.h>
  31. #include "i915_drv.h"
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_crtc_helper.h>
  34. #include <drm/drm_fb_helper.h>
  35. #include <drm/drm_dp_helper.h>
  36.  
  37. #define KBUILD_MODNAME "i915.dll"
  38.  
  39.  
  40. #define cpu_relax()     asm volatile("rep; nop")
  41.  
  42. /**
  43.  * _wait_for - magic (register) wait macro
  44.  *
  45.  * Does the right thing for modeset paths when run under kdgb or similar atomic
  46.  * contexts. Note that it's important that we check the condition again after
  47.  * having timed out, since the timeout could be due to preemption or similar and
  48.  * we've never had a chance to check the condition before the timeout.
  49.  */
  50. #define _wait_for(COND, MS, W) ({ \
  51.     unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS);  \
  52.         int ret__ = 0;                                                  \
  53.         while (!(COND)) {                                               \
  54.         if (time_after(GetTimerTicks(), timeout__)) {          \
  55.                         if (!(COND))                                    \
  56.                         ret__ = -ETIMEDOUT;                             \
  57.                         break;                                          \
  58.                 }                                                       \
  59.                 if (W )  {                              \
  60.          msleep(W); \
  61.                 } else {                                                \
  62.                         cpu_relax();                                    \
  63.                 }                                                       \
  64.         }                                                               \
  65.         ret__;                                                          \
  66. })
  67.  
  68. #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  69. #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  70. #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  71.                                                DIV_ROUND_UP((US), 1000), 0)
  72.  
  73. #define KHz(x) (1000*x)
  74. #define MHz(x) KHz(1000*x)
  75.  
  76. /*
  77.  * Display related stuff
  78.  */
  79.  
  80. /* store information about an Ixxx DVO */
  81. /* The i830->i865 use multiple DVOs with multiple i2cs */
  82. /* the i915, i945 have a single sDVO i2c bus - which is different */
  83. #define MAX_OUTPUTS 6
  84. /* maximum connectors per crtcs in the mode set */
  85. #define INTELFB_CONN_LIMIT 4
  86.  
  87. #define INTEL_I2C_BUS_DVO 1
  88. #define INTEL_I2C_BUS_SDVO 2
  89.  
  90. /* these are outputs from the chip - integrated only
  91.    external chips are via DVO or SDVO output */
  92. #define INTEL_OUTPUT_UNUSED 0
  93. #define INTEL_OUTPUT_ANALOG 1
  94. #define INTEL_OUTPUT_DVO 2
  95. #define INTEL_OUTPUT_SDVO 3
  96. #define INTEL_OUTPUT_LVDS 4
  97. #define INTEL_OUTPUT_TVOUT 5
  98. #define INTEL_OUTPUT_HDMI 6
  99. #define INTEL_OUTPUT_DISPLAYPORT 7
  100. #define INTEL_OUTPUT_EDP 8
  101. #define INTEL_OUTPUT_UNKNOWN 9
  102.  
  103. #define INTEL_DVO_CHIP_NONE 0
  104. #define INTEL_DVO_CHIP_LVDS 1
  105. #define INTEL_DVO_CHIP_TMDS 2
  106. #define INTEL_DVO_CHIP_TVOUT 4
  107.  
  108. struct intel_framebuffer {
  109.         struct drm_framebuffer base;
  110.         struct drm_i915_gem_object *obj;
  111. };
  112.  
  113. struct intel_fbdev {
  114.         struct drm_fb_helper helper;
  115.         struct intel_framebuffer ifb;
  116.         struct list_head fbdev_list;
  117.         struct drm_display_mode *our_mode;
  118. };
  119.  
  120. struct intel_encoder {
  121.         struct drm_encoder base;
  122.         /*
  123.          * The new crtc this encoder will be driven from. Only differs from
  124.          * base->crtc while a modeset is in progress.
  125.          */
  126.         struct intel_crtc *new_crtc;
  127.  
  128.         int type;
  129.         /*
  130.          * Intel hw has only one MUX where encoders could be clone, hence a
  131.          * simple flag is enough to compute the possible_clones mask.
  132.          */
  133.         bool cloneable;
  134.         bool connectors_active;
  135.         void (*hot_plug)(struct intel_encoder *);
  136.         bool (*compute_config)(struct intel_encoder *,
  137.                                struct intel_crtc_config *);
  138.         void (*pre_pll_enable)(struct intel_encoder *);
  139.         void (*pre_enable)(struct intel_encoder *);
  140.         void (*enable)(struct intel_encoder *);
  141.         void (*mode_set)(struct intel_encoder *intel_encoder);
  142.         void (*disable)(struct intel_encoder *);
  143.         void (*post_disable)(struct intel_encoder *);
  144.         /* Read out the current hw state of this connector, returning true if
  145.          * the encoder is active. If the encoder is enabled it also set the pipe
  146.          * it is connected to in the pipe parameter. */
  147.         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
  148.         /* Reconstructs the equivalent mode flags for the current hardware
  149.          * state. This must be called _after_ display->get_pipe_config has
  150.          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
  151.          * be set correctly before calling this function. */
  152.         void (*get_config)(struct intel_encoder *,
  153.                            struct intel_crtc_config *pipe_config);
  154.         int crtc_mask;
  155.         enum hpd_pin hpd_pin;
  156. };
  157.  
  158. struct intel_panel {
  159.         struct drm_display_mode *fixed_mode;
  160.         int fitting_mode;
  161. };
  162.  
  163. struct intel_connector {
  164.         struct drm_connector base;
  165.         /*
  166.          * The fixed encoder this connector is connected to.
  167.          */
  168.         struct intel_encoder *encoder;
  169.  
  170.         /*
  171.          * The new encoder this connector will be driven. Only differs from
  172.          * encoder while a modeset is in progress.
  173.          */
  174.         struct intel_encoder *new_encoder;
  175.  
  176.         /* Reads out the current hw, returning true if the connector is enabled
  177.          * and active (i.e. dpms ON state). */
  178.         bool (*get_hw_state)(struct intel_connector *);
  179.  
  180.         /* Panel info for eDP and LVDS */
  181.         struct intel_panel panel;
  182.  
  183.         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
  184.         struct edid *edid;
  185.  
  186.         /* since POLL and HPD connectors may use the same HPD line keep the native
  187.            state of connector->polled in case hotplug storm detection changes it */
  188.         u8 polled;
  189. };
  190.  
  191. typedef struct dpll {
  192.         /* given values */
  193.         int n;
  194.         int m1, m2;
  195.         int p1, p2;
  196.         /* derived values */
  197.         int     dot;
  198.         int     vco;
  199.         int     m;
  200.         int     p;
  201. } intel_clock_t;
  202.  
  203. struct intel_crtc_config {
  204.         /**
  205.          * quirks - bitfield with hw state readout quirks
  206.          *
  207.          * For various reasons the hw state readout code might not be able to
  208.          * completely faithfully read out the current state. These cases are
  209.          * tracked with quirk flags so that fastboot and state checker can act
  210.          * accordingly.
  211.          */
  212. #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
  213.         unsigned long quirks;
  214.  
  215.         struct drm_display_mode requested_mode;
  216.         struct drm_display_mode adjusted_mode;
  217.         /* Whether to set up the PCH/FDI. Note that we never allow sharing
  218.          * between pch encoders and cpu encoders. */
  219.         bool has_pch_encoder;
  220.  
  221.         /* CPU Transcoder for the pipe. Currently this can only differ from the
  222.          * pipe on Haswell (where we have a special eDP transcoder). */
  223.         enum transcoder cpu_transcoder;
  224.  
  225.         /*
  226.          * Use reduced/limited/broadcast rbg range, compressing from the full
  227.          * range fed into the crtcs.
  228.          */
  229.         bool limited_color_range;
  230.  
  231.         /* DP has a bunch of special case unfortunately, so mark the pipe
  232.          * accordingly. */
  233.         bool has_dp_encoder;
  234.  
  235.         /*
  236.          * Enable dithering, used when the selected pipe bpp doesn't match the
  237.          * plane bpp.
  238.          */
  239.         bool dither;
  240.  
  241.         /* Controls for the clock computation, to override various stages. */
  242.         bool clock_set;
  243.  
  244.         /* SDVO TV has a bunch of special case. To make multifunction encoders
  245.          * work correctly, we need to track this at runtime.*/
  246.         bool sdvo_tv_clock;
  247.  
  248.         /*
  249.          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
  250.          * required. This is set in the 2nd loop of calling encoder's
  251.          * ->compute_config if the first pick doesn't work out.
  252.          */
  253.         bool bw_constrained;
  254.  
  255.         /* Settings for the intel dpll used on pretty much everything but
  256.          * haswell. */
  257.         struct dpll dpll;
  258.  
  259.         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
  260.         enum intel_dpll_id shared_dpll;
  261.  
  262.         /* Actual register state of the dpll, for shared dpll cross-checking. */
  263.         struct intel_dpll_hw_state dpll_hw_state;
  264.  
  265.         int pipe_bpp;
  266.         struct intel_link_m_n dp_m_n;
  267.  
  268.         /*
  269.          * Frequence the dpll for the port should run at. Differs from the
  270.          * adjusted dotclock e.g. for DP or 12bpc hdmi mode.
  271.          */
  272.         int port_clock;
  273.  
  274.         /* Used by SDVO (and if we ever fix it, HDMI). */
  275.         unsigned pixel_multiplier;
  276.  
  277.         /* Panel fitter controls for gen2-gen4 + VLV */
  278.         struct {
  279.                 u32 control;
  280.                 u32 pgm_ratios;
  281.                 u32 lvds_border_bits;
  282.         } gmch_pfit;
  283.  
  284.         /* Panel fitter placement and size for Ironlake+ */
  285.         struct {
  286.                 u32 pos;
  287.                 u32 size;
  288.                 bool enabled;
  289.         } pch_pfit;
  290.  
  291.         /* FDI configuration, only valid if has_pch_encoder is set. */
  292.         int fdi_lanes;
  293.         struct intel_link_m_n fdi_m_n;
  294.  
  295.         bool ips_enabled;
  296. };
  297.  
  298. struct intel_crtc {
  299.         struct drm_crtc base;
  300.         enum pipe pipe;
  301.         enum plane plane;
  302.         u8 lut_r[256], lut_g[256], lut_b[256];
  303.         /*
  304.          * Whether the crtc and the connected output pipeline is active. Implies
  305.          * that crtc->enabled is set, i.e. the current mode configuration has
  306.          * some outputs connected to this crtc.
  307.          */
  308.         bool active;
  309.         bool eld_vld;
  310.         bool primary_disabled; /* is the crtc obscured by a plane? */
  311.         bool lowfreq_avail;
  312.         struct intel_overlay *overlay;
  313.         struct intel_unpin_work *unpin_work;
  314.  
  315.         atomic_t unpin_work_count;
  316.  
  317.         /* Display surface base address adjustement for pageflips. Note that on
  318.          * gen4+ this only adjusts up to a tile, offsets within a tile are
  319.          * handled in the hw itself (with the TILEOFF register). */
  320.         unsigned long dspaddr_offset;
  321.  
  322.         struct drm_i915_gem_object *cursor_bo;
  323.         uint32_t cursor_addr;
  324.         int16_t cursor_x, cursor_y;
  325.         int16_t cursor_width, cursor_height;
  326.         bool cursor_visible;
  327.  
  328.         struct intel_crtc_config config;
  329.  
  330.         uint32_t ddi_pll_sel;
  331.  
  332.         /* reset counter value when the last flip was submitted */
  333.         unsigned int reset_counter;
  334.  
  335.         /* Access to these should be protected by dev_priv->irq_lock. */
  336.         bool cpu_fifo_underrun_disabled;
  337.         bool pch_fifo_underrun_disabled;
  338. };
  339.  
  340. struct intel_plane_wm_parameters {
  341.         uint32_t horiz_pixels;
  342.         uint8_t bytes_per_pixel;
  343.         bool enabled;
  344.         bool scaled;
  345. };
  346.  
  347. struct intel_plane {
  348.         struct drm_plane base;
  349.         int plane;
  350.         enum pipe pipe;
  351.         struct drm_i915_gem_object *obj;
  352.         bool can_scale;
  353.         int max_downscale;
  354.         u32 lut_r[1024], lut_g[1024], lut_b[1024];
  355.         int crtc_x, crtc_y;
  356.         unsigned int crtc_w, crtc_h;
  357.         uint32_t src_x, src_y;
  358.         uint32_t src_w, src_h;
  359.  
  360.         /* Since we need to change the watermarks before/after
  361.          * enabling/disabling the planes, we need to store the parameters here
  362.          * as the other pieces of the struct may not reflect the values we want
  363.          * for the watermark calculations. Currently only Haswell uses this.
  364.          */
  365.         struct intel_plane_wm_parameters wm;
  366.  
  367.         void (*update_plane)(struct drm_plane *plane,
  368.                              struct drm_crtc *crtc,
  369.                              struct drm_framebuffer *fb,
  370.                              struct drm_i915_gem_object *obj,
  371.                              int crtc_x, int crtc_y,
  372.                              unsigned int crtc_w, unsigned int crtc_h,
  373.                              uint32_t x, uint32_t y,
  374.                              uint32_t src_w, uint32_t src_h);
  375.         void (*disable_plane)(struct drm_plane *plane,
  376.                               struct drm_crtc *crtc);
  377.         int (*update_colorkey)(struct drm_plane *plane,
  378.                                struct drm_intel_sprite_colorkey *key);
  379.         void (*get_colorkey)(struct drm_plane *plane,
  380.                              struct drm_intel_sprite_colorkey *key);
  381. };
  382.  
  383. struct intel_watermark_params {
  384.         unsigned long fifo_size;
  385.         unsigned long max_wm;
  386.         unsigned long default_wm;
  387.         unsigned long guard_size;
  388.         unsigned long cacheline_size;
  389. };
  390.  
  391. struct cxsr_latency {
  392.         int is_desktop;
  393.         int is_ddr3;
  394.         unsigned long fsb_freq;
  395.         unsigned long mem_freq;
  396.         unsigned long display_sr;
  397.         unsigned long display_hpll_disable;
  398.         unsigned long cursor_sr;
  399.         unsigned long cursor_hpll_disable;
  400. };
  401.  
  402. #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
  403. #define to_intel_connector(x) container_of(x, struct intel_connector, base)
  404. #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
  405. #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
  406. #define to_intel_plane(x) container_of(x, struct intel_plane, base)
  407.  
  408. struct intel_hdmi {
  409.         u32 hdmi_reg;
  410.         int ddc_bus;
  411.         uint32_t color_range;
  412.         bool color_range_auto;
  413.         bool has_hdmi_sink;
  414.         bool has_audio;
  415.         enum hdmi_force_audio force_audio;
  416.         bool rgb_quant_range_selectable;
  417.         void (*write_infoframe)(struct drm_encoder *encoder,
  418.                                 enum hdmi_infoframe_type type,
  419.                                 const uint8_t *frame, ssize_t len);
  420.         void (*set_infoframes)(struct drm_encoder *encoder,
  421.                                struct drm_display_mode *adjusted_mode);
  422. };
  423.  
  424. #define DP_MAX_DOWNSTREAM_PORTS         0x10
  425. #define DP_LINK_CONFIGURATION_SIZE      9
  426.  
  427. struct intel_dp {
  428.         uint32_t output_reg;
  429.         uint32_t aux_ch_ctl_reg;
  430.         uint32_t DP;
  431.         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  432.         bool has_audio;
  433.         enum hdmi_force_audio force_audio;
  434.         uint32_t color_range;
  435.         bool color_range_auto;
  436.         uint8_t link_bw;
  437.         uint8_t lane_count;
  438.         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  439.         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
  440.         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
  441.         struct i2c_adapter adapter;
  442.         struct i2c_algo_dp_aux_data algo;
  443.         uint8_t train_set[4];
  444.         int panel_power_up_delay;
  445.         int panel_power_down_delay;
  446.         int panel_power_cycle_delay;
  447.         int backlight_on_delay;
  448.         int backlight_off_delay;
  449.         struct delayed_work panel_vdd_work;
  450.         bool want_panel_vdd;
  451.         bool psr_setup_done;
  452.         struct intel_connector *attached_connector;
  453. };
  454.  
  455. struct intel_digital_port {
  456.         struct intel_encoder base;
  457.         enum port port;
  458.         u32 saved_port_bits;
  459.         struct intel_dp dp;
  460.         struct intel_hdmi hdmi;
  461. };
  462.  
  463. static inline int
  464. vlv_dport_to_channel(struct intel_digital_port *dport)
  465. {
  466.         switch (dport->port) {
  467.         case PORT_B:
  468.                 return 0;
  469.         case PORT_C:
  470.                 return 1;
  471.         default:
  472.                 BUG();
  473.         }
  474. }
  475.  
  476. static inline struct drm_crtc *
  477. intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
  478. {
  479.         struct drm_i915_private *dev_priv = dev->dev_private;
  480.         return dev_priv->pipe_to_crtc_mapping[pipe];
  481. }
  482.  
  483. static inline struct drm_crtc *
  484. intel_get_crtc_for_plane(struct drm_device *dev, int plane)
  485. {
  486.         struct drm_i915_private *dev_priv = dev->dev_private;
  487.         return dev_priv->plane_to_crtc_mapping[plane];
  488. }
  489.  
  490. struct intel_unpin_work {
  491.         struct work_struct work;
  492.         struct drm_crtc *crtc;
  493.         struct drm_i915_gem_object *old_fb_obj;
  494.         struct drm_i915_gem_object *pending_flip_obj;
  495.         struct drm_pending_vblank_event *event;
  496.         atomic_t pending;
  497. #define INTEL_FLIP_INACTIVE     0
  498. #define INTEL_FLIP_PENDING      1
  499. #define INTEL_FLIP_COMPLETE     2
  500.         bool enable_stall_check;
  501. };
  502.  
  503. int intel_pch_rawclk(struct drm_device *dev);
  504.  
  505. int intel_connector_update_modes(struct drm_connector *connector,
  506.                                 struct edid *edid);
  507. int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
  508.  
  509. extern void intel_attach_force_audio_property(struct drm_connector *connector);
  510. extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
  511.  
  512. extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  513. extern void intel_crt_init(struct drm_device *dev);
  514. extern void intel_hdmi_init(struct drm_device *dev,
  515.                             int hdmi_reg, enum port port);
  516. extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  517.                                       struct intel_connector *intel_connector);
  518. extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
  519. extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  520.                                       struct intel_crtc_config *pipe_config);
  521. extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
  522.                             bool is_sdvob);
  523. extern void intel_dvo_init(struct drm_device *dev);
  524. extern void intel_tv_init(struct drm_device *dev);
  525. extern void intel_mark_busy(struct drm_device *dev);
  526. extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  527.                                struct intel_ring_buffer *ring);
  528. extern void intel_mark_idle(struct drm_device *dev);
  529. extern void intel_lvds_init(struct drm_device *dev);
  530. extern bool intel_is_dual_link_lvds(struct drm_device *dev);
  531. extern void intel_dp_init(struct drm_device *dev, int output_reg,
  532.                           enum port port);
  533. extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  534.                                     struct intel_connector *intel_connector);
  535. extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
  536. extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
  537. extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  538. extern void intel_dp_stop_link_train(struct intel_dp *intel_dp);
  539. extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
  540. extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
  541. extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
  542. extern bool intel_dp_compute_config(struct intel_encoder *encoder,
  543.                                     struct intel_crtc_config *pipe_config);
  544. extern bool intel_dpd_is_edp(struct drm_device *dev);
  545. extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
  546. extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
  547. extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
  548. extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
  549. extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
  550. extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
  551. extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
  552. extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  553.                                       enum plane plane);
  554.  
  555. /* intel_panel.c */
  556. extern int intel_panel_init(struct intel_panel *panel,
  557.                             struct drm_display_mode *fixed_mode);
  558. extern void intel_panel_fini(struct intel_panel *panel);
  559.  
  560. extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  561.                                    struct drm_display_mode *adjusted_mode);
  562. extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
  563.                                     struct intel_crtc_config *pipe_config,
  564.                                     int fitting_mode);
  565. extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
  566.                                      struct intel_crtc_config *pipe_config,
  567.                                      int fitting_mode);
  568. extern void intel_panel_set_backlight(struct drm_device *dev,
  569.                                       u32 level, u32 max);
  570. extern int intel_panel_setup_backlight(struct drm_connector *connector);
  571. extern void intel_panel_enable_backlight(struct drm_device *dev,
  572.                                          enum pipe pipe);
  573. extern void intel_panel_disable_backlight(struct drm_device *dev);
  574. extern void intel_panel_destroy_backlight(struct drm_device *dev);
  575. extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
  576.  
  577. struct intel_set_config {
  578.         struct drm_encoder **save_connector_encoders;
  579.         struct drm_crtc **save_encoder_crtcs;
  580.  
  581.         bool fb_changed;
  582.         bool mode_changed;
  583. };
  584.  
  585. extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
  586. extern void intel_crtc_load_lut(struct drm_crtc *crtc);
  587. extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
  588. extern void intel_encoder_destroy(struct drm_encoder *encoder);
  589. extern void intel_connector_dpms(struct drm_connector *, int mode);
  590. extern bool intel_connector_get_hw_state(struct intel_connector *connector);
  591. extern void intel_modeset_check_state(struct drm_device *dev);
  592. extern void intel_plane_restore(struct drm_plane *plane);
  593. extern void intel_plane_disable(struct drm_plane *plane);
  594.  
  595.  
  596. static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
  597. {
  598.         return to_intel_connector(connector)->encoder;
  599. }
  600.  
  601. static inline struct intel_digital_port *
  602. enc_to_dig_port(struct drm_encoder *encoder)
  603. {
  604.         return container_of(encoder, struct intel_digital_port, base.base);
  605. }
  606.  
  607. static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  608. {
  609.         return &enc_to_dig_port(encoder)->dp;
  610. }
  611.  
  612. static inline struct intel_digital_port *
  613. dp_to_dig_port(struct intel_dp *intel_dp)
  614. {
  615.         return container_of(intel_dp, struct intel_digital_port, dp);
  616. }
  617.  
  618. static inline struct intel_digital_port *
  619. hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
  620. {
  621.         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
  622. }
  623.  
  624. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  625.                                 struct intel_digital_port *port);
  626.  
  627. extern void intel_connector_attach_encoder(struct intel_connector *connector,
  628.                                            struct intel_encoder *encoder);
  629. extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
  630.  
  631. extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  632.                                                     struct drm_crtc *crtc);
  633. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  634.                                 struct drm_file *file_priv);
  635. extern enum transcoder
  636. intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  637.                              enum pipe pipe);
  638. extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
  639. extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
  640. extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
  641. extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
  642.  
  643. struct intel_load_detect_pipe {
  644.         struct drm_framebuffer *release_fb;
  645.         bool load_detect_temp;
  646.         int dpms_mode;
  647. };
  648. extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
  649.                                        struct drm_display_mode *mode,
  650.                                        struct intel_load_detect_pipe *old);
  651. extern void intel_release_load_detect_pipe(struct drm_connector *connector,
  652.                                            struct intel_load_detect_pipe *old);
  653.  
  654. extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  655.                                     u16 blue, int regno);
  656. extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  657.                                     u16 *blue, int regno);
  658.  
  659. extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
  660.                                       struct drm_i915_gem_object *obj,
  661.                                       struct intel_ring_buffer *pipelined);
  662. extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
  663.  
  664. extern int intel_framebuffer_init(struct drm_device *dev,
  665.                                   struct intel_framebuffer *ifb,
  666.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  667.                                   struct drm_i915_gem_object *obj);
  668. extern void intel_framebuffer_fini(struct intel_framebuffer *fb);
  669. extern int intel_fbdev_init(struct drm_device *dev);
  670. extern void intel_fbdev_initial_config(struct drm_device *dev);
  671. extern void intel_fbdev_fini(struct drm_device *dev);
  672. extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
  673. extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
  674. extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
  675. extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
  676.  
  677. extern void intel_setup_overlay(struct drm_device *dev);
  678. extern void intel_cleanup_overlay(struct drm_device *dev);
  679. extern int intel_overlay_switch_off(struct intel_overlay *overlay);
  680. extern int intel_overlay_put_image(struct drm_device *dev, void *data,
  681.                                    struct drm_file *file_priv);
  682. extern int intel_overlay_attrs(struct drm_device *dev, void *data,
  683.                                struct drm_file *file_priv);
  684.  
  685. extern void intel_fb_output_poll_changed(struct drm_device *dev);
  686. extern void intel_fb_restore_mode(struct drm_device *dev);
  687.  
  688. struct intel_shared_dpll *
  689. intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
  690.  
  691. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  692.                         struct intel_shared_dpll *pll,
  693.                         bool state);
  694. #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
  695. #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
  696. void assert_pll(struct drm_i915_private *dev_priv,
  697.                 enum pipe pipe, bool state);
  698. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  699. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  700. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  701.                        enum pipe pipe, bool state);
  702. #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
  703. #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
  704. extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  705.                         bool state);
  706. #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
  707. #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
  708.  
  709. extern void intel_init_clock_gating(struct drm_device *dev);
  710. extern void intel_suspend_hw(struct drm_device *dev);
  711. extern void intel_write_eld(struct drm_encoder *encoder,
  712.                             struct drm_display_mode *mode);
  713. extern void intel_prepare_ddi(struct drm_device *dev);
  714. extern void hsw_fdi_link_train(struct drm_crtc *crtc);
  715. extern void intel_ddi_init(struct drm_device *dev, enum port port);
  716.  
  717. /* For use by IVB LP watermark workaround in intel_sprite.c */
  718. extern void intel_update_watermarks(struct drm_device *dev);
  719. extern void intel_update_sprite_watermarks(struct drm_plane *plane,
  720.                                            struct drm_crtc *crtc,
  721.                                            uint32_t sprite_width, int pixel_size,
  722.                                            bool enabled, bool scaled);
  723.  
  724. extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  725.                                                     unsigned int tiling_mode,
  726.                                                       unsigned int bpp,
  727.                                                       unsigned int pitch);
  728.  
  729. extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  730.                                      struct drm_file *file_priv);
  731. extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  732.                                      struct drm_file *file_priv);
  733.  
  734. /* Power-related functions, located in intel_pm.c */
  735. extern void intel_init_pm(struct drm_device *dev);
  736. /* FBC */
  737. extern bool intel_fbc_enabled(struct drm_device *dev);
  738. extern void intel_update_fbc(struct drm_device *dev);
  739. /* IPS */
  740. extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
  741. extern void intel_gpu_ips_teardown(void);
  742.  
  743. /* Power well */
  744. extern int i915_init_power_well(struct drm_device *dev);
  745. extern void i915_remove_power_well(struct drm_device *dev);
  746.  
  747. extern bool intel_display_power_enabled(struct drm_device *dev,
  748.                                         enum intel_display_power_domain domain);
  749. extern void intel_init_power_well(struct drm_device *dev);
  750. extern void intel_set_power_well(struct drm_device *dev, bool enable);
  751. extern void intel_enable_gt_powersave(struct drm_device *dev);
  752. extern void intel_disable_gt_powersave(struct drm_device *dev);
  753. extern void ironlake_teardown_rc6(struct drm_device *dev);
  754. void gen6_update_ring_freq(struct drm_device *dev);
  755.  
  756. extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
  757.                                    enum pipe *pipe);
  758. extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
  759. extern void intel_ddi_pll_init(struct drm_device *dev);
  760. extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
  761. extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
  762.                                               enum transcoder cpu_transcoder);
  763. extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
  764. extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
  765. extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
  766. extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc);
  767. extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
  768. extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
  769. extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
  770. extern bool
  771. intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
  772. extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
  773. extern void intel_ddi_get_config(struct intel_encoder *encoder,
  774.                                  struct intel_crtc_config *pipe_config);
  775.  
  776. extern void intel_display_handle_reset(struct drm_device *dev);
  777. extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
  778.                                                   enum pipe pipe,
  779.                                                   bool enable);
  780. extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
  781.                                                  enum transcoder pch_transcoder,
  782.                                                  bool enable);
  783.  
  784. extern void intel_edp_psr_enable(struct intel_dp *intel_dp);
  785. extern void intel_edp_psr_disable(struct intel_dp *intel_dp);
  786. extern void intel_edp_psr_update(struct drm_device *dev);
  787. extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  788.                               bool switch_to_fclk, bool allow_power_down);
  789. extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv);
  790. extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  791. extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv,
  792.                                uint32_t mask);
  793. extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
  794. extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv,
  795.                                uint32_t mask);
  796. extern void hsw_enable_pc8_work(struct work_struct *__work);
  797. extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv);
  798. extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv);
  799. extern void hsw_pc8_disable_interrupts(struct drm_device *dev);
  800. extern void hsw_pc8_restore_interrupts(struct drm_device *dev);
  801. extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
  802. extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
  803.  
  804. #endif /* __INTEL_DRV_H__ */
  805.