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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/dmi.h>
  28. #include <linux/module.h>
  29. #include <linux/input.h>
  30. #include <linux/i2c.h>
  31. #include <linux/kernel.h>
  32. #include <linux/slab.h>
  33. #include <linux/vgaarb.h>
  34. #include <drm/drm_edid.h>
  35. #include <drm/drmP.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39. #include "i915_trace.h"
  40. #include <drm/drm_atomic.h>
  41. #include <drm/drm_atomic_helper.h>
  42. #include <drm/drm_dp_helper.h>
  43. #include <drm/drm_crtc_helper.h>
  44. #include <drm/drm_plane_helper.h>
  45. #include <drm/drm_rect.h>
  46. #include <linux/dma_remapping.h>
  47.  
  48. /* Primary plane formats for gen <= 3 */
  49. static const uint32_t i8xx_primary_formats[] = {
  50.         DRM_FORMAT_C8,
  51.         DRM_FORMAT_RGB565,
  52.         DRM_FORMAT_XRGB1555,
  53.         DRM_FORMAT_XRGB8888,
  54. };
  55.  
  56. /* Primary plane formats for gen >= 4 */
  57. static const uint32_t i965_primary_formats[] = {
  58.         DRM_FORMAT_C8,
  59.         DRM_FORMAT_RGB565,
  60.         DRM_FORMAT_XRGB8888,
  61.         DRM_FORMAT_XBGR8888,
  62.         DRM_FORMAT_XRGB2101010,
  63.         DRM_FORMAT_XBGR2101010,
  64. };
  65.  
  66. static const uint32_t skl_primary_formats[] = {
  67.         DRM_FORMAT_C8,
  68.         DRM_FORMAT_RGB565,
  69.         DRM_FORMAT_XRGB8888,
  70.         DRM_FORMAT_XBGR8888,
  71.         DRM_FORMAT_ARGB8888,
  72.         DRM_FORMAT_ABGR8888,
  73.         DRM_FORMAT_XRGB2101010,
  74.         DRM_FORMAT_XBGR2101010,
  75.         DRM_FORMAT_YUYV,
  76.         DRM_FORMAT_YVYU,
  77.         DRM_FORMAT_UYVY,
  78.         DRM_FORMAT_VYUY,
  79. };
  80.  
  81. /* Cursor formats */
  82. static const uint32_t intel_cursor_formats[] = {
  83.         DRM_FORMAT_ARGB8888,
  84. };
  85.  
  86. void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  87.  
  88. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  89.                                 struct intel_crtc_state *pipe_config);
  90. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  91.                                    struct intel_crtc_state *pipe_config);
  92.  
  93. static int intel_framebuffer_init(struct drm_device *dev,
  94.                                   struct intel_framebuffer *ifb,
  95.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  96.                                   struct drm_i915_gem_object *obj);
  97. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  98. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
  99. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  100.                                          struct intel_link_m_n *m_n,
  101.                                          struct intel_link_m_n *m2_n2);
  102. static void ironlake_set_pipeconf(struct drm_crtc *crtc);
  103. static void haswell_set_pipeconf(struct drm_crtc *crtc);
  104. static void intel_set_pipe_csc(struct drm_crtc *crtc);
  105. static void vlv_prepare_pll(struct intel_crtc *crtc,
  106.                             const struct intel_crtc_state *pipe_config);
  107. static void chv_prepare_pll(struct intel_crtc *crtc,
  108.                             const struct intel_crtc_state *pipe_config);
  109. static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
  110. static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
  111. static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
  112.         struct intel_crtc_state *crtc_state);
  113. static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
  114.                            int num_connectors);
  115. static void skylake_pfit_enable(struct intel_crtc *crtc);
  116. static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
  117. static void ironlake_pfit_enable(struct intel_crtc *crtc);
  118. static void intel_modeset_setup_hw_state(struct drm_device *dev);
  119. static void intel_pre_disable_primary(struct drm_crtc *crtc);
  120.  
  121. typedef struct {
  122.         int     min, max;
  123. } intel_range_t;
  124.  
  125. typedef struct {
  126.         int     dot_limit;
  127.         int     p2_slow, p2_fast;
  128. } intel_p2_t;
  129.  
  130. typedef struct intel_limit intel_limit_t;
  131. struct intel_limit {
  132.         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  133.         intel_p2_t          p2;
  134. };
  135.  
  136. /* returns HPLL frequency in kHz */
  137. static int valleyview_get_vco(struct drm_i915_private *dev_priv)
  138. {
  139.         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
  140.  
  141.         /* Obtain SKU information */
  142.         mutex_lock(&dev_priv->sb_lock);
  143.         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
  144.                 CCK_FUSE_HPLL_FREQ_MASK;
  145.         mutex_unlock(&dev_priv->sb_lock);
  146.  
  147.         return vco_freq[hpll_freq] * 1000;
  148. }
  149.  
  150. static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
  151.                                   const char *name, u32 reg)
  152. {
  153.         u32 val;
  154.         int divider;
  155.  
  156.         if (dev_priv->hpll_freq == 0)
  157.                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
  158.  
  159.         mutex_lock(&dev_priv->sb_lock);
  160.         val = vlv_cck_read(dev_priv, reg);
  161.         mutex_unlock(&dev_priv->sb_lock);
  162.  
  163.         divider = val & CCK_FREQUENCY_VALUES;
  164.  
  165.         WARN((val & CCK_FREQUENCY_STATUS) !=
  166.              (divider << CCK_FREQUENCY_STATUS_SHIFT),
  167.              "%s change in progress\n", name);
  168.  
  169.         return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
  170. }
  171.  
  172. int
  173. intel_pch_rawclk(struct drm_device *dev)
  174. {
  175.         struct drm_i915_private *dev_priv = dev->dev_private;
  176.  
  177.         WARN_ON(!HAS_PCH_SPLIT(dev));
  178.  
  179.         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  180. }
  181.  
  182. /* hrawclock is 1/4 the FSB frequency */
  183. int intel_hrawclk(struct drm_device *dev)
  184. {
  185.         struct drm_i915_private *dev_priv = dev->dev_private;
  186.         uint32_t clkcfg;
  187.  
  188.         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
  189.         if (IS_VALLEYVIEW(dev))
  190.                 return 200;
  191.  
  192.         clkcfg = I915_READ(CLKCFG);
  193.         switch (clkcfg & CLKCFG_FSB_MASK) {
  194.         case CLKCFG_FSB_400:
  195.                 return 100;
  196.         case CLKCFG_FSB_533:
  197.                 return 133;
  198.         case CLKCFG_FSB_667:
  199.                 return 166;
  200.         case CLKCFG_FSB_800:
  201.                 return 200;
  202.         case CLKCFG_FSB_1067:
  203.                 return 266;
  204.         case CLKCFG_FSB_1333:
  205.                 return 333;
  206.         /* these two are just a guess; one of them might be right */
  207.         case CLKCFG_FSB_1600:
  208.         case CLKCFG_FSB_1600_ALT:
  209.                 return 400;
  210.         default:
  211.                 return 133;
  212.         }
  213. }
  214.  
  215. static void intel_update_czclk(struct drm_i915_private *dev_priv)
  216. {
  217.         if (!IS_VALLEYVIEW(dev_priv))
  218.                 return;
  219.  
  220.         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
  221.                                                       CCK_CZ_CLOCK_CONTROL);
  222.  
  223.         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
  224. }
  225.  
  226. static inline u32 /* units of 100MHz */
  227. intel_fdi_link_freq(struct drm_device *dev)
  228. {
  229.         if (IS_GEN5(dev)) {
  230.                 struct drm_i915_private *dev_priv = dev->dev_private;
  231.                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  232.         } else
  233.                 return 27;
  234. }
  235.  
  236. static const intel_limit_t intel_limits_i8xx_dac = {
  237.         .dot = { .min = 25000, .max = 350000 },
  238.         .vco = { .min = 908000, .max = 1512000 },
  239.         .n = { .min = 2, .max = 16 },
  240.         .m = { .min = 96, .max = 140 },
  241.         .m1 = { .min = 18, .max = 26 },
  242.         .m2 = { .min = 6, .max = 16 },
  243.         .p = { .min = 4, .max = 128 },
  244.         .p1 = { .min = 2, .max = 33 },
  245.         .p2 = { .dot_limit = 165000,
  246.                 .p2_slow = 4, .p2_fast = 2 },
  247. };
  248.  
  249. static const intel_limit_t intel_limits_i8xx_dvo = {
  250.         .dot = { .min = 25000, .max = 350000 },
  251.         .vco = { .min = 908000, .max = 1512000 },
  252.         .n = { .min = 2, .max = 16 },
  253.         .m = { .min = 96, .max = 140 },
  254.         .m1 = { .min = 18, .max = 26 },
  255.         .m2 = { .min = 6, .max = 16 },
  256.         .p = { .min = 4, .max = 128 },
  257.         .p1 = { .min = 2, .max = 33 },
  258.         .p2 = { .dot_limit = 165000,
  259.                 .p2_slow = 4, .p2_fast = 4 },
  260. };
  261.  
  262. static const intel_limit_t intel_limits_i8xx_lvds = {
  263.         .dot = { .min = 25000, .max = 350000 },
  264.         .vco = { .min = 908000, .max = 1512000 },
  265.         .n = { .min = 2, .max = 16 },
  266.         .m = { .min = 96, .max = 140 },
  267.         .m1 = { .min = 18, .max = 26 },
  268.         .m2 = { .min = 6, .max = 16 },
  269.         .p = { .min = 4, .max = 128 },
  270.         .p1 = { .min = 1, .max = 6 },
  271.         .p2 = { .dot_limit = 165000,
  272.                 .p2_slow = 14, .p2_fast = 7 },
  273. };
  274.  
  275. static const intel_limit_t intel_limits_i9xx_sdvo = {
  276.         .dot = { .min = 20000, .max = 400000 },
  277.         .vco = { .min = 1400000, .max = 2800000 },
  278.         .n = { .min = 1, .max = 6 },
  279.         .m = { .min = 70, .max = 120 },
  280.         .m1 = { .min = 8, .max = 18 },
  281.         .m2 = { .min = 3, .max = 7 },
  282.         .p = { .min = 5, .max = 80 },
  283.         .p1 = { .min = 1, .max = 8 },
  284.         .p2 = { .dot_limit = 200000,
  285.                 .p2_slow = 10, .p2_fast = 5 },
  286. };
  287.  
  288. static const intel_limit_t intel_limits_i9xx_lvds = {
  289.         .dot = { .min = 20000, .max = 400000 },
  290.         .vco = { .min = 1400000, .max = 2800000 },
  291.         .n = { .min = 1, .max = 6 },
  292.         .m = { .min = 70, .max = 120 },
  293.         .m1 = { .min = 8, .max = 18 },
  294.         .m2 = { .min = 3, .max = 7 },
  295.         .p = { .min = 7, .max = 98 },
  296.         .p1 = { .min = 1, .max = 8 },
  297.         .p2 = { .dot_limit = 112000,
  298.                 .p2_slow = 14, .p2_fast = 7 },
  299. };
  300.  
  301.  
  302. static const intel_limit_t intel_limits_g4x_sdvo = {
  303.         .dot = { .min = 25000, .max = 270000 },
  304.         .vco = { .min = 1750000, .max = 3500000},
  305.         .n = { .min = 1, .max = 4 },
  306.         .m = { .min = 104, .max = 138 },
  307.         .m1 = { .min = 17, .max = 23 },
  308.         .m2 = { .min = 5, .max = 11 },
  309.         .p = { .min = 10, .max = 30 },
  310.         .p1 = { .min = 1, .max = 3},
  311.         .p2 = { .dot_limit = 270000,
  312.                 .p2_slow = 10,
  313.                 .p2_fast = 10
  314.         },
  315. };
  316.  
  317. static const intel_limit_t intel_limits_g4x_hdmi = {
  318.         .dot = { .min = 22000, .max = 400000 },
  319.         .vco = { .min = 1750000, .max = 3500000},
  320.         .n = { .min = 1, .max = 4 },
  321.         .m = { .min = 104, .max = 138 },
  322.         .m1 = { .min = 16, .max = 23 },
  323.         .m2 = { .min = 5, .max = 11 },
  324.         .p = { .min = 5, .max = 80 },
  325.         .p1 = { .min = 1, .max = 8},
  326.         .p2 = { .dot_limit = 165000,
  327.                 .p2_slow = 10, .p2_fast = 5 },
  328. };
  329.  
  330. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  331.         .dot = { .min = 20000, .max = 115000 },
  332.         .vco = { .min = 1750000, .max = 3500000 },
  333.         .n = { .min = 1, .max = 3 },
  334.         .m = { .min = 104, .max = 138 },
  335.         .m1 = { .min = 17, .max = 23 },
  336.         .m2 = { .min = 5, .max = 11 },
  337.         .p = { .min = 28, .max = 112 },
  338.         .p1 = { .min = 2, .max = 8 },
  339.         .p2 = { .dot_limit = 0,
  340.                 .p2_slow = 14, .p2_fast = 14
  341.         },
  342. };
  343.  
  344. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  345.         .dot = { .min = 80000, .max = 224000 },
  346.         .vco = { .min = 1750000, .max = 3500000 },
  347.         .n = { .min = 1, .max = 3 },
  348.         .m = { .min = 104, .max = 138 },
  349.         .m1 = { .min = 17, .max = 23 },
  350.         .m2 = { .min = 5, .max = 11 },
  351.         .p = { .min = 14, .max = 42 },
  352.         .p1 = { .min = 2, .max = 6 },
  353.         .p2 = { .dot_limit = 0,
  354.                 .p2_slow = 7, .p2_fast = 7
  355.         },
  356. };
  357.  
  358. static const intel_limit_t intel_limits_pineview_sdvo = {
  359.         .dot = { .min = 20000, .max = 400000},
  360.         .vco = { .min = 1700000, .max = 3500000 },
  361.         /* Pineview's Ncounter is a ring counter */
  362.         .n = { .min = 3, .max = 6 },
  363.         .m = { .min = 2, .max = 256 },
  364.         /* Pineview only has one combined m divider, which we treat as m2. */
  365.         .m1 = { .min = 0, .max = 0 },
  366.         .m2 = { .min = 0, .max = 254 },
  367.         .p = { .min = 5, .max = 80 },
  368.         .p1 = { .min = 1, .max = 8 },
  369.         .p2 = { .dot_limit = 200000,
  370.                 .p2_slow = 10, .p2_fast = 5 },
  371. };
  372.  
  373. static const intel_limit_t intel_limits_pineview_lvds = {
  374.         .dot = { .min = 20000, .max = 400000 },
  375.         .vco = { .min = 1700000, .max = 3500000 },
  376.         .n = { .min = 3, .max = 6 },
  377.         .m = { .min = 2, .max = 256 },
  378.         .m1 = { .min = 0, .max = 0 },
  379.         .m2 = { .min = 0, .max = 254 },
  380.         .p = { .min = 7, .max = 112 },
  381.         .p1 = { .min = 1, .max = 8 },
  382.         .p2 = { .dot_limit = 112000,
  383.                 .p2_slow = 14, .p2_fast = 14 },
  384. };
  385.  
  386. /* Ironlake / Sandybridge
  387.  *
  388.  * We calculate clock using (register_value + 2) for N/M1/M2, so here
  389.  * the range value for them is (actual_value - 2).
  390.  */
  391. static const intel_limit_t intel_limits_ironlake_dac = {
  392.         .dot = { .min = 25000, .max = 350000 },
  393.         .vco = { .min = 1760000, .max = 3510000 },
  394.         .n = { .min = 1, .max = 5 },
  395.         .m = { .min = 79, .max = 127 },
  396.         .m1 = { .min = 12, .max = 22 },
  397.         .m2 = { .min = 5, .max = 9 },
  398.         .p = { .min = 5, .max = 80 },
  399.         .p1 = { .min = 1, .max = 8 },
  400.         .p2 = { .dot_limit = 225000,
  401.                 .p2_slow = 10, .p2_fast = 5 },
  402. };
  403.  
  404. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  405.         .dot = { .min = 25000, .max = 350000 },
  406.         .vco = { .min = 1760000, .max = 3510000 },
  407.         .n = { .min = 1, .max = 3 },
  408.         .m = { .min = 79, .max = 118 },
  409.         .m1 = { .min = 12, .max = 22 },
  410.         .m2 = { .min = 5, .max = 9 },
  411.         .p = { .min = 28, .max = 112 },
  412.         .p1 = { .min = 2, .max = 8 },
  413.         .p2 = { .dot_limit = 225000,
  414.                 .p2_slow = 14, .p2_fast = 14 },
  415. };
  416.  
  417. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  418.         .dot = { .min = 25000, .max = 350000 },
  419.         .vco = { .min = 1760000, .max = 3510000 },
  420.         .n = { .min = 1, .max = 3 },
  421.         .m = { .min = 79, .max = 127 },
  422.         .m1 = { .min = 12, .max = 22 },
  423.         .m2 = { .min = 5, .max = 9 },
  424.         .p = { .min = 14, .max = 56 },
  425.         .p1 = { .min = 2, .max = 8 },
  426.         .p2 = { .dot_limit = 225000,
  427.                 .p2_slow = 7, .p2_fast = 7 },
  428. };
  429.  
  430. /* LVDS 100mhz refclk limits. */
  431. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  432.         .dot = { .min = 25000, .max = 350000 },
  433.         .vco = { .min = 1760000, .max = 3510000 },
  434.         .n = { .min = 1, .max = 2 },
  435.         .m = { .min = 79, .max = 126 },
  436.         .m1 = { .min = 12, .max = 22 },
  437.         .m2 = { .min = 5, .max = 9 },
  438.         .p = { .min = 28, .max = 112 },
  439.         .p1 = { .min = 2, .max = 8 },
  440.         .p2 = { .dot_limit = 225000,
  441.                 .p2_slow = 14, .p2_fast = 14 },
  442. };
  443.  
  444. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  445.         .dot = { .min = 25000, .max = 350000 },
  446.         .vco = { .min = 1760000, .max = 3510000 },
  447.         .n = { .min = 1, .max = 3 },
  448.         .m = { .min = 79, .max = 126 },
  449.         .m1 = { .min = 12, .max = 22 },
  450.         .m2 = { .min = 5, .max = 9 },
  451.         .p = { .min = 14, .max = 42 },
  452.         .p1 = { .min = 2, .max = 6 },
  453.         .p2 = { .dot_limit = 225000,
  454.                 .p2_slow = 7, .p2_fast = 7 },
  455. };
  456.  
  457. static const intel_limit_t intel_limits_vlv = {
  458.          /*
  459.           * These are the data rate limits (measured in fast clocks)
  460.           * since those are the strictest limits we have. The fast
  461.           * clock and actual rate limits are more relaxed, so checking
  462.           * them would make no difference.
  463.           */
  464.         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
  465.         .vco = { .min = 4000000, .max = 6000000 },
  466.         .n = { .min = 1, .max = 7 },
  467.         .m1 = { .min = 2, .max = 3 },
  468.         .m2 = { .min = 11, .max = 156 },
  469.         .p1 = { .min = 2, .max = 3 },
  470.         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
  471. };
  472.  
  473. static const intel_limit_t intel_limits_chv = {
  474.         /*
  475.          * These are the data rate limits (measured in fast clocks)
  476.          * since those are the strictest limits we have.  The fast
  477.          * clock and actual rate limits are more relaxed, so checking
  478.          * them would make no difference.
  479.          */
  480.         .dot = { .min = 25000 * 5, .max = 540000 * 5},
  481.         .vco = { .min = 4800000, .max = 6480000 },
  482.         .n = { .min = 1, .max = 1 },
  483.         .m1 = { .min = 2, .max = 2 },
  484.         .m2 = { .min = 24 << 22, .max = 175 << 22 },
  485.         .p1 = { .min = 2, .max = 4 },
  486.         .p2 = { .p2_slow = 1, .p2_fast = 14 },
  487. };
  488.  
  489. static const intel_limit_t intel_limits_bxt = {
  490.         /* FIXME: find real dot limits */
  491.         .dot = { .min = 0, .max = INT_MAX },
  492.         .vco = { .min = 4800000, .max = 6700000 },
  493.         .n = { .min = 1, .max = 1 },
  494.         .m1 = { .min = 2, .max = 2 },
  495.         /* FIXME: find real m2 limits */
  496.         .m2 = { .min = 2 << 22, .max = 255 << 22 },
  497.         .p1 = { .min = 2, .max = 4 },
  498.         .p2 = { .p2_slow = 1, .p2_fast = 20 },
  499. };
  500.  
  501. static bool
  502. needs_modeset(struct drm_crtc_state *state)
  503. {
  504.         return drm_atomic_crtc_needs_modeset(state);
  505. }
  506.  
  507. /**
  508.  * Returns whether any output on the specified pipe is of the specified type
  509.  */
  510. bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
  511. {
  512.         struct drm_device *dev = crtc->base.dev;
  513.         struct intel_encoder *encoder;
  514.  
  515.         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  516.                 if (encoder->type == type)
  517.                         return true;
  518.  
  519.         return false;
  520. }
  521.  
  522. /**
  523.  * Returns whether any output on the specified pipe will have the specified
  524.  * type after a staged modeset is complete, i.e., the same as
  525.  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
  526.  * encoder->crtc.
  527.  */
  528. static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
  529.                                       int type)
  530. {
  531.         struct drm_atomic_state *state = crtc_state->base.state;
  532.         struct drm_connector *connector;
  533.         struct drm_connector_state *connector_state;
  534.         struct intel_encoder *encoder;
  535.         int i, num_connectors = 0;
  536.  
  537.         for_each_connector_in_state(state, connector, connector_state, i) {
  538.                 if (connector_state->crtc != crtc_state->base.crtc)
  539.                         continue;
  540.  
  541.                 num_connectors++;
  542.  
  543.                 encoder = to_intel_encoder(connector_state->best_encoder);
  544.                 if (encoder->type == type)
  545.                         return true;
  546.         }
  547.  
  548.         WARN_ON(num_connectors == 0);
  549.  
  550.         return false;
  551. }
  552.  
  553. static const intel_limit_t *
  554. intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
  555. {
  556.         struct drm_device *dev = crtc_state->base.crtc->dev;
  557.         const intel_limit_t *limit;
  558.  
  559.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  560.                 if (intel_is_dual_link_lvds(dev)) {
  561.                         if (refclk == 100000)
  562.                                 limit = &intel_limits_ironlake_dual_lvds_100m;
  563.                         else
  564.                                 limit = &intel_limits_ironlake_dual_lvds;
  565.                 } else {
  566.                         if (refclk == 100000)
  567.                                 limit = &intel_limits_ironlake_single_lvds_100m;
  568.                         else
  569.                                 limit = &intel_limits_ironlake_single_lvds;
  570.                 }
  571.         } else
  572.                 limit = &intel_limits_ironlake_dac;
  573.  
  574.         return limit;
  575. }
  576.  
  577. static const intel_limit_t *
  578. intel_g4x_limit(struct intel_crtc_state *crtc_state)
  579. {
  580.         struct drm_device *dev = crtc_state->base.crtc->dev;
  581.         const intel_limit_t *limit;
  582.  
  583.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  584.                 if (intel_is_dual_link_lvds(dev))
  585.                         limit = &intel_limits_g4x_dual_channel_lvds;
  586.                 else
  587.                         limit = &intel_limits_g4x_single_channel_lvds;
  588.         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
  589.                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
  590.                 limit = &intel_limits_g4x_hdmi;
  591.         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
  592.                 limit = &intel_limits_g4x_sdvo;
  593.         } else /* The option is for other outputs */
  594.                 limit = &intel_limits_i9xx_sdvo;
  595.  
  596.         return limit;
  597. }
  598.  
  599. static const intel_limit_t *
  600. intel_limit(struct intel_crtc_state *crtc_state, int refclk)
  601. {
  602.         struct drm_device *dev = crtc_state->base.crtc->dev;
  603.         const intel_limit_t *limit;
  604.  
  605.         if (IS_BROXTON(dev))
  606.                 limit = &intel_limits_bxt;
  607.         else if (HAS_PCH_SPLIT(dev))
  608.                 limit = intel_ironlake_limit(crtc_state, refclk);
  609.         else if (IS_G4X(dev)) {
  610.                 limit = intel_g4x_limit(crtc_state);
  611.         } else if (IS_PINEVIEW(dev)) {
  612.                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
  613.                         limit = &intel_limits_pineview_lvds;
  614.                 else
  615.                         limit = &intel_limits_pineview_sdvo;
  616.         } else if (IS_CHERRYVIEW(dev)) {
  617.                 limit = &intel_limits_chv;
  618.         } else if (IS_VALLEYVIEW(dev)) {
  619.                 limit = &intel_limits_vlv;
  620.         } else if (!IS_GEN2(dev)) {
  621.                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
  622.                         limit = &intel_limits_i9xx_lvds;
  623.                 else
  624.                         limit = &intel_limits_i9xx_sdvo;
  625.         } else {
  626.                 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
  627.                         limit = &intel_limits_i8xx_lvds;
  628.                 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
  629.                         limit = &intel_limits_i8xx_dvo;
  630.                 else
  631.                         limit = &intel_limits_i8xx_dac;
  632.         }
  633.         return limit;
  634. }
  635.  
  636. /*
  637.  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
  638.  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
  639.  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
  640.  * The helpers' return value is the rate of the clock that is fed to the
  641.  * display engine's pipe which can be the above fast dot clock rate or a
  642.  * divided-down version of it.
  643.  */
  644. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  645. static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
  646. {
  647.         clock->m = clock->m2 + 2;
  648.         clock->p = clock->p1 * clock->p2;
  649.         if (WARN_ON(clock->n == 0 || clock->p == 0))
  650.                 return 0;
  651.         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
  652.         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  653.  
  654.         return clock->dot;
  655. }
  656.  
  657. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  658. {
  659.         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  660. }
  661.  
  662. static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
  663. {
  664.         clock->m = i9xx_dpll_compute_m(clock);
  665.         clock->p = clock->p1 * clock->p2;
  666.         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
  667.                 return 0;
  668.         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
  669.         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  670.  
  671.         return clock->dot;
  672. }
  673.  
  674. static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
  675. {
  676.         clock->m = clock->m1 * clock->m2;
  677.         clock->p = clock->p1 * clock->p2;
  678.         if (WARN_ON(clock->n == 0 || clock->p == 0))
  679.                 return 0;
  680.         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
  681.         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  682.  
  683.         return clock->dot / 5;
  684. }
  685.  
  686. int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
  687. {
  688.         clock->m = clock->m1 * clock->m2;
  689.         clock->p = clock->p1 * clock->p2;
  690.         if (WARN_ON(clock->n == 0 || clock->p == 0))
  691.                 return 0;
  692.         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
  693.                         clock->n << 22);
  694.         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
  695.  
  696.         return clock->dot / 5;
  697. }
  698.  
  699. #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
  700. /**
  701.  * Returns whether the given set of divisors are valid for a given refclk with
  702.  * the given connectors.
  703.  */
  704.  
  705. static bool intel_PLL_is_valid(struct drm_device *dev,
  706.                                const intel_limit_t *limit,
  707.                                const intel_clock_t *clock)
  708. {
  709.         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
  710.                 INTELPllInvalid("n out of range\n");
  711.         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
  712.                 INTELPllInvalid("p1 out of range\n");
  713.         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
  714.                 INTELPllInvalid("m2 out of range\n");
  715.         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
  716.                 INTELPllInvalid("m1 out of range\n");
  717.  
  718.         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
  719.                 if (clock->m1 <= clock->m2)
  720.                         INTELPllInvalid("m1 <= m2\n");
  721.  
  722.         if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
  723.                 if (clock->p < limit->p.min || limit->p.max < clock->p)
  724.                         INTELPllInvalid("p out of range\n");
  725.                 if (clock->m < limit->m.min || limit->m.max < clock->m)
  726.                         INTELPllInvalid("m out of range\n");
  727.         }
  728.  
  729.         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  730.                 INTELPllInvalid("vco out of range\n");
  731.         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  732.          * connector, etc., rather than just a single range.
  733.          */
  734.         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  735.                 INTELPllInvalid("dot out of range\n");
  736.  
  737.         return true;
  738. }
  739.  
  740. static int
  741. i9xx_select_p2_div(const intel_limit_t *limit,
  742.                    const struct intel_crtc_state *crtc_state,
  743.                    int target)
  744. {
  745.         struct drm_device *dev = crtc_state->base.crtc->dev;
  746.  
  747.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  748.                 /*
  749.                  * For LVDS just rely on its current settings for dual-channel.
  750.                  * We haven't figured out how to reliably set up different
  751.                  * single/dual channel state, if we even can.
  752.                  */
  753.                 if (intel_is_dual_link_lvds(dev))
  754.                         return limit->p2.p2_fast;
  755.                 else
  756.                         return limit->p2.p2_slow;
  757.         } else {
  758.                 if (target < limit->p2.dot_limit)
  759.                         return limit->p2.p2_slow;
  760.                 else
  761.                         return limit->p2.p2_fast;
  762.         }
  763. }
  764.  
  765. static bool
  766. i9xx_find_best_dpll(const intel_limit_t *limit,
  767.                     struct intel_crtc_state *crtc_state,
  768.                     int target, int refclk, intel_clock_t *match_clock,
  769.                     intel_clock_t *best_clock)
  770. {
  771.         struct drm_device *dev = crtc_state->base.crtc->dev;
  772.         intel_clock_t clock;
  773.         int err = target;
  774.  
  775.         memset(best_clock, 0, sizeof(*best_clock));
  776.  
  777.         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
  778.  
  779.         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  780.              clock.m1++) {
  781.                 for (clock.m2 = limit->m2.min;
  782.                      clock.m2 <= limit->m2.max; clock.m2++) {
  783.                         if (clock.m2 >= clock.m1)
  784.                                 break;
  785.                         for (clock.n = limit->n.min;
  786.                              clock.n <= limit->n.max; clock.n++) {
  787.                                 for (clock.p1 = limit->p1.min;
  788.                                         clock.p1 <= limit->p1.max; clock.p1++) {
  789.                                         int this_err;
  790.  
  791.                                         i9xx_calc_dpll_params(refclk, &clock);
  792.                                         if (!intel_PLL_is_valid(dev, limit,
  793.                                                                 &clock))
  794.                                                 continue;
  795.                                         if (match_clock &&
  796.                                             clock.p != match_clock->p)
  797.                                                 continue;
  798.  
  799.                                         this_err = abs(clock.dot - target);
  800.                                         if (this_err < err) {
  801.                                                 *best_clock = clock;
  802.                                                 err = this_err;
  803.                                         }
  804.                                 }
  805.                         }
  806.                 }
  807.         }
  808.  
  809.         return (err != target);
  810. }
  811.  
  812. static bool
  813. pnv_find_best_dpll(const intel_limit_t *limit,
  814.                    struct intel_crtc_state *crtc_state,
  815.                    int target, int refclk, intel_clock_t *match_clock,
  816.                    intel_clock_t *best_clock)
  817. {
  818.         struct drm_device *dev = crtc_state->base.crtc->dev;
  819.         intel_clock_t clock;
  820.         int err = target;
  821.  
  822.         memset(best_clock, 0, sizeof(*best_clock));
  823.  
  824.         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
  825.  
  826.         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  827.              clock.m1++) {
  828.                 for (clock.m2 = limit->m2.min;
  829.                      clock.m2 <= limit->m2.max; clock.m2++) {
  830.                         for (clock.n = limit->n.min;
  831.                              clock.n <= limit->n.max; clock.n++) {
  832.                                 for (clock.p1 = limit->p1.min;
  833.                                         clock.p1 <= limit->p1.max; clock.p1++) {
  834.                                         int this_err;
  835.  
  836.                                         pnv_calc_dpll_params(refclk, &clock);
  837.                                         if (!intel_PLL_is_valid(dev, limit,
  838.                                                                 &clock))
  839.                                                 continue;
  840.                                         if (match_clock &&
  841.                                             clock.p != match_clock->p)
  842.                                                 continue;
  843.  
  844.                                         this_err = abs(clock.dot - target);
  845.                                         if (this_err < err) {
  846.                                                 *best_clock = clock;
  847.                                                 err = this_err;
  848.                                         }
  849.                                 }
  850.                         }
  851.                 }
  852.         }
  853.  
  854.         return (err != target);
  855. }
  856.  
  857. static bool
  858. g4x_find_best_dpll(const intel_limit_t *limit,
  859.                    struct intel_crtc_state *crtc_state,
  860.                    int target, int refclk, intel_clock_t *match_clock,
  861.                    intel_clock_t *best_clock)
  862. {
  863.         struct drm_device *dev = crtc_state->base.crtc->dev;
  864.         intel_clock_t clock;
  865.         int max_n;
  866.         bool found = false;
  867.         /* approximately equals target * 0.00585 */
  868.         int err_most = (target >> 8) + (target >> 9);
  869.  
  870.         memset(best_clock, 0, sizeof(*best_clock));
  871.  
  872.         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
  873.  
  874.         max_n = limit->n.max;
  875.         /* based on hardware requirement, prefer smaller n to precision */
  876.         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  877.                 /* based on hardware requirement, prefere larger m1,m2 */
  878.                 for (clock.m1 = limit->m1.max;
  879.                      clock.m1 >= limit->m1.min; clock.m1--) {
  880.                         for (clock.m2 = limit->m2.max;
  881.                              clock.m2 >= limit->m2.min; clock.m2--) {
  882.                                 for (clock.p1 = limit->p1.max;
  883.                                      clock.p1 >= limit->p1.min; clock.p1--) {
  884.                                         int this_err;
  885.  
  886.                                         i9xx_calc_dpll_params(refclk, &clock);
  887.                                         if (!intel_PLL_is_valid(dev, limit,
  888.                                                                 &clock))
  889.                                                 continue;
  890.  
  891.                                         this_err = abs(clock.dot - target);
  892.                                         if (this_err < err_most) {
  893.                                                 *best_clock = clock;
  894.                                                 err_most = this_err;
  895.                                                 max_n = clock.n;
  896.                                                 found = true;
  897.                                         }
  898.                                 }
  899.                         }
  900.                 }
  901.         }
  902.         return found;
  903. }
  904.  
  905. /*
  906.  * Check if the calculated PLL configuration is more optimal compared to the
  907.  * best configuration and error found so far. Return the calculated error.
  908.  */
  909. static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
  910.                                const intel_clock_t *calculated_clock,
  911.                                const intel_clock_t *best_clock,
  912.                                unsigned int best_error_ppm,
  913.                                unsigned int *error_ppm)
  914. {
  915.         /*
  916.          * For CHV ignore the error and consider only the P value.
  917.          * Prefer a bigger P value based on HW requirements.
  918.          */
  919.         if (IS_CHERRYVIEW(dev)) {
  920.                 *error_ppm = 0;
  921.  
  922.                 return calculated_clock->p > best_clock->p;
  923.         }
  924.  
  925.         if (WARN_ON_ONCE(!target_freq))
  926.                 return false;
  927.  
  928.         *error_ppm = div_u64(1000000ULL *
  929.                                 abs(target_freq - calculated_clock->dot),
  930.                              target_freq);
  931.         /*
  932.          * Prefer a better P value over a better (smaller) error if the error
  933.          * is small. Ensure this preference for future configurations too by
  934.          * setting the error to 0.
  935.          */
  936.         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
  937.                 *error_ppm = 0;
  938.  
  939.                 return true;
  940.         }
  941.  
  942.         return *error_ppm + 10 < best_error_ppm;
  943. }
  944.  
  945. static bool
  946. vlv_find_best_dpll(const intel_limit_t *limit,
  947.                    struct intel_crtc_state *crtc_state,
  948.                    int target, int refclk, intel_clock_t *match_clock,
  949.                    intel_clock_t *best_clock)
  950. {
  951.         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
  952.         struct drm_device *dev = crtc->base.dev;
  953.         intel_clock_t clock;
  954.         unsigned int bestppm = 1000000;
  955.         /* min update 19.2 MHz */
  956.         int max_n = min(limit->n.max, refclk / 19200);
  957.         bool found = false;
  958.  
  959.         target *= 5; /* fast clock */
  960.  
  961.         memset(best_clock, 0, sizeof(*best_clock));
  962.  
  963.         /* based on hardware requirement, prefer smaller n to precision */
  964.         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  965.                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  966.                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
  967.                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
  968.                                 clock.p = clock.p1 * clock.p2;
  969.                                 /* based on hardware requirement, prefer bigger m1,m2 values */
  970.                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
  971.                                         unsigned int ppm;
  972.  
  973.                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
  974.                                                                      refclk * clock.m1);
  975.  
  976.                                         vlv_calc_dpll_params(refclk, &clock);
  977.  
  978.                                         if (!intel_PLL_is_valid(dev, limit,
  979.                                                                 &clock))
  980.                                                 continue;
  981.  
  982.                                         if (!vlv_PLL_is_optimal(dev, target,
  983.                                                                 &clock,
  984.                                                                 best_clock,
  985.                                                                 bestppm, &ppm))
  986.                                                 continue;
  987.  
  988.                                         *best_clock = clock;
  989.                                         bestppm = ppm;
  990.                                         found = true;
  991.                                 }
  992.                         }
  993.                 }
  994.         }
  995.  
  996.         return found;
  997. }
  998.  
  999. static bool
  1000. chv_find_best_dpll(const intel_limit_t *limit,
  1001.                    struct intel_crtc_state *crtc_state,
  1002.                    int target, int refclk, intel_clock_t *match_clock,
  1003.                    intel_clock_t *best_clock)
  1004. {
  1005.         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
  1006.         struct drm_device *dev = crtc->base.dev;
  1007.         unsigned int best_error_ppm;
  1008.         intel_clock_t clock;
  1009.         uint64_t m2;
  1010.         int found = false;
  1011.  
  1012.         memset(best_clock, 0, sizeof(*best_clock));
  1013.         best_error_ppm = 1000000;
  1014.  
  1015.         /*
  1016.          * Based on hardware doc, the n always set to 1, and m1 always
  1017.          * set to 2.  If requires to support 200Mhz refclk, we need to
  1018.          * revisit this because n may not 1 anymore.
  1019.          */
  1020.         clock.n = 1, clock.m1 = 2;
  1021.         target *= 5;    /* fast clock */
  1022.  
  1023.         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
  1024.                 for (clock.p2 = limit->p2.p2_fast;
  1025.                                 clock.p2 >= limit->p2.p2_slow;
  1026.                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
  1027.                         unsigned int error_ppm;
  1028.  
  1029.                         clock.p = clock.p1 * clock.p2;
  1030.  
  1031.                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
  1032.                                         clock.n) << 22, refclk * clock.m1);
  1033.  
  1034.                         if (m2 > INT_MAX/clock.m1)
  1035.                                 continue;
  1036.  
  1037.                         clock.m2 = m2;
  1038.  
  1039.                         chv_calc_dpll_params(refclk, &clock);
  1040.  
  1041.                         if (!intel_PLL_is_valid(dev, limit, &clock))
  1042.                                 continue;
  1043.  
  1044.                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
  1045.                                                 best_error_ppm, &error_ppm))
  1046.                                 continue;
  1047.  
  1048.                         *best_clock = clock;
  1049.                         best_error_ppm = error_ppm;
  1050.                         found = true;
  1051.                 }
  1052.         }
  1053.  
  1054.         return found;
  1055. }
  1056.  
  1057. bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
  1058.                         intel_clock_t *best_clock)
  1059. {
  1060.         int refclk = i9xx_get_refclk(crtc_state, 0);
  1061.  
  1062.         return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
  1063.                                   target_clock, refclk, NULL, best_clock);
  1064. }
  1065.  
  1066. bool intel_crtc_active(struct drm_crtc *crtc)
  1067. {
  1068.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1069.  
  1070.         /* Be paranoid as we can arrive here with only partial
  1071.          * state retrieved from the hardware during setup.
  1072.          *
  1073.          * We can ditch the adjusted_mode.crtc_clock check as soon
  1074.          * as Haswell has gained clock readout/fastboot support.
  1075.          *
  1076.          * We can ditch the crtc->primary->fb check as soon as we can
  1077.          * properly reconstruct framebuffers.
  1078.          *
  1079.          * FIXME: The intel_crtc->active here should be switched to
  1080.          * crtc->state->active once we have proper CRTC states wired up
  1081.          * for atomic.
  1082.          */
  1083.         return intel_crtc->active && crtc->primary->state->fb &&
  1084.                 intel_crtc->config->base.adjusted_mode.crtc_clock;
  1085. }
  1086.  
  1087. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  1088.                                              enum pipe pipe)
  1089. {
  1090.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1091.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1092.  
  1093.         return intel_crtc->config->cpu_transcoder;
  1094. }
  1095.  
  1096. static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
  1097. {
  1098.         struct drm_i915_private *dev_priv = dev->dev_private;
  1099.         u32 reg = PIPEDSL(pipe);
  1100.         u32 line1, line2;
  1101.         u32 line_mask;
  1102.  
  1103.         if (IS_GEN2(dev))
  1104.                 line_mask = DSL_LINEMASK_GEN2;
  1105.         else
  1106.                 line_mask = DSL_LINEMASK_GEN3;
  1107.  
  1108.         line1 = I915_READ(reg) & line_mask;
  1109.         msleep(5);
  1110.         line2 = I915_READ(reg) & line_mask;
  1111.  
  1112.         return line1 == line2;
  1113. }
  1114.  
  1115. /*
  1116.  * intel_wait_for_pipe_off - wait for pipe to turn off
  1117.  * @crtc: crtc whose pipe to wait for
  1118.  *
  1119.  * After disabling a pipe, we can't wait for vblank in the usual way,
  1120.  * spinning on the vblank interrupt status bit, since we won't actually
  1121.  * see an interrupt when the pipe is disabled.
  1122.  *
  1123.  * On Gen4 and above:
  1124.  *   wait for the pipe register state bit to turn off
  1125.  *
  1126.  * Otherwise:
  1127.  *   wait for the display line value to settle (it usually
  1128.  *   ends up stopping at the start of the next frame).
  1129.  *
  1130.  */
  1131. static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
  1132. {
  1133.         struct drm_device *dev = crtc->base.dev;
  1134.         struct drm_i915_private *dev_priv = dev->dev_private;
  1135.         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  1136.         enum pipe pipe = crtc->pipe;
  1137.  
  1138.         if (INTEL_INFO(dev)->gen >= 4) {
  1139.                 int reg = PIPECONF(cpu_transcoder);
  1140.  
  1141.                 /* Wait for the Pipe State to go off */
  1142.                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  1143.                              100))
  1144.                         WARN(1, "pipe_off wait timed out\n");
  1145.         } else {
  1146.                 /* Wait for the display line to settle */
  1147.                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
  1148.                         WARN(1, "pipe_off wait timed out\n");
  1149.         }
  1150. }
  1151.  
  1152. static const char *state_string(bool enabled)
  1153. {
  1154.         return enabled ? "on" : "off";
  1155. }
  1156.  
  1157. /* Only for pre-ILK configs */
  1158. void assert_pll(struct drm_i915_private *dev_priv,
  1159.                 enum pipe pipe, bool state)
  1160. {
  1161.         u32 val;
  1162.         bool cur_state;
  1163.  
  1164.         val = I915_READ(DPLL(pipe));
  1165.         cur_state = !!(val & DPLL_VCO_ENABLE);
  1166.         I915_STATE_WARN(cur_state != state,
  1167.              "PLL state assertion failure (expected %s, current %s)\n",
  1168.              state_string(state), state_string(cur_state));
  1169. }
  1170.  
  1171. /* XXX: the dsi pll is shared between MIPI DSI ports */
  1172. static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
  1173. {
  1174.         u32 val;
  1175.         bool cur_state;
  1176.  
  1177.         mutex_lock(&dev_priv->sb_lock);
  1178.         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
  1179.         mutex_unlock(&dev_priv->sb_lock);
  1180.  
  1181.         cur_state = val & DSI_PLL_VCO_EN;
  1182.         I915_STATE_WARN(cur_state != state,
  1183.              "DSI PLL state assertion failure (expected %s, current %s)\n",
  1184.              state_string(state), state_string(cur_state));
  1185. }
  1186. #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
  1187. #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
  1188.  
  1189. struct intel_shared_dpll *
  1190. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  1191. {
  1192.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1193.  
  1194.         if (crtc->config->shared_dpll < 0)
  1195.                 return NULL;
  1196.  
  1197.         return &dev_priv->shared_dplls[crtc->config->shared_dpll];
  1198. }
  1199.  
  1200. /* For ILK+ */
  1201. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  1202.                         struct intel_shared_dpll *pll,
  1203.                         bool state)
  1204. {
  1205.         bool cur_state;
  1206.         struct intel_dpll_hw_state hw_state;
  1207.  
  1208.         if (WARN (!pll,
  1209.                   "asserting DPLL %s with no DPLL\n", state_string(state)))
  1210.                 return;
  1211.  
  1212.         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  1213.         I915_STATE_WARN(cur_state != state,
  1214.              "%s assertion failure (expected %s, current %s)\n",
  1215.              pll->name, state_string(state), state_string(cur_state));
  1216. }
  1217.  
  1218. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  1219.                           enum pipe pipe, bool state)
  1220. {
  1221.         bool cur_state;
  1222.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1223.                                                                       pipe);
  1224.  
  1225.         if (HAS_DDI(dev_priv->dev)) {
  1226.                 /* DDI does not have a specific FDI_TX register */
  1227.                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  1228.                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  1229.         } else {
  1230.                 u32 val = I915_READ(FDI_TX_CTL(pipe));
  1231.                 cur_state = !!(val & FDI_TX_ENABLE);
  1232.         }
  1233.         I915_STATE_WARN(cur_state != state,
  1234.              "FDI TX state assertion failure (expected %s, current %s)\n",
  1235.              state_string(state), state_string(cur_state));
  1236. }
  1237. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  1238. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  1239.  
  1240. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  1241.                           enum pipe pipe, bool state)
  1242. {
  1243.         u32 val;
  1244.         bool cur_state;
  1245.  
  1246.         val = I915_READ(FDI_RX_CTL(pipe));
  1247.         cur_state = !!(val & FDI_RX_ENABLE);
  1248.         I915_STATE_WARN(cur_state != state,
  1249.              "FDI RX state assertion failure (expected %s, current %s)\n",
  1250.              state_string(state), state_string(cur_state));
  1251. }
  1252. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1253. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1254.  
  1255. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1256.                                       enum pipe pipe)
  1257. {
  1258.         u32 val;
  1259.  
  1260.         /* ILK FDI PLL is always enabled */
  1261.         if (INTEL_INFO(dev_priv->dev)->gen == 5)
  1262.                 return;
  1263.  
  1264.         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1265.         if (HAS_DDI(dev_priv->dev))
  1266.                 return;
  1267.  
  1268.         val = I915_READ(FDI_TX_CTL(pipe));
  1269.         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1270. }
  1271.  
  1272. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  1273.                        enum pipe pipe, bool state)
  1274. {
  1275.         u32 val;
  1276.         bool cur_state;
  1277.  
  1278.         val = I915_READ(FDI_RX_CTL(pipe));
  1279.         cur_state = !!(val & FDI_RX_PLL_ENABLE);
  1280.         I915_STATE_WARN(cur_state != state,
  1281.              "FDI RX PLL assertion failure (expected %s, current %s)\n",
  1282.              state_string(state), state_string(cur_state));
  1283. }
  1284.  
  1285. void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1286.                            enum pipe pipe)
  1287. {
  1288.         struct drm_device *dev = dev_priv->dev;
  1289.         int pp_reg;
  1290.         u32 val;
  1291.         enum pipe panel_pipe = PIPE_A;
  1292.         bool locked = true;
  1293.  
  1294.         if (WARN_ON(HAS_DDI(dev)))
  1295.                 return;
  1296.  
  1297.         if (HAS_PCH_SPLIT(dev)) {
  1298.                 u32 port_sel;
  1299.  
  1300.                 pp_reg = PCH_PP_CONTROL;
  1301.                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
  1302.  
  1303.                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
  1304.                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
  1305.                         panel_pipe = PIPE_B;
  1306.                 /* XXX: else fix for eDP */
  1307.         } else if (IS_VALLEYVIEW(dev)) {
  1308.                 /* presumably write lock depends on pipe, not port select */
  1309.                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
  1310.                 panel_pipe = pipe;
  1311.         } else {
  1312.                 pp_reg = PP_CONTROL;
  1313.                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
  1314.                         panel_pipe = PIPE_B;
  1315.         }
  1316.  
  1317.         val = I915_READ(pp_reg);
  1318.         if (!(val & PANEL_POWER_ON) ||
  1319.             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
  1320.                 locked = false;
  1321.  
  1322.         I915_STATE_WARN(panel_pipe == pipe && locked,
  1323.              "panel assertion failure, pipe %c regs locked\n",
  1324.              pipe_name(pipe));
  1325. }
  1326.  
  1327. static void assert_cursor(struct drm_i915_private *dev_priv,
  1328.                           enum pipe pipe, bool state)
  1329. {
  1330.         struct drm_device *dev = dev_priv->dev;
  1331.         bool cur_state;
  1332.  
  1333.         if (IS_845G(dev) || IS_I865G(dev))
  1334.                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
  1335.         else
  1336.                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
  1337.  
  1338.         I915_STATE_WARN(cur_state != state,
  1339.              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
  1340.              pipe_name(pipe), state_string(state), state_string(cur_state));
  1341. }
  1342. #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
  1343. #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
  1344.  
  1345. void assert_pipe(struct drm_i915_private *dev_priv,
  1346.                  enum pipe pipe, bool state)
  1347. {
  1348.         bool cur_state;
  1349.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1350.                                                                       pipe);
  1351.  
  1352.         /* if we need the pipe quirk it must be always on */
  1353.         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  1354.             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  1355.                 state = true;
  1356.  
  1357.         if (!intel_display_power_is_enabled(dev_priv,
  1358.                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  1359.                 cur_state = false;
  1360.         } else {
  1361.                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
  1362.                 cur_state = !!(val & PIPECONF_ENABLE);
  1363.         }
  1364.  
  1365.         I915_STATE_WARN(cur_state != state,
  1366.              "pipe %c assertion failure (expected %s, current %s)\n",
  1367.              pipe_name(pipe), state_string(state), state_string(cur_state));
  1368. }
  1369.  
  1370. static void assert_plane(struct drm_i915_private *dev_priv,
  1371.                          enum plane plane, bool state)
  1372. {
  1373.         u32 val;
  1374.         bool cur_state;
  1375.  
  1376.         val = I915_READ(DSPCNTR(plane));
  1377.         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1378.         I915_STATE_WARN(cur_state != state,
  1379.              "plane %c assertion failure (expected %s, current %s)\n",
  1380.              plane_name(plane), state_string(state), state_string(cur_state));
  1381. }
  1382.  
  1383. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1384. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1385.  
  1386. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1387.                                    enum pipe pipe)
  1388. {
  1389.         struct drm_device *dev = dev_priv->dev;
  1390.         int i;
  1391.  
  1392.         /* Primary planes are fixed to pipes on gen4+ */
  1393.         if (INTEL_INFO(dev)->gen >= 4) {
  1394.                 u32 val = I915_READ(DSPCNTR(pipe));
  1395.                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
  1396.                      "plane %c assertion failure, should be disabled but not\n",
  1397.                      plane_name(pipe));
  1398.                 return;
  1399.         }
  1400.  
  1401.         /* Need to check both planes against the pipe */
  1402.         for_each_pipe(dev_priv, i) {
  1403.                 u32 val = I915_READ(DSPCNTR(i));
  1404.                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1405.                         DISPPLANE_SEL_PIPE_SHIFT;
  1406.                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1407.                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1408.                      plane_name(i), pipe_name(pipe));
  1409.         }
  1410. }
  1411.  
  1412. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1413.                                     enum pipe pipe)
  1414. {
  1415.         struct drm_device *dev = dev_priv->dev;
  1416.         int sprite;
  1417.  
  1418.         if (INTEL_INFO(dev)->gen >= 9) {
  1419.                 for_each_sprite(dev_priv, pipe, sprite) {
  1420.                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
  1421.                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
  1422.                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
  1423.                              sprite, pipe_name(pipe));
  1424.                 }
  1425.         } else if (IS_VALLEYVIEW(dev)) {
  1426.                 for_each_sprite(dev_priv, pipe, sprite) {
  1427.                         u32 val = I915_READ(SPCNTR(pipe, sprite));
  1428.                         I915_STATE_WARN(val & SP_ENABLE,
  1429.                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1430.                              sprite_name(pipe, sprite), pipe_name(pipe));
  1431.                 }
  1432.         } else if (INTEL_INFO(dev)->gen >= 7) {
  1433.                 u32 val = I915_READ(SPRCTL(pipe));
  1434.                 I915_STATE_WARN(val & SPRITE_ENABLE,
  1435.                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1436.                      plane_name(pipe), pipe_name(pipe));
  1437.         } else if (INTEL_INFO(dev)->gen >= 5) {
  1438.                 u32 val = I915_READ(DVSCNTR(pipe));
  1439.                 I915_STATE_WARN(val & DVS_ENABLE,
  1440.                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1441.                      plane_name(pipe), pipe_name(pipe));
  1442.         }
  1443. }
  1444.  
  1445. static void assert_vblank_disabled(struct drm_crtc *crtc)
  1446. {
  1447.         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
  1448.                 drm_crtc_vblank_put(crtc);
  1449. }
  1450.  
  1451. static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1452. {
  1453.         u32 val;
  1454.         bool enabled;
  1455.  
  1456.         I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
  1457.  
  1458.         val = I915_READ(PCH_DREF_CONTROL);
  1459.         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1460.                             DREF_SUPERSPREAD_SOURCE_MASK));
  1461.         I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1462. }
  1463.  
  1464. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1465.                                            enum pipe pipe)
  1466. {
  1467.         u32 val;
  1468.         bool enabled;
  1469.  
  1470.         val = I915_READ(PCH_TRANSCONF(pipe));
  1471.         enabled = !!(val & TRANS_ENABLE);
  1472.         I915_STATE_WARN(enabled,
  1473.              "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1474.              pipe_name(pipe));
  1475. }
  1476.  
  1477. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1478.                             enum pipe pipe, u32 port_sel, u32 val)
  1479. {
  1480.         if ((val & DP_PORT_EN) == 0)
  1481.                 return false;
  1482.  
  1483.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1484.                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1485.                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1486.                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1487.                         return false;
  1488.         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
  1489.                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
  1490.                         return false;
  1491.         } else {
  1492.                 if ((val & DP_PIPE_MASK) != (pipe << 30))
  1493.                         return false;
  1494.         }
  1495.         return true;
  1496. }
  1497.  
  1498. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1499.                               enum pipe pipe, u32 val)
  1500. {
  1501.         if ((val & SDVO_ENABLE) == 0)
  1502.                 return false;
  1503.  
  1504.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1505.                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1506.                         return false;
  1507.         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
  1508.                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
  1509.                         return false;
  1510.         } else {
  1511.                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1512.                         return false;
  1513.         }
  1514.         return true;
  1515. }
  1516.  
  1517. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1518.                               enum pipe pipe, u32 val)
  1519. {
  1520.         if ((val & LVDS_PORT_EN) == 0)
  1521.                 return false;
  1522.  
  1523.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1524.                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1525.                         return false;
  1526.         } else {
  1527.                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1528.                         return false;
  1529.         }
  1530.         return true;
  1531. }
  1532.  
  1533. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1534.                               enum pipe pipe, u32 val)
  1535. {
  1536.         if ((val & ADPA_DAC_ENABLE) == 0)
  1537.                 return false;
  1538.         if (HAS_PCH_CPT(dev_priv->dev)) {
  1539.                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1540.                         return false;
  1541.         } else {
  1542.                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1543.                         return false;
  1544.         }
  1545.         return true;
  1546. }
  1547.  
  1548. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1549.                                    enum pipe pipe, int reg, u32 port_sel)
  1550. {
  1551.         u32 val = I915_READ(reg);
  1552.         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1553.              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1554.              reg, pipe_name(pipe));
  1555.  
  1556.         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1557.              && (val & DP_PIPEB_SELECT),
  1558.              "IBX PCH dp port still using transcoder B\n");
  1559. }
  1560.  
  1561. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1562.                                      enum pipe pipe, int reg)
  1563. {
  1564.         u32 val = I915_READ(reg);
  1565.         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1566.              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1567.              reg, pipe_name(pipe));
  1568.  
  1569.         I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1570.              && (val & SDVO_PIPE_B_SELECT),
  1571.              "IBX PCH hdmi port still using transcoder B\n");
  1572. }
  1573.  
  1574. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1575.                                       enum pipe pipe)
  1576. {
  1577.         u32 val;
  1578.  
  1579.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1580.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1581.         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1582.  
  1583.         val = I915_READ(PCH_ADPA);
  1584.         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1585.              "PCH VGA enabled on transcoder %c, should be disabled\n",
  1586.              pipe_name(pipe));
  1587.  
  1588.         val = I915_READ(PCH_LVDS);
  1589.         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1590.              "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1591.              pipe_name(pipe));
  1592.  
  1593.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1594.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1595.         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1596. }
  1597.  
  1598. static void vlv_enable_pll(struct intel_crtc *crtc,
  1599.                            const struct intel_crtc_state *pipe_config)
  1600. {
  1601.         struct drm_device *dev = crtc->base.dev;
  1602.         struct drm_i915_private *dev_priv = dev->dev_private;
  1603.         int reg = DPLL(crtc->pipe);
  1604.         u32 dpll = pipe_config->dpll_hw_state.dpll;
  1605.  
  1606.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1607.  
  1608.         /* No really, not for ILK+ */
  1609.         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1610.  
  1611.         /* PLL is protected by panel, make sure we can write it */
  1612.         if (IS_MOBILE(dev_priv->dev))
  1613.                 assert_panel_unlocked(dev_priv, crtc->pipe);
  1614.  
  1615.         I915_WRITE(reg, dpll);
  1616.         POSTING_READ(reg);
  1617.         udelay(150);
  1618.  
  1619.         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1620.                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1621.  
  1622.         I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
  1623.         POSTING_READ(DPLL_MD(crtc->pipe));
  1624.  
  1625.         /* We do this three times for luck */
  1626.         I915_WRITE(reg, dpll);
  1627.         POSTING_READ(reg);
  1628.         udelay(150); /* wait for warmup */
  1629.         I915_WRITE(reg, dpll);
  1630.         POSTING_READ(reg);
  1631.         udelay(150); /* wait for warmup */
  1632.         I915_WRITE(reg, dpll);
  1633.         POSTING_READ(reg);
  1634.         udelay(150); /* wait for warmup */
  1635. }
  1636.  
  1637. static void chv_enable_pll(struct intel_crtc *crtc,
  1638.                            const struct intel_crtc_state *pipe_config)
  1639. {
  1640.         struct drm_device *dev = crtc->base.dev;
  1641.         struct drm_i915_private *dev_priv = dev->dev_private;
  1642.         int pipe = crtc->pipe;
  1643.         enum dpio_channel port = vlv_pipe_to_channel(pipe);
  1644.         u32 tmp;
  1645.  
  1646.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1647.  
  1648.         BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
  1649.  
  1650.         mutex_lock(&dev_priv->sb_lock);
  1651.  
  1652.         /* Enable back the 10bit clock to display controller */
  1653.         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
  1654.         tmp |= DPIO_DCLKP_EN;
  1655.         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
  1656.  
  1657.         mutex_unlock(&dev_priv->sb_lock);
  1658.  
  1659.         /*
  1660.          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
  1661.          */
  1662.         udelay(1);
  1663.  
  1664.         /* Enable PLL */
  1665.         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
  1666.  
  1667.         /* Check PLL is locked */
  1668.         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1669.                 DRM_ERROR("PLL %d failed to lock\n", pipe);
  1670.  
  1671.         /* not sure when this should be written */
  1672.         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
  1673.         POSTING_READ(DPLL_MD(pipe));
  1674. }
  1675.  
  1676. static int intel_num_dvo_pipes(struct drm_device *dev)
  1677. {
  1678.         struct intel_crtc *crtc;
  1679.         int count = 0;
  1680.  
  1681.         for_each_intel_crtc(dev, crtc)
  1682.                 count += crtc->base.state->active &&
  1683.                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
  1684.  
  1685.         return count;
  1686. }
  1687.  
  1688. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1689. {
  1690.         struct drm_device *dev = crtc->base.dev;
  1691.         struct drm_i915_private *dev_priv = dev->dev_private;
  1692.         int reg = DPLL(crtc->pipe);
  1693.         u32 dpll = crtc->config->dpll_hw_state.dpll;
  1694.  
  1695.         assert_pipe_disabled(dev_priv, crtc->pipe);
  1696.  
  1697.         /* No really, not for ILK+ */
  1698.         BUG_ON(INTEL_INFO(dev)->gen >= 5);
  1699.  
  1700.         /* PLL is protected by panel, make sure we can write it */
  1701.         if (IS_MOBILE(dev) && !IS_I830(dev))
  1702.                 assert_panel_unlocked(dev_priv, crtc->pipe);
  1703.  
  1704.         /* Enable DVO 2x clock on both PLLs if necessary */
  1705.         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
  1706.                 /*
  1707.                  * It appears to be important that we don't enable this
  1708.                  * for the current pipe before otherwise configuring the
  1709.                  * PLL. No idea how this should be handled if multiple
  1710.                  * DVO outputs are enabled simultaneosly.
  1711.                  */
  1712.                 dpll |= DPLL_DVO_2X_MODE;
  1713.                 I915_WRITE(DPLL(!crtc->pipe),
  1714.                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
  1715.         }
  1716.  
  1717.         /*
  1718.          * Apparently we need to have VGA mode enabled prior to changing
  1719.          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
  1720.          * dividers, even though the register value does change.
  1721.          */
  1722.         I915_WRITE(reg, 0);
  1723.  
  1724.         I915_WRITE(reg, dpll);
  1725.  
  1726.         /* Wait for the clocks to stabilize. */
  1727.         POSTING_READ(reg);
  1728.         udelay(150);
  1729.  
  1730.         if (INTEL_INFO(dev)->gen >= 4) {
  1731.                 I915_WRITE(DPLL_MD(crtc->pipe),
  1732.                            crtc->config->dpll_hw_state.dpll_md);
  1733.         } else {
  1734.                 /* The pixel multiplier can only be updated once the
  1735.                  * DPLL is enabled and the clocks are stable.
  1736.                  *
  1737.                  * So write it again.
  1738.                  */
  1739.                 I915_WRITE(reg, dpll);
  1740.         }
  1741.  
  1742.         /* We do this three times for luck */
  1743.         I915_WRITE(reg, dpll);
  1744.         POSTING_READ(reg);
  1745.         udelay(150); /* wait for warmup */
  1746.         I915_WRITE(reg, dpll);
  1747.         POSTING_READ(reg);
  1748.         udelay(150); /* wait for warmup */
  1749.         I915_WRITE(reg, dpll);
  1750.         POSTING_READ(reg);
  1751.         udelay(150); /* wait for warmup */
  1752. }
  1753.  
  1754. /**
  1755.  * i9xx_disable_pll - disable a PLL
  1756.  * @dev_priv: i915 private structure
  1757.  * @pipe: pipe PLL to disable
  1758.  *
  1759.  * Disable the PLL for @pipe, making sure the pipe is off first.
  1760.  *
  1761.  * Note!  This is for pre-ILK only.
  1762.  */
  1763. static void i9xx_disable_pll(struct intel_crtc *crtc)
  1764. {
  1765.         struct drm_device *dev = crtc->base.dev;
  1766.         struct drm_i915_private *dev_priv = dev->dev_private;
  1767.         enum pipe pipe = crtc->pipe;
  1768.  
  1769.         /* Disable DVO 2x clock on both PLLs if necessary */
  1770.         if (IS_I830(dev) &&
  1771.             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
  1772.             !intel_num_dvo_pipes(dev)) {
  1773.                 I915_WRITE(DPLL(PIPE_B),
  1774.                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
  1775.                 I915_WRITE(DPLL(PIPE_A),
  1776.                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
  1777.         }
  1778.  
  1779.         /* Don't disable pipe or pipe PLLs if needed */
  1780.         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  1781.             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  1782.                 return;
  1783.  
  1784.         /* Make sure the pipe isn't still relying on us */
  1785.         assert_pipe_disabled(dev_priv, pipe);
  1786.  
  1787.         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
  1788.         POSTING_READ(DPLL(pipe));
  1789. }
  1790.  
  1791. static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1792. {
  1793.         u32 val;
  1794.  
  1795.         /* Make sure the pipe isn't still relying on us */
  1796.         assert_pipe_disabled(dev_priv, pipe);
  1797.  
  1798.         /*
  1799.          * Leave integrated clock source and reference clock enabled for pipe B.
  1800.          * The latter is needed for VGA hotplug / manual detection.
  1801.          */
  1802.         val = DPLL_VGA_MODE_DIS;
  1803.         if (pipe == PIPE_B)
  1804.                 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
  1805.         I915_WRITE(DPLL(pipe), val);
  1806.         POSTING_READ(DPLL(pipe));
  1807.  
  1808. }
  1809.  
  1810. static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1811. {
  1812.         enum dpio_channel port = vlv_pipe_to_channel(pipe);
  1813.         u32 val;
  1814.  
  1815.         /* Make sure the pipe isn't still relying on us */
  1816.         assert_pipe_disabled(dev_priv, pipe);
  1817.  
  1818.         /* Set PLL en = 0 */
  1819.         val = DPLL_SSC_REF_CLK_CHV |
  1820.                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
  1821.         if (pipe != PIPE_A)
  1822.                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
  1823.         I915_WRITE(DPLL(pipe), val);
  1824.         POSTING_READ(DPLL(pipe));
  1825.  
  1826.         mutex_lock(&dev_priv->sb_lock);
  1827.  
  1828.         /* Disable 10bit clock to display controller */
  1829.         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
  1830.         val &= ~DPIO_DCLKP_EN;
  1831.         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
  1832.  
  1833.         mutex_unlock(&dev_priv->sb_lock);
  1834. }
  1835.  
  1836. void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
  1837.                          struct intel_digital_port *dport,
  1838.                          unsigned int expected_mask)
  1839. {
  1840.         u32 port_mask;
  1841.         int dpll_reg;
  1842.  
  1843.         switch (dport->port) {
  1844.         case PORT_B:
  1845.                 port_mask = DPLL_PORTB_READY_MASK;
  1846.                 dpll_reg = DPLL(0);
  1847.                 break;
  1848.         case PORT_C:
  1849.                 port_mask = DPLL_PORTC_READY_MASK;
  1850.                 dpll_reg = DPLL(0);
  1851.                 expected_mask <<= 4;
  1852.                 break;
  1853.         case PORT_D:
  1854.                 port_mask = DPLL_PORTD_READY_MASK;
  1855.                 dpll_reg = DPIO_PHY_STATUS;
  1856.                 break;
  1857.         default:
  1858.                 BUG();
  1859.         }
  1860.  
  1861.         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
  1862.                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
  1863.                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
  1864. }
  1865.  
  1866. static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
  1867. {
  1868.         struct drm_device *dev = crtc->base.dev;
  1869.         struct drm_i915_private *dev_priv = dev->dev_private;
  1870.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1871.  
  1872.         if (WARN_ON(pll == NULL))
  1873.                 return;
  1874.  
  1875.         WARN_ON(!pll->config.crtc_mask);
  1876.         if (pll->active == 0) {
  1877.                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
  1878.                 WARN_ON(pll->on);
  1879.                 assert_shared_dpll_disabled(dev_priv, pll);
  1880.  
  1881.                 pll->mode_set(dev_priv, pll);
  1882.         }
  1883. }
  1884.  
  1885. /**
  1886.  * intel_enable_shared_dpll - enable PCH PLL
  1887.  * @dev_priv: i915 private structure
  1888.  * @pipe: pipe PLL to enable
  1889.  *
  1890.  * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1891.  * drives the transcoder clock.
  1892.  */
  1893. static void intel_enable_shared_dpll(struct intel_crtc *crtc)
  1894. {
  1895.         struct drm_device *dev = crtc->base.dev;
  1896.         struct drm_i915_private *dev_priv = dev->dev_private;
  1897.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1898.  
  1899.         if (WARN_ON(pll == NULL))
  1900.                 return;
  1901.  
  1902.         if (WARN_ON(pll->config.crtc_mask == 0))
  1903.                 return;
  1904.  
  1905.         DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
  1906.                       pll->name, pll->active, pll->on,
  1907.                       crtc->base.base.id);
  1908.  
  1909.         if (pll->active++) {
  1910.                 WARN_ON(!pll->on);
  1911.                 assert_shared_dpll_enabled(dev_priv, pll);
  1912.                 return;
  1913.         }
  1914.         WARN_ON(pll->on);
  1915.  
  1916.         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
  1917.  
  1918.         DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1919.         pll->enable(dev_priv, pll);
  1920.         pll->on = true;
  1921. }
  1922.  
  1923. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1924. {
  1925.         struct drm_device *dev = crtc->base.dev;
  1926.         struct drm_i915_private *dev_priv = dev->dev_private;
  1927.         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1928.  
  1929.         /* PCH only available on ILK+ */
  1930.         if (INTEL_INFO(dev)->gen < 5)
  1931.                 return;
  1932.  
  1933.         if (pll == NULL)
  1934.                 return;
  1935.  
  1936.         if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
  1937.                 return;
  1938.  
  1939.         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1940.                       pll->name, pll->active, pll->on,
  1941.                       crtc->base.base.id);
  1942.  
  1943.         if (WARN_ON(pll->active == 0)) {
  1944.                 assert_shared_dpll_disabled(dev_priv, pll);
  1945.                 return;
  1946.         }
  1947.  
  1948.         assert_shared_dpll_enabled(dev_priv, pll);
  1949.         WARN_ON(!pll->on);
  1950.         if (--pll->active)
  1951.                 return;
  1952.  
  1953.         DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1954.         pll->disable(dev_priv, pll);
  1955.         pll->on = false;
  1956.  
  1957.         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
  1958. }
  1959.  
  1960. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1961.                                            enum pipe pipe)
  1962. {
  1963.         struct drm_device *dev = dev_priv->dev;
  1964.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1965.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1966.         uint32_t reg, val, pipeconf_val;
  1967.  
  1968.         /* PCH only available on ILK+ */
  1969.         BUG_ON(!HAS_PCH_SPLIT(dev));
  1970.  
  1971.         /* Make sure PCH DPLL is enabled */
  1972.         assert_shared_dpll_enabled(dev_priv,
  1973.                                    intel_crtc_to_shared_dpll(intel_crtc));
  1974.  
  1975.         /* FDI must be feeding us bits for PCH ports */
  1976.         assert_fdi_tx_enabled(dev_priv, pipe);
  1977.         assert_fdi_rx_enabled(dev_priv, pipe);
  1978.  
  1979.         if (HAS_PCH_CPT(dev)) {
  1980.                 /* Workaround: Set the timing override bit before enabling the
  1981.                  * pch transcoder. */
  1982.                 reg = TRANS_CHICKEN2(pipe);
  1983.                 val = I915_READ(reg);
  1984.                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1985.                 I915_WRITE(reg, val);
  1986.         }
  1987.  
  1988.         reg = PCH_TRANSCONF(pipe);
  1989.         val = I915_READ(reg);
  1990.         pipeconf_val = I915_READ(PIPECONF(pipe));
  1991.  
  1992.         if (HAS_PCH_IBX(dev_priv->dev)) {
  1993.                 /*
  1994.                  * Make the BPC in transcoder be consistent with
  1995.                  * that in pipeconf reg. For HDMI we must use 8bpc
  1996.                  * here for both 8bpc and 12bpc.
  1997.                  */
  1998.                 val &= ~PIPECONF_BPC_MASK;
  1999.                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
  2000.                         val |= PIPECONF_8BPC;
  2001.                 else
  2002.                         val |= pipeconf_val & PIPECONF_BPC_MASK;
  2003.         }
  2004.  
  2005.         val &= ~TRANS_INTERLACE_MASK;
  2006.         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  2007.                 if (HAS_PCH_IBX(dev_priv->dev) &&
  2008.                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
  2009.                         val |= TRANS_LEGACY_INTERLACED_ILK;
  2010.                 else
  2011.                         val |= TRANS_INTERLACED;
  2012.         else
  2013.                 val |= TRANS_PROGRESSIVE;
  2014.  
  2015.         I915_WRITE(reg, val | TRANS_ENABLE);
  2016.         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  2017.                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  2018. }
  2019.  
  2020. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  2021.                                       enum transcoder cpu_transcoder)
  2022. {
  2023.         u32 val, pipeconf_val;
  2024.  
  2025.         /* PCH only available on ILK+ */
  2026.         BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
  2027.  
  2028.         /* FDI must be feeding us bits for PCH ports */
  2029.         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  2030.         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  2031.  
  2032.         /* Workaround: set timing override bit. */
  2033.         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
  2034.         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  2035.         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
  2036.  
  2037.         val = TRANS_ENABLE;
  2038.         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  2039.  
  2040.         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  2041.             PIPECONF_INTERLACED_ILK)
  2042.                 val |= TRANS_INTERLACED;
  2043.         else
  2044.                 val |= TRANS_PROGRESSIVE;
  2045.  
  2046.         I915_WRITE(LPT_TRANSCONF, val);
  2047.         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  2048.                 DRM_ERROR("Failed to enable PCH transcoder\n");
  2049. }
  2050.  
  2051. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  2052.                                             enum pipe pipe)
  2053. {
  2054.         struct drm_device *dev = dev_priv->dev;
  2055.         uint32_t reg, val;
  2056.  
  2057.         /* FDI relies on the transcoder */
  2058.         assert_fdi_tx_disabled(dev_priv, pipe);
  2059.         assert_fdi_rx_disabled(dev_priv, pipe);
  2060.  
  2061.         /* Ports must be off as well */
  2062.         assert_pch_ports_disabled(dev_priv, pipe);
  2063.  
  2064.         reg = PCH_TRANSCONF(pipe);
  2065.         val = I915_READ(reg);
  2066.         val &= ~TRANS_ENABLE;
  2067.         I915_WRITE(reg, val);
  2068.         /* wait for PCH transcoder off, transcoder state */
  2069.         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  2070.                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  2071.  
  2072.         if (!HAS_PCH_IBX(dev)) {
  2073.                 /* Workaround: Clear the timing override chicken bit again. */
  2074.                 reg = TRANS_CHICKEN2(pipe);
  2075.                 val = I915_READ(reg);
  2076.                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  2077.                 I915_WRITE(reg, val);
  2078.         }
  2079. }
  2080.  
  2081. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  2082. {
  2083.         u32 val;
  2084.  
  2085.         val = I915_READ(LPT_TRANSCONF);
  2086.         val &= ~TRANS_ENABLE;
  2087.         I915_WRITE(LPT_TRANSCONF, val);
  2088.         /* wait for PCH transcoder off, transcoder state */
  2089.         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  2090.                 DRM_ERROR("Failed to disable PCH transcoder\n");
  2091.  
  2092.         /* Workaround: clear timing override bit. */
  2093.         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
  2094.         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  2095.         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
  2096. }
  2097.  
  2098. /**
  2099.  * intel_enable_pipe - enable a pipe, asserting requirements
  2100.  * @crtc: crtc responsible for the pipe
  2101.  *
  2102.  * Enable @crtc's pipe, making sure that various hardware specific requirements
  2103.  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  2104.  */
  2105. static void intel_enable_pipe(struct intel_crtc *crtc)
  2106. {
  2107.         struct drm_device *dev = crtc->base.dev;
  2108.         struct drm_i915_private *dev_priv = dev->dev_private;
  2109.         enum pipe pipe = crtc->pipe;
  2110.         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  2111.                                                                       pipe);
  2112.         enum pipe pch_transcoder;
  2113.         int reg;
  2114.         u32 val;
  2115.  
  2116.         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
  2117.  
  2118.         assert_planes_disabled(dev_priv, pipe);
  2119.         assert_cursor_disabled(dev_priv, pipe);
  2120.         assert_sprites_disabled(dev_priv, pipe);
  2121.  
  2122.         if (HAS_PCH_LPT(dev_priv->dev))
  2123.                 pch_transcoder = TRANSCODER_A;
  2124.         else
  2125.                 pch_transcoder = pipe;
  2126.  
  2127.         /*
  2128.          * A pipe without a PLL won't actually be able to drive bits from
  2129.          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
  2130.          * need the check.
  2131.          */
  2132.         if (HAS_GMCH_DISPLAY(dev_priv->dev))
  2133.                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
  2134.                         assert_dsi_pll_enabled(dev_priv);
  2135.                 else
  2136.                         assert_pll_enabled(dev_priv, pipe);
  2137.         else {
  2138.                 if (crtc->config->has_pch_encoder) {
  2139.                         /* if driving the PCH, we need FDI enabled */
  2140.                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  2141.                         assert_fdi_tx_pll_enabled(dev_priv,
  2142.                                                   (enum pipe) cpu_transcoder);
  2143.                 }
  2144.                 /* FIXME: assert CPU port conditions for SNB+ */
  2145.         }
  2146.  
  2147.         reg = PIPECONF(cpu_transcoder);
  2148.         val = I915_READ(reg);
  2149.         if (val & PIPECONF_ENABLE) {
  2150.                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  2151.                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
  2152.                 return;
  2153.         }
  2154.  
  2155.         I915_WRITE(reg, val | PIPECONF_ENABLE);
  2156.         POSTING_READ(reg);
  2157. }
  2158.  
  2159. /**
  2160.  * intel_disable_pipe - disable a pipe, asserting requirements
  2161.  * @crtc: crtc whose pipes is to be disabled
  2162.  *
  2163.  * Disable the pipe of @crtc, making sure that various hardware
  2164.  * specific requirements are met, if applicable, e.g. plane
  2165.  * disabled, panel fitter off, etc.
  2166.  *
  2167.  * Will wait until the pipe has shut down before returning.
  2168.  */
  2169. static void intel_disable_pipe(struct intel_crtc *crtc)
  2170. {
  2171.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2172.         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  2173.         enum pipe pipe = crtc->pipe;
  2174.         int reg;
  2175.         u32 val;
  2176.  
  2177.         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
  2178.  
  2179.         /*
  2180.          * Make sure planes won't keep trying to pump pixels to us,
  2181.          * or we might hang the display.
  2182.          */
  2183.         assert_planes_disabled(dev_priv, pipe);
  2184.         assert_cursor_disabled(dev_priv, pipe);
  2185.         assert_sprites_disabled(dev_priv, pipe);
  2186.  
  2187.         reg = PIPECONF(cpu_transcoder);
  2188.         val = I915_READ(reg);
  2189.         if ((val & PIPECONF_ENABLE) == 0)
  2190.                 return;
  2191.  
  2192.         /*
  2193.          * Double wide has implications for planes
  2194.          * so best keep it disabled when not needed.
  2195.          */
  2196.         if (crtc->config->double_wide)
  2197.                 val &= ~PIPECONF_DOUBLE_WIDE;
  2198.  
  2199.         /* Don't disable pipe or pipe PLLs if needed */
  2200.         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
  2201.             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  2202.                 val &= ~PIPECONF_ENABLE;
  2203.  
  2204.         I915_WRITE(reg, val);
  2205.         if ((val & PIPECONF_ENABLE) == 0)
  2206.                 intel_wait_for_pipe_off(crtc);
  2207. }
  2208.  
  2209. static bool need_vtd_wa(struct drm_device *dev)
  2210. {
  2211. #ifdef CONFIG_INTEL_IOMMU
  2212.         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  2213.                 return true;
  2214. #endif
  2215.         return false;
  2216. }
  2217.  
  2218. unsigned int
  2219. intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
  2220.                   uint64_t fb_format_modifier, unsigned int plane)
  2221. {
  2222.         unsigned int tile_height;
  2223.         uint32_t pixel_bytes;
  2224.  
  2225.         switch (fb_format_modifier) {
  2226.         case DRM_FORMAT_MOD_NONE:
  2227.                 tile_height = 1;
  2228.                 break;
  2229.         case I915_FORMAT_MOD_X_TILED:
  2230.                 tile_height = IS_GEN2(dev) ? 16 : 8;
  2231.                 break;
  2232.         case I915_FORMAT_MOD_Y_TILED:
  2233.                 tile_height = 32;
  2234.                 break;
  2235.         case I915_FORMAT_MOD_Yf_TILED:
  2236.                 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
  2237.                 switch (pixel_bytes) {
  2238.                 default:
  2239.                 case 1:
  2240.                         tile_height = 64;
  2241.                         break;
  2242.                 case 2:
  2243.                 case 4:
  2244.                         tile_height = 32;
  2245.                         break;
  2246.                 case 8:
  2247.                         tile_height = 16;
  2248.                         break;
  2249.                 case 16:
  2250.                         WARN_ONCE(1,
  2251.                                   "128-bit pixels are not supported for display!");
  2252.                         tile_height = 16;
  2253.                         break;
  2254.                 }
  2255.                 break;
  2256.         default:
  2257.                 MISSING_CASE(fb_format_modifier);
  2258.                 tile_height = 1;
  2259.                 break;
  2260.         }
  2261.  
  2262.         return tile_height;
  2263. }
  2264.  
  2265. unsigned int
  2266. intel_fb_align_height(struct drm_device *dev, unsigned int height,
  2267.                       uint32_t pixel_format, uint64_t fb_format_modifier)
  2268. {
  2269.         return ALIGN(height, intel_tile_height(dev, pixel_format,
  2270.                                                fb_format_modifier, 0));
  2271. }
  2272.  
  2273. static int
  2274. intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
  2275.                         const struct drm_plane_state *plane_state)
  2276. {
  2277.         struct intel_rotation_info *info = &view->rotation_info;
  2278.         unsigned int tile_height, tile_pitch;
  2279.  
  2280.         *view = i915_ggtt_view_normal;
  2281.  
  2282.         if (!plane_state)
  2283.                 return 0;
  2284.  
  2285.         if (!intel_rotation_90_or_270(plane_state->rotation))
  2286.                 return 0;
  2287.  
  2288.         *view = i915_ggtt_view_rotated;
  2289.  
  2290.         info->height = fb->height;
  2291.         info->pixel_format = fb->pixel_format;
  2292.         info->pitch = fb->pitches[0];
  2293.         info->uv_offset = fb->offsets[1];
  2294.         info->fb_modifier = fb->modifier[0];
  2295.  
  2296.         tile_height = intel_tile_height(fb->dev, fb->pixel_format,
  2297.                                         fb->modifier[0], 0);
  2298.         tile_pitch = PAGE_SIZE / tile_height;
  2299.         info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
  2300.         info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
  2301.         info->size = info->width_pages * info->height_pages * PAGE_SIZE;
  2302.  
  2303.         if (info->pixel_format == DRM_FORMAT_NV12) {
  2304.                 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
  2305.                                                 fb->modifier[0], 1);
  2306.                 tile_pitch = PAGE_SIZE / tile_height;
  2307.                 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
  2308.                 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
  2309.                                                      tile_height);
  2310.                 info->size_uv = info->width_pages_uv * info->height_pages_uv *
  2311.                                 PAGE_SIZE;
  2312.         }
  2313.  
  2314.         return 0;
  2315. }
  2316.  
  2317. static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
  2318. {
  2319.         if (INTEL_INFO(dev_priv)->gen >= 9)
  2320.                 return 256 * 1024;
  2321.         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
  2322.                  IS_VALLEYVIEW(dev_priv))
  2323.                 return 128 * 1024;
  2324.         else if (INTEL_INFO(dev_priv)->gen >= 4)
  2325.                 return 4 * 1024;
  2326.         else
  2327.                 return 0;
  2328. }
  2329.  
  2330. int
  2331. intel_pin_and_fence_fb_obj(struct drm_plane *plane,
  2332.                            struct drm_framebuffer *fb,
  2333.                            const struct drm_plane_state *plane_state,
  2334.                            struct intel_engine_cs *pipelined,
  2335.                            struct drm_i915_gem_request **pipelined_request)
  2336. {
  2337.         struct drm_device *dev = fb->dev;
  2338.         struct drm_i915_private *dev_priv = dev->dev_private;
  2339.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  2340.         struct i915_ggtt_view view;
  2341.         u32 alignment;
  2342.         int ret;
  2343.  
  2344.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  2345.  
  2346.         switch (fb->modifier[0]) {
  2347.         case DRM_FORMAT_MOD_NONE:
  2348.                 alignment = intel_linear_alignment(dev_priv);
  2349.                 break;
  2350.         case I915_FORMAT_MOD_X_TILED:
  2351.                 if (INTEL_INFO(dev)->gen >= 9)
  2352.                         alignment = 256 * 1024;
  2353.                 else {
  2354.                         /* pin() will align the object as required by fence */
  2355.                         alignment = 0;
  2356.                 }
  2357.                 break;
  2358.         case I915_FORMAT_MOD_Y_TILED:
  2359.         case I915_FORMAT_MOD_Yf_TILED:
  2360.                 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
  2361.                           "Y tiling bo slipped through, driver bug!\n"))
  2362.                         return -EINVAL;
  2363.                 alignment = 1 * 1024 * 1024;
  2364.                 break;
  2365.         default:
  2366.                 MISSING_CASE(fb->modifier[0]);
  2367.                 return -EINVAL;
  2368.         }
  2369.  
  2370.         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
  2371.         if (ret)
  2372.                 return ret;
  2373.  
  2374.         /* Note that the w/a also requires 64 PTE of padding following the
  2375.          * bo. We currently fill all unused PTE with the shadow page and so
  2376.          * we should always have valid PTE following the scanout preventing
  2377.          * the VT-d warning.
  2378.          */
  2379.         if (need_vtd_wa(dev) && alignment < 256 * 1024)
  2380.                 alignment = 256 * 1024;
  2381.  
  2382.         /*
  2383.          * Global gtt pte registers are special registers which actually forward
  2384.          * writes to a chunk of system memory. Which means that there is no risk
  2385.          * that the register values disappear as soon as we call
  2386.          * intel_runtime_pm_put(), so it is correct to wrap only the
  2387.          * pin/unpin/fence and not more.
  2388.          */
  2389.         intel_runtime_pm_get(dev_priv);
  2390.  
  2391.         dev_priv->mm.interruptible = false;
  2392.         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
  2393.                                                    pipelined_request, &view);
  2394.         if (ret)
  2395.                 goto err_interruptible;
  2396.  
  2397.         /* Install a fence for tiled scan-out. Pre-i965 always needs a
  2398.          * fence, whereas 965+ only requires a fence if using
  2399.          * framebuffer compression.  For simplicity, we always install
  2400.          * a fence as the cost is not that onerous.
  2401.          */
  2402.         if (view.type == I915_GGTT_VIEW_NORMAL) {
  2403.                 ret = i915_gem_object_get_fence(obj);
  2404.                 if (ret == -EDEADLK) {
  2405.                         /*
  2406.                          * -EDEADLK means there are no free fences
  2407.                          * no pending flips.
  2408.                          *
  2409.                          * This is propagated to atomic, but it uses
  2410.                          * -EDEADLK to force a locking recovery, so
  2411.                          * change the returned error to -EBUSY.
  2412.                          */
  2413.                         ret = -EBUSY;
  2414.                         goto err_unpin;
  2415.                 } else if (ret)
  2416.                         goto err_unpin;
  2417.  
  2418.                 i915_gem_object_pin_fence(obj);
  2419.         }
  2420.  
  2421.         dev_priv->mm.interruptible = true;
  2422.         intel_runtime_pm_put(dev_priv);
  2423.         return 0;
  2424.  
  2425. err_unpin:
  2426.         i915_gem_object_unpin_from_display_plane(obj, &view);
  2427. err_interruptible:
  2428.         dev_priv->mm.interruptible = true;
  2429.         intel_runtime_pm_put(dev_priv);
  2430.         return ret;
  2431. }
  2432.  
  2433. static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
  2434.                                const struct drm_plane_state *plane_state)
  2435. {
  2436.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  2437.         struct i915_ggtt_view view;
  2438.         int ret;
  2439.  
  2440.         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
  2441.  
  2442.         ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
  2443.         WARN_ONCE(ret, "Couldn't get view from plane state!");
  2444.  
  2445.         if (view.type == I915_GGTT_VIEW_NORMAL)
  2446.                 i915_gem_object_unpin_fence(obj);
  2447.  
  2448.         i915_gem_object_unpin_from_display_plane(obj, &view);
  2449. }
  2450.  
  2451. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  2452.  * is assumed to be a power-of-two. */
  2453. unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
  2454.                                              int *x, int *y,
  2455.                                              unsigned int tiling_mode,
  2456.                                              unsigned int cpp,
  2457.                                              unsigned int pitch)
  2458. {
  2459.         if (tiling_mode != I915_TILING_NONE) {
  2460.                 unsigned int tile_rows, tiles;
  2461.  
  2462.                 tile_rows = *y / 8;
  2463.                 *y %= 8;
  2464.  
  2465.                 tiles = *x / (512/cpp);
  2466.                 *x %= 512/cpp;
  2467.  
  2468.                 return tile_rows * pitch * 8 + tiles * 4096;
  2469.         } else {
  2470.                 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
  2471.                 unsigned int offset;
  2472.  
  2473.                 offset = *y * pitch + *x * cpp;
  2474.                 *y = (offset & alignment) / pitch;
  2475.                 *x = ((offset & alignment) - *y * pitch) / cpp;
  2476.                 return offset & ~alignment;
  2477.         }
  2478. }
  2479.  
  2480. static int i9xx_format_to_fourcc(int format)
  2481. {
  2482.         switch (format) {
  2483.         case DISPPLANE_8BPP:
  2484.                 return DRM_FORMAT_C8;
  2485.         case DISPPLANE_BGRX555:
  2486.                 return DRM_FORMAT_XRGB1555;
  2487.         case DISPPLANE_BGRX565:
  2488.                 return DRM_FORMAT_RGB565;
  2489.         default:
  2490.         case DISPPLANE_BGRX888:
  2491.                 return DRM_FORMAT_XRGB8888;
  2492.         case DISPPLANE_RGBX888:
  2493.                 return DRM_FORMAT_XBGR8888;
  2494.         case DISPPLANE_BGRX101010:
  2495.                 return DRM_FORMAT_XRGB2101010;
  2496.         case DISPPLANE_RGBX101010:
  2497.                 return DRM_FORMAT_XBGR2101010;
  2498.         }
  2499. }
  2500.  
  2501. static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
  2502. {
  2503.         switch (format) {
  2504.         case PLANE_CTL_FORMAT_RGB_565:
  2505.                 return DRM_FORMAT_RGB565;
  2506.         default:
  2507.         case PLANE_CTL_FORMAT_XRGB_8888:
  2508.                 if (rgb_order) {
  2509.                         if (alpha)
  2510.                                 return DRM_FORMAT_ABGR8888;
  2511.                         else
  2512.                                 return DRM_FORMAT_XBGR8888;
  2513.                 } else {
  2514.                         if (alpha)
  2515.                                 return DRM_FORMAT_ARGB8888;
  2516.                         else
  2517.                                 return DRM_FORMAT_XRGB8888;
  2518.                 }
  2519.         case PLANE_CTL_FORMAT_XRGB_2101010:
  2520.                 if (rgb_order)
  2521.                         return DRM_FORMAT_XBGR2101010;
  2522.                 else
  2523.                         return DRM_FORMAT_XRGB2101010;
  2524.         }
  2525. }
  2526.  
  2527. static bool
  2528. intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
  2529.                               struct intel_initial_plane_config *plane_config)
  2530. {
  2531.         struct drm_device *dev = crtc->base.dev;
  2532.         struct drm_i915_private *dev_priv = to_i915(dev);
  2533.         struct drm_i915_gem_object *obj = NULL;
  2534.         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  2535.         struct drm_framebuffer *fb = &plane_config->fb->base;
  2536.         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
  2537.         u32 size_aligned = round_up(plane_config->base + plane_config->size,
  2538.                                     PAGE_SIZE);
  2539.  
  2540.         size_aligned -= base_aligned;
  2541.  
  2542.         if (plane_config->size == 0)
  2543.                 return false;
  2544.  
  2545.         /* If the FB is too big, just don't use it since fbdev is not very
  2546.          * important and we should probably use that space with FBC or other
  2547.          * features. */
  2548.         if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
  2549.                 return false;
  2550.  
  2551.         obj = i915_gem_object_create_stolen_for_preallocated(dev,
  2552.                                                              base_aligned,
  2553.                                                              base_aligned,
  2554.                                                              size_aligned);
  2555.         if (!obj)
  2556.                 return false;
  2557.  
  2558.         obj->tiling_mode = plane_config->tiling;
  2559.         if (obj->tiling_mode == I915_TILING_X)
  2560.                 obj->stride = fb->pitches[0];
  2561.  
  2562.         mode_cmd.pixel_format = fb->pixel_format;
  2563.         mode_cmd.width = fb->width;
  2564.         mode_cmd.height = fb->height;
  2565.         mode_cmd.pitches[0] = fb->pitches[0];
  2566.         mode_cmd.modifier[0] = fb->modifier[0];
  2567.         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
  2568.  
  2569.         mutex_lock(&dev->struct_mutex);
  2570.         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
  2571.                                    &mode_cmd, obj)) {
  2572.                 DRM_DEBUG_KMS("intel fb init failed\n");
  2573.                 goto out_unref_obj;
  2574.         }
  2575.         mutex_unlock(&dev->struct_mutex);
  2576.  
  2577.         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
  2578.         return true;
  2579.  
  2580. out_unref_obj:
  2581.         drm_gem_object_unreference(&obj->base);
  2582.         mutex_unlock(&dev->struct_mutex);
  2583.         return false;
  2584. }
  2585.  
  2586. /* Update plane->state->fb to match plane->fb after driver-internal updates */
  2587. static void
  2588. update_state_fb(struct drm_plane *plane)
  2589. {
  2590.         if (plane->fb == plane->state->fb)
  2591.                 return;
  2592.  
  2593.         if (plane->state->fb)
  2594.                 drm_framebuffer_unreference(plane->state->fb);
  2595.         plane->state->fb = plane->fb;
  2596.         if (plane->state->fb)
  2597.                 drm_framebuffer_reference(plane->state->fb);
  2598. }
  2599.  
  2600. static void
  2601. intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
  2602.                              struct intel_initial_plane_config *plane_config)
  2603. {
  2604.         struct drm_device *dev = intel_crtc->base.dev;
  2605.         struct drm_i915_private *dev_priv = dev->dev_private;
  2606.         struct drm_crtc *c;
  2607.         struct intel_crtc *i;
  2608.         struct drm_i915_gem_object *obj;
  2609.         struct drm_plane *primary = intel_crtc->base.primary;
  2610.         struct drm_plane_state *plane_state = primary->state;
  2611.         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
  2612.         struct intel_plane *intel_plane = to_intel_plane(primary);
  2613.         struct drm_framebuffer *fb;
  2614.  
  2615.         if (!plane_config->fb)
  2616.                 return;
  2617.  
  2618.         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
  2619.                 fb = &plane_config->fb->base;
  2620.                 goto valid_fb;
  2621.         }
  2622.  
  2623.         kfree(plane_config->fb);
  2624.  
  2625.         /*
  2626.          * Failed to alloc the obj, check to see if we should share
  2627.          * an fb with another CRTC instead
  2628.          */
  2629.         for_each_crtc(dev, c) {
  2630.                 i = to_intel_crtc(c);
  2631.  
  2632.                 if (c == &intel_crtc->base)
  2633.                         continue;
  2634.  
  2635.                 if (!i->active)
  2636.                         continue;
  2637.  
  2638.                 fb = c->primary->fb;
  2639.                 if (!fb)
  2640.                         continue;
  2641.  
  2642.                 obj = intel_fb_obj(fb);
  2643.                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
  2644.                         drm_framebuffer_reference(fb);
  2645.                         goto valid_fb;
  2646.                 }
  2647.         }
  2648.  
  2649.         /*
  2650.          * We've failed to reconstruct the BIOS FB.  Current display state
  2651.          * indicates that the primary plane is visible, but has a NULL FB,
  2652.          * which will lead to problems later if we don't fix it up.  The
  2653.          * simplest solution is to just disable the primary plane now and
  2654.          * pretend the BIOS never had it enabled.
  2655.          */
  2656.         to_intel_plane_state(plane_state)->visible = false;
  2657.         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
  2658.         intel_pre_disable_primary(&intel_crtc->base);
  2659.         intel_plane->disable_plane(primary, &intel_crtc->base);
  2660.  
  2661.         return;
  2662.  
  2663. valid_fb:
  2664.         plane_state->src_x = 0;
  2665.         plane_state->src_y = 0;
  2666.         plane_state->src_w = fb->width << 16;
  2667.         plane_state->src_h = fb->height << 16;
  2668.  
  2669.         plane_state->crtc_x = 0;
  2670.         plane_state->crtc_y = 0;
  2671.         plane_state->crtc_w = fb->width;
  2672.         plane_state->crtc_h = fb->height;
  2673.  
  2674.         obj = intel_fb_obj(fb);
  2675.         if (obj->tiling_mode != I915_TILING_NONE)
  2676.                 dev_priv->preserve_bios_swizzle = true;
  2677.  
  2678.         drm_framebuffer_reference(fb);
  2679.         primary->fb = primary->state->fb = fb;
  2680.         primary->crtc = primary->state->crtc = &intel_crtc->base;
  2681.         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
  2682.         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
  2683. }
  2684.  
  2685. static void i9xx_update_primary_plane(struct drm_crtc *crtc,
  2686.                                       struct drm_framebuffer *fb,
  2687.                                       int x, int y)
  2688. {
  2689.         struct drm_device *dev = crtc->dev;
  2690.         struct drm_i915_private *dev_priv = dev->dev_private;
  2691.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2692.         struct drm_plane *primary = crtc->primary;
  2693.         bool visible = to_intel_plane_state(primary->state)->visible;
  2694.         struct drm_i915_gem_object *obj;
  2695.         int plane = intel_crtc->plane;
  2696.         unsigned long linear_offset;
  2697.         u32 dspcntr;
  2698.         u32 reg = DSPCNTR(plane);
  2699.         int pixel_size;
  2700.  
  2701.         if (!visible || !fb) {
  2702.                 I915_WRITE(reg, 0);
  2703.                 if (INTEL_INFO(dev)->gen >= 4)
  2704.                         I915_WRITE(DSPSURF(plane), 0);
  2705.                 else
  2706.                         I915_WRITE(DSPADDR(plane), 0);
  2707.                 POSTING_READ(reg);
  2708.                 return;
  2709.         }
  2710.  
  2711.         obj = intel_fb_obj(fb);
  2712.         if (WARN_ON(obj == NULL))
  2713.                 return;
  2714.  
  2715.         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  2716.  
  2717.         dspcntr = DISPPLANE_GAMMA_ENABLE;
  2718.  
  2719.         dspcntr |= DISPLAY_PLANE_ENABLE;
  2720.  
  2721.         if (INTEL_INFO(dev)->gen < 4) {
  2722.                 if (intel_crtc->pipe == PIPE_B)
  2723.                         dspcntr |= DISPPLANE_SEL_PIPE_B;
  2724.  
  2725.                 /* pipesrc and dspsize control the size that is scaled from,
  2726.                  * which should always be the user's requested size.
  2727.                  */
  2728.                 I915_WRITE(DSPSIZE(plane),
  2729.                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
  2730.                            (intel_crtc->config->pipe_src_w - 1));
  2731.                 I915_WRITE(DSPPOS(plane), 0);
  2732.         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
  2733.                 I915_WRITE(PRIMSIZE(plane),
  2734.                            ((intel_crtc->config->pipe_src_h - 1) << 16) |
  2735.                            (intel_crtc->config->pipe_src_w - 1));
  2736.                 I915_WRITE(PRIMPOS(plane), 0);
  2737.                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
  2738.         }
  2739.  
  2740.         switch (fb->pixel_format) {
  2741.         case DRM_FORMAT_C8:
  2742.                 dspcntr |= DISPPLANE_8BPP;
  2743.                 break;
  2744.         case DRM_FORMAT_XRGB1555:
  2745.                 dspcntr |= DISPPLANE_BGRX555;
  2746.                 break;
  2747.         case DRM_FORMAT_RGB565:
  2748.                 dspcntr |= DISPPLANE_BGRX565;
  2749.                 break;
  2750.         case DRM_FORMAT_XRGB8888:
  2751.                 dspcntr |= DISPPLANE_BGRX888;
  2752.                 break;
  2753.         case DRM_FORMAT_XBGR8888:
  2754.                 dspcntr |= DISPPLANE_RGBX888;
  2755.                 break;
  2756.         case DRM_FORMAT_XRGB2101010:
  2757.                 dspcntr |= DISPPLANE_BGRX101010;
  2758.                 break;
  2759.         case DRM_FORMAT_XBGR2101010:
  2760.                 dspcntr |= DISPPLANE_RGBX101010;
  2761.                 break;
  2762.         default:
  2763.                 BUG();
  2764.         }
  2765.  
  2766.         if (INTEL_INFO(dev)->gen >= 4 &&
  2767.             obj->tiling_mode != I915_TILING_NONE)
  2768.                 dspcntr |= DISPPLANE_TILED;
  2769.  
  2770.         if (IS_G4X(dev))
  2771.                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  2772.  
  2773.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  2774.  
  2775.         if (INTEL_INFO(dev)->gen >= 4) {
  2776.                 intel_crtc->dspaddr_offset =
  2777.                         intel_gen4_compute_page_offset(dev_priv,
  2778.                                                        &x, &y, obj->tiling_mode,
  2779.                                                        pixel_size,
  2780.                                                        fb->pitches[0]);
  2781.                 linear_offset -= intel_crtc->dspaddr_offset;
  2782.         } else {
  2783.                 intel_crtc->dspaddr_offset = linear_offset;
  2784.         }
  2785.  
  2786.         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
  2787.                 dspcntr |= DISPPLANE_ROTATE_180;
  2788.  
  2789.                 x += (intel_crtc->config->pipe_src_w - 1);
  2790.                 y += (intel_crtc->config->pipe_src_h - 1);
  2791.  
  2792.                 /* Finding the last pixel of the last line of the display
  2793.                 data and adding to linear_offset*/
  2794.                 linear_offset +=
  2795.                         (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
  2796.                         (intel_crtc->config->pipe_src_w - 1) * pixel_size;
  2797.         }
  2798.  
  2799.         intel_crtc->adjusted_x = x;
  2800.         intel_crtc->adjusted_y = y;
  2801.  
  2802.         I915_WRITE(reg, dspcntr);
  2803.  
  2804.         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2805.         if (INTEL_INFO(dev)->gen >= 4) {
  2806.                 I915_WRITE(DSPSURF(plane),
  2807.                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2808.                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2809.                 I915_WRITE(DSPLINOFF(plane), linear_offset);
  2810.         } else
  2811.                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  2812.         POSTING_READ(reg);
  2813. }
  2814.  
  2815. static void ironlake_update_primary_plane(struct drm_crtc *crtc,
  2816.                                           struct drm_framebuffer *fb,
  2817.                                           int x, int y)
  2818. {
  2819.         struct drm_device *dev = crtc->dev;
  2820.         struct drm_i915_private *dev_priv = dev->dev_private;
  2821.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2822.         struct drm_plane *primary = crtc->primary;
  2823.         bool visible = to_intel_plane_state(primary->state)->visible;
  2824.         struct drm_i915_gem_object *obj;
  2825.         int plane = intel_crtc->plane;
  2826.         unsigned long linear_offset;
  2827.         u32 dspcntr;
  2828.         u32 reg = DSPCNTR(plane);
  2829.         int pixel_size;
  2830.  
  2831.         if (!visible || !fb) {
  2832.                 I915_WRITE(reg, 0);
  2833.                 I915_WRITE(DSPSURF(plane), 0);
  2834.                 POSTING_READ(reg);
  2835.                 return;
  2836.         }
  2837.  
  2838.         obj = intel_fb_obj(fb);
  2839.         if (WARN_ON(obj == NULL))
  2840.                 return;
  2841.  
  2842.         pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  2843.  
  2844.         dspcntr = DISPPLANE_GAMMA_ENABLE;
  2845.  
  2846.         dspcntr |= DISPLAY_PLANE_ENABLE;
  2847.  
  2848.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  2849.                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
  2850.  
  2851.         switch (fb->pixel_format) {
  2852.         case DRM_FORMAT_C8:
  2853.                 dspcntr |= DISPPLANE_8BPP;
  2854.                 break;
  2855.         case DRM_FORMAT_RGB565:
  2856.                 dspcntr |= DISPPLANE_BGRX565;
  2857.                 break;
  2858.         case DRM_FORMAT_XRGB8888:
  2859.                 dspcntr |= DISPPLANE_BGRX888;
  2860.                 break;
  2861.         case DRM_FORMAT_XBGR8888:
  2862.                 dspcntr |= DISPPLANE_RGBX888;
  2863.                 break;
  2864.         case DRM_FORMAT_XRGB2101010:
  2865.                 dspcntr |= DISPPLANE_BGRX101010;
  2866.                 break;
  2867.         case DRM_FORMAT_XBGR2101010:
  2868.                 dspcntr |= DISPPLANE_RGBX101010;
  2869.                 break;
  2870.         default:
  2871.                 BUG();
  2872.         }
  2873.  
  2874.         if (obj->tiling_mode != I915_TILING_NONE)
  2875.                 dspcntr |= DISPPLANE_TILED;
  2876.  
  2877.         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
  2878.                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  2879.  
  2880.         linear_offset = y * fb->pitches[0] + x * pixel_size;
  2881.         intel_crtc->dspaddr_offset =
  2882.                 intel_gen4_compute_page_offset(dev_priv,
  2883.                                                &x, &y, obj->tiling_mode,
  2884.                                                pixel_size,
  2885.                                                fb->pitches[0]);
  2886.         linear_offset -= intel_crtc->dspaddr_offset;
  2887.         if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
  2888.                 dspcntr |= DISPPLANE_ROTATE_180;
  2889.  
  2890.                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
  2891.                         x += (intel_crtc->config->pipe_src_w - 1);
  2892.                         y += (intel_crtc->config->pipe_src_h - 1);
  2893.  
  2894.                         /* Finding the last pixel of the last line of the display
  2895.                         data and adding to linear_offset*/
  2896.                         linear_offset +=
  2897.                                 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
  2898.                                 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
  2899.                 }
  2900.         }
  2901.  
  2902.         intel_crtc->adjusted_x = x;
  2903.         intel_crtc->adjusted_y = y;
  2904.  
  2905.         I915_WRITE(reg, dspcntr);
  2906.  
  2907.         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  2908.         I915_WRITE(DSPSURF(plane),
  2909.                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  2910.         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  2911.                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  2912.         } else {
  2913.                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  2914.                 I915_WRITE(DSPLINOFF(plane), linear_offset);
  2915.         }
  2916.         POSTING_READ(reg);
  2917. }
  2918.  
  2919. u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
  2920.                               uint32_t pixel_format)
  2921. {
  2922.         u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
  2923.  
  2924.         /*
  2925.          * The stride is either expressed as a multiple of 64 bytes
  2926.          * chunks for linear buffers or in number of tiles for tiled
  2927.          * buffers.
  2928.          */
  2929.         switch (fb_modifier) {
  2930.         case DRM_FORMAT_MOD_NONE:
  2931.                 return 64;
  2932.         case I915_FORMAT_MOD_X_TILED:
  2933.                 if (INTEL_INFO(dev)->gen == 2)
  2934.                         return 128;
  2935.                 return 512;
  2936.         case I915_FORMAT_MOD_Y_TILED:
  2937.                 /* No need to check for old gens and Y tiling since this is
  2938.                  * about the display engine and those will be blocked before
  2939.                  * we get here.
  2940.                  */
  2941.                 return 128;
  2942.         case I915_FORMAT_MOD_Yf_TILED:
  2943.                 if (bits_per_pixel == 8)
  2944.                         return 64;
  2945.                 else
  2946.                         return 128;
  2947.         default:
  2948.                 MISSING_CASE(fb_modifier);
  2949.                 return 64;
  2950.         }
  2951. }
  2952.  
  2953. unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
  2954.                                      struct drm_i915_gem_object *obj,
  2955.                                      unsigned int plane)
  2956. {
  2957.         const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
  2958.         struct i915_vma *vma;
  2959.         unsigned char *offset;
  2960.  
  2961.         if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
  2962.                 view = &i915_ggtt_view_rotated;
  2963.  
  2964.         vma = i915_gem_obj_to_ggtt_view(obj, view);
  2965.         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
  2966.                 view->type))
  2967.                 return -1;
  2968.  
  2969.         offset = (unsigned char *)vma->node.start;
  2970.  
  2971.         if (plane == 1) {
  2972.                 offset += vma->ggtt_view.rotation_info.uv_start_page *
  2973.                           PAGE_SIZE;
  2974.         }
  2975.  
  2976.         return (unsigned long)offset;
  2977. }
  2978.  
  2979. static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
  2980. {
  2981.         struct drm_device *dev = intel_crtc->base.dev;
  2982.         struct drm_i915_private *dev_priv = dev->dev_private;
  2983.  
  2984.         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
  2985.         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
  2986.         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
  2987. }
  2988.  
  2989. /*
  2990.  * This function detaches (aka. unbinds) unused scalers in hardware
  2991.  */
  2992. static void skl_detach_scalers(struct intel_crtc *intel_crtc)
  2993. {
  2994.         struct intel_crtc_scaler_state *scaler_state;
  2995.         int i;
  2996.  
  2997.         scaler_state = &intel_crtc->config->scaler_state;
  2998.  
  2999.         /* loop through and disable scalers that aren't in use */
  3000.         for (i = 0; i < intel_crtc->num_scalers; i++) {
  3001.                 if (!scaler_state->scalers[i].in_use)
  3002.                         skl_detach_scaler(intel_crtc, i);
  3003.         }
  3004. }
  3005.  
  3006. u32 skl_plane_ctl_format(uint32_t pixel_format)
  3007. {
  3008.         switch (pixel_format) {
  3009.         case DRM_FORMAT_C8:
  3010.                 return PLANE_CTL_FORMAT_INDEXED;
  3011.         case DRM_FORMAT_RGB565:
  3012.                 return PLANE_CTL_FORMAT_RGB_565;
  3013.         case DRM_FORMAT_XBGR8888:
  3014.                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
  3015.         case DRM_FORMAT_XRGB8888:
  3016.                 return PLANE_CTL_FORMAT_XRGB_8888;
  3017.         /*
  3018.          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
  3019.          * to be already pre-multiplied. We need to add a knob (or a different
  3020.          * DRM_FORMAT) for user-space to configure that.
  3021.          */
  3022.         case DRM_FORMAT_ABGR8888:
  3023.                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
  3024.                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
  3025.         case DRM_FORMAT_ARGB8888:
  3026.                 return PLANE_CTL_FORMAT_XRGB_8888 |
  3027.                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
  3028.         case DRM_FORMAT_XRGB2101010:
  3029.                 return PLANE_CTL_FORMAT_XRGB_2101010;
  3030.         case DRM_FORMAT_XBGR2101010:
  3031.                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
  3032.         case DRM_FORMAT_YUYV:
  3033.                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
  3034.         case DRM_FORMAT_YVYU:
  3035.                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
  3036.         case DRM_FORMAT_UYVY:
  3037.                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
  3038.         case DRM_FORMAT_VYUY:
  3039.                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
  3040.         default:
  3041.                 MISSING_CASE(pixel_format);
  3042.         }
  3043.  
  3044.         return 0;
  3045. }
  3046.  
  3047. u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
  3048. {
  3049.         switch (fb_modifier) {
  3050.         case DRM_FORMAT_MOD_NONE:
  3051.                 break;
  3052.         case I915_FORMAT_MOD_X_TILED:
  3053.                 return PLANE_CTL_TILED_X;
  3054.         case I915_FORMAT_MOD_Y_TILED:
  3055.                 return PLANE_CTL_TILED_Y;
  3056.         case I915_FORMAT_MOD_Yf_TILED:
  3057.                 return PLANE_CTL_TILED_YF;
  3058.         default:
  3059.                 MISSING_CASE(fb_modifier);
  3060.         }
  3061.  
  3062.         return 0;
  3063. }
  3064.  
  3065. u32 skl_plane_ctl_rotation(unsigned int rotation)
  3066. {
  3067.         switch (rotation) {
  3068.         case BIT(DRM_ROTATE_0):
  3069.                 break;
  3070.         /*
  3071.          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
  3072.          * while i915 HW rotation is clockwise, thats why this swapping.
  3073.          */
  3074.         case BIT(DRM_ROTATE_90):
  3075.                 return PLANE_CTL_ROTATE_270;
  3076.         case BIT(DRM_ROTATE_180):
  3077.                 return PLANE_CTL_ROTATE_180;
  3078.         case BIT(DRM_ROTATE_270):
  3079.                 return PLANE_CTL_ROTATE_90;
  3080.         default:
  3081.                 MISSING_CASE(rotation);
  3082.         }
  3083.  
  3084.         return 0;
  3085. }
  3086.  
  3087. static void skylake_update_primary_plane(struct drm_crtc *crtc,
  3088.                                          struct drm_framebuffer *fb,
  3089.                                          int x, int y)
  3090. {
  3091.         struct drm_device *dev = crtc->dev;
  3092.         struct drm_i915_private *dev_priv = dev->dev_private;
  3093.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3094.         struct drm_plane *plane = crtc->primary;
  3095.         bool visible = to_intel_plane_state(plane->state)->visible;
  3096.         struct drm_i915_gem_object *obj;
  3097.         int pipe = intel_crtc->pipe;
  3098.         u32 plane_ctl, stride_div, stride;
  3099.         u32 tile_height, plane_offset, plane_size;
  3100.         unsigned int rotation;
  3101.         int x_offset, y_offset;
  3102.         unsigned long surf_addr;
  3103.         struct intel_crtc_state *crtc_state = intel_crtc->config;
  3104.         struct intel_plane_state *plane_state;
  3105.         int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
  3106.         int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
  3107.         int scaler_id = -1;
  3108.  
  3109.         plane_state = to_intel_plane_state(plane->state);
  3110.  
  3111.         if (!visible || !fb) {
  3112.                 I915_WRITE(PLANE_CTL(pipe, 0), 0);
  3113.                 I915_WRITE(PLANE_SURF(pipe, 0), 0);
  3114.                 POSTING_READ(PLANE_CTL(pipe, 0));
  3115.                 return;
  3116.         }
  3117.  
  3118.         plane_ctl = PLANE_CTL_ENABLE |
  3119.                     PLANE_CTL_PIPE_GAMMA_ENABLE |
  3120.                     PLANE_CTL_PIPE_CSC_ENABLE;
  3121.  
  3122.         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
  3123.         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
  3124.         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
  3125.  
  3126.         rotation = plane->state->rotation;
  3127.         plane_ctl |= skl_plane_ctl_rotation(rotation);
  3128.  
  3129.         obj = intel_fb_obj(fb);
  3130.         stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
  3131.                                                fb->pixel_format);
  3132.         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
  3133.  
  3134.         WARN_ON(drm_rect_width(&plane_state->src) == 0);
  3135.  
  3136.         scaler_id = plane_state->scaler_id;
  3137.         src_x = plane_state->src.x1 >> 16;
  3138.         src_y = plane_state->src.y1 >> 16;
  3139.         src_w = drm_rect_width(&plane_state->src) >> 16;
  3140.         src_h = drm_rect_height(&plane_state->src) >> 16;
  3141.         dst_x = plane_state->dst.x1;
  3142.         dst_y = plane_state->dst.y1;
  3143.         dst_w = drm_rect_width(&plane_state->dst);
  3144.         dst_h = drm_rect_height(&plane_state->dst);
  3145.  
  3146.         WARN_ON(x != src_x || y != src_y);
  3147.  
  3148.         if (intel_rotation_90_or_270(rotation)) {
  3149.                 /* stride = Surface height in tiles */
  3150.                 tile_height = intel_tile_height(dev, fb->pixel_format,
  3151.                                                 fb->modifier[0], 0);
  3152.                 stride = DIV_ROUND_UP(fb->height, tile_height);
  3153.                 x_offset = stride * tile_height - y - src_h;
  3154.                 y_offset = x;
  3155.                 plane_size = (src_w - 1) << 16 | (src_h - 1);
  3156.         } else {
  3157.                 stride = fb->pitches[0] / stride_div;
  3158.                 x_offset = x;
  3159.                 y_offset = y;
  3160.                 plane_size = (src_h - 1) << 16 | (src_w - 1);
  3161.         }
  3162.         plane_offset = y_offset << 16 | x_offset;
  3163.  
  3164.         intel_crtc->adjusted_x = x_offset;
  3165.         intel_crtc->adjusted_y = y_offset;
  3166.  
  3167.         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
  3168.         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
  3169.         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
  3170.         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
  3171.  
  3172.         if (scaler_id >= 0) {
  3173.                 uint32_t ps_ctrl = 0;
  3174.  
  3175.                 WARN_ON(!dst_w || !dst_h);
  3176.                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
  3177.                         crtc_state->scaler_state.scalers[scaler_id].mode;
  3178.                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
  3179.                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
  3180.                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
  3181.                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
  3182.                 I915_WRITE(PLANE_POS(pipe, 0), 0);
  3183.         } else {
  3184.                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
  3185.         }
  3186.  
  3187.         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
  3188.  
  3189.         POSTING_READ(PLANE_SURF(pipe, 0));
  3190. }
  3191.  
  3192. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  3193. static int
  3194. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  3195.                            int x, int y, enum mode_set_atomic state)
  3196. {
  3197.         struct drm_device *dev = crtc->dev;
  3198.         struct drm_i915_private *dev_priv = dev->dev_private;
  3199.  
  3200.         if (dev_priv->fbc.disable_fbc)
  3201.                 dev_priv->fbc.disable_fbc(dev_priv);
  3202.  
  3203.         dev_priv->display.update_primary_plane(crtc, fb, x, y);
  3204.  
  3205.         return 0;
  3206. }
  3207.  
  3208. #if 0
  3209. static void intel_complete_page_flips(struct drm_device *dev)
  3210. {
  3211.         struct drm_crtc *crtc;
  3212.  
  3213.         for_each_crtc(dev, crtc) {
  3214.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3215.                 enum plane plane = intel_crtc->plane;
  3216.  
  3217.                 intel_prepare_page_flip(dev, plane);
  3218.                 intel_finish_page_flip_plane(dev, plane);
  3219.         }
  3220. }
  3221.  
  3222. static void intel_update_primary_planes(struct drm_device *dev)
  3223. {
  3224.         struct drm_crtc *crtc;
  3225.  
  3226.         for_each_crtc(dev, crtc) {
  3227.                 struct intel_plane *plane = to_intel_plane(crtc->primary);
  3228.                 struct intel_plane_state *plane_state;
  3229.  
  3230.                 drm_modeset_lock_crtc(crtc, &plane->base);
  3231.  
  3232.                 plane_state = to_intel_plane_state(plane->base.state);
  3233.  
  3234.                 if (plane_state->base.fb)
  3235.                         plane->commit_plane(&plane->base, plane_state);
  3236.  
  3237.                 drm_modeset_unlock_crtc(crtc);
  3238.         }
  3239. }
  3240.  
  3241. void intel_prepare_reset(struct drm_device *dev)
  3242. {
  3243.         /* no reset support for gen2 */
  3244.         if (IS_GEN2(dev))
  3245.                 return;
  3246.  
  3247.         /* reset doesn't touch the display */
  3248.         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
  3249.                 return;
  3250.  
  3251.         drm_modeset_lock_all(dev);
  3252.         /*
  3253.          * Disabling the crtcs gracefully seems nicer. Also the
  3254.          * g33 docs say we should at least disable all the planes.
  3255.          */
  3256.         intel_display_suspend(dev);
  3257. }
  3258.  
  3259. void intel_finish_reset(struct drm_device *dev)
  3260. {
  3261.         struct drm_i915_private *dev_priv = to_i915(dev);
  3262.  
  3263.         /*
  3264.          * Flips in the rings will be nuked by the reset,
  3265.          * so complete all pending flips so that user space
  3266.          * will get its events and not get stuck.
  3267.          */
  3268.         intel_complete_page_flips(dev);
  3269.  
  3270.         /* no reset support for gen2 */
  3271.         if (IS_GEN2(dev))
  3272.                 return;
  3273.  
  3274.         /* reset doesn't touch the display */
  3275.         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
  3276.                 /*
  3277.                  * Flips in the rings have been nuked by the reset,
  3278.                  * so update the base address of all primary
  3279.                  * planes to the the last fb to make sure we're
  3280.                  * showing the correct fb after a reset.
  3281.                  *
  3282.                  * FIXME: Atomic will make this obsolete since we won't schedule
  3283.                  * CS-based flips (which might get lost in gpu resets) any more.
  3284.                  */
  3285.                 intel_update_primary_planes(dev);
  3286.                 return;
  3287.         }
  3288.  
  3289.         /*
  3290.          * The display has been reset as well,
  3291.          * so need a full re-initialization.
  3292.          */
  3293.         intel_runtime_pm_disable_interrupts(dev_priv);
  3294.         intel_runtime_pm_enable_interrupts(dev_priv);
  3295.  
  3296.         intel_modeset_init_hw(dev);
  3297.  
  3298.         spin_lock_irq(&dev_priv->irq_lock);
  3299.         if (dev_priv->display.hpd_irq_setup)
  3300.                 dev_priv->display.hpd_irq_setup(dev);
  3301.         spin_unlock_irq(&dev_priv->irq_lock);
  3302.  
  3303.         intel_display_resume(dev);
  3304.  
  3305.         intel_hpd_init(dev_priv);
  3306.  
  3307.         drm_modeset_unlock_all(dev);
  3308. }
  3309.  
  3310. static void
  3311. intel_finish_fb(struct drm_framebuffer *old_fb)
  3312. {
  3313.         struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
  3314.         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
  3315.         bool was_interruptible = dev_priv->mm.interruptible;
  3316.         int ret;
  3317.  
  3318.         /* Big Hammer, we also need to ensure that any pending
  3319.          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  3320.          * current scanout is retired before unpinning the old
  3321.          * framebuffer. Note that we rely on userspace rendering
  3322.          * into the buffer attached to the pipe they are waiting
  3323.          * on. If not, userspace generates a GPU hang with IPEHR
  3324.          * point to the MI_WAIT_FOR_EVENT.
  3325.          *
  3326.          * This should only fail upon a hung GPU, in which case we
  3327.          * can safely continue.
  3328.          */
  3329.         dev_priv->mm.interruptible = false;
  3330.         ret = i915_gem_object_wait_rendering(obj, true);
  3331.         dev_priv->mm.interruptible = was_interruptible;
  3332.  
  3333.         WARN_ON(ret);
  3334. }
  3335.  
  3336. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  3337. {
  3338.         struct drm_device *dev = crtc->dev;
  3339.         struct drm_i915_private *dev_priv = dev->dev_private;
  3340.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3341.         bool pending;
  3342.  
  3343.         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  3344.             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  3345.                 return false;
  3346.  
  3347.         spin_lock_irq(&dev->event_lock);
  3348.         pending = to_intel_crtc(crtc)->unpin_work != NULL;
  3349.         spin_unlock_irq(&dev->event_lock);
  3350.  
  3351.         return pending;
  3352. }
  3353. #endif
  3354.  
  3355. static void intel_update_pipe_config(struct intel_crtc *crtc,
  3356.                                      struct intel_crtc_state *old_crtc_state)
  3357. {
  3358.         struct drm_device *dev = crtc->base.dev;
  3359.         struct drm_i915_private *dev_priv = dev->dev_private;
  3360.         struct intel_crtc_state *pipe_config =
  3361.                 to_intel_crtc_state(crtc->base.state);
  3362.  
  3363.         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
  3364.         crtc->base.mode = crtc->base.state->mode;
  3365.  
  3366.         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
  3367.                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
  3368.                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  3369.  
  3370.         if (HAS_DDI(dev))
  3371.                 intel_set_pipe_csc(&crtc->base);
  3372.  
  3373.         /*
  3374.          * Update pipe size and adjust fitter if needed: the reason for this is
  3375.          * that in compute_mode_changes we check the native mode (not the pfit
  3376.          * mode) to see if we can flip rather than do a full mode set. In the
  3377.          * fastboot case, we'll flip, but if we don't update the pipesrc and
  3378.          * pfit state, we'll end up with a big fb scanned out into the wrong
  3379.          * sized surface.
  3380.          */
  3381.  
  3382.         I915_WRITE(PIPESRC(crtc->pipe),
  3383.                    ((pipe_config->pipe_src_w - 1) << 16) |
  3384.                    (pipe_config->pipe_src_h - 1));
  3385.  
  3386.         /* on skylake this is done by detaching scalers */
  3387.         if (INTEL_INFO(dev)->gen >= 9) {
  3388.                 skl_detach_scalers(crtc);
  3389.  
  3390.                 if (pipe_config->pch_pfit.enabled)
  3391.                         skylake_pfit_enable(crtc);
  3392.         } else if (HAS_PCH_SPLIT(dev)) {
  3393.                 if (pipe_config->pch_pfit.enabled)
  3394.                         ironlake_pfit_enable(crtc);
  3395.                 else if (old_crtc_state->pch_pfit.enabled)
  3396.                         ironlake_pfit_disable(crtc, true);
  3397.         }
  3398. }
  3399.  
  3400. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  3401. {
  3402.         struct drm_device *dev = crtc->dev;
  3403.         struct drm_i915_private *dev_priv = dev->dev_private;
  3404.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3405.         int pipe = intel_crtc->pipe;
  3406.         u32 reg, temp;
  3407.  
  3408.         /* enable normal train */
  3409.         reg = FDI_TX_CTL(pipe);
  3410.         temp = I915_READ(reg);
  3411.         if (IS_IVYBRIDGE(dev)) {
  3412.                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  3413.                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  3414.         } else {
  3415.                 temp &= ~FDI_LINK_TRAIN_NONE;
  3416.                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  3417.         }
  3418.         I915_WRITE(reg, temp);
  3419.  
  3420.         reg = FDI_RX_CTL(pipe);
  3421.         temp = I915_READ(reg);
  3422.         if (HAS_PCH_CPT(dev)) {
  3423.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3424.                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  3425.         } else {
  3426.                 temp &= ~FDI_LINK_TRAIN_NONE;
  3427.                 temp |= FDI_LINK_TRAIN_NONE;
  3428.         }
  3429.         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  3430.  
  3431.         /* wait one idle pattern time */
  3432.         POSTING_READ(reg);
  3433.         udelay(1000);
  3434.  
  3435.         /* IVB wants error correction enabled */
  3436.         if (IS_IVYBRIDGE(dev))
  3437.                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  3438.                            FDI_FE_ERRC_ENABLE);
  3439. }
  3440.  
  3441. /* The FDI link training functions for ILK/Ibexpeak. */
  3442. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  3443. {
  3444.         struct drm_device *dev = crtc->dev;
  3445.         struct drm_i915_private *dev_priv = dev->dev_private;
  3446.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3447.         int pipe = intel_crtc->pipe;
  3448.         u32 reg, temp, tries;
  3449.  
  3450.         /* FDI needs bits from pipe first */
  3451.         assert_pipe_enabled(dev_priv, pipe);
  3452.  
  3453.         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  3454.            for train result */
  3455.         reg = FDI_RX_IMR(pipe);
  3456.         temp = I915_READ(reg);
  3457.         temp &= ~FDI_RX_SYMBOL_LOCK;
  3458.         temp &= ~FDI_RX_BIT_LOCK;
  3459.         I915_WRITE(reg, temp);
  3460.         I915_READ(reg);
  3461.         udelay(150);
  3462.  
  3463.         /* enable CPU FDI TX and PCH FDI RX */
  3464.         reg = FDI_TX_CTL(pipe);
  3465.         temp = I915_READ(reg);
  3466.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  3467.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  3468.         temp &= ~FDI_LINK_TRAIN_NONE;
  3469.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  3470.         I915_WRITE(reg, temp | FDI_TX_ENABLE);
  3471.  
  3472.         reg = FDI_RX_CTL(pipe);
  3473.         temp = I915_READ(reg);
  3474.         temp &= ~FDI_LINK_TRAIN_NONE;
  3475.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  3476.         I915_WRITE(reg, temp | FDI_RX_ENABLE);
  3477.  
  3478.         POSTING_READ(reg);
  3479.         udelay(150);
  3480.  
  3481.         /* Ironlake workaround, enable clock pointer after FDI enable*/
  3482.         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  3483.         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  3484.                    FDI_RX_PHASE_SYNC_POINTER_EN);
  3485.  
  3486.         reg = FDI_RX_IIR(pipe);
  3487.         for (tries = 0; tries < 5; tries++) {
  3488.                 temp = I915_READ(reg);
  3489.                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3490.  
  3491.                 if ((temp & FDI_RX_BIT_LOCK)) {
  3492.                         DRM_DEBUG_KMS("FDI train 1 done.\n");
  3493.                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  3494.                         break;
  3495.                 }
  3496.         }
  3497.         if (tries == 5)
  3498.                 DRM_ERROR("FDI train 1 fail!\n");
  3499.  
  3500.         /* Train 2 */
  3501.         reg = FDI_TX_CTL(pipe);
  3502.         temp = I915_READ(reg);
  3503.         temp &= ~FDI_LINK_TRAIN_NONE;
  3504.         temp |= FDI_LINK_TRAIN_PATTERN_2;
  3505.         I915_WRITE(reg, temp);
  3506.  
  3507.         reg = FDI_RX_CTL(pipe);
  3508.         temp = I915_READ(reg);
  3509.         temp &= ~FDI_LINK_TRAIN_NONE;
  3510.         temp |= FDI_LINK_TRAIN_PATTERN_2;
  3511.         I915_WRITE(reg, temp);
  3512.  
  3513.         POSTING_READ(reg);
  3514.         udelay(150);
  3515.  
  3516.         reg = FDI_RX_IIR(pipe);
  3517.         for (tries = 0; tries < 5; tries++) {
  3518.                 temp = I915_READ(reg);
  3519.                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3520.  
  3521.                 if (temp & FDI_RX_SYMBOL_LOCK) {
  3522.                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  3523.                         DRM_DEBUG_KMS("FDI train 2 done.\n");
  3524.                         break;
  3525.                 }
  3526.         }
  3527.         if (tries == 5)
  3528.                 DRM_ERROR("FDI train 2 fail!\n");
  3529.  
  3530.         DRM_DEBUG_KMS("FDI train done\n");
  3531.  
  3532. }
  3533.  
  3534. static const int snb_b_fdi_train_param[] = {
  3535.         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  3536.         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  3537.         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  3538.         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  3539. };
  3540.  
  3541. /* The FDI link training functions for SNB/Cougarpoint. */
  3542. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  3543. {
  3544.         struct drm_device *dev = crtc->dev;
  3545.         struct drm_i915_private *dev_priv = dev->dev_private;
  3546.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3547.         int pipe = intel_crtc->pipe;
  3548.         u32 reg, temp, i, retry;
  3549.  
  3550.         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  3551.            for train result */
  3552.         reg = FDI_RX_IMR(pipe);
  3553.         temp = I915_READ(reg);
  3554.         temp &= ~FDI_RX_SYMBOL_LOCK;
  3555.         temp &= ~FDI_RX_BIT_LOCK;
  3556.         I915_WRITE(reg, temp);
  3557.  
  3558.         POSTING_READ(reg);
  3559.         udelay(150);
  3560.  
  3561.         /* enable CPU FDI TX and PCH FDI RX */
  3562.         reg = FDI_TX_CTL(pipe);
  3563.         temp = I915_READ(reg);
  3564.         temp &= ~FDI_DP_PORT_WIDTH_MASK;
  3565.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  3566.         temp &= ~FDI_LINK_TRAIN_NONE;
  3567.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  3568.         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3569.         /* SNB-B */
  3570.         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  3571.         I915_WRITE(reg, temp | FDI_TX_ENABLE);
  3572.  
  3573.         I915_WRITE(FDI_RX_MISC(pipe),
  3574.                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  3575.  
  3576.         reg = FDI_RX_CTL(pipe);
  3577.         temp = I915_READ(reg);
  3578.         if (HAS_PCH_CPT(dev)) {
  3579.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3580.                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  3581.         } else {
  3582.                 temp &= ~FDI_LINK_TRAIN_NONE;
  3583.                 temp |= FDI_LINK_TRAIN_PATTERN_1;
  3584.         }
  3585.         I915_WRITE(reg, temp | FDI_RX_ENABLE);
  3586.  
  3587.         POSTING_READ(reg);
  3588.         udelay(150);
  3589.  
  3590.         for (i = 0; i < 4; i++) {
  3591.                 reg = FDI_TX_CTL(pipe);
  3592.                 temp = I915_READ(reg);
  3593.                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3594.                 temp |= snb_b_fdi_train_param[i];
  3595.                 I915_WRITE(reg, temp);
  3596.  
  3597.                 POSTING_READ(reg);
  3598.                 udelay(500);
  3599.  
  3600.                 for (retry = 0; retry < 5; retry++) {
  3601.                         reg = FDI_RX_IIR(pipe);
  3602.                         temp = I915_READ(reg);
  3603.                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3604.                         if (temp & FDI_RX_BIT_LOCK) {
  3605.                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  3606.                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
  3607.                                 break;
  3608.                         }
  3609.                         udelay(50);
  3610.                 }
  3611.                 if (retry < 5)
  3612.                         break;
  3613.         }
  3614.         if (i == 4)
  3615.                 DRM_ERROR("FDI train 1 fail!\n");
  3616.  
  3617.         /* Train 2 */
  3618.         reg = FDI_TX_CTL(pipe);
  3619.         temp = I915_READ(reg);
  3620.         temp &= ~FDI_LINK_TRAIN_NONE;
  3621.         temp |= FDI_LINK_TRAIN_PATTERN_2;
  3622.         if (IS_GEN6(dev)) {
  3623.                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3624.                 /* SNB-B */
  3625.                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  3626.         }
  3627.         I915_WRITE(reg, temp);
  3628.  
  3629.         reg = FDI_RX_CTL(pipe);
  3630.         temp = I915_READ(reg);
  3631.         if (HAS_PCH_CPT(dev)) {
  3632.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3633.                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  3634.         } else {
  3635.                 temp &= ~FDI_LINK_TRAIN_NONE;
  3636.                 temp |= FDI_LINK_TRAIN_PATTERN_2;
  3637.         }
  3638.         I915_WRITE(reg, temp);
  3639.  
  3640.         POSTING_READ(reg);
  3641.         udelay(150);
  3642.  
  3643.         for (i = 0; i < 4; i++) {
  3644.                 reg = FDI_TX_CTL(pipe);
  3645.                 temp = I915_READ(reg);
  3646.                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3647.                 temp |= snb_b_fdi_train_param[i];
  3648.                 I915_WRITE(reg, temp);
  3649.  
  3650.                 POSTING_READ(reg);
  3651.                 udelay(500);
  3652.  
  3653.                 for (retry = 0; retry < 5; retry++) {
  3654.                         reg = FDI_RX_IIR(pipe);
  3655.                         temp = I915_READ(reg);
  3656.                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3657.                         if (temp & FDI_RX_SYMBOL_LOCK) {
  3658.                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  3659.                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
  3660.                                 break;
  3661.                         }
  3662.                         udelay(50);
  3663.                 }
  3664.                 if (retry < 5)
  3665.                         break;
  3666.         }
  3667.         if (i == 4)
  3668.                 DRM_ERROR("FDI train 2 fail!\n");
  3669.  
  3670.         DRM_DEBUG_KMS("FDI train done.\n");
  3671. }
  3672.  
  3673. /* Manual link training for Ivy Bridge A0 parts */
  3674. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  3675. {
  3676.         struct drm_device *dev = crtc->dev;
  3677.         struct drm_i915_private *dev_priv = dev->dev_private;
  3678.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3679.         int pipe = intel_crtc->pipe;
  3680.         u32 reg, temp, i, j;
  3681.  
  3682.         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  3683.            for train result */
  3684.         reg = FDI_RX_IMR(pipe);
  3685.         temp = I915_READ(reg);
  3686.         temp &= ~FDI_RX_SYMBOL_LOCK;
  3687.         temp &= ~FDI_RX_BIT_LOCK;
  3688.         I915_WRITE(reg, temp);
  3689.  
  3690.         POSTING_READ(reg);
  3691.         udelay(150);
  3692.  
  3693.         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  3694.                       I915_READ(FDI_RX_IIR(pipe)));
  3695.  
  3696.         /* Try each vswing and preemphasis setting twice before moving on */
  3697.         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
  3698.                 /* disable first in case we need to retry */
  3699.                 reg = FDI_TX_CTL(pipe);
  3700.                 temp = I915_READ(reg);
  3701.                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  3702.                 temp &= ~FDI_TX_ENABLE;
  3703.                 I915_WRITE(reg, temp);
  3704.  
  3705.                 reg = FDI_RX_CTL(pipe);
  3706.                 temp = I915_READ(reg);
  3707.                 temp &= ~FDI_LINK_TRAIN_AUTO;
  3708.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3709.                 temp &= ~FDI_RX_ENABLE;
  3710.                 I915_WRITE(reg, temp);
  3711.  
  3712.                 /* enable CPU FDI TX and PCH FDI RX */
  3713.                 reg = FDI_TX_CTL(pipe);
  3714.                 temp = I915_READ(reg);
  3715.                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
  3716.                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  3717.                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  3718.                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  3719.                 temp |= snb_b_fdi_train_param[j/2];
  3720.                 temp |= FDI_COMPOSITE_SYNC;
  3721.                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
  3722.  
  3723.                 I915_WRITE(FDI_RX_MISC(pipe),
  3724.                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  3725.  
  3726.                 reg = FDI_RX_CTL(pipe);
  3727.                 temp = I915_READ(reg);
  3728.                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  3729.                 temp |= FDI_COMPOSITE_SYNC;
  3730.                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
  3731.  
  3732.                 POSTING_READ(reg);
  3733.                 udelay(1); /* should be 0.5us */
  3734.  
  3735.                 for (i = 0; i < 4; i++) {
  3736.                         reg = FDI_RX_IIR(pipe);
  3737.                         temp = I915_READ(reg);
  3738.                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3739.  
  3740.                         if (temp & FDI_RX_BIT_LOCK ||
  3741.                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  3742.                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  3743.                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
  3744.                                               i);
  3745.                                 break;
  3746.                         }
  3747.                         udelay(1); /* should be 0.5us */
  3748.                 }
  3749.                 if (i == 4) {
  3750.                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
  3751.                         continue;
  3752.                 }
  3753.  
  3754.                 /* Train 2 */
  3755.                 reg = FDI_TX_CTL(pipe);
  3756.                 temp = I915_READ(reg);
  3757.                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  3758.                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  3759.                 I915_WRITE(reg, temp);
  3760.  
  3761.                 reg = FDI_RX_CTL(pipe);
  3762.                 temp = I915_READ(reg);
  3763.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3764.                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  3765.                 I915_WRITE(reg, temp);
  3766.  
  3767.                 POSTING_READ(reg);
  3768.                 udelay(2); /* should be 1.5us */
  3769.  
  3770.                 for (i = 0; i < 4; i++) {
  3771.                         reg = FDI_RX_IIR(pipe);
  3772.                         temp = I915_READ(reg);
  3773.                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  3774.  
  3775.                         if (temp & FDI_RX_SYMBOL_LOCK ||
  3776.                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
  3777.                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  3778.                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
  3779.                                               i);
  3780.                                 goto train_done;
  3781.                         }
  3782.                         udelay(2); /* should be 1.5us */
  3783.                 }
  3784.                 if (i == 4)
  3785.                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
  3786.         }
  3787.  
  3788. train_done:
  3789.         DRM_DEBUG_KMS("FDI train done.\n");
  3790. }
  3791.  
  3792. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  3793. {
  3794.         struct drm_device *dev = intel_crtc->base.dev;
  3795.         struct drm_i915_private *dev_priv = dev->dev_private;
  3796.         int pipe = intel_crtc->pipe;
  3797.         u32 reg, temp;
  3798.  
  3799.  
  3800.         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  3801.         reg = FDI_RX_CTL(pipe);
  3802.         temp = I915_READ(reg);
  3803.         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  3804.         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
  3805.         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  3806.         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  3807.  
  3808.         POSTING_READ(reg);
  3809.         udelay(200);
  3810.  
  3811.         /* Switch from Rawclk to PCDclk */
  3812.         temp = I915_READ(reg);
  3813.         I915_WRITE(reg, temp | FDI_PCDCLK);
  3814.  
  3815.         POSTING_READ(reg);
  3816.         udelay(200);
  3817.  
  3818.         /* Enable CPU FDI TX PLL, always on for Ironlake */
  3819.         reg = FDI_TX_CTL(pipe);
  3820.         temp = I915_READ(reg);
  3821.         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  3822.                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  3823.  
  3824.                 POSTING_READ(reg);
  3825.                 udelay(100);
  3826.         }
  3827. }
  3828.  
  3829. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  3830. {
  3831.         struct drm_device *dev = intel_crtc->base.dev;
  3832.         struct drm_i915_private *dev_priv = dev->dev_private;
  3833.         int pipe = intel_crtc->pipe;
  3834.         u32 reg, temp;
  3835.  
  3836.         /* Switch from PCDclk to Rawclk */
  3837.         reg = FDI_RX_CTL(pipe);
  3838.         temp = I915_READ(reg);
  3839.         I915_WRITE(reg, temp & ~FDI_PCDCLK);
  3840.  
  3841.         /* Disable CPU FDI TX PLL */
  3842.         reg = FDI_TX_CTL(pipe);
  3843.         temp = I915_READ(reg);
  3844.         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  3845.  
  3846.         POSTING_READ(reg);
  3847.         udelay(100);
  3848.  
  3849.         reg = FDI_RX_CTL(pipe);
  3850.         temp = I915_READ(reg);
  3851.         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  3852.  
  3853.         /* Wait for the clocks to turn off. */
  3854.         POSTING_READ(reg);
  3855.         udelay(100);
  3856. }
  3857.  
  3858. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  3859. {
  3860.         struct drm_device *dev = crtc->dev;
  3861.         struct drm_i915_private *dev_priv = dev->dev_private;
  3862.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3863.         int pipe = intel_crtc->pipe;
  3864.         u32 reg, temp;
  3865.  
  3866.         /* disable CPU FDI tx and PCH FDI rx */
  3867.         reg = FDI_TX_CTL(pipe);
  3868.         temp = I915_READ(reg);
  3869.         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  3870.         POSTING_READ(reg);
  3871.  
  3872.         reg = FDI_RX_CTL(pipe);
  3873.         temp = I915_READ(reg);
  3874.         temp &= ~(0x7 << 16);
  3875.         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  3876.         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  3877.  
  3878.         POSTING_READ(reg);
  3879.         udelay(100);
  3880.  
  3881.         /* Ironlake workaround, disable clock pointer after downing FDI */
  3882.         if (HAS_PCH_IBX(dev))
  3883.                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  3884.  
  3885.         /* still set train pattern 1 */
  3886.         reg = FDI_TX_CTL(pipe);
  3887.         temp = I915_READ(reg);
  3888.         temp &= ~FDI_LINK_TRAIN_NONE;
  3889.         temp |= FDI_LINK_TRAIN_PATTERN_1;
  3890.         I915_WRITE(reg, temp);
  3891.  
  3892.         reg = FDI_RX_CTL(pipe);
  3893.         temp = I915_READ(reg);
  3894.         if (HAS_PCH_CPT(dev)) {
  3895.                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  3896.                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  3897.         } else {
  3898.                 temp &= ~FDI_LINK_TRAIN_NONE;
  3899.                 temp |= FDI_LINK_TRAIN_PATTERN_1;
  3900.         }
  3901.         /* BPC in FDI rx is consistent with that in PIPECONF */
  3902.         temp &= ~(0x07 << 16);
  3903.         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  3904.         I915_WRITE(reg, temp);
  3905.  
  3906.         POSTING_READ(reg);
  3907.         udelay(100);
  3908. }
  3909.  
  3910. bool intel_has_pending_fb_unpin(struct drm_device *dev)
  3911. {
  3912.         struct intel_crtc *crtc;
  3913.  
  3914.         /* Note that we don't need to be called with mode_config.lock here
  3915.          * as our list of CRTC objects is static for the lifetime of the
  3916.          * device and so cannot disappear as we iterate. Similarly, we can
  3917.          * happily treat the predicates as racy, atomic checks as userspace
  3918.          * cannot claim and pin a new fb without at least acquring the
  3919.          * struct_mutex and so serialising with us.
  3920.          */
  3921.         for_each_intel_crtc(dev, crtc) {
  3922.                 if (atomic_read(&crtc->unpin_work_count) == 0)
  3923.                         continue;
  3924.  
  3925.                 if (crtc->unpin_work)
  3926.                         intel_wait_for_vblank(dev, crtc->pipe);
  3927.  
  3928.                 return true;
  3929.         }
  3930.  
  3931.         return false;
  3932. }
  3933.  
  3934. #if 0
  3935. void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  3936. {
  3937.         struct drm_device *dev = crtc->dev;
  3938.         struct drm_i915_private *dev_priv = dev->dev_private;
  3939.  
  3940.         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  3941.         if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
  3942.                                        !intel_crtc_has_pending_flip(crtc),
  3943.                                        60*HZ) == 0)) {
  3944.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3945.  
  3946.                 spin_lock_irq(&dev->event_lock);
  3947.                 if (intel_crtc->unpin_work) {
  3948.                         WARN_ONCE(1, "Removing stuck page flip\n");
  3949.                         page_flip_completed(intel_crtc);
  3950.                 }
  3951.                 spin_unlock_irq(&dev->event_lock);
  3952.         }
  3953.  
  3954.         if (crtc->primary->fb) {
  3955.                 mutex_lock(&dev->struct_mutex);
  3956.                 intel_finish_fb(crtc->primary->fb);
  3957.                 mutex_unlock(&dev->struct_mutex);
  3958.         }
  3959. }
  3960. #endif
  3961.  
  3962. /* Program iCLKIP clock to the desired frequency */
  3963. static void lpt_program_iclkip(struct drm_crtc *crtc)
  3964. {
  3965.         struct drm_device *dev = crtc->dev;
  3966.         struct drm_i915_private *dev_priv = dev->dev_private;
  3967.         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
  3968.         u32 divsel, phaseinc, auxdiv, phasedir = 0;
  3969.         u32 temp;
  3970.  
  3971.         mutex_lock(&dev_priv->sb_lock);
  3972.  
  3973.         /* It is necessary to ungate the pixclk gate prior to programming
  3974.          * the divisors, and gate it back when it is done.
  3975.          */
  3976.         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  3977.  
  3978.         /* Disable SSCCTL */
  3979.         intel_sbi_write(dev_priv, SBI_SSCCTL6,
  3980.                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  3981.                                 SBI_SSCCTL_DISABLE,
  3982.                         SBI_ICLK);
  3983.  
  3984.         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  3985.         if (clock == 20000) {
  3986.                 auxdiv = 1;
  3987.                 divsel = 0x41;
  3988.                 phaseinc = 0x20;
  3989.         } else {
  3990.                 /* The iCLK virtual clock root frequency is in MHz,
  3991.                  * but the adjusted_mode->crtc_clock in in KHz. To get the
  3992.                  * divisors, it is necessary to divide one by another, so we
  3993.                  * convert the virtual clock precision to KHz here for higher
  3994.                  * precision.
  3995.                  */
  3996.                 u32 iclk_virtual_root_freq = 172800 * 1000;
  3997.                 u32 iclk_pi_range = 64;
  3998.                 u32 desired_divisor, msb_divisor_value, pi_value;
  3999.  
  4000.                 desired_divisor = (iclk_virtual_root_freq / clock);
  4001.                 msb_divisor_value = desired_divisor / iclk_pi_range;
  4002.                 pi_value = desired_divisor % iclk_pi_range;
  4003.  
  4004.                 auxdiv = 0;
  4005.                 divsel = msb_divisor_value - 2;
  4006.                 phaseinc = pi_value;
  4007.         }
  4008.  
  4009.         /* This should not happen with any sane values */
  4010.         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  4011.                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  4012.         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  4013.                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  4014.  
  4015.         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  4016.                         clock,
  4017.                         auxdiv,
  4018.                         divsel,
  4019.                         phasedir,
  4020.                         phaseinc);
  4021.  
  4022.         /* Program SSCDIVINTPHASE6 */
  4023.         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  4024.         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  4025.         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  4026.         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  4027.         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  4028.         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  4029.         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  4030.         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  4031.  
  4032.         /* Program SSCAUXDIV */
  4033.         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  4034.         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  4035.         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  4036.         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  4037.  
  4038.         /* Enable modulator and associated divider */
  4039.         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  4040.         temp &= ~SBI_SSCCTL_DISABLE;
  4041.         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  4042.  
  4043.         /* Wait for initialization time */
  4044.         udelay(24);
  4045.  
  4046.         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  4047.  
  4048.         mutex_unlock(&dev_priv->sb_lock);
  4049. }
  4050.  
  4051. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  4052.                                                 enum pipe pch_transcoder)
  4053. {
  4054.         struct drm_device *dev = crtc->base.dev;
  4055.         struct drm_i915_private *dev_priv = dev->dev_private;
  4056.         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
  4057.  
  4058.         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  4059.                    I915_READ(HTOTAL(cpu_transcoder)));
  4060.         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  4061.                    I915_READ(HBLANK(cpu_transcoder)));
  4062.         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  4063.                    I915_READ(HSYNC(cpu_transcoder)));
  4064.  
  4065.         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  4066.                    I915_READ(VTOTAL(cpu_transcoder)));
  4067.         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  4068.                    I915_READ(VBLANK(cpu_transcoder)));
  4069.         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  4070.                    I915_READ(VSYNC(cpu_transcoder)));
  4071.         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  4072.                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
  4073. }
  4074.  
  4075. static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
  4076. {
  4077.         struct drm_i915_private *dev_priv = dev->dev_private;
  4078.         uint32_t temp;
  4079.  
  4080.         temp = I915_READ(SOUTH_CHICKEN1);
  4081.         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
  4082.                 return;
  4083.  
  4084.         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4085.         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4086.  
  4087.         temp &= ~FDI_BC_BIFURCATION_SELECT;
  4088.         if (enable)
  4089.                 temp |= FDI_BC_BIFURCATION_SELECT;
  4090.  
  4091.         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
  4092.         I915_WRITE(SOUTH_CHICKEN1, temp);
  4093.         POSTING_READ(SOUTH_CHICKEN1);
  4094. }
  4095.  
  4096. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  4097. {
  4098.         struct drm_device *dev = intel_crtc->base.dev;
  4099.  
  4100.         switch (intel_crtc->pipe) {
  4101.         case PIPE_A:
  4102.                 break;
  4103.         case PIPE_B:
  4104.                 if (intel_crtc->config->fdi_lanes > 2)
  4105.                         cpt_set_fdi_bc_bifurcation(dev, false);
  4106.                 else
  4107.                         cpt_set_fdi_bc_bifurcation(dev, true);
  4108.  
  4109.                 break;
  4110.         case PIPE_C:
  4111.                 cpt_set_fdi_bc_bifurcation(dev, true);
  4112.  
  4113.                 break;
  4114.         default:
  4115.                 BUG();
  4116.         }
  4117. }
  4118.  
  4119. /*
  4120.  * Enable PCH resources required for PCH ports:
  4121.  *   - PCH PLLs
  4122.  *   - FDI training & RX/TX
  4123.  *   - update transcoder timings
  4124.  *   - DP transcoding bits
  4125.  *   - transcoder
  4126.  */
  4127. static void ironlake_pch_enable(struct drm_crtc *crtc)
  4128. {
  4129.         struct drm_device *dev = crtc->dev;
  4130.         struct drm_i915_private *dev_priv = dev->dev_private;
  4131.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4132.         int pipe = intel_crtc->pipe;
  4133.         u32 reg, temp;
  4134.  
  4135.         assert_pch_transcoder_disabled(dev_priv, pipe);
  4136.  
  4137.         if (IS_IVYBRIDGE(dev))
  4138.                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  4139.  
  4140.         /* Write the TU size bits before fdi link training, so that error
  4141.          * detection works. */
  4142.         I915_WRITE(FDI_RX_TUSIZE1(pipe),
  4143.                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  4144.  
  4145.         /* For PCH output, training FDI link */
  4146.         dev_priv->display.fdi_link_train(crtc);
  4147.  
  4148.         /* We need to program the right clock selection before writing the pixel
  4149.          * mutliplier into the DPLL. */
  4150.         if (HAS_PCH_CPT(dev)) {
  4151.                 u32 sel;
  4152.  
  4153.                 temp = I915_READ(PCH_DPLL_SEL);
  4154.                 temp |= TRANS_DPLL_ENABLE(pipe);
  4155.                 sel = TRANS_DPLLB_SEL(pipe);
  4156.                 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
  4157.                         temp |= sel;
  4158.                 else
  4159.                         temp &= ~sel;
  4160.                 I915_WRITE(PCH_DPLL_SEL, temp);
  4161.         }
  4162.  
  4163.         /* XXX: pch pll's can be enabled any time before we enable the PCH
  4164.          * transcoder, and we actually should do this to not upset any PCH
  4165.          * transcoder that already use the clock when we share it.
  4166.          *
  4167.          * Note that enable_shared_dpll tries to do the right thing, but
  4168.          * get_shared_dpll unconditionally resets the pll - we need that to have
  4169.          * the right LVDS enable sequence. */
  4170.         intel_enable_shared_dpll(intel_crtc);
  4171.  
  4172.         /* set transcoder timing, panel must allow it */
  4173.         assert_panel_unlocked(dev_priv, pipe);
  4174.         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  4175.  
  4176.         intel_fdi_normal_train(crtc);
  4177.  
  4178.         /* For PCH DP, enable TRANS_DP_CTL */
  4179.         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
  4180.                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  4181.                 reg = TRANS_DP_CTL(pipe);
  4182.                 temp = I915_READ(reg);
  4183.                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
  4184.                           TRANS_DP_SYNC_MASK |
  4185.                           TRANS_DP_BPC_MASK);
  4186.                 temp |= TRANS_DP_OUTPUT_ENABLE;
  4187.                 temp |= bpc << 9; /* same format but at 11:9 */
  4188.  
  4189.                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  4190.                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  4191.                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  4192.                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  4193.  
  4194.                 switch (intel_trans_dp_port_sel(crtc)) {
  4195.                 case PCH_DP_B:
  4196.                         temp |= TRANS_DP_PORT_SEL_B;
  4197.                         break;
  4198.                 case PCH_DP_C:
  4199.                         temp |= TRANS_DP_PORT_SEL_C;
  4200.                         break;
  4201.                 case PCH_DP_D:
  4202.                         temp |= TRANS_DP_PORT_SEL_D;
  4203.                         break;
  4204.                 default:
  4205.                         BUG();
  4206.                 }
  4207.  
  4208.                 I915_WRITE(reg, temp);
  4209.         }
  4210.  
  4211.         ironlake_enable_pch_transcoder(dev_priv, pipe);
  4212. }
  4213.  
  4214. static void lpt_pch_enable(struct drm_crtc *crtc)
  4215. {
  4216.         struct drm_device *dev = crtc->dev;
  4217.         struct drm_i915_private *dev_priv = dev->dev_private;
  4218.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4219.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  4220.  
  4221.         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  4222.  
  4223.         lpt_program_iclkip(crtc);
  4224.  
  4225.         /* Set transcoder timing. */
  4226.         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  4227.  
  4228.         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  4229. }
  4230.  
  4231. struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
  4232.                                                 struct intel_crtc_state *crtc_state)
  4233. {
  4234.         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  4235.         struct intel_shared_dpll *pll;
  4236.         struct intel_shared_dpll_config *shared_dpll;
  4237.         enum intel_dpll_id i;
  4238.         int max = dev_priv->num_shared_dpll;
  4239.  
  4240.         shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
  4241.  
  4242.         if (HAS_PCH_IBX(dev_priv->dev)) {
  4243.                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  4244.                 i = (enum intel_dpll_id) crtc->pipe;
  4245.                 pll = &dev_priv->shared_dplls[i];
  4246.  
  4247.                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  4248.                               crtc->base.base.id, pll->name);
  4249.  
  4250.                 WARN_ON(shared_dpll[i].crtc_mask);
  4251.  
  4252.                 goto found;
  4253.         }
  4254.  
  4255.         if (IS_BROXTON(dev_priv->dev)) {
  4256.                 /* PLL is attached to port in bxt */
  4257.                 struct intel_encoder *encoder;
  4258.                 struct intel_digital_port *intel_dig_port;
  4259.  
  4260.                 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
  4261.                 if (WARN_ON(!encoder))
  4262.                         return NULL;
  4263.  
  4264.                 intel_dig_port = enc_to_dig_port(&encoder->base);
  4265.                 /* 1:1 mapping between ports and PLLs */
  4266.                 i = (enum intel_dpll_id)intel_dig_port->port;
  4267.                 pll = &dev_priv->shared_dplls[i];
  4268.                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  4269.                         crtc->base.base.id, pll->name);
  4270.                 WARN_ON(shared_dpll[i].crtc_mask);
  4271.  
  4272.                 goto found;
  4273.         } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
  4274.                 /* Do not consider SPLL */
  4275.                 max = 2;
  4276.  
  4277.         for (i = 0; i < max; i++) {
  4278.                 pll = &dev_priv->shared_dplls[i];
  4279.  
  4280.                 /* Only want to check enabled timings first */
  4281.                 if (shared_dpll[i].crtc_mask == 0)
  4282.                         continue;
  4283.  
  4284.                 if (memcmp(&crtc_state->dpll_hw_state,
  4285.                            &shared_dpll[i].hw_state,
  4286.                            sizeof(crtc_state->dpll_hw_state)) == 0) {
  4287.                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
  4288.                                       crtc->base.base.id, pll->name,
  4289.                                       shared_dpll[i].crtc_mask,
  4290.                                       pll->active);
  4291.                         goto found;
  4292.                 }
  4293.         }
  4294.  
  4295.         /* Ok no matching timings, maybe there's a free one? */
  4296.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  4297.                 pll = &dev_priv->shared_dplls[i];
  4298.                 if (shared_dpll[i].crtc_mask == 0) {
  4299.                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  4300.                                       crtc->base.base.id, pll->name);
  4301.                         goto found;
  4302.                 }
  4303.         }
  4304.  
  4305.         return NULL;
  4306.  
  4307. found:
  4308.         if (shared_dpll[i].crtc_mask == 0)
  4309.                 shared_dpll[i].hw_state =
  4310.                         crtc_state->dpll_hw_state;
  4311.  
  4312.         crtc_state->shared_dpll = i;
  4313.         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
  4314.                          pipe_name(crtc->pipe));
  4315.  
  4316.         shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
  4317.  
  4318.         return pll;
  4319. }
  4320.  
  4321. static void intel_shared_dpll_commit(struct drm_atomic_state *state)
  4322. {
  4323.         struct drm_i915_private *dev_priv = to_i915(state->dev);
  4324.         struct intel_shared_dpll_config *shared_dpll;
  4325.         struct intel_shared_dpll *pll;
  4326.         enum intel_dpll_id i;
  4327.  
  4328.         if (!to_intel_atomic_state(state)->dpll_set)
  4329.                 return;
  4330.  
  4331.         shared_dpll = to_intel_atomic_state(state)->shared_dpll;
  4332.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  4333.                 pll = &dev_priv->shared_dplls[i];
  4334.                 pll->config = shared_dpll[i];
  4335.         }
  4336. }
  4337.  
  4338. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  4339. {
  4340.         struct drm_i915_private *dev_priv = dev->dev_private;
  4341.         int dslreg = PIPEDSL(pipe);
  4342.         u32 temp;
  4343.  
  4344.         temp = I915_READ(dslreg);
  4345.         udelay(500);
  4346.         if (wait_for(I915_READ(dslreg) != temp, 5)) {
  4347.                 if (wait_for(I915_READ(dslreg) != temp, 5))
  4348.                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  4349.         }
  4350. }
  4351.  
  4352. static int
  4353. skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
  4354.                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
  4355.                   int src_w, int src_h, int dst_w, int dst_h)
  4356. {
  4357.         struct intel_crtc_scaler_state *scaler_state =
  4358.                 &crtc_state->scaler_state;
  4359.         struct intel_crtc *intel_crtc =
  4360.                 to_intel_crtc(crtc_state->base.crtc);
  4361.         int need_scaling;
  4362.  
  4363.         need_scaling = intel_rotation_90_or_270(rotation) ?
  4364.                 (src_h != dst_w || src_w != dst_h):
  4365.                 (src_w != dst_w || src_h != dst_h);
  4366.  
  4367.         /*
  4368.          * if plane is being disabled or scaler is no more required or force detach
  4369.          *  - free scaler binded to this plane/crtc
  4370.          *  - in order to do this, update crtc->scaler_usage
  4371.          *
  4372.          * Here scaler state in crtc_state is set free so that
  4373.          * scaler can be assigned to other user. Actual register
  4374.          * update to free the scaler is done in plane/panel-fit programming.
  4375.          * For this purpose crtc/plane_state->scaler_id isn't reset here.
  4376.          */
  4377.         if (force_detach || !need_scaling) {
  4378.                 if (*scaler_id >= 0) {
  4379.                         scaler_state->scaler_users &= ~(1 << scaler_user);
  4380.                         scaler_state->scalers[*scaler_id].in_use = 0;
  4381.  
  4382.                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
  4383.                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
  4384.                                 intel_crtc->pipe, scaler_user, *scaler_id,
  4385.                                 scaler_state->scaler_users);
  4386.                         *scaler_id = -1;
  4387.                 }
  4388.                 return 0;
  4389.         }
  4390.  
  4391.         /* range checks */
  4392.         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
  4393.                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
  4394.  
  4395.                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
  4396.                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
  4397.                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
  4398.                         "size is out of scaler range\n",
  4399.                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
  4400.                 return -EINVAL;
  4401.         }
  4402.  
  4403.         /* mark this plane as a scaler user in crtc_state */
  4404.         scaler_state->scaler_users |= (1 << scaler_user);
  4405.         DRM_DEBUG_KMS("scaler_user index %u.%u: "
  4406.                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
  4407.                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
  4408.                 scaler_state->scaler_users);
  4409.  
  4410.         return 0;
  4411. }
  4412.  
  4413. /**
  4414.  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
  4415.  *
  4416.  * @state: crtc's scaler state
  4417.  *
  4418.  * Return
  4419.  *     0 - scaler_usage updated successfully
  4420.  *    error - requested scaling cannot be supported or other error condition
  4421.  */
  4422. int skl_update_scaler_crtc(struct intel_crtc_state *state)
  4423. {
  4424.         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
  4425.         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
  4426.  
  4427.         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
  4428.                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
  4429.  
  4430.         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
  4431.                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
  4432.                 state->pipe_src_w, state->pipe_src_h,
  4433.                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
  4434. }
  4435.  
  4436. /**
  4437.  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
  4438.  *
  4439.  * @state: crtc's scaler state
  4440.  * @plane_state: atomic plane state to update
  4441.  *
  4442.  * Return
  4443.  *     0 - scaler_usage updated successfully
  4444.  *    error - requested scaling cannot be supported or other error condition
  4445.  */
  4446. static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
  4447.                                    struct intel_plane_state *plane_state)
  4448. {
  4449.  
  4450.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
  4451.         struct intel_plane *intel_plane =
  4452.                 to_intel_plane(plane_state->base.plane);
  4453.         struct drm_framebuffer *fb = plane_state->base.fb;
  4454.         int ret;
  4455.  
  4456.         bool force_detach = !fb || !plane_state->visible;
  4457.  
  4458.         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
  4459.                       intel_plane->base.base.id, intel_crtc->pipe,
  4460.                       drm_plane_index(&intel_plane->base));
  4461.  
  4462.         ret = skl_update_scaler(crtc_state, force_detach,
  4463.                                 drm_plane_index(&intel_plane->base),
  4464.                                 &plane_state->scaler_id,
  4465.                                 plane_state->base.rotation,
  4466.                                 drm_rect_width(&plane_state->src) >> 16,
  4467.                                 drm_rect_height(&plane_state->src) >> 16,
  4468.                                 drm_rect_width(&plane_state->dst),
  4469.                                 drm_rect_height(&plane_state->dst));
  4470.  
  4471.         if (ret || plane_state->scaler_id < 0)
  4472.                 return ret;
  4473.  
  4474.         /* check colorkey */
  4475.         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
  4476.                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
  4477.                               intel_plane->base.base.id);
  4478.                 return -EINVAL;
  4479.         }
  4480.  
  4481.         /* Check src format */
  4482.         switch (fb->pixel_format) {
  4483.         case DRM_FORMAT_RGB565:
  4484.         case DRM_FORMAT_XBGR8888:
  4485.         case DRM_FORMAT_XRGB8888:
  4486.         case DRM_FORMAT_ABGR8888:
  4487.         case DRM_FORMAT_ARGB8888:
  4488.         case DRM_FORMAT_XRGB2101010:
  4489.         case DRM_FORMAT_XBGR2101010:
  4490.         case DRM_FORMAT_YUYV:
  4491.         case DRM_FORMAT_YVYU:
  4492.         case DRM_FORMAT_UYVY:
  4493.         case DRM_FORMAT_VYUY:
  4494.                 break;
  4495.         default:
  4496.                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
  4497.                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
  4498.                 return -EINVAL;
  4499.         }
  4500.  
  4501.         return 0;
  4502. }
  4503.  
  4504. static void skylake_scaler_disable(struct intel_crtc *crtc)
  4505. {
  4506.         int i;
  4507.  
  4508.         for (i = 0; i < crtc->num_scalers; i++)
  4509.                 skl_detach_scaler(crtc, i);
  4510. }
  4511.  
  4512. static void skylake_pfit_enable(struct intel_crtc *crtc)
  4513. {
  4514.         struct drm_device *dev = crtc->base.dev;
  4515.         struct drm_i915_private *dev_priv = dev->dev_private;
  4516.         int pipe = crtc->pipe;
  4517.         struct intel_crtc_scaler_state *scaler_state =
  4518.                 &crtc->config->scaler_state;
  4519.  
  4520.         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
  4521.  
  4522.         if (crtc->config->pch_pfit.enabled) {
  4523.                 int id;
  4524.  
  4525.                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
  4526.                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
  4527.                         return;
  4528.                 }
  4529.  
  4530.                 id = scaler_state->scaler_id;
  4531.                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
  4532.                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
  4533.                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
  4534.                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
  4535.  
  4536.                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
  4537.         }
  4538. }
  4539.  
  4540. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  4541. {
  4542.         struct drm_device *dev = crtc->base.dev;
  4543.         struct drm_i915_private *dev_priv = dev->dev_private;
  4544.         int pipe = crtc->pipe;
  4545.  
  4546.         if (crtc->config->pch_pfit.enabled) {
  4547.                 /* Force use of hard-coded filter coefficients
  4548.                  * as some pre-programmed values are broken,
  4549.                  * e.g. x201.
  4550.                  */
  4551.                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  4552.                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  4553.                                                  PF_PIPE_SEL_IVB(pipe));
  4554.                 else
  4555.                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  4556.                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
  4557.                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
  4558.         }
  4559. }
  4560.  
  4561. void hsw_enable_ips(struct intel_crtc *crtc)
  4562. {
  4563.         struct drm_device *dev = crtc->base.dev;
  4564.         struct drm_i915_private *dev_priv = dev->dev_private;
  4565.  
  4566.         if (!crtc->config->ips_enabled)
  4567.                 return;
  4568.  
  4569.         /* We can only enable IPS after we enable a plane and wait for a vblank */
  4570.         intel_wait_for_vblank(dev, crtc->pipe);
  4571.  
  4572.         assert_plane_enabled(dev_priv, crtc->plane);
  4573.         if (IS_BROADWELL(dev)) {
  4574.                 mutex_lock(&dev_priv->rps.hw_lock);
  4575.                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
  4576.                 mutex_unlock(&dev_priv->rps.hw_lock);
  4577.                 /* Quoting Art Runyan: "its not safe to expect any particular
  4578.                  * value in IPS_CTL bit 31 after enabling IPS through the
  4579.                  * mailbox." Moreover, the mailbox may return a bogus state,
  4580.                  * so we need to just enable it and continue on.
  4581.                  */
  4582.         } else {
  4583.                 I915_WRITE(IPS_CTL, IPS_ENABLE);
  4584.                 /* The bit only becomes 1 in the next vblank, so this wait here
  4585.                  * is essentially intel_wait_for_vblank. If we don't have this
  4586.                  * and don't wait for vblanks until the end of crtc_enable, then
  4587.                  * the HW state readout code will complain that the expected
  4588.                  * IPS_CTL value is not the one we read. */
  4589.                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
  4590.                         DRM_ERROR("Timed out waiting for IPS enable\n");
  4591.         }
  4592. }
  4593.  
  4594. void hsw_disable_ips(struct intel_crtc *crtc)
  4595. {
  4596.         struct drm_device *dev = crtc->base.dev;
  4597.         struct drm_i915_private *dev_priv = dev->dev_private;
  4598.  
  4599.         if (!crtc->config->ips_enabled)
  4600.                 return;
  4601.  
  4602.         assert_plane_enabled(dev_priv, crtc->plane);
  4603.         if (IS_BROADWELL(dev)) {
  4604.                 mutex_lock(&dev_priv->rps.hw_lock);
  4605.                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
  4606.                 mutex_unlock(&dev_priv->rps.hw_lock);
  4607.                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
  4608.                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
  4609.                         DRM_ERROR("Timed out waiting for IPS disable\n");
  4610.         } else {
  4611.                 I915_WRITE(IPS_CTL, 0);
  4612.                 POSTING_READ(IPS_CTL);
  4613.         }
  4614.  
  4615.         /* We need to wait for a vblank before we can disable the plane. */
  4616.         intel_wait_for_vblank(dev, crtc->pipe);
  4617. }
  4618.  
  4619. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  4620. static void intel_crtc_load_lut(struct drm_crtc *crtc)
  4621. {
  4622.         struct drm_device *dev = crtc->dev;
  4623.         struct drm_i915_private *dev_priv = dev->dev_private;
  4624.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4625.         enum pipe pipe = intel_crtc->pipe;
  4626.         int i;
  4627.         bool reenable_ips = false;
  4628.  
  4629.         /* The clocks have to be on to load the palette. */
  4630.         if (!crtc->state->active)
  4631.                 return;
  4632.  
  4633.         if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
  4634.                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
  4635.                         assert_dsi_pll_enabled(dev_priv);
  4636.                 else
  4637.                         assert_pll_enabled(dev_priv, pipe);
  4638.         }
  4639.  
  4640.         /* Workaround : Do not read or write the pipe palette/gamma data while
  4641.          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
  4642.          */
  4643.         if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
  4644.             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
  4645.              GAMMA_MODE_MODE_SPLIT)) {
  4646.                 hsw_disable_ips(intel_crtc);
  4647.                 reenable_ips = true;
  4648.         }
  4649.  
  4650.         for (i = 0; i < 256; i++) {
  4651.                 u32 palreg;
  4652.  
  4653.                 if (HAS_GMCH_DISPLAY(dev))
  4654.                         palreg = PALETTE(pipe, i);
  4655.                 else
  4656.                         palreg = LGC_PALETTE(pipe, i);
  4657.  
  4658.                 I915_WRITE(palreg,
  4659.                            (intel_crtc->lut_r[i] << 16) |
  4660.                            (intel_crtc->lut_g[i] << 8) |
  4661.                            intel_crtc->lut_b[i]);
  4662.         }
  4663.  
  4664.         if (reenable_ips)
  4665.                 hsw_enable_ips(intel_crtc);
  4666. }
  4667.  
  4668. static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
  4669. {
  4670.         if (intel_crtc->overlay) {
  4671.                 struct drm_device *dev = intel_crtc->base.dev;
  4672.                 struct drm_i915_private *dev_priv = dev->dev_private;
  4673.  
  4674.                 mutex_lock(&dev->struct_mutex);
  4675.                 dev_priv->mm.interruptible = false;
  4676. //       (void) intel_overlay_switch_off(intel_crtc->overlay);
  4677.                 dev_priv->mm.interruptible = true;
  4678.                 mutex_unlock(&dev->struct_mutex);
  4679.         }
  4680.  
  4681.         /* Let userspace switch the overlay on again. In most cases userspace
  4682.          * has to recompute where to put it anyway.
  4683.          */
  4684. }
  4685.  
  4686. /**
  4687.  * intel_post_enable_primary - Perform operations after enabling primary plane
  4688.  * @crtc: the CRTC whose primary plane was just enabled
  4689.  *
  4690.  * Performs potentially sleeping operations that must be done after the primary
  4691.  * plane is enabled, such as updating FBC and IPS.  Note that this may be
  4692.  * called due to an explicit primary plane update, or due to an implicit
  4693.  * re-enable that is caused when a sprite plane is updated to no longer
  4694.  * completely hide the primary plane.
  4695.  */
  4696. static void
  4697. intel_post_enable_primary(struct drm_crtc *crtc)
  4698. {
  4699.         struct drm_device *dev = crtc->dev;
  4700.         struct drm_i915_private *dev_priv = dev->dev_private;
  4701.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4702.         int pipe = intel_crtc->pipe;
  4703.  
  4704.         /*
  4705.          * BDW signals flip done immediately if the plane
  4706.          * is disabled, even if the plane enable is already
  4707.          * armed to occur at the next vblank :(
  4708.          */
  4709.         if (IS_BROADWELL(dev))
  4710.                 intel_wait_for_vblank(dev, pipe);
  4711.  
  4712.         /*
  4713.          * FIXME IPS should be fine as long as one plane is
  4714.          * enabled, but in practice it seems to have problems
  4715.          * when going from primary only to sprite only and vice
  4716.          * versa.
  4717.          */
  4718.         hsw_enable_ips(intel_crtc);
  4719.  
  4720.         /*
  4721.          * Gen2 reports pipe underruns whenever all planes are disabled.
  4722.          * So don't enable underrun reporting before at least some planes
  4723.          * are enabled.
  4724.          * FIXME: Need to fix the logic to work when we turn off all planes
  4725.          * but leave the pipe running.
  4726.          */
  4727.         if (IS_GEN2(dev))
  4728.                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4729.  
  4730.         /* Underruns don't raise interrupts, so check manually. */
  4731.         if (HAS_GMCH_DISPLAY(dev))
  4732.                 i9xx_check_fifo_underruns(dev_priv);
  4733. }
  4734.  
  4735. /**
  4736.  * intel_pre_disable_primary - Perform operations before disabling primary plane
  4737.  * @crtc: the CRTC whose primary plane is to be disabled
  4738.  *
  4739.  * Performs potentially sleeping operations that must be done before the
  4740.  * primary plane is disabled, such as updating FBC and IPS.  Note that this may
  4741.  * be called due to an explicit primary plane update, or due to an implicit
  4742.  * disable that is caused when a sprite plane completely hides the primary
  4743.  * plane.
  4744.  */
  4745. static void
  4746. intel_pre_disable_primary(struct drm_crtc *crtc)
  4747. {
  4748.         struct drm_device *dev = crtc->dev;
  4749.         struct drm_i915_private *dev_priv = dev->dev_private;
  4750.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4751.         int pipe = intel_crtc->pipe;
  4752.  
  4753.         /*
  4754.          * Gen2 reports pipe underruns whenever all planes are disabled.
  4755.          * So diasble underrun reporting before all the planes get disabled.
  4756.          * FIXME: Need to fix the logic to work when we turn off all planes
  4757.          * but leave the pipe running.
  4758.          */
  4759.         if (IS_GEN2(dev))
  4760.                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  4761.  
  4762.         /*
  4763.          * Vblank time updates from the shadow to live plane control register
  4764.          * are blocked if the memory self-refresh mode is active at that
  4765.          * moment. So to make sure the plane gets truly disabled, disable
  4766.          * first the self-refresh mode. The self-refresh enable bit in turn
  4767.          * will be checked/applied by the HW only at the next frame start
  4768.          * event which is after the vblank start event, so we need to have a
  4769.          * wait-for-vblank between disabling the plane and the pipe.
  4770.          */
  4771.         if (HAS_GMCH_DISPLAY(dev)) {
  4772.                 intel_set_memory_cxsr(dev_priv, false);
  4773.                 dev_priv->wm.vlv.cxsr = false;
  4774.                 intel_wait_for_vblank(dev, pipe);
  4775.         }
  4776.  
  4777.         /*
  4778.          * FIXME IPS should be fine as long as one plane is
  4779.          * enabled, but in practice it seems to have problems
  4780.          * when going from primary only to sprite only and vice
  4781.          * versa.
  4782.          */
  4783.         hsw_disable_ips(intel_crtc);
  4784. }
  4785.  
  4786. static void intel_post_plane_update(struct intel_crtc *crtc)
  4787. {
  4788.         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
  4789.         struct drm_device *dev = crtc->base.dev;
  4790.         struct drm_i915_private *dev_priv = dev->dev_private;
  4791.         struct drm_plane *plane;
  4792.  
  4793.         if (atomic->wait_vblank)
  4794.                 intel_wait_for_vblank(dev, crtc->pipe);
  4795.  
  4796.         intel_frontbuffer_flip(dev, atomic->fb_bits);
  4797.  
  4798.         if (atomic->disable_cxsr)
  4799.                 crtc->wm.cxsr_allowed = true;
  4800.  
  4801.         if (crtc->atomic.update_wm_post)
  4802.                 intel_update_watermarks(&crtc->base);
  4803.  
  4804.         if (atomic->update_fbc)
  4805.                 intel_fbc_update(dev_priv);
  4806.  
  4807.         if (atomic->post_enable_primary)
  4808.                 intel_post_enable_primary(&crtc->base);
  4809.  
  4810.         drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
  4811.                 intel_update_sprite_watermarks(plane, &crtc->base,
  4812.                                                0, 0, 0, false, false);
  4813.  
  4814.         memset(atomic, 0, sizeof(*atomic));
  4815. }
  4816.  
  4817. static void intel_pre_plane_update(struct intel_crtc *crtc)
  4818. {
  4819.         struct drm_device *dev = crtc->base.dev;
  4820.         struct drm_i915_private *dev_priv = dev->dev_private;
  4821.         struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
  4822.         struct drm_plane *p;
  4823.  
  4824.         /* Track fb's for any planes being disabled */
  4825.         drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
  4826.                 struct intel_plane *plane = to_intel_plane(p);
  4827.  
  4828.                 mutex_lock(&dev->struct_mutex);
  4829.                 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
  4830.                                   plane->frontbuffer_bit);
  4831.                 mutex_unlock(&dev->struct_mutex);
  4832.         }
  4833.  
  4834.         if (atomic->disable_fbc)
  4835.                 intel_fbc_disable_crtc(crtc);
  4836.  
  4837.         if (crtc->atomic.disable_ips)
  4838.                 hsw_disable_ips(crtc);
  4839.  
  4840.         if (atomic->pre_disable_primary)
  4841.                 intel_pre_disable_primary(&crtc->base);
  4842.  
  4843.         if (atomic->disable_cxsr) {
  4844.                 crtc->wm.cxsr_allowed = false;
  4845.                 intel_set_memory_cxsr(dev_priv, false);
  4846.         }
  4847. }
  4848.  
  4849. static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
  4850. {
  4851.         struct drm_device *dev = crtc->dev;
  4852.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4853.         struct drm_plane *p;
  4854.         int pipe = intel_crtc->pipe;
  4855.  
  4856.         intel_crtc_dpms_overlay_disable(intel_crtc);
  4857.  
  4858.         drm_for_each_plane_mask(p, dev, plane_mask)
  4859.                 to_intel_plane(p)->disable_plane(p, crtc);
  4860.  
  4861.         /*
  4862.          * FIXME: Once we grow proper nuclear flip support out of this we need
  4863.          * to compute the mask of flip planes precisely. For the time being
  4864.          * consider this a flip to a NULL plane.
  4865.          */
  4866. //      intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
  4867. }
  4868.  
  4869. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  4870. {
  4871.         struct drm_device *dev = crtc->dev;
  4872.         struct drm_i915_private *dev_priv = dev->dev_private;
  4873.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4874.         struct intel_encoder *encoder;
  4875.         int pipe = intel_crtc->pipe;
  4876.  
  4877.         if (WARN_ON(intel_crtc->active))
  4878.                 return;
  4879.  
  4880.         if (intel_crtc->config->has_pch_encoder)
  4881.                 intel_prepare_shared_dpll(intel_crtc);
  4882.  
  4883.         if (intel_crtc->config->has_dp_encoder)
  4884.                 intel_dp_set_m_n(intel_crtc, M1_N1);
  4885.  
  4886.         intel_set_pipe_timings(intel_crtc);
  4887.  
  4888.         if (intel_crtc->config->has_pch_encoder) {
  4889.                 intel_cpu_transcoder_set_m_n(intel_crtc,
  4890.                                      &intel_crtc->config->fdi_m_n, NULL);
  4891.         }
  4892.  
  4893.         ironlake_set_pipeconf(crtc);
  4894.  
  4895.         intel_crtc->active = true;
  4896.  
  4897.         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4898.         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
  4899.  
  4900.         for_each_encoder_on_crtc(dev, crtc, encoder)
  4901.                 if (encoder->pre_enable)
  4902.                         encoder->pre_enable(encoder);
  4903.  
  4904.         if (intel_crtc->config->has_pch_encoder) {
  4905.                 /* Note: FDI PLL enabling _must_ be done before we enable the
  4906.                  * cpu pipes, hence this is separate from all the other fdi/pch
  4907.                  * enabling. */
  4908.                 ironlake_fdi_pll_enable(intel_crtc);
  4909.         } else {
  4910.                 assert_fdi_tx_disabled(dev_priv, pipe);
  4911.                 assert_fdi_rx_disabled(dev_priv, pipe);
  4912.         }
  4913.  
  4914.         ironlake_pfit_enable(intel_crtc);
  4915.  
  4916.         /*
  4917.          * On ILK+ LUT must be loaded before the pipe is running but with
  4918.          * clocks enabled
  4919.          */
  4920.         intel_crtc_load_lut(crtc);
  4921.  
  4922.         intel_update_watermarks(crtc);
  4923.         intel_enable_pipe(intel_crtc);
  4924.  
  4925.         if (intel_crtc->config->has_pch_encoder)
  4926.                 ironlake_pch_enable(crtc);
  4927.  
  4928.         assert_vblank_disabled(crtc);
  4929.         drm_crtc_vblank_on(crtc);
  4930.  
  4931.         for_each_encoder_on_crtc(dev, crtc, encoder)
  4932.                 encoder->enable(encoder);
  4933.  
  4934.         if (HAS_PCH_CPT(dev))
  4935.                 cpt_verify_modeset(dev, intel_crtc->pipe);
  4936. }
  4937.  
  4938. /* IPS only exists on ULT machines and is tied to pipe A. */
  4939. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  4940. {
  4941.         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  4942. }
  4943.  
  4944. static void haswell_crtc_enable(struct drm_crtc *crtc)
  4945. {
  4946.         struct drm_device *dev = crtc->dev;
  4947.         struct drm_i915_private *dev_priv = dev->dev_private;
  4948.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4949.         struct intel_encoder *encoder;
  4950.         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
  4951.         struct intel_crtc_state *pipe_config =
  4952.                 to_intel_crtc_state(crtc->state);
  4953.         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
  4954.  
  4955.         if (WARN_ON(intel_crtc->active))
  4956.                 return;
  4957.  
  4958.         if (intel_crtc_to_shared_dpll(intel_crtc))
  4959.                 intel_enable_shared_dpll(intel_crtc);
  4960.  
  4961.         if (intel_crtc->config->has_dp_encoder)
  4962.                 intel_dp_set_m_n(intel_crtc, M1_N1);
  4963.  
  4964.         intel_set_pipe_timings(intel_crtc);
  4965.  
  4966.         if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
  4967.                 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
  4968.                            intel_crtc->config->pixel_multiplier - 1);
  4969.         }
  4970.  
  4971.         if (intel_crtc->config->has_pch_encoder) {
  4972.                 intel_cpu_transcoder_set_m_n(intel_crtc,
  4973.                                      &intel_crtc->config->fdi_m_n, NULL);
  4974.         }
  4975.  
  4976.         haswell_set_pipeconf(crtc);
  4977.  
  4978.         intel_set_pipe_csc(crtc);
  4979.  
  4980.         intel_crtc->active = true;
  4981.  
  4982.         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  4983.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  4984.                 if (encoder->pre_pll_enable)
  4985.                         encoder->pre_pll_enable(encoder);
  4986.                 if (encoder->pre_enable)
  4987.                         encoder->pre_enable(encoder);
  4988.         }
  4989.  
  4990.         if (intel_crtc->config->has_pch_encoder) {
  4991.                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  4992.                                                       true);
  4993.                 dev_priv->display.fdi_link_train(crtc);
  4994.         }
  4995.  
  4996.         if (!is_dsi)
  4997.                 intel_ddi_enable_pipe_clock(intel_crtc);
  4998.  
  4999.         if (INTEL_INFO(dev)->gen >= 9)
  5000.                 skylake_pfit_enable(intel_crtc);
  5001.         else
  5002.                 ironlake_pfit_enable(intel_crtc);
  5003.  
  5004.         /*
  5005.          * On ILK+ LUT must be loaded before the pipe is running but with
  5006.          * clocks enabled
  5007.          */
  5008.         intel_crtc_load_lut(crtc);
  5009.  
  5010.         intel_ddi_set_pipe_settings(crtc);
  5011.         if (!is_dsi)
  5012.                 intel_ddi_enable_transcoder_func(crtc);
  5013.  
  5014.         intel_update_watermarks(crtc);
  5015.         intel_enable_pipe(intel_crtc);
  5016.  
  5017.         if (intel_crtc->config->has_pch_encoder)
  5018.                 lpt_pch_enable(crtc);
  5019.  
  5020.         if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
  5021.                 intel_ddi_set_vc_payload_alloc(crtc, true);
  5022.  
  5023.         assert_vblank_disabled(crtc);
  5024.         drm_crtc_vblank_on(crtc);
  5025.  
  5026.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  5027.                 encoder->enable(encoder);
  5028.                 intel_opregion_notify_encoder(encoder, true);
  5029.         }
  5030.  
  5031.         /* If we change the relative order between pipe/planes enabling, we need
  5032.          * to change the workaround. */
  5033.         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
  5034.         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
  5035.                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
  5036.                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
  5037.         }
  5038. }
  5039.  
  5040. static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
  5041. {
  5042.         struct drm_device *dev = crtc->base.dev;
  5043.         struct drm_i915_private *dev_priv = dev->dev_private;
  5044.         int pipe = crtc->pipe;
  5045.  
  5046.         /* To avoid upsetting the power well on haswell only disable the pfit if
  5047.          * it's in use. The hw state code will make sure we get this right. */
  5048.         if (force || crtc->config->pch_pfit.enabled) {
  5049.                 I915_WRITE(PF_CTL(pipe), 0);
  5050.                 I915_WRITE(PF_WIN_POS(pipe), 0);
  5051.                 I915_WRITE(PF_WIN_SZ(pipe), 0);
  5052.         }
  5053. }
  5054.  
  5055. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  5056. {
  5057.         struct drm_device *dev = crtc->dev;
  5058.         struct drm_i915_private *dev_priv = dev->dev_private;
  5059.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5060.         struct intel_encoder *encoder;
  5061.         int pipe = intel_crtc->pipe;
  5062.         u32 reg, temp;
  5063.  
  5064.         for_each_encoder_on_crtc(dev, crtc, encoder)
  5065.                 encoder->disable(encoder);
  5066.  
  5067.         drm_crtc_vblank_off(crtc);
  5068.         assert_vblank_disabled(crtc);
  5069.  
  5070.         if (intel_crtc->config->has_pch_encoder)
  5071.                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
  5072.  
  5073.         intel_disable_pipe(intel_crtc);
  5074.  
  5075.         ironlake_pfit_disable(intel_crtc, false);
  5076.  
  5077.         if (intel_crtc->config->has_pch_encoder)
  5078.                 ironlake_fdi_disable(crtc);
  5079.  
  5080.         for_each_encoder_on_crtc(dev, crtc, encoder)
  5081.                 if (encoder->post_disable)
  5082.                         encoder->post_disable(encoder);
  5083.  
  5084.         if (intel_crtc->config->has_pch_encoder) {
  5085.                 ironlake_disable_pch_transcoder(dev_priv, pipe);
  5086.  
  5087.                 if (HAS_PCH_CPT(dev)) {
  5088.                         /* disable TRANS_DP_CTL */
  5089.                         reg = TRANS_DP_CTL(pipe);
  5090.                         temp = I915_READ(reg);
  5091.                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  5092.                                   TRANS_DP_PORT_SEL_MASK);
  5093.                         temp |= TRANS_DP_PORT_SEL_NONE;
  5094.                         I915_WRITE(reg, temp);
  5095.  
  5096.                         /* disable DPLL_SEL */
  5097.                         temp = I915_READ(PCH_DPLL_SEL);
  5098.                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  5099.                         I915_WRITE(PCH_DPLL_SEL, temp);
  5100.                 }
  5101.  
  5102.                 ironlake_fdi_pll_disable(intel_crtc);
  5103.         }
  5104. }
  5105.  
  5106. static void haswell_crtc_disable(struct drm_crtc *crtc)
  5107. {
  5108.         struct drm_device *dev = crtc->dev;
  5109.         struct drm_i915_private *dev_priv = dev->dev_private;
  5110.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5111.         struct intel_encoder *encoder;
  5112.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  5113.         bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
  5114.  
  5115.         for_each_encoder_on_crtc(dev, crtc, encoder) {
  5116.                 intel_opregion_notify_encoder(encoder, false);
  5117.                 encoder->disable(encoder);
  5118.         }
  5119.  
  5120.         drm_crtc_vblank_off(crtc);
  5121.         assert_vblank_disabled(crtc);
  5122.  
  5123.         if (intel_crtc->config->has_pch_encoder)
  5124.                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  5125.                                                       false);
  5126.         intel_disable_pipe(intel_crtc);
  5127.  
  5128.         if (intel_crtc->config->dp_encoder_is_mst)
  5129.                 intel_ddi_set_vc_payload_alloc(crtc, false);
  5130.  
  5131.         if (!is_dsi)
  5132.                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  5133.  
  5134.         if (INTEL_INFO(dev)->gen >= 9)
  5135.                 skylake_scaler_disable(intel_crtc);
  5136.         else
  5137.                 ironlake_pfit_disable(intel_crtc, false);
  5138.  
  5139.         if (!is_dsi)
  5140.                 intel_ddi_disable_pipe_clock(intel_crtc);
  5141.  
  5142.         if (intel_crtc->config->has_pch_encoder) {
  5143.                 lpt_disable_pch_transcoder(dev_priv);
  5144.                 intel_ddi_fdi_disable(crtc);
  5145.         }
  5146.  
  5147.         for_each_encoder_on_crtc(dev, crtc, encoder)
  5148.                 if (encoder->post_disable)
  5149.                         encoder->post_disable(encoder);
  5150. }
  5151.  
  5152. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  5153. {
  5154.         struct drm_device *dev = crtc->base.dev;
  5155.         struct drm_i915_private *dev_priv = dev->dev_private;
  5156.         struct intel_crtc_state *pipe_config = crtc->config;
  5157.  
  5158.         if (!pipe_config->gmch_pfit.control)
  5159.                 return;
  5160.  
  5161.         /*
  5162.          * The panel fitter should only be adjusted whilst the pipe is disabled,
  5163.          * according to register description and PRM.
  5164.          */
  5165.         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  5166.         assert_pipe_disabled(dev_priv, crtc->pipe);
  5167.  
  5168.         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  5169.         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  5170.  
  5171.         /* Border color in case we don't scale up to the full screen. Black by
  5172.          * default, change to something else for debugging. */
  5173.         I915_WRITE(BCLRPAT(crtc->pipe), 0);
  5174. }
  5175.  
  5176. static enum intel_display_power_domain port_to_power_domain(enum port port)
  5177. {
  5178.         switch (port) {
  5179.         case PORT_A:
  5180.                 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
  5181.         case PORT_B:
  5182.                 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
  5183.         case PORT_C:
  5184.                 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
  5185.         case PORT_D:
  5186.                 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
  5187.         case PORT_E:
  5188.                 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
  5189.         default:
  5190.                 MISSING_CASE(port);
  5191.                 return POWER_DOMAIN_PORT_OTHER;
  5192.         }
  5193. }
  5194.  
  5195. static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
  5196. {
  5197.         switch (port) {
  5198.         case PORT_A:
  5199.                 return POWER_DOMAIN_AUX_A;
  5200.         case PORT_B:
  5201.                 return POWER_DOMAIN_AUX_B;
  5202.         case PORT_C:
  5203.                 return POWER_DOMAIN_AUX_C;
  5204.         case PORT_D:
  5205.                 return POWER_DOMAIN_AUX_D;
  5206.         case PORT_E:
  5207.                 /* FIXME: Check VBT for actual wiring of PORT E */
  5208.                 return POWER_DOMAIN_AUX_D;
  5209.         default:
  5210.                 MISSING_CASE(port);
  5211.                 return POWER_DOMAIN_AUX_A;
  5212.         }
  5213. }
  5214.  
  5215. #define for_each_power_domain(domain, mask)                             \
  5216.         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
  5217.                 if ((1 << (domain)) & (mask))
  5218.  
  5219. enum intel_display_power_domain
  5220. intel_display_port_power_domain(struct intel_encoder *intel_encoder)
  5221. {
  5222.         struct drm_device *dev = intel_encoder->base.dev;
  5223.         struct intel_digital_port *intel_dig_port;
  5224.  
  5225.         switch (intel_encoder->type) {
  5226.         case INTEL_OUTPUT_UNKNOWN:
  5227.                 /* Only DDI platforms should ever use this output type */
  5228.                 WARN_ON_ONCE(!HAS_DDI(dev));
  5229.         case INTEL_OUTPUT_DISPLAYPORT:
  5230.         case INTEL_OUTPUT_HDMI:
  5231.         case INTEL_OUTPUT_EDP:
  5232.                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
  5233.                 return port_to_power_domain(intel_dig_port->port);
  5234.         case INTEL_OUTPUT_DP_MST:
  5235.                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
  5236.                 return port_to_power_domain(intel_dig_port->port);
  5237.         case INTEL_OUTPUT_ANALOG:
  5238.                 return POWER_DOMAIN_PORT_CRT;
  5239.         case INTEL_OUTPUT_DSI:
  5240.                 return POWER_DOMAIN_PORT_DSI;
  5241.         default:
  5242.                 return POWER_DOMAIN_PORT_OTHER;
  5243.         }
  5244. }
  5245.  
  5246. enum intel_display_power_domain
  5247. intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
  5248. {
  5249.         struct drm_device *dev = intel_encoder->base.dev;
  5250.         struct intel_digital_port *intel_dig_port;
  5251.  
  5252.         switch (intel_encoder->type) {
  5253.         case INTEL_OUTPUT_UNKNOWN:
  5254.         case INTEL_OUTPUT_HDMI:
  5255.                 /*
  5256.                  * Only DDI platforms should ever use these output types.
  5257.                  * We can get here after the HDMI detect code has already set
  5258.                  * the type of the shared encoder. Since we can't be sure
  5259.                  * what's the status of the given connectors, play safe and
  5260.                  * run the DP detection too.
  5261.                  */
  5262.                 WARN_ON_ONCE(!HAS_DDI(dev));
  5263.         case INTEL_OUTPUT_DISPLAYPORT:
  5264.         case INTEL_OUTPUT_EDP:
  5265.                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
  5266.                 return port_to_aux_power_domain(intel_dig_port->port);
  5267.         case INTEL_OUTPUT_DP_MST:
  5268.                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
  5269.                 return port_to_aux_power_domain(intel_dig_port->port);
  5270.         default:
  5271.                 MISSING_CASE(intel_encoder->type);
  5272.                 return POWER_DOMAIN_AUX_A;
  5273.         }
  5274. }
  5275.  
  5276. static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
  5277. {
  5278.         struct drm_device *dev = crtc->dev;
  5279.         struct intel_encoder *intel_encoder;
  5280.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5281.         enum pipe pipe = intel_crtc->pipe;
  5282.         unsigned long mask;
  5283.         enum transcoder transcoder;
  5284.  
  5285.         if (!crtc->state->active)
  5286.                 return 0;
  5287.  
  5288.         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
  5289.  
  5290.         mask = BIT(POWER_DOMAIN_PIPE(pipe));
  5291.         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
  5292.         if (intel_crtc->config->pch_pfit.enabled ||
  5293.             intel_crtc->config->pch_pfit.force_thru)
  5294.                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
  5295.  
  5296.         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  5297.                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
  5298.  
  5299.         return mask;
  5300. }
  5301.  
  5302. static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
  5303. {
  5304.         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  5305.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5306.         enum intel_display_power_domain domain;
  5307.         unsigned long domains, new_domains, old_domains;
  5308.  
  5309.         old_domains = intel_crtc->enabled_power_domains;
  5310.         intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
  5311.  
  5312.         domains = new_domains & ~old_domains;
  5313.  
  5314.         for_each_power_domain(domain, domains)
  5315.                 intel_display_power_get(dev_priv, domain);
  5316.  
  5317.         return old_domains & ~new_domains;
  5318. }
  5319.  
  5320. static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
  5321.                                       unsigned long domains)
  5322. {
  5323.         enum intel_display_power_domain domain;
  5324.  
  5325.         for_each_power_domain(domain, domains)
  5326.                 intel_display_power_put(dev_priv, domain);
  5327. }
  5328.  
  5329. static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
  5330. {
  5331.         struct drm_device *dev = state->dev;
  5332.         struct drm_i915_private *dev_priv = dev->dev_private;
  5333.         unsigned long put_domains[I915_MAX_PIPES] = {};
  5334.         struct drm_crtc_state *crtc_state;
  5335.         struct drm_crtc *crtc;
  5336.         int i;
  5337.  
  5338.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  5339.                 if (needs_modeset(crtc->state))
  5340.                         put_domains[to_intel_crtc(crtc)->pipe] =
  5341.                                 modeset_get_crtc_power_domains(crtc);
  5342.         }
  5343.  
  5344.         if (dev_priv->display.modeset_commit_cdclk) {
  5345.                 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
  5346.  
  5347.                 if (cdclk != dev_priv->cdclk_freq &&
  5348.                     !WARN_ON(!state->allow_modeset))
  5349.                         dev_priv->display.modeset_commit_cdclk(state);
  5350.         }
  5351.  
  5352.         for (i = 0; i < I915_MAX_PIPES; i++)
  5353.                 if (put_domains[i])
  5354.                         modeset_put_power_domains(dev_priv, put_domains[i]);
  5355. }
  5356.  
  5357. static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
  5358. {
  5359.         int max_cdclk_freq = dev_priv->max_cdclk_freq;
  5360.  
  5361.         if (INTEL_INFO(dev_priv)->gen >= 9 ||
  5362.             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
  5363.                 return max_cdclk_freq;
  5364.         else if (IS_CHERRYVIEW(dev_priv))
  5365.                 return max_cdclk_freq*95/100;
  5366.         else if (INTEL_INFO(dev_priv)->gen < 4)
  5367.                 return 2*max_cdclk_freq*90/100;
  5368.         else
  5369.                 return max_cdclk_freq*90/100;
  5370. }
  5371.  
  5372. static void intel_update_max_cdclk(struct drm_device *dev)
  5373. {
  5374.         struct drm_i915_private *dev_priv = dev->dev_private;
  5375.  
  5376.         if (IS_SKYLAKE(dev)) {
  5377.                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
  5378.  
  5379.                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
  5380.                         dev_priv->max_cdclk_freq = 675000;
  5381.                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
  5382.                         dev_priv->max_cdclk_freq = 540000;
  5383.                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
  5384.                         dev_priv->max_cdclk_freq = 450000;
  5385.                 else
  5386.                         dev_priv->max_cdclk_freq = 337500;
  5387.         } else if (IS_BROADWELL(dev))  {
  5388.                 /*
  5389.                  * FIXME with extra cooling we can allow
  5390.                  * 540 MHz for ULX and 675 Mhz for ULT.
  5391.                  * How can we know if extra cooling is
  5392.                  * available? PCI ID, VTB, something else?
  5393.                  */
  5394.                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
  5395.                         dev_priv->max_cdclk_freq = 450000;
  5396.                 else if (IS_BDW_ULX(dev))
  5397.                         dev_priv->max_cdclk_freq = 450000;
  5398.                 else if (IS_BDW_ULT(dev))
  5399.                         dev_priv->max_cdclk_freq = 540000;
  5400.                 else
  5401.                         dev_priv->max_cdclk_freq = 675000;
  5402.         } else if (IS_CHERRYVIEW(dev)) {
  5403.                 dev_priv->max_cdclk_freq = 320000;
  5404.         } else if (IS_VALLEYVIEW(dev)) {
  5405.                 dev_priv->max_cdclk_freq = 400000;
  5406.         } else {
  5407.                 /* otherwise assume cdclk is fixed */
  5408.                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
  5409.         }
  5410.  
  5411.         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
  5412.  
  5413.         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
  5414.                          dev_priv->max_cdclk_freq);
  5415.  
  5416.         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
  5417.                          dev_priv->max_dotclk_freq);
  5418. }
  5419.  
  5420. static void intel_update_cdclk(struct drm_device *dev)
  5421. {
  5422.         struct drm_i915_private *dev_priv = dev->dev_private;
  5423.  
  5424.         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
  5425.         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
  5426.                          dev_priv->cdclk_freq);
  5427.  
  5428.         /*
  5429.          * Program the gmbus_freq based on the cdclk frequency.
  5430.          * BSpec erroneously claims we should aim for 4MHz, but
  5431.          * in fact 1MHz is the correct frequency.
  5432.          */
  5433.         if (IS_VALLEYVIEW(dev)) {
  5434.                 /*
  5435.                  * Program the gmbus_freq based on the cdclk frequency.
  5436.                  * BSpec erroneously claims we should aim for 4MHz, but
  5437.                  * in fact 1MHz is the correct frequency.
  5438.                  */
  5439.                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
  5440.         }
  5441.  
  5442.         if (dev_priv->max_cdclk_freq == 0)
  5443.                 intel_update_max_cdclk(dev);
  5444. }
  5445.  
  5446. static void broxton_set_cdclk(struct drm_device *dev, int frequency)
  5447. {
  5448.         struct drm_i915_private *dev_priv = dev->dev_private;
  5449.         uint32_t divider;
  5450.         uint32_t ratio;
  5451.         uint32_t current_freq;
  5452.         int ret;
  5453.  
  5454.         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
  5455.         switch (frequency) {
  5456.         case 144000:
  5457.                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
  5458.                 ratio = BXT_DE_PLL_RATIO(60);
  5459.                 break;
  5460.         case 288000:
  5461.                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
  5462.                 ratio = BXT_DE_PLL_RATIO(60);
  5463.                 break;
  5464.         case 384000:
  5465.                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
  5466.                 ratio = BXT_DE_PLL_RATIO(60);
  5467.                 break;
  5468.         case 576000:
  5469.                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
  5470.                 ratio = BXT_DE_PLL_RATIO(60);
  5471.                 break;
  5472.         case 624000:
  5473.                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
  5474.                 ratio = BXT_DE_PLL_RATIO(65);
  5475.                 break;
  5476.         case 19200:
  5477.                 /*
  5478.                  * Bypass frequency with DE PLL disabled. Init ratio, divider
  5479.                  * to suppress GCC warning.
  5480.                  */
  5481.                 ratio = 0;
  5482.                 divider = 0;
  5483.                 break;
  5484.         default:
  5485.                 DRM_ERROR("unsupported CDCLK freq %d", frequency);
  5486.  
  5487.                 return;
  5488.         }
  5489.  
  5490.         mutex_lock(&dev_priv->rps.hw_lock);
  5491.         /* Inform power controller of upcoming frequency change */
  5492.         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
  5493.                                       0x80000000);
  5494.         mutex_unlock(&dev_priv->rps.hw_lock);
  5495.  
  5496.         if (ret) {
  5497.                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
  5498.                           ret, frequency);
  5499.                 return;
  5500.         }
  5501.  
  5502.         current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
  5503.         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
  5504.         current_freq = current_freq * 500 + 1000;
  5505.  
  5506.         /*
  5507.          * DE PLL has to be disabled when
  5508.          * - setting to 19.2MHz (bypass, PLL isn't used)
  5509.          * - before setting to 624MHz (PLL needs toggling)
  5510.          * - before setting to any frequency from 624MHz (PLL needs toggling)
  5511.          */
  5512.         if (frequency == 19200 || frequency == 624000 ||
  5513.             current_freq == 624000) {
  5514.                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
  5515.                 /* Timeout 200us */
  5516.                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
  5517.                              1))
  5518.                         DRM_ERROR("timout waiting for DE PLL unlock\n");
  5519.         }
  5520.  
  5521.         if (frequency != 19200) {
  5522.                 uint32_t val;
  5523.  
  5524.                 val = I915_READ(BXT_DE_PLL_CTL);
  5525.                 val &= ~BXT_DE_PLL_RATIO_MASK;
  5526.                 val |= ratio;
  5527.                 I915_WRITE(BXT_DE_PLL_CTL, val);
  5528.  
  5529.                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
  5530.                 /* Timeout 200us */
  5531.                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
  5532.                         DRM_ERROR("timeout waiting for DE PLL lock\n");
  5533.  
  5534.                 val = I915_READ(CDCLK_CTL);
  5535.                 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
  5536.                 val |= divider;
  5537.                 /*
  5538.                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
  5539.                  * enable otherwise.
  5540.                  */
  5541.                 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
  5542.                 if (frequency >= 500000)
  5543.                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
  5544.  
  5545.                 val &= ~CDCLK_FREQ_DECIMAL_MASK;
  5546.                 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
  5547.                 val |= (frequency - 1000) / 500;
  5548.                 I915_WRITE(CDCLK_CTL, val);
  5549.         }
  5550.  
  5551.         mutex_lock(&dev_priv->rps.hw_lock);
  5552.         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
  5553.                                       DIV_ROUND_UP(frequency, 25000));
  5554.         mutex_unlock(&dev_priv->rps.hw_lock);
  5555.  
  5556.         if (ret) {
  5557.                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
  5558.                           ret, frequency);
  5559.                 return;
  5560.         }
  5561.  
  5562.         intel_update_cdclk(dev);
  5563. }
  5564.  
  5565. void broxton_init_cdclk(struct drm_device *dev)
  5566. {
  5567.         struct drm_i915_private *dev_priv = dev->dev_private;
  5568.         uint32_t val;
  5569.  
  5570.         /*
  5571.          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
  5572.          * or else the reset will hang because there is no PCH to respond.
  5573.          * Move the handshake programming to initialization sequence.
  5574.          * Previously was left up to BIOS.
  5575.          */
  5576.         val = I915_READ(HSW_NDE_RSTWRN_OPT);
  5577.         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
  5578.         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
  5579.  
  5580.         /* Enable PG1 for cdclk */
  5581.         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
  5582.  
  5583.         /* check if cd clock is enabled */
  5584.         if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
  5585.                 DRM_DEBUG_KMS("Display already initialized\n");
  5586.                 return;
  5587.         }
  5588.  
  5589.         /*
  5590.          * FIXME:
  5591.          * - The initial CDCLK needs to be read from VBT.
  5592.          *   Need to make this change after VBT has changes for BXT.
  5593.          * - check if setting the max (or any) cdclk freq is really necessary
  5594.          *   here, it belongs to modeset time
  5595.          */
  5596.         broxton_set_cdclk(dev, 624000);
  5597.  
  5598.         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
  5599.         POSTING_READ(DBUF_CTL);
  5600.  
  5601.         udelay(10);
  5602.  
  5603.         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
  5604.                 DRM_ERROR("DBuf power enable timeout!\n");
  5605. }
  5606.  
  5607. void broxton_uninit_cdclk(struct drm_device *dev)
  5608. {
  5609.         struct drm_i915_private *dev_priv = dev->dev_private;
  5610.  
  5611.         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
  5612.         POSTING_READ(DBUF_CTL);
  5613.  
  5614.         udelay(10);
  5615.  
  5616.         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
  5617.                 DRM_ERROR("DBuf power disable timeout!\n");
  5618.  
  5619.         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
  5620.         broxton_set_cdclk(dev, 19200);
  5621.  
  5622.         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
  5623. }
  5624.  
  5625. static const struct skl_cdclk_entry {
  5626.         unsigned int freq;
  5627.         unsigned int vco;
  5628. } skl_cdclk_frequencies[] = {
  5629.         { .freq = 308570, .vco = 8640 },
  5630.         { .freq = 337500, .vco = 8100 },
  5631.         { .freq = 432000, .vco = 8640 },
  5632.         { .freq = 450000, .vco = 8100 },
  5633.         { .freq = 540000, .vco = 8100 },
  5634.         { .freq = 617140, .vco = 8640 },
  5635.         { .freq = 675000, .vco = 8100 },
  5636. };
  5637.  
  5638. static unsigned int skl_cdclk_decimal(unsigned int freq)
  5639. {
  5640.         return (freq - 1000) / 500;
  5641. }
  5642.  
  5643. static unsigned int skl_cdclk_get_vco(unsigned int freq)
  5644. {
  5645.         unsigned int i;
  5646.  
  5647.         for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
  5648.                 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
  5649.  
  5650.                 if (e->freq == freq)
  5651.                         return e->vco;
  5652.         }
  5653.  
  5654.         return 8100;
  5655. }
  5656.  
  5657. static void
  5658. skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
  5659. {
  5660.         unsigned int min_freq;
  5661.         u32 val;
  5662.  
  5663.         /* select the minimum CDCLK before enabling DPLL 0 */
  5664.         val = I915_READ(CDCLK_CTL);
  5665.         val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
  5666.         val |= CDCLK_FREQ_337_308;
  5667.  
  5668.         if (required_vco == 8640)
  5669.                 min_freq = 308570;
  5670.         else
  5671.                 min_freq = 337500;
  5672.  
  5673.         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
  5674.  
  5675.         I915_WRITE(CDCLK_CTL, val);
  5676.         POSTING_READ(CDCLK_CTL);
  5677.  
  5678.         /*
  5679.          * We always enable DPLL0 with the lowest link rate possible, but still
  5680.          * taking into account the VCO required to operate the eDP panel at the
  5681.          * desired frequency. The usual DP link rates operate with a VCO of
  5682.          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
  5683.          * The modeset code is responsible for the selection of the exact link
  5684.          * rate later on, with the constraint of choosing a frequency that
  5685.          * works with required_vco.
  5686.          */
  5687.         val = I915_READ(DPLL_CTRL1);
  5688.  
  5689.         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
  5690.                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
  5691.         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
  5692.         if (required_vco == 8640)
  5693.                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
  5694.                                             SKL_DPLL0);
  5695.         else
  5696.                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
  5697.                                             SKL_DPLL0);
  5698.  
  5699.         I915_WRITE(DPLL_CTRL1, val);
  5700.         POSTING_READ(DPLL_CTRL1);
  5701.  
  5702.         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
  5703.  
  5704.         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
  5705.                 DRM_ERROR("DPLL0 not locked\n");
  5706. }
  5707.  
  5708. static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
  5709. {
  5710.         int ret;
  5711.         u32 val;
  5712.  
  5713.         /* inform PCU we want to change CDCLK */
  5714.         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
  5715.         mutex_lock(&dev_priv->rps.hw_lock);
  5716.         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
  5717.         mutex_unlock(&dev_priv->rps.hw_lock);
  5718.  
  5719.         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
  5720. }
  5721.  
  5722. static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
  5723. {
  5724.         unsigned int i;
  5725.  
  5726.         for (i = 0; i < 15; i++) {
  5727.                 if (skl_cdclk_pcu_ready(dev_priv))
  5728.                         return true;
  5729.                 udelay(10);
  5730.         }
  5731.  
  5732.         return false;
  5733. }
  5734.  
  5735. static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
  5736. {
  5737.         struct drm_device *dev = dev_priv->dev;
  5738.         u32 freq_select, pcu_ack;
  5739.  
  5740.         DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
  5741.  
  5742.         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
  5743.                 DRM_ERROR("failed to inform PCU about cdclk change\n");
  5744.                 return;
  5745.         }
  5746.  
  5747.         /* set CDCLK_CTL */
  5748.         switch(freq) {
  5749.         case 450000:
  5750.         case 432000:
  5751.                 freq_select = CDCLK_FREQ_450_432;
  5752.                 pcu_ack = 1;
  5753.                 break;
  5754.         case 540000:
  5755.                 freq_select = CDCLK_FREQ_540;
  5756.                 pcu_ack = 2;
  5757.                 break;
  5758.         case 308570:
  5759.         case 337500:
  5760.         default:
  5761.                 freq_select = CDCLK_FREQ_337_308;
  5762.                 pcu_ack = 0;
  5763.                 break;
  5764.         case 617140:
  5765.         case 675000:
  5766.                 freq_select = CDCLK_FREQ_675_617;
  5767.                 pcu_ack = 3;
  5768.                 break;
  5769.         }
  5770.  
  5771.         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
  5772.         POSTING_READ(CDCLK_CTL);
  5773.  
  5774.         /* inform PCU of the change */
  5775.         mutex_lock(&dev_priv->rps.hw_lock);
  5776.         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
  5777.         mutex_unlock(&dev_priv->rps.hw_lock);
  5778.  
  5779.         intel_update_cdclk(dev);
  5780. }
  5781.  
  5782. void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
  5783. {
  5784.         /* disable DBUF power */
  5785.         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
  5786.         POSTING_READ(DBUF_CTL);
  5787.  
  5788.         udelay(10);
  5789.  
  5790.         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
  5791.                 DRM_ERROR("DBuf power disable timeout\n");
  5792.  
  5793.         /*
  5794.          * DMC assumes ownership of LCPLL and will get confused if we touch it.
  5795.          */
  5796.         if (dev_priv->csr.dmc_payload) {
  5797.                 /* disable DPLL0 */
  5798.                 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
  5799.                                         ~LCPLL_PLL_ENABLE);
  5800.                 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
  5801.                         DRM_ERROR("Couldn't disable DPLL0\n");
  5802.         }
  5803.  
  5804.         intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
  5805. }
  5806.  
  5807. void skl_init_cdclk(struct drm_i915_private *dev_priv)
  5808. {
  5809.         u32 val;
  5810.         unsigned int required_vco;
  5811.  
  5812.         /* enable PCH reset handshake */
  5813.         val = I915_READ(HSW_NDE_RSTWRN_OPT);
  5814.         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
  5815.  
  5816.         /* enable PG1 and Misc I/O */
  5817.         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
  5818.  
  5819.         /* DPLL0 not enabled (happens on early BIOS versions) */
  5820.         if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
  5821.                 /* enable DPLL0 */
  5822.                 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
  5823.                 skl_dpll0_enable(dev_priv, required_vco);
  5824.         }
  5825.  
  5826.         /* set CDCLK to the frequency the BIOS chose */
  5827.         skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
  5828.  
  5829.         /* enable DBUF power */
  5830.         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
  5831.         POSTING_READ(DBUF_CTL);
  5832.  
  5833.         udelay(10);
  5834.  
  5835.         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
  5836.                 DRM_ERROR("DBuf power enable timeout\n");
  5837. }
  5838.  
  5839. /* Adjust CDclk dividers to allow high res or save power if possible */
  5840. static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
  5841. {
  5842.         struct drm_i915_private *dev_priv = dev->dev_private;
  5843.         u32 val, cmd;
  5844.  
  5845.         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
  5846.                                         != dev_priv->cdclk_freq);
  5847.  
  5848.         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
  5849.                 cmd = 2;
  5850.         else if (cdclk == 266667)
  5851.                 cmd = 1;
  5852.         else
  5853.                 cmd = 0;
  5854.  
  5855.         mutex_lock(&dev_priv->rps.hw_lock);
  5856.         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
  5857.         val &= ~DSPFREQGUAR_MASK;
  5858.         val |= (cmd << DSPFREQGUAR_SHIFT);
  5859.         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
  5860.         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
  5861.                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
  5862.                      50)) {
  5863.                 DRM_ERROR("timed out waiting for CDclk change\n");
  5864.         }
  5865.         mutex_unlock(&dev_priv->rps.hw_lock);
  5866.  
  5867.         mutex_lock(&dev_priv->sb_lock);
  5868.  
  5869.         if (cdclk == 400000) {
  5870.                 u32 divider;
  5871.  
  5872.                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
  5873.  
  5874.                 /* adjust cdclk divider */
  5875.                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
  5876.                 val &= ~CCK_FREQUENCY_VALUES;
  5877.                 val |= divider;
  5878.                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
  5879.  
  5880.                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
  5881.                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
  5882.                              50))
  5883.                         DRM_ERROR("timed out waiting for CDclk change\n");
  5884.         }
  5885.  
  5886.         /* adjust self-refresh exit latency value */
  5887.         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
  5888.         val &= ~0x7f;
  5889.  
  5890.         /*
  5891.          * For high bandwidth configs, we set a higher latency in the bunit
  5892.          * so that the core display fetch happens in time to avoid underruns.
  5893.          */
  5894.         if (cdclk == 400000)
  5895.                 val |= 4500 / 250; /* 4.5 usec */
  5896.         else
  5897.                 val |= 3000 / 250; /* 3.0 usec */
  5898.         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
  5899.  
  5900.         mutex_unlock(&dev_priv->sb_lock);
  5901.  
  5902.         intel_update_cdclk(dev);
  5903. }
  5904.  
  5905. static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
  5906. {
  5907.         struct drm_i915_private *dev_priv = dev->dev_private;
  5908.         u32 val, cmd;
  5909.  
  5910.         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
  5911.                                                 != dev_priv->cdclk_freq);
  5912.  
  5913.         switch (cdclk) {
  5914.         case 333333:
  5915.         case 320000:
  5916.         case 266667:
  5917.         case 200000:
  5918.                 break;
  5919.         default:
  5920.                 MISSING_CASE(cdclk);
  5921.                 return;
  5922.         }
  5923.  
  5924.         /*
  5925.          * Specs are full of misinformation, but testing on actual
  5926.          * hardware has shown that we just need to write the desired
  5927.          * CCK divider into the Punit register.
  5928.          */
  5929.         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
  5930.  
  5931.         mutex_lock(&dev_priv->rps.hw_lock);
  5932.         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
  5933.         val &= ~DSPFREQGUAR_MASK_CHV;
  5934.         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
  5935.         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
  5936.         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
  5937.                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
  5938.                      50)) {
  5939.                 DRM_ERROR("timed out waiting for CDclk change\n");
  5940.         }
  5941.         mutex_unlock(&dev_priv->rps.hw_lock);
  5942.  
  5943.         intel_update_cdclk(dev);
  5944. }
  5945.  
  5946. static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
  5947.                                  int max_pixclk)
  5948. {
  5949.         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
  5950.         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
  5951.  
  5952.         /*
  5953.          * Really only a few cases to deal with, as only 4 CDclks are supported:
  5954.          *   200MHz
  5955.          *   267MHz
  5956.          *   320/333MHz (depends on HPLL freq)
  5957.          *   400MHz (VLV only)
  5958.          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
  5959.          * of the lower bin and adjust if needed.
  5960.          *
  5961.          * We seem to get an unstable or solid color picture at 200MHz.
  5962.          * Not sure what's wrong. For now use 200MHz only when all pipes
  5963.          * are off.
  5964.          */
  5965.         if (!IS_CHERRYVIEW(dev_priv) &&
  5966.             max_pixclk > freq_320*limit/100)
  5967.                 return 400000;
  5968.         else if (max_pixclk > 266667*limit/100)
  5969.                 return freq_320;
  5970.         else if (max_pixclk > 0)
  5971.                 return 266667;
  5972.         else
  5973.                 return 200000;
  5974. }
  5975.  
  5976. static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
  5977.                               int max_pixclk)
  5978. {
  5979.         /*
  5980.          * FIXME:
  5981.          * - remove the guardband, it's not needed on BXT
  5982.          * - set 19.2MHz bypass frequency if there are no active pipes
  5983.          */
  5984.         if (max_pixclk > 576000*9/10)
  5985.                 return 624000;
  5986.         else if (max_pixclk > 384000*9/10)
  5987.                 return 576000;
  5988.         else if (max_pixclk > 288000*9/10)
  5989.                 return 384000;
  5990.         else if (max_pixclk > 144000*9/10)
  5991.                 return 288000;
  5992.         else
  5993.                 return 144000;
  5994. }
  5995.  
  5996. /* Compute the max pixel clock for new configuration. Uses atomic state if
  5997.  * that's non-NULL, look at current state otherwise. */
  5998. static int intel_mode_max_pixclk(struct drm_device *dev,
  5999.                                  struct drm_atomic_state *state)
  6000. {
  6001.         struct intel_crtc *intel_crtc;
  6002.         struct intel_crtc_state *crtc_state;
  6003.         int max_pixclk = 0;
  6004.  
  6005.         for_each_intel_crtc(dev, intel_crtc) {
  6006.                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
  6007.                 if (IS_ERR(crtc_state))
  6008.                         return PTR_ERR(crtc_state);
  6009.  
  6010.                 if (!crtc_state->base.enable)
  6011.                         continue;
  6012.  
  6013.                 max_pixclk = max(max_pixclk,
  6014.                                  crtc_state->base.adjusted_mode.crtc_clock);
  6015.         }
  6016.  
  6017.         return max_pixclk;
  6018. }
  6019.  
  6020. static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
  6021. {
  6022.         struct drm_device *dev = state->dev;
  6023.         struct drm_i915_private *dev_priv = dev->dev_private;
  6024.         int max_pixclk = intel_mode_max_pixclk(dev, state);
  6025.  
  6026.         if (max_pixclk < 0)
  6027.                 return max_pixclk;
  6028.  
  6029.         to_intel_atomic_state(state)->cdclk =
  6030.                 valleyview_calc_cdclk(dev_priv, max_pixclk);
  6031.  
  6032.         return 0;
  6033. }
  6034.  
  6035. static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
  6036. {
  6037.         struct drm_device *dev = state->dev;
  6038.         struct drm_i915_private *dev_priv = dev->dev_private;
  6039.         int max_pixclk = intel_mode_max_pixclk(dev, state);
  6040.  
  6041.         if (max_pixclk < 0)
  6042.                 return max_pixclk;
  6043.  
  6044.         to_intel_atomic_state(state)->cdclk =
  6045.                 broxton_calc_cdclk(dev_priv, max_pixclk);
  6046.  
  6047.         return 0;
  6048. }
  6049.  
  6050. static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
  6051. {
  6052.         unsigned int credits, default_credits;
  6053.  
  6054.         if (IS_CHERRYVIEW(dev_priv))
  6055.                 default_credits = PFI_CREDIT(12);
  6056.         else
  6057.                 default_credits = PFI_CREDIT(8);
  6058.  
  6059.         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
  6060.                 /* CHV suggested value is 31 or 63 */
  6061.                 if (IS_CHERRYVIEW(dev_priv))
  6062.                         credits = PFI_CREDIT_63;
  6063.                 else
  6064.                         credits = PFI_CREDIT(15);
  6065.         } else {
  6066.                 credits = default_credits;
  6067.         }
  6068.  
  6069.         /*
  6070.          * WA - write default credits before re-programming
  6071.          * FIXME: should we also set the resend bit here?
  6072.          */
  6073.         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
  6074.                    default_credits);
  6075.  
  6076.         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
  6077.                    credits | PFI_CREDIT_RESEND);
  6078.  
  6079.         /*
  6080.          * FIXME is this guaranteed to clear
  6081.          * immediately or should we poll for it?
  6082.          */
  6083.         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
  6084. }
  6085.  
  6086. static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
  6087. {
  6088.         struct drm_device *dev = old_state->dev;
  6089.         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
  6090.         struct drm_i915_private *dev_priv = dev->dev_private;
  6091.  
  6092.         /*
  6093.          * FIXME: We can end up here with all power domains off, yet
  6094.          * with a CDCLK frequency other than the minimum. To account
  6095.          * for this take the PIPE-A power domain, which covers the HW
  6096.          * blocks needed for the following programming. This can be
  6097.          * removed once it's guaranteed that we get here either with
  6098.          * the minimum CDCLK set, or the required power domains
  6099.          * enabled.
  6100.          */
  6101.         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
  6102.  
  6103.         if (IS_CHERRYVIEW(dev))
  6104.                 cherryview_set_cdclk(dev, req_cdclk);
  6105.         else
  6106.                 valleyview_set_cdclk(dev, req_cdclk);
  6107.  
  6108.         vlv_program_pfi_credits(dev_priv);
  6109.  
  6110.         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
  6111. }
  6112.  
  6113. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  6114. {
  6115.         struct drm_device *dev = crtc->dev;
  6116.         struct drm_i915_private *dev_priv = to_i915(dev);
  6117.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6118.         struct intel_encoder *encoder;
  6119.         int pipe = intel_crtc->pipe;
  6120.         bool is_dsi;
  6121.  
  6122.         if (WARN_ON(intel_crtc->active))
  6123.                 return;
  6124.  
  6125.         is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
  6126.  
  6127.         if (intel_crtc->config->has_dp_encoder)
  6128.                 intel_dp_set_m_n(intel_crtc, M1_N1);
  6129.  
  6130.         intel_set_pipe_timings(intel_crtc);
  6131.  
  6132.         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
  6133.                 struct drm_i915_private *dev_priv = dev->dev_private;
  6134.  
  6135.                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
  6136.                 I915_WRITE(CHV_CANVAS(pipe), 0);
  6137.         }
  6138.  
  6139.         i9xx_set_pipeconf(intel_crtc);
  6140.  
  6141.         intel_crtc->active = true;
  6142.  
  6143.         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  6144.  
  6145.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6146.                 if (encoder->pre_pll_enable)
  6147.                         encoder->pre_pll_enable(encoder);
  6148.  
  6149.         if (!is_dsi) {
  6150.                 if (IS_CHERRYVIEW(dev)) {
  6151.                         chv_prepare_pll(intel_crtc, intel_crtc->config);
  6152.                         chv_enable_pll(intel_crtc, intel_crtc->config);
  6153.                 } else {
  6154.                         vlv_prepare_pll(intel_crtc, intel_crtc->config);
  6155.                         vlv_enable_pll(intel_crtc, intel_crtc->config);
  6156.                 }
  6157.         }
  6158.  
  6159.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6160.                 if (encoder->pre_enable)
  6161.                         encoder->pre_enable(encoder);
  6162.  
  6163.         i9xx_pfit_enable(intel_crtc);
  6164.  
  6165.         intel_crtc_load_lut(crtc);
  6166.  
  6167.         intel_enable_pipe(intel_crtc);
  6168.  
  6169.         assert_vblank_disabled(crtc);
  6170.         drm_crtc_vblank_on(crtc);
  6171.  
  6172.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6173.                 encoder->enable(encoder);
  6174. }
  6175.  
  6176. static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
  6177. {
  6178.         struct drm_device *dev = crtc->base.dev;
  6179.         struct drm_i915_private *dev_priv = dev->dev_private;
  6180.  
  6181.         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
  6182.         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
  6183. }
  6184.  
  6185. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  6186. {
  6187.         struct drm_device *dev = crtc->dev;
  6188.         struct drm_i915_private *dev_priv = to_i915(dev);
  6189.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6190.         struct intel_encoder *encoder;
  6191.         int pipe = intel_crtc->pipe;
  6192.  
  6193.         if (WARN_ON(intel_crtc->active))
  6194.                 return;
  6195.  
  6196.         i9xx_set_pll_dividers(intel_crtc);
  6197.  
  6198.         if (intel_crtc->config->has_dp_encoder)
  6199.                 intel_dp_set_m_n(intel_crtc, M1_N1);
  6200.  
  6201.         intel_set_pipe_timings(intel_crtc);
  6202.  
  6203.         i9xx_set_pipeconf(intel_crtc);
  6204.  
  6205.         intel_crtc->active = true;
  6206.  
  6207.         if (!IS_GEN2(dev))
  6208.                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
  6209.  
  6210.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6211.                 if (encoder->pre_enable)
  6212.                         encoder->pre_enable(encoder);
  6213.  
  6214.         i9xx_enable_pll(intel_crtc);
  6215.  
  6216.         i9xx_pfit_enable(intel_crtc);
  6217.  
  6218.         intel_crtc_load_lut(crtc);
  6219.  
  6220.         intel_update_watermarks(crtc);
  6221.         intel_enable_pipe(intel_crtc);
  6222.  
  6223.         assert_vblank_disabled(crtc);
  6224.         drm_crtc_vblank_on(crtc);
  6225.  
  6226.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6227.                 encoder->enable(encoder);
  6228. }
  6229.  
  6230. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  6231. {
  6232.         struct drm_device *dev = crtc->base.dev;
  6233.         struct drm_i915_private *dev_priv = dev->dev_private;
  6234.  
  6235.         if (!crtc->config->gmch_pfit.control)
  6236.                 return;
  6237.  
  6238.         assert_pipe_disabled(dev_priv, crtc->pipe);
  6239.  
  6240.         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  6241.                          I915_READ(PFIT_CONTROL));
  6242.         I915_WRITE(PFIT_CONTROL, 0);
  6243. }
  6244.  
  6245. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  6246. {
  6247.         struct drm_device *dev = crtc->dev;
  6248.         struct drm_i915_private *dev_priv = dev->dev_private;
  6249.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6250.         struct intel_encoder *encoder;
  6251.         int pipe = intel_crtc->pipe;
  6252.  
  6253.         /*
  6254.          * On gen2 planes are double buffered but the pipe isn't, so we must
  6255.          * wait for planes to fully turn off before disabling the pipe.
  6256.          * We also need to wait on all gmch platforms because of the
  6257.          * self-refresh mode constraint explained above.
  6258.          */
  6259.         intel_wait_for_vblank(dev, pipe);
  6260.  
  6261.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6262.                 encoder->disable(encoder);
  6263.  
  6264.         drm_crtc_vblank_off(crtc);
  6265.         assert_vblank_disabled(crtc);
  6266.  
  6267.         intel_disable_pipe(intel_crtc);
  6268.  
  6269.         i9xx_pfit_disable(intel_crtc);
  6270.  
  6271.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6272.                 if (encoder->post_disable)
  6273.                         encoder->post_disable(encoder);
  6274.  
  6275.         if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
  6276.                 if (IS_CHERRYVIEW(dev))
  6277.                         chv_disable_pll(dev_priv, pipe);
  6278.                 else if (IS_VALLEYVIEW(dev))
  6279.                         vlv_disable_pll(dev_priv, pipe);
  6280.                 else
  6281.                         i9xx_disable_pll(intel_crtc);
  6282.         }
  6283.  
  6284.         for_each_encoder_on_crtc(dev, crtc, encoder)
  6285.                 if (encoder->post_pll_disable)
  6286.                         encoder->post_pll_disable(encoder);
  6287.  
  6288.         if (!IS_GEN2(dev))
  6289.                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
  6290. }
  6291.  
  6292. static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
  6293. {
  6294.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6295.         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
  6296.         enum intel_display_power_domain domain;
  6297.         unsigned long domains;
  6298.  
  6299.         if (!intel_crtc->active)
  6300.                 return;
  6301.  
  6302.         if (to_intel_plane_state(crtc->primary->state)->visible) {
  6303.                 intel_pre_disable_primary(crtc);
  6304.  
  6305.                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
  6306.                 to_intel_plane_state(crtc->primary->state)->visible = false;
  6307.         }
  6308.  
  6309.         dev_priv->display.crtc_disable(crtc);
  6310.         intel_crtc->active = false;
  6311.         intel_update_watermarks(crtc);
  6312.         intel_disable_shared_dpll(intel_crtc);
  6313.  
  6314.         domains = intel_crtc->enabled_power_domains;
  6315.         for_each_power_domain(domain, domains)
  6316.                 intel_display_power_put(dev_priv, domain);
  6317.         intel_crtc->enabled_power_domains = 0;
  6318. }
  6319.  
  6320. /*
  6321.  * turn all crtc's off, but do not adjust state
  6322.  * This has to be paired with a call to intel_modeset_setup_hw_state.
  6323.  */
  6324. int intel_display_suspend(struct drm_device *dev)
  6325. {
  6326.         struct drm_mode_config *config = &dev->mode_config;
  6327.         struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
  6328.         struct drm_atomic_state *state;
  6329.         struct drm_crtc *crtc;
  6330.         unsigned crtc_mask = 0;
  6331.         int ret = 0;
  6332.  
  6333.         if (WARN_ON(!ctx))
  6334.                 return 0;
  6335.  
  6336.         lockdep_assert_held(&ctx->ww_ctx);
  6337.         state = drm_atomic_state_alloc(dev);
  6338.         if (WARN_ON(!state))
  6339.                 return -ENOMEM;
  6340.  
  6341.         state->acquire_ctx = ctx;
  6342.         state->allow_modeset = true;
  6343.  
  6344.         for_each_crtc(dev, crtc) {
  6345.                 struct drm_crtc_state *crtc_state =
  6346.                         drm_atomic_get_crtc_state(state, crtc);
  6347.  
  6348.                 ret = PTR_ERR_OR_ZERO(crtc_state);
  6349.                 if (ret)
  6350.                         goto free;
  6351.  
  6352.                 if (!crtc_state->active)
  6353.                         continue;
  6354.  
  6355.                 crtc_state->active = false;
  6356.                 crtc_mask |= 1 << drm_crtc_index(crtc);
  6357.         }
  6358.  
  6359.         if (crtc_mask) {
  6360.                 ret = drm_atomic_commit(state);
  6361.  
  6362.                 if (!ret) {
  6363.                         for_each_crtc(dev, crtc)
  6364.                                 if (crtc_mask & (1 << drm_crtc_index(crtc)))
  6365.                                         crtc->state->active = true;
  6366.  
  6367.                         return ret;
  6368.                 }
  6369.         }
  6370.  
  6371. free:
  6372.         if (ret)
  6373.                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
  6374.         drm_atomic_state_free(state);
  6375.         return ret;
  6376. }
  6377.  
  6378. void intel_encoder_destroy(struct drm_encoder *encoder)
  6379. {
  6380.         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  6381.  
  6382.         drm_encoder_cleanup(encoder);
  6383.         kfree(intel_encoder);
  6384. }
  6385.  
  6386. /* Cross check the actual hw state with our own modeset state tracking (and it's
  6387.  * internal consistency). */
  6388. static void intel_connector_check_state(struct intel_connector *connector)
  6389. {
  6390.         struct drm_crtc *crtc = connector->base.state->crtc;
  6391.  
  6392.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  6393.                       connector->base.base.id,
  6394.                       connector->base.name);
  6395.  
  6396.         if (connector->get_hw_state(connector)) {
  6397.                 struct intel_encoder *encoder = connector->encoder;
  6398.                 struct drm_connector_state *conn_state = connector->base.state;
  6399.  
  6400.                 I915_STATE_WARN(!crtc,
  6401.                          "connector enabled without attached crtc\n");
  6402.  
  6403.                 if (!crtc)
  6404.                         return;
  6405.  
  6406.                 I915_STATE_WARN(!crtc->state->active,
  6407.                       "connector is active, but attached crtc isn't\n");
  6408.  
  6409.                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
  6410.                         return;
  6411.  
  6412.                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
  6413.                         "atomic encoder doesn't match attached encoder\n");
  6414.  
  6415.                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
  6416.                         "attached encoder crtc differs from connector crtc\n");
  6417.         } else {
  6418.                 I915_STATE_WARN(crtc && crtc->state->active,
  6419.                         "attached crtc is active, but connector isn't\n");
  6420.                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
  6421.                         "best encoder set without crtc!\n");
  6422.         }
  6423. }
  6424.  
  6425. int intel_connector_init(struct intel_connector *connector)
  6426. {
  6427.         struct drm_connector_state *connector_state;
  6428.  
  6429.         connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
  6430.         if (!connector_state)
  6431.                 return -ENOMEM;
  6432.  
  6433.         connector->base.state = connector_state;
  6434.         return 0;
  6435. }
  6436.  
  6437. struct intel_connector *intel_connector_alloc(void)
  6438. {
  6439.         struct intel_connector *connector;
  6440.  
  6441.         connector = kzalloc(sizeof *connector, GFP_KERNEL);
  6442.         if (!connector)
  6443.                 return NULL;
  6444.  
  6445.         if (intel_connector_init(connector) < 0) {
  6446.                 kfree(connector);
  6447.                 return NULL;
  6448.         }
  6449.  
  6450.         return connector;
  6451. }
  6452.  
  6453. /* Simple connector->get_hw_state implementation for encoders that support only
  6454.  * one connector and no cloning and hence the encoder state determines the state
  6455.  * of the connector. */
  6456. bool intel_connector_get_hw_state(struct intel_connector *connector)
  6457. {
  6458.         enum pipe pipe = 0;
  6459.         struct intel_encoder *encoder = connector->encoder;
  6460.  
  6461.         return encoder->get_hw_state(encoder, &pipe);
  6462. }
  6463.  
  6464. static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
  6465. {
  6466.         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
  6467.                 return crtc_state->fdi_lanes;
  6468.  
  6469.         return 0;
  6470. }
  6471.  
  6472. static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  6473.                                      struct intel_crtc_state *pipe_config)
  6474. {
  6475.         struct drm_atomic_state *state = pipe_config->base.state;
  6476.         struct intel_crtc *other_crtc;
  6477.         struct intel_crtc_state *other_crtc_state;
  6478.  
  6479.         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  6480.                       pipe_name(pipe), pipe_config->fdi_lanes);
  6481.         if (pipe_config->fdi_lanes > 4) {
  6482.                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  6483.                               pipe_name(pipe), pipe_config->fdi_lanes);
  6484.                 return -EINVAL;
  6485.         }
  6486.  
  6487.         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  6488.                 if (pipe_config->fdi_lanes > 2) {
  6489.                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  6490.                                       pipe_config->fdi_lanes);
  6491.                         return -EINVAL;
  6492.                 } else {
  6493.                         return 0;
  6494.                 }
  6495.         }
  6496.  
  6497.         if (INTEL_INFO(dev)->num_pipes == 2)
  6498.                 return 0;
  6499.  
  6500.         /* Ivybridge 3 pipe is really complicated */
  6501.         switch (pipe) {
  6502.         case PIPE_A:
  6503.                 return 0;
  6504.         case PIPE_B:
  6505.                 if (pipe_config->fdi_lanes <= 2)
  6506.                         return 0;
  6507.  
  6508.                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
  6509.                 other_crtc_state =
  6510.                         intel_atomic_get_crtc_state(state, other_crtc);
  6511.                 if (IS_ERR(other_crtc_state))
  6512.                         return PTR_ERR(other_crtc_state);
  6513.  
  6514.                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
  6515.                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  6516.                                       pipe_name(pipe), pipe_config->fdi_lanes);
  6517.                         return -EINVAL;
  6518.                 }
  6519.                 return 0;
  6520.         case PIPE_C:
  6521.                 if (pipe_config->fdi_lanes > 2) {
  6522.                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
  6523.                                       pipe_name(pipe), pipe_config->fdi_lanes);
  6524.                         return -EINVAL;
  6525.                 }
  6526.  
  6527.                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
  6528.                 other_crtc_state =
  6529.                         intel_atomic_get_crtc_state(state, other_crtc);
  6530.                 if (IS_ERR(other_crtc_state))
  6531.                         return PTR_ERR(other_crtc_state);
  6532.  
  6533.                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
  6534.                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  6535.                         return -EINVAL;
  6536.                 }
  6537.                 return 0;
  6538.         default:
  6539.                 BUG();
  6540.         }
  6541. }
  6542.  
  6543. #define RETRY 1
  6544. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  6545.                                        struct intel_crtc_state *pipe_config)
  6546. {
  6547.         struct drm_device *dev = intel_crtc->base.dev;
  6548.         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  6549.         int lane, link_bw, fdi_dotclock, ret;
  6550.         bool needs_recompute = false;
  6551.  
  6552. retry:
  6553.         /* FDI is a binary signal running at ~2.7GHz, encoding
  6554.          * each output octet as 10 bits. The actual frequency
  6555.          * is stored as a divider into a 100MHz clock, and the
  6556.          * mode pixel clock is stored in units of 1KHz.
  6557.          * Hence the bw of each lane in terms of the mode signal
  6558.          * is:
  6559.          */
  6560.         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  6561.  
  6562.         fdi_dotclock = adjusted_mode->crtc_clock;
  6563.  
  6564.         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  6565.                                            pipe_config->pipe_bpp);
  6566.  
  6567.         pipe_config->fdi_lanes = lane;
  6568.  
  6569.         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  6570.                                link_bw, &pipe_config->fdi_m_n);
  6571.  
  6572.         ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
  6573.                                        intel_crtc->pipe, pipe_config);
  6574.         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
  6575.                 pipe_config->pipe_bpp -= 2*3;
  6576.                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  6577.                               pipe_config->pipe_bpp);
  6578.                 needs_recompute = true;
  6579.                 pipe_config->bw_constrained = true;
  6580.  
  6581.                 goto retry;
  6582.         }
  6583.  
  6584.         if (needs_recompute)
  6585.                 return RETRY;
  6586.  
  6587.         return ret;
  6588. }
  6589.  
  6590. static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
  6591.                                      struct intel_crtc_state *pipe_config)
  6592. {
  6593.         if (pipe_config->pipe_bpp > 24)
  6594.                 return false;
  6595.  
  6596.         /* HSW can handle pixel rate up to cdclk? */
  6597.         if (IS_HASWELL(dev_priv->dev))
  6598.                 return true;
  6599.  
  6600.         /*
  6601.          * We compare against max which means we must take
  6602.          * the increased cdclk requirement into account when
  6603.          * calculating the new cdclk.
  6604.          *
  6605.          * Should measure whether using a lower cdclk w/o IPS
  6606.          */
  6607.         return ilk_pipe_pixel_rate(pipe_config) <=
  6608.                 dev_priv->max_cdclk_freq * 95 / 100;
  6609. }
  6610.  
  6611. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  6612.                                    struct intel_crtc_state *pipe_config)
  6613. {
  6614.         struct drm_device *dev = crtc->base.dev;
  6615.         struct drm_i915_private *dev_priv = dev->dev_private;
  6616.  
  6617.         pipe_config->ips_enabled = i915.enable_ips &&
  6618.                 hsw_crtc_supports_ips(crtc) &&
  6619.                 pipe_config_supports_ips(dev_priv, pipe_config);
  6620. }
  6621.  
  6622. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  6623.                                      struct intel_crtc_state *pipe_config)
  6624. {
  6625.         struct drm_device *dev = crtc->base.dev;
  6626.         struct drm_i915_private *dev_priv = dev->dev_private;
  6627.         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
  6628.  
  6629.         /* FIXME should check pixel clock limits on all platforms */
  6630.         if (INTEL_INFO(dev)->gen < 4) {
  6631.                 int clock_limit = dev_priv->max_cdclk_freq;
  6632.  
  6633.                 /*
  6634.                  * Enable pixel doubling when the dot clock
  6635.                  * is > 90% of the (display) core speed.
  6636.                  *
  6637.                  * GDG double wide on either pipe,
  6638.                  * otherwise pipe A only.
  6639.                  */
  6640.                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
  6641.                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
  6642.                         clock_limit *= 2;
  6643.                         pipe_config->double_wide = true;
  6644.                 }
  6645.  
  6646.                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
  6647.                         return -EINVAL;
  6648.         }
  6649.  
  6650.         /*
  6651.          * Pipe horizontal size must be even in:
  6652.          * - DVO ganged mode
  6653.          * - LVDS dual channel mode
  6654.          * - Double wide pipe
  6655.          */
  6656.         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
  6657.              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
  6658.                 pipe_config->pipe_src_w &= ~1;
  6659.  
  6660.         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  6661.          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  6662.          */
  6663.         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  6664.                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
  6665.                 return -EINVAL;
  6666.  
  6667.         if (HAS_IPS(dev))
  6668.                 hsw_compute_ips_config(crtc, pipe_config);
  6669.  
  6670.         if (pipe_config->has_pch_encoder)
  6671.                 return ironlake_fdi_compute_config(crtc, pipe_config);
  6672.  
  6673.         return 0;
  6674. }
  6675.  
  6676. static int skylake_get_display_clock_speed(struct drm_device *dev)
  6677. {
  6678.         struct drm_i915_private *dev_priv = to_i915(dev);
  6679.         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
  6680.         uint32_t cdctl = I915_READ(CDCLK_CTL);
  6681.         uint32_t linkrate;
  6682.  
  6683.         if (!(lcpll1 & LCPLL_PLL_ENABLE))
  6684.                 return 24000; /* 24MHz is the cd freq with NSSC ref */
  6685.  
  6686.         if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
  6687.                 return 540000;
  6688.  
  6689.         linkrate = (I915_READ(DPLL_CTRL1) &
  6690.                     DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
  6691.  
  6692.         if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
  6693.             linkrate == DPLL_CTRL1_LINK_RATE_1080) {
  6694.                 /* vco 8640 */
  6695.                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
  6696.                 case CDCLK_FREQ_450_432:
  6697.                         return 432000;
  6698.                 case CDCLK_FREQ_337_308:
  6699.                         return 308570;
  6700.                 case CDCLK_FREQ_675_617:
  6701.                         return 617140;
  6702.                 default:
  6703.                         WARN(1, "Unknown cd freq selection\n");
  6704.                 }
  6705.         } else {
  6706.                 /* vco 8100 */
  6707.                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
  6708.                 case CDCLK_FREQ_450_432:
  6709.                         return 450000;
  6710.                 case CDCLK_FREQ_337_308:
  6711.                         return 337500;
  6712.                 case CDCLK_FREQ_675_617:
  6713.                         return 675000;
  6714.                 default:
  6715.                         WARN(1, "Unknown cd freq selection\n");
  6716.                 }
  6717.         }
  6718.  
  6719.         /* error case, do as if DPLL0 isn't enabled */
  6720.         return 24000;
  6721. }
  6722.  
  6723. static int broxton_get_display_clock_speed(struct drm_device *dev)
  6724. {
  6725.         struct drm_i915_private *dev_priv = to_i915(dev);
  6726.         uint32_t cdctl = I915_READ(CDCLK_CTL);
  6727.         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
  6728.         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
  6729.         int cdclk;
  6730.  
  6731.         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
  6732.                 return 19200;
  6733.  
  6734.         cdclk = 19200 * pll_ratio / 2;
  6735.  
  6736.         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
  6737.         case BXT_CDCLK_CD2X_DIV_SEL_1:
  6738.                 return cdclk;  /* 576MHz or 624MHz */
  6739.         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
  6740.                 return cdclk * 2 / 3; /* 384MHz */
  6741.         case BXT_CDCLK_CD2X_DIV_SEL_2:
  6742.                 return cdclk / 2; /* 288MHz */
  6743.         case BXT_CDCLK_CD2X_DIV_SEL_4:
  6744.                 return cdclk / 4; /* 144MHz */
  6745.         }
  6746.  
  6747.         /* error case, do as if DE PLL isn't enabled */
  6748.         return 19200;
  6749. }
  6750.  
  6751. static int broadwell_get_display_clock_speed(struct drm_device *dev)
  6752. {
  6753.         struct drm_i915_private *dev_priv = dev->dev_private;
  6754.         uint32_t lcpll = I915_READ(LCPLL_CTL);
  6755.         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
  6756.  
  6757.         if (lcpll & LCPLL_CD_SOURCE_FCLK)
  6758.                 return 800000;
  6759.         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
  6760.                 return 450000;
  6761.         else if (freq == LCPLL_CLK_FREQ_450)
  6762.                 return 450000;
  6763.         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
  6764.                 return 540000;
  6765.         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
  6766.                 return 337500;
  6767.         else
  6768.                 return 675000;
  6769. }
  6770.  
  6771. static int haswell_get_display_clock_speed(struct drm_device *dev)
  6772. {
  6773.         struct drm_i915_private *dev_priv = dev->dev_private;
  6774.         uint32_t lcpll = I915_READ(LCPLL_CTL);
  6775.         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
  6776.  
  6777.         if (lcpll & LCPLL_CD_SOURCE_FCLK)
  6778.                 return 800000;
  6779.         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
  6780.                 return 450000;
  6781.         else if (freq == LCPLL_CLK_FREQ_450)
  6782.                 return 450000;
  6783.         else if (IS_HSW_ULT(dev))
  6784.                 return 337500;
  6785.         else
  6786.                 return 540000;
  6787. }
  6788.  
  6789. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  6790. {
  6791.         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
  6792.                                       CCK_DISPLAY_CLOCK_CONTROL);
  6793. }
  6794.  
  6795. static int ilk_get_display_clock_speed(struct drm_device *dev)
  6796. {
  6797.         return 450000;
  6798. }
  6799.  
  6800. static int i945_get_display_clock_speed(struct drm_device *dev)
  6801. {
  6802.         return 400000;
  6803. }
  6804.  
  6805. static int i915_get_display_clock_speed(struct drm_device *dev)
  6806. {
  6807.         return 333333;
  6808. }
  6809.  
  6810. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  6811. {
  6812.         return 200000;
  6813. }
  6814.  
  6815. static int pnv_get_display_clock_speed(struct drm_device *dev)
  6816. {
  6817.         u16 gcfgc = 0;
  6818.  
  6819.         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  6820.  
  6821.         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  6822.         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  6823.                 return 266667;
  6824.         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  6825.                 return 333333;
  6826.         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  6827.                 return 444444;
  6828.         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  6829.                 return 200000;
  6830.         default:
  6831.                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  6832.         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  6833.                 return 133333;
  6834.         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  6835.                 return 166667;
  6836.         }
  6837. }
  6838.  
  6839. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  6840. {
  6841.         u16 gcfgc = 0;
  6842.  
  6843.         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  6844.  
  6845.         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  6846.                 return 133333;
  6847.         else {
  6848.                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  6849.                 case GC_DISPLAY_CLOCK_333_MHZ:
  6850.                         return 333333;
  6851.                 default:
  6852.                 case GC_DISPLAY_CLOCK_190_200_MHZ:
  6853.                         return 190000;
  6854.                 }
  6855.         }
  6856. }
  6857.  
  6858. static int i865_get_display_clock_speed(struct drm_device *dev)
  6859. {
  6860.         return 266667;
  6861. }
  6862.  
  6863. static int i85x_get_display_clock_speed(struct drm_device *dev)
  6864. {
  6865.         u16 hpllcc = 0;
  6866.  
  6867.         /*
  6868.          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  6869.          * encoding is different :(
  6870.          * FIXME is this the right way to detect 852GM/852GMV?
  6871.          */
  6872.         if (dev->pdev->revision == 0x1)
  6873.                 return 133333;
  6874.  
  6875. //   pci_bus_read_config_word(dev->pdev->bus,
  6876. //                PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
  6877.  
  6878.         /* Assume that the hardware is in the high speed state.  This
  6879.          * should be the default.
  6880.          */
  6881.         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  6882.         case GC_CLOCK_133_200:
  6883.         case GC_CLOCK_133_200_2:
  6884.         case GC_CLOCK_100_200:
  6885.                 return 200000;
  6886.         case GC_CLOCK_166_250:
  6887.                 return 250000;
  6888.         case GC_CLOCK_100_133:
  6889.                 return 133333;
  6890.         case GC_CLOCK_133_266:
  6891.         case GC_CLOCK_133_266_2:
  6892.         case GC_CLOCK_166_266:
  6893.                 return 266667;
  6894.         }
  6895.  
  6896.         /* Shouldn't happen */
  6897.         return 0;
  6898. }
  6899.  
  6900. static int i830_get_display_clock_speed(struct drm_device *dev)
  6901. {
  6902.         return 133333;
  6903. }
  6904.  
  6905. static unsigned int intel_hpll_vco(struct drm_device *dev)
  6906. {
  6907.         struct drm_i915_private *dev_priv = dev->dev_private;
  6908.         static const unsigned int blb_vco[8] = {
  6909.                 [0] = 3200000,
  6910.                 [1] = 4000000,
  6911.                 [2] = 5333333,
  6912.                 [3] = 4800000,
  6913.                 [4] = 6400000,
  6914.         };
  6915.         static const unsigned int pnv_vco[8] = {
  6916.                 [0] = 3200000,
  6917.                 [1] = 4000000,
  6918.                 [2] = 5333333,
  6919.                 [3] = 4800000,
  6920.                 [4] = 2666667,
  6921.         };
  6922.         static const unsigned int cl_vco[8] = {
  6923.                 [0] = 3200000,
  6924.                 [1] = 4000000,
  6925.                 [2] = 5333333,
  6926.                 [3] = 6400000,
  6927.                 [4] = 3333333,
  6928.                 [5] = 3566667,
  6929.                 [6] = 4266667,
  6930.         };
  6931.         static const unsigned int elk_vco[8] = {
  6932.                 [0] = 3200000,
  6933.                 [1] = 4000000,
  6934.                 [2] = 5333333,
  6935.                 [3] = 4800000,
  6936.         };
  6937.         static const unsigned int ctg_vco[8] = {
  6938.                 [0] = 3200000,
  6939.                 [1] = 4000000,
  6940.                 [2] = 5333333,
  6941.                 [3] = 6400000,
  6942.                 [4] = 2666667,
  6943.                 [5] = 4266667,
  6944.         };
  6945.         const unsigned int *vco_table;
  6946.         unsigned int vco;
  6947.         uint8_t tmp = 0;
  6948.  
  6949.         /* FIXME other chipsets? */
  6950.         if (IS_GM45(dev))
  6951.                 vco_table = ctg_vco;
  6952.         else if (IS_G4X(dev))
  6953.                 vco_table = elk_vco;
  6954.         else if (IS_CRESTLINE(dev))
  6955.                 vco_table = cl_vco;
  6956.         else if (IS_PINEVIEW(dev))
  6957.                 vco_table = pnv_vco;
  6958.         else if (IS_G33(dev))
  6959.                 vco_table = blb_vco;
  6960.         else
  6961.                 return 0;
  6962.  
  6963.         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
  6964.  
  6965.         vco = vco_table[tmp & 0x7];
  6966.         if (vco == 0)
  6967.                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
  6968.         else
  6969.                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
  6970.  
  6971.         return vco;
  6972. }
  6973.  
  6974. static int gm45_get_display_clock_speed(struct drm_device *dev)
  6975. {
  6976.         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
  6977.         uint16_t tmp = 0;
  6978.  
  6979.         pci_read_config_word(dev->pdev, GCFGC, &tmp);
  6980.  
  6981.         cdclk_sel = (tmp >> 12) & 0x1;
  6982.  
  6983.         switch (vco) {
  6984.         case 2666667:
  6985.         case 4000000:
  6986.         case 5333333:
  6987.                 return cdclk_sel ? 333333 : 222222;
  6988.         case 3200000:
  6989.                 return cdclk_sel ? 320000 : 228571;
  6990.         default:
  6991.                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
  6992.                 return 222222;
  6993.         }
  6994. }
  6995.  
  6996. static int i965gm_get_display_clock_speed(struct drm_device *dev)
  6997. {
  6998.         static const uint8_t div_3200[] = { 16, 10,  8 };
  6999.         static const uint8_t div_4000[] = { 20, 12, 10 };
  7000.         static const uint8_t div_5333[] = { 24, 16, 14 };
  7001.         const uint8_t *div_table;
  7002.         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
  7003.         uint16_t tmp = 0;
  7004.  
  7005.         pci_read_config_word(dev->pdev, GCFGC, &tmp);
  7006.  
  7007.         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
  7008.  
  7009.         if (cdclk_sel >= ARRAY_SIZE(div_3200))
  7010.                 goto fail;
  7011.  
  7012.         switch (vco) {
  7013.         case 3200000:
  7014.                 div_table = div_3200;
  7015.                 break;
  7016.         case 4000000:
  7017.                 div_table = div_4000;
  7018.                 break;
  7019.         case 5333333:
  7020.                 div_table = div_5333;
  7021.                 break;
  7022.         default:
  7023.                 goto fail;
  7024.         }
  7025.  
  7026.         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
  7027.  
  7028. fail:
  7029.         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
  7030.         return 200000;
  7031. }
  7032.  
  7033. static int g33_get_display_clock_speed(struct drm_device *dev)
  7034. {
  7035.         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
  7036.         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
  7037.         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
  7038.         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
  7039.         const uint8_t *div_table;
  7040.         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
  7041.         uint16_t tmp = 0;
  7042.  
  7043.         pci_read_config_word(dev->pdev, GCFGC, &tmp);
  7044.  
  7045.         cdclk_sel = (tmp >> 4) & 0x7;
  7046.  
  7047.         if (cdclk_sel >= ARRAY_SIZE(div_3200))
  7048.                 goto fail;
  7049.  
  7050.         switch (vco) {
  7051.         case 3200000:
  7052.                 div_table = div_3200;
  7053.                 break;
  7054.         case 4000000:
  7055.                 div_table = div_4000;
  7056.                 break;
  7057.         case 4800000:
  7058.                 div_table = div_4800;
  7059.                 break;
  7060.         case 5333333:
  7061.                 div_table = div_5333;
  7062.                 break;
  7063.         default:
  7064.                 goto fail;
  7065.         }
  7066.  
  7067.         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
  7068.  
  7069. fail:
  7070.         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
  7071.         return 190476;
  7072. }
  7073.  
  7074. static void
  7075. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  7076. {
  7077.         while (*num > DATA_LINK_M_N_MASK ||
  7078.                *den > DATA_LINK_M_N_MASK) {
  7079.                 *num >>= 1;
  7080.                 *den >>= 1;
  7081.         }
  7082. }
  7083.  
  7084. static void compute_m_n(unsigned int m, unsigned int n,
  7085.                         uint32_t *ret_m, uint32_t *ret_n)
  7086. {
  7087.         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  7088.         *ret_m = div_u64((uint64_t) m * *ret_n, n);
  7089.         intel_reduce_m_n_ratio(ret_m, ret_n);
  7090. }
  7091.  
  7092. void
  7093. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  7094.                        int pixel_clock, int link_clock,
  7095.                        struct intel_link_m_n *m_n)
  7096. {
  7097.         m_n->tu = 64;
  7098.  
  7099.         compute_m_n(bits_per_pixel * pixel_clock,
  7100.                     link_clock * nlanes * 8,
  7101.                     &m_n->gmch_m, &m_n->gmch_n);
  7102.  
  7103.         compute_m_n(pixel_clock, link_clock,
  7104.                     &m_n->link_m, &m_n->link_n);
  7105. }
  7106.  
  7107. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  7108. {
  7109.         if (i915.panel_use_ssc >= 0)
  7110.                 return i915.panel_use_ssc != 0;
  7111.         return dev_priv->vbt.lvds_use_ssc
  7112.                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  7113. }
  7114.  
  7115. static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
  7116.                            int num_connectors)
  7117. {
  7118.         struct drm_device *dev = crtc_state->base.crtc->dev;
  7119.         struct drm_i915_private *dev_priv = dev->dev_private;
  7120.         int refclk;
  7121.  
  7122.         WARN_ON(!crtc_state->base.state);
  7123.  
  7124.         if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
  7125.                 refclk = 100000;
  7126.         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  7127.             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  7128.                 refclk = dev_priv->vbt.lvds_ssc_freq;
  7129.                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
  7130.         } else if (!IS_GEN2(dev)) {
  7131.                 refclk = 96000;
  7132.         } else {
  7133.                 refclk = 48000;
  7134.         }
  7135.  
  7136.         return refclk;
  7137. }
  7138.  
  7139. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  7140. {
  7141.         return (1 << dpll->n) << 16 | dpll->m2;
  7142. }
  7143.  
  7144. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  7145. {
  7146.         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  7147. }
  7148.  
  7149. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  7150.                                      struct intel_crtc_state *crtc_state,
  7151.                                      intel_clock_t *reduced_clock)
  7152. {
  7153.         struct drm_device *dev = crtc->base.dev;
  7154.         u32 fp, fp2 = 0;
  7155.  
  7156.         if (IS_PINEVIEW(dev)) {
  7157.                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
  7158.                 if (reduced_clock)
  7159.                         fp2 = pnv_dpll_compute_fp(reduced_clock);
  7160.         } else {
  7161.                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
  7162.                 if (reduced_clock)
  7163.                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
  7164.         }
  7165.  
  7166.         crtc_state->dpll_hw_state.fp0 = fp;
  7167.  
  7168.         crtc->lowfreq_avail = false;
  7169.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  7170.             reduced_clock) {
  7171.                 crtc_state->dpll_hw_state.fp1 = fp2;
  7172.                 crtc->lowfreq_avail = true;
  7173.         } else {
  7174.                 crtc_state->dpll_hw_state.fp1 = fp;
  7175.         }
  7176. }
  7177.  
  7178. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
  7179.                 pipe)
  7180. {
  7181.         u32 reg_val;
  7182.  
  7183.         /*
  7184.          * PLLB opamp always calibrates to max value of 0x3f, force enable it
  7185.          * and set it to a reasonable value instead.
  7186.          */
  7187.         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
  7188.         reg_val &= 0xffffff00;
  7189.         reg_val |= 0x00000030;
  7190.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
  7191.  
  7192.         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
  7193.         reg_val &= 0x8cffffff;
  7194.         reg_val = 0x8c000000;
  7195.         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
  7196.  
  7197.         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
  7198.         reg_val &= 0xffffff00;
  7199.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
  7200.  
  7201.         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
  7202.         reg_val &= 0x00ffffff;
  7203.         reg_val |= 0xb0000000;
  7204.         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
  7205. }
  7206.  
  7207. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  7208.                                          struct intel_link_m_n *m_n)
  7209. {
  7210.         struct drm_device *dev = crtc->base.dev;
  7211.         struct drm_i915_private *dev_priv = dev->dev_private;
  7212.         int pipe = crtc->pipe;
  7213.  
  7214.         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  7215.         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  7216.         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  7217.         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  7218. }
  7219.  
  7220. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  7221.                                          struct intel_link_m_n *m_n,
  7222.                                          struct intel_link_m_n *m2_n2)
  7223. {
  7224.         struct drm_device *dev = crtc->base.dev;
  7225.         struct drm_i915_private *dev_priv = dev->dev_private;
  7226.         int pipe = crtc->pipe;
  7227.         enum transcoder transcoder = crtc->config->cpu_transcoder;
  7228.  
  7229.         if (INTEL_INFO(dev)->gen >= 5) {
  7230.                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  7231.                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  7232.                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  7233.                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  7234.                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
  7235.                  * for gen < 8) and if DRRS is supported (to make sure the
  7236.                  * registers are not unnecessarily accessed).
  7237.                  */
  7238.                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
  7239.                         crtc->config->has_drrs) {
  7240.                         I915_WRITE(PIPE_DATA_M2(transcoder),
  7241.                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
  7242.                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
  7243.                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
  7244.                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
  7245.                 }
  7246.         } else {
  7247.                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  7248.                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  7249.                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  7250.                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  7251.         }
  7252. }
  7253.  
  7254. void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
  7255. {
  7256.         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
  7257.  
  7258.         if (m_n == M1_N1) {
  7259.                 dp_m_n = &crtc->config->dp_m_n;
  7260.                 dp_m2_n2 = &crtc->config->dp_m2_n2;
  7261.         } else if (m_n == M2_N2) {
  7262.  
  7263.                 /*
  7264.                  * M2_N2 registers are not supported. Hence m2_n2 divider value
  7265.                  * needs to be programmed into M1_N1.
  7266.                  */
  7267.                 dp_m_n = &crtc->config->dp_m2_n2;
  7268.         } else {
  7269.                 DRM_ERROR("Unsupported divider value\n");
  7270.                 return;
  7271.         }
  7272.  
  7273.         if (crtc->config->has_pch_encoder)
  7274.                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
  7275.         else
  7276.                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
  7277. }
  7278.  
  7279. static void vlv_compute_dpll(struct intel_crtc *crtc,
  7280.                              struct intel_crtc_state *pipe_config)
  7281. {
  7282.         u32 dpll, dpll_md;
  7283.  
  7284.         /*
  7285.          * Enable DPIO clock input. We should never disable the reference
  7286.          * clock for pipe B, since VGA hotplug / manual detection depends
  7287.          * on it.
  7288.          */
  7289.         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
  7290.                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
  7291.         /* We should never disable this, set it here for state tracking */
  7292.         if (crtc->pipe == PIPE_B)
  7293.                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  7294.         dpll |= DPLL_VCO_ENABLE;
  7295.         pipe_config->dpll_hw_state.dpll = dpll;
  7296.  
  7297.         dpll_md = (pipe_config->pixel_multiplier - 1)
  7298.                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  7299.         pipe_config->dpll_hw_state.dpll_md = dpll_md;
  7300. }
  7301.  
  7302. static void vlv_prepare_pll(struct intel_crtc *crtc,
  7303.                             const struct intel_crtc_state *pipe_config)
  7304. {
  7305.         struct drm_device *dev = crtc->base.dev;
  7306.         struct drm_i915_private *dev_priv = dev->dev_private;
  7307.         int pipe = crtc->pipe;
  7308.         u32 mdiv;
  7309.         u32 bestn, bestm1, bestm2, bestp1, bestp2;
  7310.         u32 coreclk, reg_val;
  7311.  
  7312.         mutex_lock(&dev_priv->sb_lock);
  7313.  
  7314.         bestn = pipe_config->dpll.n;
  7315.         bestm1 = pipe_config->dpll.m1;
  7316.         bestm2 = pipe_config->dpll.m2;
  7317.         bestp1 = pipe_config->dpll.p1;
  7318.         bestp2 = pipe_config->dpll.p2;
  7319.  
  7320.         /* See eDP HDMI DPIO driver vbios notes doc */
  7321.  
  7322.         /* PLL B needs special handling */
  7323.         if (pipe == PIPE_B)
  7324.                 vlv_pllb_recal_opamp(dev_priv, pipe);
  7325.  
  7326.         /* Set up Tx target for periodic Rcomp update */
  7327.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
  7328.  
  7329.         /* Disable target IRef on PLL */
  7330.         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
  7331.         reg_val &= 0x00ffffff;
  7332.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
  7333.  
  7334.         /* Disable fast lock */
  7335.         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
  7336.  
  7337.         /* Set idtafcrecal before PLL is enabled */
  7338.         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  7339.         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  7340.         mdiv |= ((bestn << DPIO_N_SHIFT));
  7341.         mdiv |= (1 << DPIO_K_SHIFT);
  7342.  
  7343.         /*
  7344.          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  7345.          * but we don't support that).
  7346.          * Note: don't use the DAC post divider as it seems unstable.
  7347.          */
  7348.         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  7349.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
  7350.  
  7351.         mdiv |= DPIO_ENABLE_CALIBRATION;
  7352.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
  7353.  
  7354.         /* Set HBR and RBR LPF coefficients */
  7355.         if (pipe_config->port_clock == 162000 ||
  7356.             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
  7357.             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  7358.                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
  7359.                                  0x009f0003);
  7360.         else
  7361.                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
  7362.                                  0x00d0000f);
  7363.  
  7364.         if (pipe_config->has_dp_encoder) {
  7365.                 /* Use SSC source */
  7366.                 if (pipe == PIPE_A)
  7367.                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  7368.                                          0x0df40000);
  7369.                 else
  7370.                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  7371.                                          0x0df70000);
  7372.         } else { /* HDMI or VGA */
  7373.                 /* Use bend source */
  7374.                 if (pipe == PIPE_A)
  7375.                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  7376.                                          0x0df70000);
  7377.                 else
  7378.                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
  7379.                                          0x0df40000);
  7380.         }
  7381.  
  7382.         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
  7383.         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  7384.         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  7385.             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  7386.                 coreclk |= 0x01000000;
  7387.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
  7388.  
  7389.         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
  7390.         mutex_unlock(&dev_priv->sb_lock);
  7391. }
  7392.  
  7393. static void chv_compute_dpll(struct intel_crtc *crtc,
  7394.                              struct intel_crtc_state *pipe_config)
  7395. {
  7396.         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
  7397.                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
  7398.                 DPLL_VCO_ENABLE;
  7399.         if (crtc->pipe != PIPE_A)
  7400.                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  7401.  
  7402.         pipe_config->dpll_hw_state.dpll_md =
  7403.                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  7404. }
  7405.  
  7406. static void chv_prepare_pll(struct intel_crtc *crtc,
  7407.                             const struct intel_crtc_state *pipe_config)
  7408. {
  7409.         struct drm_device *dev = crtc->base.dev;
  7410.         struct drm_i915_private *dev_priv = dev->dev_private;
  7411.         int pipe = crtc->pipe;
  7412.         int dpll_reg = DPLL(crtc->pipe);
  7413.         enum dpio_channel port = vlv_pipe_to_channel(pipe);
  7414.         u32 loopfilter, tribuf_calcntr;
  7415.         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
  7416.         u32 dpio_val;
  7417.         int vco;
  7418.  
  7419.         bestn = pipe_config->dpll.n;
  7420.         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
  7421.         bestm1 = pipe_config->dpll.m1;
  7422.         bestm2 = pipe_config->dpll.m2 >> 22;
  7423.         bestp1 = pipe_config->dpll.p1;
  7424.         bestp2 = pipe_config->dpll.p2;
  7425.         vco = pipe_config->dpll.vco;
  7426.         dpio_val = 0;
  7427.         loopfilter = 0;
  7428.  
  7429.         /*
  7430.          * Enable Refclk and SSC
  7431.          */
  7432.         I915_WRITE(dpll_reg,
  7433.                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
  7434.  
  7435.         mutex_lock(&dev_priv->sb_lock);
  7436.  
  7437.         /* p1 and p2 divider */
  7438.         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
  7439.                         5 << DPIO_CHV_S1_DIV_SHIFT |
  7440.                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
  7441.                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
  7442.                         1 << DPIO_CHV_K_DIV_SHIFT);
  7443.  
  7444.         /* Feedback post-divider - m2 */
  7445.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
  7446.  
  7447.         /* Feedback refclk divider - n and m1 */
  7448.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
  7449.                         DPIO_CHV_M1_DIV_BY_2 |
  7450.                         1 << DPIO_CHV_N_DIV_SHIFT);
  7451.  
  7452.         /* M2 fraction division */
  7453.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
  7454.  
  7455.         /* M2 fraction division enable */
  7456.         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
  7457.         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
  7458.         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
  7459.         if (bestm2_frac)
  7460.                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
  7461.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
  7462.  
  7463.         /* Program digital lock detect threshold */
  7464.         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
  7465.         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
  7466.                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
  7467.         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
  7468.         if (!bestm2_frac)
  7469.                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
  7470.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
  7471.  
  7472.         /* Loop filter */
  7473.         if (vco == 5400000) {
  7474.                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
  7475.                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
  7476.                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
  7477.                 tribuf_calcntr = 0x9;
  7478.         } else if (vco <= 6200000) {
  7479.                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
  7480.                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
  7481.                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
  7482.                 tribuf_calcntr = 0x9;
  7483.         } else if (vco <= 6480000) {
  7484.                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
  7485.                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
  7486.                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
  7487.                 tribuf_calcntr = 0x8;
  7488.         } else {
  7489.                 /* Not supported. Apply the same limits as in the max case */
  7490.                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
  7491.                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
  7492.                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
  7493.                 tribuf_calcntr = 0;
  7494.         }
  7495.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
  7496.  
  7497.         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
  7498.         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
  7499.         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
  7500.         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
  7501.  
  7502.         /* AFC Recal */
  7503.         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
  7504.                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
  7505.                         DPIO_AFC_RECAL);
  7506.  
  7507.         mutex_unlock(&dev_priv->sb_lock);
  7508. }
  7509.  
  7510. /**
  7511.  * vlv_force_pll_on - forcibly enable just the PLL
  7512.  * @dev_priv: i915 private structure
  7513.  * @pipe: pipe PLL to enable
  7514.  * @dpll: PLL configuration
  7515.  *
  7516.  * Enable the PLL for @pipe using the supplied @dpll config. To be used
  7517.  * in cases where we need the PLL enabled even when @pipe is not going to
  7518.  * be enabled.
  7519.  */
  7520. void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
  7521.                       const struct dpll *dpll)
  7522. {
  7523.         struct intel_crtc *crtc =
  7524.                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
  7525.         struct intel_crtc_state pipe_config = {
  7526.                 .base.crtc = &crtc->base,
  7527.                 .pixel_multiplier = 1,
  7528.                 .dpll = *dpll,
  7529.         };
  7530.  
  7531.         if (IS_CHERRYVIEW(dev)) {
  7532.                 chv_compute_dpll(crtc, &pipe_config);
  7533.                 chv_prepare_pll(crtc, &pipe_config);
  7534.                 chv_enable_pll(crtc, &pipe_config);
  7535.         } else {
  7536.                 vlv_compute_dpll(crtc, &pipe_config);
  7537.                 vlv_prepare_pll(crtc, &pipe_config);
  7538.                 vlv_enable_pll(crtc, &pipe_config);
  7539.         }
  7540. }
  7541.  
  7542. /**
  7543.  * vlv_force_pll_off - forcibly disable just the PLL
  7544.  * @dev_priv: i915 private structure
  7545.  * @pipe: pipe PLL to disable
  7546.  *
  7547.  * Disable the PLL for @pipe. To be used in cases where we need
  7548.  * the PLL enabled even when @pipe is not going to be enabled.
  7549.  */
  7550. void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
  7551. {
  7552.         if (IS_CHERRYVIEW(dev))
  7553.                 chv_disable_pll(to_i915(dev), pipe);
  7554.         else
  7555.                 vlv_disable_pll(to_i915(dev), pipe);
  7556. }
  7557.  
  7558. static void i9xx_compute_dpll(struct intel_crtc *crtc,
  7559.                               struct intel_crtc_state *crtc_state,
  7560.                               intel_clock_t *reduced_clock,
  7561.                               int num_connectors)
  7562. {
  7563.         struct drm_device *dev = crtc->base.dev;
  7564.         struct drm_i915_private *dev_priv = dev->dev_private;
  7565.         u32 dpll;
  7566.         bool is_sdvo;
  7567.         struct dpll *clock = &crtc_state->dpll;
  7568.  
  7569.         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
  7570.  
  7571.         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
  7572.                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
  7573.  
  7574.         dpll = DPLL_VGA_MODE_DIS;
  7575.  
  7576.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
  7577.                 dpll |= DPLLB_MODE_LVDS;
  7578.         else
  7579.                 dpll |= DPLLB_MODE_DAC_SERIAL;
  7580.  
  7581.         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  7582.                 dpll |= (crtc_state->pixel_multiplier - 1)
  7583.                         << SDVO_MULTIPLIER_SHIFT_HIRES;
  7584.         }
  7585.  
  7586.         if (is_sdvo)
  7587.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  7588.  
  7589.         if (crtc_state->has_dp_encoder)
  7590.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  7591.  
  7592.         /* compute bitmask from p1 value */
  7593.         if (IS_PINEVIEW(dev))
  7594.                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  7595.         else {
  7596.                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  7597.                 if (IS_G4X(dev) && reduced_clock)
  7598.                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  7599.         }
  7600.         switch (clock->p2) {
  7601.         case 5:
  7602.                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  7603.                 break;
  7604.         case 7:
  7605.                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  7606.                 break;
  7607.         case 10:
  7608.                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  7609.                 break;
  7610.         case 14:
  7611.                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  7612.                 break;
  7613.         }
  7614.         if (INTEL_INFO(dev)->gen >= 4)
  7615.                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  7616.  
  7617.         if (crtc_state->sdvo_tv_clock)
  7618.                 dpll |= PLL_REF_INPUT_TVCLKINBC;
  7619.         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  7620.                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  7621.                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  7622.         else
  7623.                 dpll |= PLL_REF_INPUT_DREFCLK;
  7624.  
  7625.         dpll |= DPLL_VCO_ENABLE;
  7626.         crtc_state->dpll_hw_state.dpll = dpll;
  7627.  
  7628.         if (INTEL_INFO(dev)->gen >= 4) {
  7629.                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
  7630.                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  7631.                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
  7632.         }
  7633. }
  7634.  
  7635. static void i8xx_compute_dpll(struct intel_crtc *crtc,
  7636.                               struct intel_crtc_state *crtc_state,
  7637.                               intel_clock_t *reduced_clock,
  7638.                               int num_connectors)
  7639. {
  7640.         struct drm_device *dev = crtc->base.dev;
  7641.         struct drm_i915_private *dev_priv = dev->dev_private;
  7642.         u32 dpll;
  7643.         struct dpll *clock = &crtc_state->dpll;
  7644.  
  7645.         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
  7646.  
  7647.         dpll = DPLL_VGA_MODE_DIS;
  7648.  
  7649.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
  7650.                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  7651.         } else {
  7652.                 if (clock->p1 == 2)
  7653.                         dpll |= PLL_P1_DIVIDE_BY_TWO;
  7654.                 else
  7655.                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  7656.                 if (clock->p2 == 4)
  7657.                         dpll |= PLL_P2_DIVIDE_BY_4;
  7658.         }
  7659.  
  7660.         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
  7661.                 dpll |= DPLL_DVO_2X_MODE;
  7662.  
  7663.         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
  7664.                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  7665.                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  7666.         else
  7667.                 dpll |= PLL_REF_INPUT_DREFCLK;
  7668.  
  7669.         dpll |= DPLL_VCO_ENABLE;
  7670.         crtc_state->dpll_hw_state.dpll = dpll;
  7671. }
  7672.  
  7673. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  7674. {
  7675.         struct drm_device *dev = intel_crtc->base.dev;
  7676.         struct drm_i915_private *dev_priv = dev->dev_private;
  7677.         enum pipe pipe = intel_crtc->pipe;
  7678.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  7679.         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
  7680.         uint32_t crtc_vtotal, crtc_vblank_end;
  7681.         int vsyncshift = 0;
  7682.  
  7683.         /* We need to be careful not to changed the adjusted mode, for otherwise
  7684.          * the hw state checker will get angry at the mismatch. */
  7685.         crtc_vtotal = adjusted_mode->crtc_vtotal;
  7686.         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  7687.  
  7688.         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  7689.                 /* the chip adds 2 halflines automatically */
  7690.                 crtc_vtotal -= 1;
  7691.                 crtc_vblank_end -= 1;
  7692.  
  7693.                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
  7694.                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
  7695.                 else
  7696.                         vsyncshift = adjusted_mode->crtc_hsync_start -
  7697.                                 adjusted_mode->crtc_htotal / 2;
  7698.                 if (vsyncshift < 0)
  7699.                         vsyncshift += adjusted_mode->crtc_htotal;
  7700.         }
  7701.  
  7702.         if (INTEL_INFO(dev)->gen > 3)
  7703.                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  7704.  
  7705.         I915_WRITE(HTOTAL(cpu_transcoder),
  7706.                    (adjusted_mode->crtc_hdisplay - 1) |
  7707.                    ((adjusted_mode->crtc_htotal - 1) << 16));
  7708.         I915_WRITE(HBLANK(cpu_transcoder),
  7709.                    (adjusted_mode->crtc_hblank_start - 1) |
  7710.                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
  7711.         I915_WRITE(HSYNC(cpu_transcoder),
  7712.                    (adjusted_mode->crtc_hsync_start - 1) |
  7713.                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
  7714.  
  7715.         I915_WRITE(VTOTAL(cpu_transcoder),
  7716.                    (adjusted_mode->crtc_vdisplay - 1) |
  7717.                    ((crtc_vtotal - 1) << 16));
  7718.         I915_WRITE(VBLANK(cpu_transcoder),
  7719.                    (adjusted_mode->crtc_vblank_start - 1) |
  7720.                    ((crtc_vblank_end - 1) << 16));
  7721.         I915_WRITE(VSYNC(cpu_transcoder),
  7722.                    (adjusted_mode->crtc_vsync_start - 1) |
  7723.                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
  7724.  
  7725.         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  7726.          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  7727.          * documented on the DDI_FUNC_CTL register description, EDP Input Select
  7728.          * bits. */
  7729.         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  7730.             (pipe == PIPE_B || pipe == PIPE_C))
  7731.                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  7732.  
  7733.         /* pipesrc controls the size that is scaled from, which should
  7734.          * always be the user's requested size.
  7735.          */
  7736.         I915_WRITE(PIPESRC(pipe),
  7737.                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
  7738.                    (intel_crtc->config->pipe_src_h - 1));
  7739. }
  7740.  
  7741. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  7742.                                    struct intel_crtc_state *pipe_config)
  7743. {
  7744.         struct drm_device *dev = crtc->base.dev;
  7745.         struct drm_i915_private *dev_priv = dev->dev_private;
  7746.         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  7747.         uint32_t tmp;
  7748.  
  7749.         tmp = I915_READ(HTOTAL(cpu_transcoder));
  7750.         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  7751.         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  7752.         tmp = I915_READ(HBLANK(cpu_transcoder));
  7753.         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  7754.         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  7755.         tmp = I915_READ(HSYNC(cpu_transcoder));
  7756.         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  7757.         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  7758.  
  7759.         tmp = I915_READ(VTOTAL(cpu_transcoder));
  7760.         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  7761.         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  7762.         tmp = I915_READ(VBLANK(cpu_transcoder));
  7763.         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  7764.         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  7765.         tmp = I915_READ(VSYNC(cpu_transcoder));
  7766.         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  7767.         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  7768.  
  7769.         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  7770.                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  7771.                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
  7772.                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
  7773.         }
  7774.  
  7775.         tmp = I915_READ(PIPESRC(crtc->pipe));
  7776.         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
  7777.         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
  7778.  
  7779.         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
  7780.         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
  7781. }
  7782.  
  7783. void intel_mode_from_pipe_config(struct drm_display_mode *mode,
  7784.                                  struct intel_crtc_state *pipe_config)
  7785. {
  7786.         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
  7787.         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
  7788.         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
  7789.         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
  7790.  
  7791.         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
  7792.         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
  7793.         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
  7794.         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
  7795.  
  7796.         mode->flags = pipe_config->base.adjusted_mode.flags;
  7797.         mode->type = DRM_MODE_TYPE_DRIVER;
  7798.  
  7799.         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
  7800.         mode->flags |= pipe_config->base.adjusted_mode.flags;
  7801.  
  7802.         mode->hsync = drm_mode_hsync(mode);
  7803.         mode->vrefresh = drm_mode_vrefresh(mode);
  7804.         drm_mode_set_name(mode);
  7805. }
  7806.  
  7807. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  7808. {
  7809.         struct drm_device *dev = intel_crtc->base.dev;
  7810.         struct drm_i915_private *dev_priv = dev->dev_private;
  7811.         uint32_t pipeconf;
  7812.  
  7813.         pipeconf = 0;
  7814.  
  7815.         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  7816.             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  7817.                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
  7818.  
  7819.         if (intel_crtc->config->double_wide)
  7820.                 pipeconf |= PIPECONF_DOUBLE_WIDE;
  7821.  
  7822.         /* only g4x and later have fancy bpc/dither controls */
  7823.         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  7824.                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
  7825.                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
  7826.                         pipeconf |= PIPECONF_DITHER_EN |
  7827.                                     PIPECONF_DITHER_TYPE_SP;
  7828.  
  7829.                 switch (intel_crtc->config->pipe_bpp) {
  7830.                 case 18:
  7831.                         pipeconf |= PIPECONF_6BPC;
  7832.                         break;
  7833.                 case 24:
  7834.                         pipeconf |= PIPECONF_8BPC;
  7835.                         break;
  7836.                 case 30:
  7837.                         pipeconf |= PIPECONF_10BPC;
  7838.                         break;
  7839.                 default:
  7840.                         /* Case prevented by intel_choose_pipe_bpp_dither. */
  7841.                         BUG();
  7842.                 }
  7843.         }
  7844.  
  7845.         if (HAS_PIPE_CXSR(dev)) {
  7846.                 if (intel_crtc->lowfreq_avail) {
  7847.                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  7848.                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  7849.                 } else {
  7850.                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  7851.                 }
  7852.         }
  7853.  
  7854.         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
  7855.                 if (INTEL_INFO(dev)->gen < 4 ||
  7856.                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
  7857.                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  7858.                 else
  7859.                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
  7860.         } else
  7861.                 pipeconf |= PIPECONF_PROGRESSIVE;
  7862.  
  7863.         if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
  7864.                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  7865.  
  7866.         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  7867.         POSTING_READ(PIPECONF(intel_crtc->pipe));
  7868. }
  7869.  
  7870. static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
  7871.                                    struct intel_crtc_state *crtc_state)
  7872. {
  7873.         struct drm_device *dev = crtc->base.dev;
  7874.         struct drm_i915_private *dev_priv = dev->dev_private;
  7875.         int refclk, num_connectors = 0;
  7876.         intel_clock_t clock;
  7877.         bool ok;
  7878.         bool is_dsi = false;
  7879.         struct intel_encoder *encoder;
  7880.         const intel_limit_t *limit;
  7881.         struct drm_atomic_state *state = crtc_state->base.state;
  7882.         struct drm_connector *connector;
  7883.         struct drm_connector_state *connector_state;
  7884.         int i;
  7885.  
  7886.         memset(&crtc_state->dpll_hw_state, 0,
  7887.                sizeof(crtc_state->dpll_hw_state));
  7888.  
  7889.         for_each_connector_in_state(state, connector, connector_state, i) {
  7890.                 if (connector_state->crtc != &crtc->base)
  7891.                         continue;
  7892.  
  7893.                 encoder = to_intel_encoder(connector_state->best_encoder);
  7894.  
  7895.                 switch (encoder->type) {
  7896.                 case INTEL_OUTPUT_DSI:
  7897.                         is_dsi = true;
  7898.                         break;
  7899.                 default:
  7900.                         break;
  7901.                 }
  7902.  
  7903.                 num_connectors++;
  7904.         }
  7905.  
  7906.         if (is_dsi)
  7907.                 return 0;
  7908.  
  7909.         if (!crtc_state->clock_set) {
  7910.                 refclk = i9xx_get_refclk(crtc_state, num_connectors);
  7911.  
  7912.                 /*
  7913.                  * Returns a set of divisors for the desired target clock with
  7914.                  * the given refclk, or FALSE.  The returned values represent
  7915.                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
  7916.                  * 2) / p1 / p2.
  7917.                  */
  7918.                 limit = intel_limit(crtc_state, refclk);
  7919.                 ok = dev_priv->display.find_dpll(limit, crtc_state,
  7920.                                                  crtc_state->port_clock,
  7921.                                                  refclk, NULL, &clock);
  7922.                 if (!ok) {
  7923.                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
  7924.                         return -EINVAL;
  7925.                 }
  7926.  
  7927.                 /* Compat-code for transition, will disappear. */
  7928.                 crtc_state->dpll.n = clock.n;
  7929.                 crtc_state->dpll.m1 = clock.m1;
  7930.                 crtc_state->dpll.m2 = clock.m2;
  7931.                 crtc_state->dpll.p1 = clock.p1;
  7932.                 crtc_state->dpll.p2 = clock.p2;
  7933.         }
  7934.  
  7935.         if (IS_GEN2(dev)) {
  7936.                 i8xx_compute_dpll(crtc, crtc_state, NULL,
  7937.                                   num_connectors);
  7938.         } else if (IS_CHERRYVIEW(dev)) {
  7939.                 chv_compute_dpll(crtc, crtc_state);
  7940.         } else if (IS_VALLEYVIEW(dev)) {
  7941.                 vlv_compute_dpll(crtc, crtc_state);
  7942.         } else {
  7943.                 i9xx_compute_dpll(crtc, crtc_state, NULL,
  7944.                                   num_connectors);
  7945.         }
  7946.  
  7947.         return 0;
  7948. }
  7949.  
  7950. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  7951.                                  struct intel_crtc_state *pipe_config)
  7952. {
  7953.         struct drm_device *dev = crtc->base.dev;
  7954.         struct drm_i915_private *dev_priv = dev->dev_private;
  7955.         uint32_t tmp;
  7956.  
  7957.         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
  7958.                 return;
  7959.  
  7960.         tmp = I915_READ(PFIT_CONTROL);
  7961.         if (!(tmp & PFIT_ENABLE))
  7962.                 return;
  7963.  
  7964.         /* Check whether the pfit is attached to our pipe. */
  7965.         if (INTEL_INFO(dev)->gen < 4) {
  7966.                 if (crtc->pipe != PIPE_B)
  7967.                         return;
  7968.         } else {
  7969.                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  7970.                         return;
  7971.         }
  7972.  
  7973.         pipe_config->gmch_pfit.control = tmp;
  7974.         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  7975.         if (INTEL_INFO(dev)->gen < 5)
  7976.                 pipe_config->gmch_pfit.lvds_border_bits =
  7977.                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
  7978. }
  7979.  
  7980. static void vlv_crtc_clock_get(struct intel_crtc *crtc,
  7981.                                struct intel_crtc_state *pipe_config)
  7982. {
  7983.         struct drm_device *dev = crtc->base.dev;
  7984.         struct drm_i915_private *dev_priv = dev->dev_private;
  7985.         int pipe = pipe_config->cpu_transcoder;
  7986.         intel_clock_t clock;
  7987.         u32 mdiv;
  7988.         int refclk = 100000;
  7989.  
  7990.         /* In case of MIPI DPLL will not even be used */
  7991.         if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
  7992.                 return;
  7993.  
  7994.         mutex_lock(&dev_priv->sb_lock);
  7995.         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
  7996.         mutex_unlock(&dev_priv->sb_lock);
  7997.  
  7998.         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
  7999.         clock.m2 = mdiv & DPIO_M2DIV_MASK;
  8000.         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
  8001.         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
  8002.         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
  8003.  
  8004.         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
  8005. }
  8006.  
  8007. static void
  8008. i9xx_get_initial_plane_config(struct intel_crtc *crtc,
  8009.                               struct intel_initial_plane_config *plane_config)
  8010. {
  8011.         struct drm_device *dev = crtc->base.dev;
  8012.         struct drm_i915_private *dev_priv = dev->dev_private;
  8013.         u32 val, base, offset;
  8014.         int pipe = crtc->pipe, plane = crtc->plane;
  8015.         int fourcc, pixel_format;
  8016.         unsigned int aligned_height;
  8017.         struct drm_framebuffer *fb;
  8018.         struct intel_framebuffer *intel_fb;
  8019.  
  8020.         val = I915_READ(DSPCNTR(plane));
  8021.         if (!(val & DISPLAY_PLANE_ENABLE))
  8022.                 return;
  8023.  
  8024.         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  8025.         if (!intel_fb) {
  8026.                 DRM_DEBUG_KMS("failed to alloc fb\n");
  8027.                 return;
  8028.         }
  8029.  
  8030.         fb = &intel_fb->base;
  8031.  
  8032.         if (INTEL_INFO(dev)->gen >= 4) {
  8033.                 if (val & DISPPLANE_TILED) {
  8034.                         plane_config->tiling = I915_TILING_X;
  8035.                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
  8036.                 }
  8037.         }
  8038.  
  8039.         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
  8040.         fourcc = i9xx_format_to_fourcc(pixel_format);
  8041.         fb->pixel_format = fourcc;
  8042.         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  8043.  
  8044.         if (INTEL_INFO(dev)->gen >= 4) {
  8045.                 if (plane_config->tiling)
  8046.                         offset = I915_READ(DSPTILEOFF(plane));
  8047.                 else
  8048.                         offset = I915_READ(DSPLINOFF(plane));
  8049.                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
  8050.         } else {
  8051.                 base = I915_READ(DSPADDR(plane));
  8052.         }
  8053.         plane_config->base = base;
  8054.  
  8055.         val = I915_READ(PIPESRC(pipe));
  8056.         fb->width = ((val >> 16) & 0xfff) + 1;
  8057.         fb->height = ((val >> 0) & 0xfff) + 1;
  8058.  
  8059.         val = I915_READ(DSPSTRIDE(pipe));
  8060. //   fb->pitches[0] = val & 0xffffffc0;
  8061.         fb->pitches[0] = 2560*4;
  8062.  
  8063.         aligned_height = intel_fb_align_height(dev, fb->height,
  8064.                                                fb->pixel_format,
  8065.                                                fb->modifier[0]);
  8066.  
  8067. //   plane_config->size = fb->pitches[0] * aligned_height;
  8068.     plane_config->size = i915.fbsize*1024*1024;
  8069.  
  8070.         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
  8071.                       pipe_name(pipe), plane, fb->width, fb->height,
  8072.                       fb->bits_per_pixel, base, fb->pitches[0],
  8073.                       plane_config->size);
  8074.  
  8075.         plane_config->fb = intel_fb;
  8076. }
  8077.  
  8078. static void chv_crtc_clock_get(struct intel_crtc *crtc,
  8079.                                struct intel_crtc_state *pipe_config)
  8080. {
  8081.         struct drm_device *dev = crtc->base.dev;
  8082.         struct drm_i915_private *dev_priv = dev->dev_private;
  8083.         int pipe = pipe_config->cpu_transcoder;
  8084.         enum dpio_channel port = vlv_pipe_to_channel(pipe);
  8085.         intel_clock_t clock;
  8086.         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
  8087.         int refclk = 100000;
  8088.  
  8089.         mutex_lock(&dev_priv->sb_lock);
  8090.         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
  8091.         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
  8092.         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
  8093.         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
  8094.         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
  8095.         mutex_unlock(&dev_priv->sb_lock);
  8096.  
  8097.         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
  8098.         clock.m2 = (pll_dw0 & 0xff) << 22;
  8099.         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
  8100.                 clock.m2 |= pll_dw2 & 0x3fffff;
  8101.         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
  8102.         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
  8103.         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
  8104.  
  8105.         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
  8106. }
  8107.  
  8108. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  8109.                                  struct intel_crtc_state *pipe_config)
  8110. {
  8111.         struct drm_device *dev = crtc->base.dev;
  8112.         struct drm_i915_private *dev_priv = dev->dev_private;
  8113.         uint32_t tmp;
  8114.  
  8115.         if (!intel_display_power_is_enabled(dev_priv,
  8116.                                             POWER_DOMAIN_PIPE(crtc->pipe)))
  8117.                 return false;
  8118.  
  8119.         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  8120.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  8121.  
  8122.         tmp = I915_READ(PIPECONF(crtc->pipe));
  8123.         if (!(tmp & PIPECONF_ENABLE))
  8124.                 return false;
  8125.  
  8126.         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  8127.                 switch (tmp & PIPECONF_BPC_MASK) {
  8128.                 case PIPECONF_6BPC:
  8129.                         pipe_config->pipe_bpp = 18;
  8130.                         break;
  8131.                 case PIPECONF_8BPC:
  8132.                         pipe_config->pipe_bpp = 24;
  8133.                         break;
  8134.                 case PIPECONF_10BPC:
  8135.                         pipe_config->pipe_bpp = 30;
  8136.                         break;
  8137.                 default:
  8138.                         break;
  8139.                 }
  8140.         }
  8141.  
  8142.         if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
  8143.                 pipe_config->limited_color_range = true;
  8144.  
  8145.         if (INTEL_INFO(dev)->gen < 4)
  8146.                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
  8147.  
  8148.         intel_get_pipe_timings(crtc, pipe_config);
  8149.  
  8150.         i9xx_get_pfit_config(crtc, pipe_config);
  8151.  
  8152.         if (INTEL_INFO(dev)->gen >= 4) {
  8153.                 tmp = I915_READ(DPLL_MD(crtc->pipe));
  8154.                 pipe_config->pixel_multiplier =
  8155.                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  8156.                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  8157.                 pipe_config->dpll_hw_state.dpll_md = tmp;
  8158.         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  8159.                 tmp = I915_READ(DPLL(crtc->pipe));
  8160.                 pipe_config->pixel_multiplier =
  8161.                         ((tmp & SDVO_MULTIPLIER_MASK)
  8162.                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  8163.         } else {
  8164.                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
  8165.                  * port and will be fixed up in the encoder->get_config
  8166.                  * function. */
  8167.                 pipe_config->pixel_multiplier = 1;
  8168.         }
  8169.         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  8170.         if (!IS_VALLEYVIEW(dev)) {
  8171.                 /*
  8172.                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
  8173.                  * on 830. Filter it out here so that we don't
  8174.                  * report errors due to that.
  8175.                  */
  8176.                 if (IS_I830(dev))
  8177.                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
  8178.  
  8179.                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  8180.                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  8181.         } else {
  8182.                 /* Mask out read-only status bits. */
  8183.                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  8184.                                                      DPLL_PORTC_READY_MASK |
  8185.                                                      DPLL_PORTB_READY_MASK);
  8186.         }
  8187.  
  8188.         if (IS_CHERRYVIEW(dev))
  8189.                 chv_crtc_clock_get(crtc, pipe_config);
  8190.         else if (IS_VALLEYVIEW(dev))
  8191.                 vlv_crtc_clock_get(crtc, pipe_config);
  8192.         else
  8193.                 i9xx_crtc_clock_get(crtc, pipe_config);
  8194.  
  8195.         /*
  8196.          * Normally the dotclock is filled in by the encoder .get_config()
  8197.          * but in case the pipe is enabled w/o any ports we need a sane
  8198.          * default.
  8199.          */
  8200.         pipe_config->base.adjusted_mode.crtc_clock =
  8201.                 pipe_config->port_clock / pipe_config->pixel_multiplier;
  8202.  
  8203.         return true;
  8204. }
  8205.  
  8206. static void ironlake_init_pch_refclk(struct drm_device *dev)
  8207. {
  8208.         struct drm_i915_private *dev_priv = dev->dev_private;
  8209.         struct intel_encoder *encoder;
  8210.         u32 val, final;
  8211.         bool has_lvds = false;
  8212.         bool has_cpu_edp = false;
  8213.         bool has_panel = false;
  8214.         bool has_ck505 = false;
  8215.         bool can_ssc = false;
  8216.  
  8217.         /* We need to take the global config into account */
  8218.         for_each_intel_encoder(dev, encoder) {
  8219.                 switch (encoder->type) {
  8220.                 case INTEL_OUTPUT_LVDS:
  8221.                         has_panel = true;
  8222.                         has_lvds = true;
  8223.                         break;
  8224.                 case INTEL_OUTPUT_EDP:
  8225.                         has_panel = true;
  8226.                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  8227.                                 has_cpu_edp = true;
  8228.                         break;
  8229.                 default:
  8230.                         break;
  8231.                 }
  8232.         }
  8233.  
  8234.         if (HAS_PCH_IBX(dev)) {
  8235.                 has_ck505 = dev_priv->vbt.display_clock_mode;
  8236.                 can_ssc = has_ck505;
  8237.         } else {
  8238.                 has_ck505 = false;
  8239.                 can_ssc = true;
  8240.         }
  8241.  
  8242.         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  8243.                       has_panel, has_lvds, has_ck505);
  8244.  
  8245.         /* Ironlake: try to setup display ref clock before DPLL
  8246.          * enabling. This is only under driver's control after
  8247.          * PCH B stepping, previous chipset stepping should be
  8248.          * ignoring this setting.
  8249.          */
  8250.         val = I915_READ(PCH_DREF_CONTROL);
  8251.  
  8252.         /* As we must carefully and slowly disable/enable each source in turn,
  8253.          * compute the final state we want first and check if we need to
  8254.          * make any changes at all.
  8255.          */
  8256.         final = val;
  8257.         final &= ~DREF_NONSPREAD_SOURCE_MASK;
  8258.         if (has_ck505)
  8259.                 final |= DREF_NONSPREAD_CK505_ENABLE;
  8260.         else
  8261.                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
  8262.  
  8263.         final &= ~DREF_SSC_SOURCE_MASK;
  8264.         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  8265.         final &= ~DREF_SSC1_ENABLE;
  8266.  
  8267.         if (has_panel) {
  8268.                 final |= DREF_SSC_SOURCE_ENABLE;
  8269.  
  8270.                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
  8271.                         final |= DREF_SSC1_ENABLE;
  8272.  
  8273.                 if (has_cpu_edp) {
  8274.                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
  8275.                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  8276.                         else
  8277.                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  8278.                 } else
  8279.                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  8280.         } else {
  8281.                 final |= DREF_SSC_SOURCE_DISABLE;
  8282.                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  8283.         }
  8284.  
  8285.         if (final == val)
  8286.                 return;
  8287.  
  8288.         /* Always enable nonspread source */
  8289.         val &= ~DREF_NONSPREAD_SOURCE_MASK;
  8290.  
  8291.         if (has_ck505)
  8292.                 val |= DREF_NONSPREAD_CK505_ENABLE;
  8293.         else
  8294.                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
  8295.  
  8296.         if (has_panel) {
  8297.                 val &= ~DREF_SSC_SOURCE_MASK;
  8298.                 val |= DREF_SSC_SOURCE_ENABLE;
  8299.  
  8300.                 /* SSC must be turned on before enabling the CPU output  */
  8301.                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  8302.                         DRM_DEBUG_KMS("Using SSC on panel\n");
  8303.                         val |= DREF_SSC1_ENABLE;
  8304.                 } else
  8305.                         val &= ~DREF_SSC1_ENABLE;
  8306.  
  8307.                 /* Get SSC going before enabling the outputs */
  8308.                 I915_WRITE(PCH_DREF_CONTROL, val);
  8309.                 POSTING_READ(PCH_DREF_CONTROL);
  8310.                 udelay(200);
  8311.  
  8312.                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  8313.  
  8314.                 /* Enable CPU source on CPU attached eDP */
  8315.                 if (has_cpu_edp) {
  8316.                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  8317.                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
  8318.                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  8319.                         } else
  8320.                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  8321.                 } else
  8322.                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  8323.  
  8324.                 I915_WRITE(PCH_DREF_CONTROL, val);
  8325.                 POSTING_READ(PCH_DREF_CONTROL);
  8326.                 udelay(200);
  8327.         } else {
  8328.                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
  8329.  
  8330.                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  8331.  
  8332.                 /* Turn off CPU output */
  8333.                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  8334.  
  8335.                 I915_WRITE(PCH_DREF_CONTROL, val);
  8336.                 POSTING_READ(PCH_DREF_CONTROL);
  8337.                 udelay(200);
  8338.  
  8339.                 /* Turn off the SSC source */
  8340.                 val &= ~DREF_SSC_SOURCE_MASK;
  8341.                 val |= DREF_SSC_SOURCE_DISABLE;
  8342.  
  8343.                 /* Turn off SSC1 */
  8344.                 val &= ~DREF_SSC1_ENABLE;
  8345.  
  8346.                 I915_WRITE(PCH_DREF_CONTROL, val);
  8347.                 POSTING_READ(PCH_DREF_CONTROL);
  8348.                 udelay(200);
  8349.         }
  8350.  
  8351.         BUG_ON(val != final);
  8352. }
  8353.  
  8354. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  8355. {
  8356.         uint32_t tmp;
  8357.  
  8358.         tmp = I915_READ(SOUTH_CHICKEN2);
  8359.         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  8360.         I915_WRITE(SOUTH_CHICKEN2, tmp);
  8361.  
  8362.         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  8363.                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  8364.                 DRM_ERROR("FDI mPHY reset assert timeout\n");
  8365.  
  8366.         tmp = I915_READ(SOUTH_CHICKEN2);
  8367.         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  8368.         I915_WRITE(SOUTH_CHICKEN2, tmp);
  8369.  
  8370.         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  8371.                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  8372.                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  8373. }
  8374.  
  8375. /* WaMPhyProgramming:hsw */
  8376. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  8377. {
  8378.         uint32_t tmp;
  8379.  
  8380.         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  8381.         tmp &= ~(0xFF << 24);
  8382.         tmp |= (0x12 << 24);
  8383.         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  8384.  
  8385.         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  8386.         tmp |= (1 << 11);
  8387.         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  8388.  
  8389.         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  8390.         tmp |= (1 << 11);
  8391.         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  8392.  
  8393.         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  8394.         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  8395.         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  8396.  
  8397.         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  8398.         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  8399.         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  8400.  
  8401.         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  8402.         tmp &= ~(7 << 13);
  8403.         tmp |= (5 << 13);
  8404.         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  8405.  
  8406.         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  8407.         tmp &= ~(7 << 13);
  8408.         tmp |= (5 << 13);
  8409.         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  8410.  
  8411.         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  8412.         tmp &= ~0xFF;
  8413.         tmp |= 0x1C;
  8414.         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  8415.  
  8416.         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  8417.         tmp &= ~0xFF;
  8418.         tmp |= 0x1C;
  8419.         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  8420.  
  8421.         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  8422.         tmp &= ~(0xFF << 16);
  8423.         tmp |= (0x1C << 16);
  8424.         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  8425.  
  8426.         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  8427.         tmp &= ~(0xFF << 16);
  8428.         tmp |= (0x1C << 16);
  8429.         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  8430.  
  8431.         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  8432.         tmp |= (1 << 27);
  8433.         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  8434.  
  8435.         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  8436.         tmp |= (1 << 27);
  8437.         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  8438.  
  8439.         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  8440.         tmp &= ~(0xF << 28);
  8441.         tmp |= (4 << 28);
  8442.         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  8443.  
  8444.         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  8445.         tmp &= ~(0xF << 28);
  8446.         tmp |= (4 << 28);
  8447.         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  8448. }
  8449.  
  8450. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  8451.  * Programming" based on the parameters passed:
  8452.  * - Sequence to enable CLKOUT_DP
  8453.  * - Sequence to enable CLKOUT_DP without spread
  8454.  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  8455.  */
  8456. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  8457.                                  bool with_fdi)
  8458. {
  8459.         struct drm_i915_private *dev_priv = dev->dev_private;
  8460.         uint32_t reg, tmp;
  8461.  
  8462.         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  8463.                 with_spread = true;
  8464.         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
  8465.                 with_fdi = false;
  8466.  
  8467.         mutex_lock(&dev_priv->sb_lock);
  8468.  
  8469.         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  8470.         tmp &= ~SBI_SSCCTL_DISABLE;
  8471.         tmp |= SBI_SSCCTL_PATHALT;
  8472.         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  8473.  
  8474.         udelay(24);
  8475.  
  8476.         if (with_spread) {
  8477.                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  8478.                 tmp &= ~SBI_SSCCTL_PATHALT;
  8479.                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  8480.  
  8481.                 if (with_fdi) {
  8482.                         lpt_reset_fdi_mphy(dev_priv);
  8483.                         lpt_program_fdi_mphy(dev_priv);
  8484.                 }
  8485.         }
  8486.  
  8487.         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
  8488.         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  8489.         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  8490.         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  8491.  
  8492.         mutex_unlock(&dev_priv->sb_lock);
  8493. }
  8494.  
  8495. /* Sequence to disable CLKOUT_DP */
  8496. static void lpt_disable_clkout_dp(struct drm_device *dev)
  8497. {
  8498.         struct drm_i915_private *dev_priv = dev->dev_private;
  8499.         uint32_t reg, tmp;
  8500.  
  8501.         mutex_lock(&dev_priv->sb_lock);
  8502.  
  8503.         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
  8504.         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  8505.         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  8506.         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  8507.  
  8508.         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  8509.         if (!(tmp & SBI_SSCCTL_DISABLE)) {
  8510.                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
  8511.                         tmp |= SBI_SSCCTL_PATHALT;
  8512.                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  8513.                         udelay(32);
  8514.                 }
  8515.                 tmp |= SBI_SSCCTL_DISABLE;
  8516.                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  8517.         }
  8518.  
  8519.         mutex_unlock(&dev_priv->sb_lock);
  8520. }
  8521.  
  8522. static void lpt_init_pch_refclk(struct drm_device *dev)
  8523. {
  8524.         struct intel_encoder *encoder;
  8525.         bool has_vga = false;
  8526.  
  8527.         for_each_intel_encoder(dev, encoder) {
  8528.                 switch (encoder->type) {
  8529.                 case INTEL_OUTPUT_ANALOG:
  8530.                         has_vga = true;
  8531.                         break;
  8532.                 default:
  8533.                         break;
  8534.                 }
  8535.         }
  8536.  
  8537.         if (has_vga)
  8538.                 lpt_enable_clkout_dp(dev, true, true);
  8539.         else
  8540.                 lpt_disable_clkout_dp(dev);
  8541. }
  8542.  
  8543. /*
  8544.  * Initialize reference clocks when the driver loads
  8545.  */
  8546. void intel_init_pch_refclk(struct drm_device *dev)
  8547. {
  8548.         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  8549.                 ironlake_init_pch_refclk(dev);
  8550.         else if (HAS_PCH_LPT(dev))
  8551.                 lpt_init_pch_refclk(dev);
  8552. }
  8553.  
  8554. static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
  8555. {
  8556.         struct drm_device *dev = crtc_state->base.crtc->dev;
  8557.         struct drm_i915_private *dev_priv = dev->dev_private;
  8558.         struct drm_atomic_state *state = crtc_state->base.state;
  8559.         struct drm_connector *connector;
  8560.         struct drm_connector_state *connector_state;
  8561.         struct intel_encoder *encoder;
  8562.         int num_connectors = 0, i;
  8563.         bool is_lvds = false;
  8564.  
  8565.         for_each_connector_in_state(state, connector, connector_state, i) {
  8566.                 if (connector_state->crtc != crtc_state->base.crtc)
  8567.                         continue;
  8568.  
  8569.                 encoder = to_intel_encoder(connector_state->best_encoder);
  8570.  
  8571.                 switch (encoder->type) {
  8572.                 case INTEL_OUTPUT_LVDS:
  8573.                         is_lvds = true;
  8574.                         break;
  8575.                 default:
  8576.                         break;
  8577.                 }
  8578.                 num_connectors++;
  8579.         }
  8580.  
  8581.         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  8582.                 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
  8583.                               dev_priv->vbt.lvds_ssc_freq);
  8584.                 return dev_priv->vbt.lvds_ssc_freq;
  8585.         }
  8586.  
  8587.         return 120000;
  8588. }
  8589.  
  8590. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  8591. {
  8592.         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  8593.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  8594.         int pipe = intel_crtc->pipe;
  8595.         uint32_t val;
  8596.  
  8597.         val = 0;
  8598.  
  8599.         switch (intel_crtc->config->pipe_bpp) {
  8600.         case 18:
  8601.                 val |= PIPECONF_6BPC;
  8602.                 break;
  8603.         case 24:
  8604.                 val |= PIPECONF_8BPC;
  8605.                 break;
  8606.         case 30:
  8607.                 val |= PIPECONF_10BPC;
  8608.                 break;
  8609.         case 36:
  8610.                 val |= PIPECONF_12BPC;
  8611.                 break;
  8612.         default:
  8613.                 /* Case prevented by intel_choose_pipe_bpp_dither. */
  8614.                 BUG();
  8615.         }
  8616.  
  8617.         if (intel_crtc->config->dither)
  8618.                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  8619.  
  8620.         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  8621.                 val |= PIPECONF_INTERLACED_ILK;
  8622.         else
  8623.                 val |= PIPECONF_PROGRESSIVE;
  8624.  
  8625.         if (intel_crtc->config->limited_color_range)
  8626.                 val |= PIPECONF_COLOR_RANGE_SELECT;
  8627.  
  8628.         I915_WRITE(PIPECONF(pipe), val);
  8629.         POSTING_READ(PIPECONF(pipe));
  8630. }
  8631.  
  8632. /*
  8633.  * Set up the pipe CSC unit.
  8634.  *
  8635.  * Currently only full range RGB to limited range RGB conversion
  8636.  * is supported, but eventually this should handle various
  8637.  * RGB<->YCbCr scenarios as well.
  8638.  */
  8639. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  8640. {
  8641.         struct drm_device *dev = crtc->dev;
  8642.         struct drm_i915_private *dev_priv = dev->dev_private;
  8643.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  8644.         int pipe = intel_crtc->pipe;
  8645.         uint16_t coeff = 0x7800; /* 1.0 */
  8646.  
  8647.         /*
  8648.          * TODO: Check what kind of values actually come out of the pipe
  8649.          * with these coeff/postoff values and adjust to get the best
  8650.          * accuracy. Perhaps we even need to take the bpc value into
  8651.          * consideration.
  8652.          */
  8653.  
  8654.         if (intel_crtc->config->limited_color_range)
  8655.                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  8656.  
  8657.         /*
  8658.          * GY/GU and RY/RU should be the other way around according
  8659.          * to BSpec, but reality doesn't agree. Just set them up in
  8660.          * a way that results in the correct picture.
  8661.          */
  8662.         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  8663.         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  8664.  
  8665.         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  8666.         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  8667.  
  8668.         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  8669.         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  8670.  
  8671.         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  8672.         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  8673.         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  8674.  
  8675.         if (INTEL_INFO(dev)->gen > 6) {
  8676.                 uint16_t postoff = 0;
  8677.  
  8678.                 if (intel_crtc->config->limited_color_range)
  8679.                         postoff = (16 * (1 << 12) / 255) & 0x1fff;
  8680.  
  8681.                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  8682.                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  8683.                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  8684.  
  8685.                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  8686.         } else {
  8687.                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
  8688.  
  8689.                 if (intel_crtc->config->limited_color_range)
  8690.                         mode |= CSC_BLACK_SCREEN_OFFSET;
  8691.  
  8692.                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  8693.         }
  8694. }
  8695.  
  8696. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  8697. {
  8698.         struct drm_device *dev = crtc->dev;
  8699.         struct drm_i915_private *dev_priv = dev->dev_private;
  8700.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  8701.         enum pipe pipe = intel_crtc->pipe;
  8702.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  8703.         uint32_t val;
  8704.  
  8705.         val = 0;
  8706.  
  8707.         if (IS_HASWELL(dev) && intel_crtc->config->dither)
  8708.                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  8709.  
  8710.         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  8711.                 val |= PIPECONF_INTERLACED_ILK;
  8712.         else
  8713.                 val |= PIPECONF_PROGRESSIVE;
  8714.  
  8715.         I915_WRITE(PIPECONF(cpu_transcoder), val);
  8716.         POSTING_READ(PIPECONF(cpu_transcoder));
  8717.  
  8718.         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
  8719.         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
  8720.  
  8721.         if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
  8722.                 val = 0;
  8723.  
  8724.                 switch (intel_crtc->config->pipe_bpp) {
  8725.                 case 18:
  8726.                         val |= PIPEMISC_DITHER_6_BPC;
  8727.                         break;
  8728.                 case 24:
  8729.                         val |= PIPEMISC_DITHER_8_BPC;
  8730.                         break;
  8731.                 case 30:
  8732.                         val |= PIPEMISC_DITHER_10_BPC;
  8733.                         break;
  8734.                 case 36:
  8735.                         val |= PIPEMISC_DITHER_12_BPC;
  8736.                         break;
  8737.                 default:
  8738.                         /* Case prevented by pipe_config_set_bpp. */
  8739.                         BUG();
  8740.                 }
  8741.  
  8742.                 if (intel_crtc->config->dither)
  8743.                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
  8744.  
  8745.                 I915_WRITE(PIPEMISC(pipe), val);
  8746.         }
  8747. }
  8748.  
  8749. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  8750.                                     struct intel_crtc_state *crtc_state,
  8751.                                     intel_clock_t *clock,
  8752.                                     bool *has_reduced_clock,
  8753.                                     intel_clock_t *reduced_clock)
  8754. {
  8755.         struct drm_device *dev = crtc->dev;
  8756.         struct drm_i915_private *dev_priv = dev->dev_private;
  8757.         int refclk;
  8758.         const intel_limit_t *limit;
  8759.         bool ret;
  8760.  
  8761.         refclk = ironlake_get_refclk(crtc_state);
  8762.  
  8763.         /*
  8764.          * Returns a set of divisors for the desired target clock with the given
  8765.          * refclk, or FALSE.  The returned values represent the clock equation:
  8766.          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  8767.          */
  8768.         limit = intel_limit(crtc_state, refclk);
  8769.         ret = dev_priv->display.find_dpll(limit, crtc_state,
  8770.                                           crtc_state->port_clock,
  8771.                                           refclk, NULL, clock);
  8772.         if (!ret)
  8773.                 return false;
  8774.  
  8775.         return true;
  8776. }
  8777.  
  8778. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  8779. {
  8780.         /*
  8781.          * Account for spread spectrum to avoid
  8782.          * oversubscribing the link. Max center spread
  8783.          * is 2.5%; use 5% for safety's sake.
  8784.          */
  8785.         u32 bps = target_clock * bpp * 21 / 20;
  8786.         return DIV_ROUND_UP(bps, link_bw * 8);
  8787. }
  8788.  
  8789. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  8790. {
  8791.         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  8792. }
  8793.  
  8794. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  8795.                                       struct intel_crtc_state *crtc_state,
  8796.                                       u32 *fp,
  8797.                                       intel_clock_t *reduced_clock, u32 *fp2)
  8798. {
  8799.         struct drm_crtc *crtc = &intel_crtc->base;
  8800.         struct drm_device *dev = crtc->dev;
  8801.         struct drm_i915_private *dev_priv = dev->dev_private;
  8802.         struct drm_atomic_state *state = crtc_state->base.state;
  8803.         struct drm_connector *connector;
  8804.         struct drm_connector_state *connector_state;
  8805.         struct intel_encoder *encoder;
  8806.         uint32_t dpll;
  8807.         int factor, num_connectors = 0, i;
  8808.         bool is_lvds = false, is_sdvo = false;
  8809.  
  8810.         for_each_connector_in_state(state, connector, connector_state, i) {
  8811.                 if (connector_state->crtc != crtc_state->base.crtc)
  8812.                         continue;
  8813.  
  8814.                 encoder = to_intel_encoder(connector_state->best_encoder);
  8815.  
  8816.                 switch (encoder->type) {
  8817.                 case INTEL_OUTPUT_LVDS:
  8818.                         is_lvds = true;
  8819.                         break;
  8820.                 case INTEL_OUTPUT_SDVO:
  8821.                 case INTEL_OUTPUT_HDMI:
  8822.                         is_sdvo = true;
  8823.                         break;
  8824.                 default:
  8825.                         break;
  8826.                 }
  8827.  
  8828.                 num_connectors++;
  8829.         }
  8830.  
  8831.         /* Enable autotuning of the PLL clock (if permissible) */
  8832.         factor = 21;
  8833.         if (is_lvds) {
  8834.                 if ((intel_panel_use_ssc(dev_priv) &&
  8835.                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
  8836.                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  8837.                         factor = 25;
  8838.         } else if (crtc_state->sdvo_tv_clock)
  8839.                 factor = 20;
  8840.  
  8841.         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
  8842.                 *fp |= FP_CB_TUNE;
  8843.  
  8844.         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  8845.                 *fp2 |= FP_CB_TUNE;
  8846.  
  8847.         dpll = 0;
  8848.  
  8849.         if (is_lvds)
  8850.                 dpll |= DPLLB_MODE_LVDS;
  8851.         else
  8852.                 dpll |= DPLLB_MODE_DAC_SERIAL;
  8853.  
  8854.         dpll |= (crtc_state->pixel_multiplier - 1)
  8855.                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  8856.  
  8857.         if (is_sdvo)
  8858.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  8859.         if (crtc_state->has_dp_encoder)
  8860.                 dpll |= DPLL_SDVO_HIGH_SPEED;
  8861.  
  8862.         /* compute bitmask from p1 value */
  8863.         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  8864.         /* also FPA1 */
  8865.         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  8866.  
  8867.         switch (crtc_state->dpll.p2) {
  8868.         case 5:
  8869.                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  8870.                 break;
  8871.         case 7:
  8872.                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  8873.                 break;
  8874.         case 10:
  8875.                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  8876.                 break;
  8877.         case 14:
  8878.                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  8879.                 break;
  8880.         }
  8881.  
  8882.         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  8883.                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  8884.         else
  8885.                 dpll |= PLL_REF_INPUT_DREFCLK;
  8886.  
  8887.         return dpll | DPLL_VCO_ENABLE;
  8888. }
  8889.  
  8890. static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
  8891.                                        struct intel_crtc_state *crtc_state)
  8892. {
  8893.         struct drm_device *dev = crtc->base.dev;
  8894.         intel_clock_t clock, reduced_clock;
  8895.         u32 dpll = 0, fp = 0, fp2 = 0;
  8896.         bool ok, has_reduced_clock = false;
  8897.         bool is_lvds = false;
  8898.         struct intel_shared_dpll *pll;
  8899.  
  8900.         memset(&crtc_state->dpll_hw_state, 0,
  8901.                sizeof(crtc_state->dpll_hw_state));
  8902.  
  8903.         is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
  8904.  
  8905.         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  8906.              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  8907.  
  8908.         ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
  8909.                                      &has_reduced_clock, &reduced_clock);
  8910.         if (!ok && !crtc_state->clock_set) {
  8911.                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
  8912.                 return -EINVAL;
  8913.         }
  8914.         /* Compat-code for transition, will disappear. */
  8915.         if (!crtc_state->clock_set) {
  8916.                 crtc_state->dpll.n = clock.n;
  8917.                 crtc_state->dpll.m1 = clock.m1;
  8918.                 crtc_state->dpll.m2 = clock.m2;
  8919.                 crtc_state->dpll.p1 = clock.p1;
  8920.                 crtc_state->dpll.p2 = clock.p2;
  8921.         }
  8922.  
  8923.         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  8924.         if (crtc_state->has_pch_encoder) {
  8925.                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
  8926.                 if (has_reduced_clock)
  8927.                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
  8928.  
  8929.                 dpll = ironlake_compute_dpll(crtc, crtc_state,
  8930.                                              &fp, &reduced_clock,
  8931.                                              has_reduced_clock ? &fp2 : NULL);
  8932.  
  8933.                 crtc_state->dpll_hw_state.dpll = dpll;
  8934.                 crtc_state->dpll_hw_state.fp0 = fp;
  8935.                 if (has_reduced_clock)
  8936.                         crtc_state->dpll_hw_state.fp1 = fp2;
  8937.                 else
  8938.                         crtc_state->dpll_hw_state.fp1 = fp;
  8939.  
  8940.                 pll = intel_get_shared_dpll(crtc, crtc_state);
  8941.                 if (pll == NULL) {
  8942.                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  8943.                                          pipe_name(crtc->pipe));
  8944.                         return -EINVAL;
  8945.                 }
  8946.         }
  8947.  
  8948.         if (is_lvds && has_reduced_clock)
  8949.                 crtc->lowfreq_avail = true;
  8950.         else
  8951.                 crtc->lowfreq_avail = false;
  8952.  
  8953.         return 0;
  8954. }
  8955.  
  8956. static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
  8957.                                          struct intel_link_m_n *m_n)
  8958. {
  8959.         struct drm_device *dev = crtc->base.dev;
  8960.         struct drm_i915_private *dev_priv = dev->dev_private;
  8961.         enum pipe pipe = crtc->pipe;
  8962.  
  8963.         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
  8964.         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
  8965.         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
  8966.                 & ~TU_SIZE_MASK;
  8967.         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
  8968.         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
  8969.                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  8970. }
  8971.  
  8972. static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
  8973.                                          enum transcoder transcoder,
  8974.                                          struct intel_link_m_n *m_n,
  8975.                                          struct intel_link_m_n *m2_n2)
  8976. {
  8977.         struct drm_device *dev = crtc->base.dev;
  8978.         struct drm_i915_private *dev_priv = dev->dev_private;
  8979.         enum pipe pipe = crtc->pipe;
  8980.  
  8981.         if (INTEL_INFO(dev)->gen >= 5) {
  8982.                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
  8983.                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
  8984.                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  8985.                         & ~TU_SIZE_MASK;
  8986.                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  8987.                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  8988.                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  8989.                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
  8990.                  * gen < 8) and if DRRS is supported (to make sure the
  8991.                  * registers are not unnecessarily read).
  8992.                  */
  8993.                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
  8994.                         crtc->config->has_drrs) {
  8995.                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
  8996.                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
  8997.                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
  8998.                                         & ~TU_SIZE_MASK;
  8999.                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
  9000.                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
  9001.                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  9002.                 }
  9003.         } else {
  9004.                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
  9005.                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
  9006.                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
  9007.                         & ~TU_SIZE_MASK;
  9008.                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
  9009.                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
  9010.                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  9011.         }
  9012. }
  9013.  
  9014. void intel_dp_get_m_n(struct intel_crtc *crtc,
  9015.                       struct intel_crtc_state *pipe_config)
  9016. {
  9017.         if (pipe_config->has_pch_encoder)
  9018.                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
  9019.         else
  9020.                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  9021.                                              &pipe_config->dp_m_n,
  9022.                                              &pipe_config->dp_m2_n2);
  9023. }
  9024.  
  9025. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  9026.                                         struct intel_crtc_state *pipe_config)
  9027. {
  9028.         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
  9029.                                      &pipe_config->fdi_m_n, NULL);
  9030. }
  9031.  
  9032. static void skylake_get_pfit_config(struct intel_crtc *crtc,
  9033.                                     struct intel_crtc_state *pipe_config)
  9034. {
  9035.         struct drm_device *dev = crtc->base.dev;
  9036.         struct drm_i915_private *dev_priv = dev->dev_private;
  9037.         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
  9038.         uint32_t ps_ctrl = 0;
  9039.         int id = -1;
  9040.         int i;
  9041.  
  9042.         /* find scaler attached to this pipe */
  9043.         for (i = 0; i < crtc->num_scalers; i++) {
  9044.                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
  9045.                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
  9046.                         id = i;
  9047.                         pipe_config->pch_pfit.enabled = true;
  9048.                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
  9049.                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
  9050.                         break;
  9051.                 }
  9052.         }
  9053.  
  9054.         scaler_state->scaler_id = id;
  9055.         if (id >= 0) {
  9056.                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
  9057.         } else {
  9058.                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
  9059.         }
  9060. }
  9061.  
  9062. static void
  9063. skylake_get_initial_plane_config(struct intel_crtc *crtc,
  9064.                                  struct intel_initial_plane_config *plane_config)
  9065. {
  9066.         struct drm_device *dev = crtc->base.dev;
  9067.         struct drm_i915_private *dev_priv = dev->dev_private;
  9068.         u32 val, base, offset, stride_mult, tiling;
  9069.         int pipe = crtc->pipe;
  9070.         int fourcc, pixel_format;
  9071.         unsigned int aligned_height;
  9072.         struct drm_framebuffer *fb;
  9073.         struct intel_framebuffer *intel_fb;
  9074.  
  9075.         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  9076.         if (!intel_fb) {
  9077.                 DRM_DEBUG_KMS("failed to alloc fb\n");
  9078.                 return;
  9079.         }
  9080.  
  9081.         fb = &intel_fb->base;
  9082.  
  9083.         val = I915_READ(PLANE_CTL(pipe, 0));
  9084.         if (!(val & PLANE_CTL_ENABLE))
  9085.                 goto error;
  9086.  
  9087.         pixel_format = val & PLANE_CTL_FORMAT_MASK;
  9088.         fourcc = skl_format_to_fourcc(pixel_format,
  9089.                                       val & PLANE_CTL_ORDER_RGBX,
  9090.                                       val & PLANE_CTL_ALPHA_MASK);
  9091.         fb->pixel_format = fourcc;
  9092.         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  9093.  
  9094.         tiling = val & PLANE_CTL_TILED_MASK;
  9095.         switch (tiling) {
  9096.         case PLANE_CTL_TILED_LINEAR:
  9097.                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
  9098.                 break;
  9099.         case PLANE_CTL_TILED_X:
  9100.                 plane_config->tiling = I915_TILING_X;
  9101.                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
  9102.                 break;
  9103.         case PLANE_CTL_TILED_Y:
  9104.                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
  9105.                 break;
  9106.         case PLANE_CTL_TILED_YF:
  9107.                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
  9108.                 break;
  9109.         default:
  9110.                 MISSING_CASE(tiling);
  9111.                 goto error;
  9112.         }
  9113.  
  9114.         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
  9115.         plane_config->base = base;
  9116.  
  9117.         offset = I915_READ(PLANE_OFFSET(pipe, 0));
  9118.  
  9119.         val = I915_READ(PLANE_SIZE(pipe, 0));
  9120.         fb->height = ((val >> 16) & 0xfff) + 1;
  9121.         fb->width = ((val >> 0) & 0x1fff) + 1;
  9122.  
  9123.         val = I915_READ(PLANE_STRIDE(pipe, 0));
  9124.         stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
  9125.                                                 fb->pixel_format);
  9126. //   fb->pitches[0] = (val & 0x3ff) * stride_mult;
  9127.     fb->pitches[0] = 2560*4;
  9128.  
  9129.         aligned_height = intel_fb_align_height(dev, fb->height,
  9130.                                                fb->pixel_format,
  9131.                                                fb->modifier[0]);
  9132.  
  9133. //   plane_config->size = fb->pitches[0] * aligned_height;
  9134.     plane_config->size = i915.fbsize*1024*1024;
  9135.  
  9136.         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
  9137.                       pipe_name(pipe), fb->width, fb->height,
  9138.                       fb->bits_per_pixel, base, fb->pitches[0],
  9139.                       plane_config->size);
  9140.  
  9141.         plane_config->fb = intel_fb;
  9142.         return;
  9143.  
  9144. error:
  9145.         kfree(fb);
  9146. }
  9147.  
  9148. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  9149.                                      struct intel_crtc_state *pipe_config)
  9150. {
  9151.         struct drm_device *dev = crtc->base.dev;
  9152.         struct drm_i915_private *dev_priv = dev->dev_private;
  9153.         uint32_t tmp;
  9154.  
  9155.         tmp = I915_READ(PF_CTL(crtc->pipe));
  9156.  
  9157.         if (tmp & PF_ENABLE) {
  9158.                 pipe_config->pch_pfit.enabled = true;
  9159.                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  9160.                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  9161.  
  9162.                 /* We currently do not free assignements of panel fitters on
  9163.                  * ivb/hsw (since we don't use the higher upscaling modes which
  9164.                  * differentiates them) so just WARN about this case for now. */
  9165.                 if (IS_GEN7(dev)) {
  9166.                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  9167.                                 PF_PIPE_SEL_IVB(crtc->pipe));
  9168.                 }
  9169.         }
  9170. }
  9171.  
  9172. static void
  9173. ironlake_get_initial_plane_config(struct intel_crtc *crtc,
  9174.                                   struct intel_initial_plane_config *plane_config)
  9175. {
  9176.         struct drm_device *dev = crtc->base.dev;
  9177.         struct drm_i915_private *dev_priv = dev->dev_private;
  9178.         u32 val, base, offset;
  9179.         int pipe = crtc->pipe;
  9180.         int fourcc, pixel_format;
  9181.         unsigned int aligned_height;
  9182.         struct drm_framebuffer *fb;
  9183.         struct intel_framebuffer *intel_fb;
  9184.  
  9185.         val = I915_READ(DSPCNTR(pipe));
  9186.         if (!(val & DISPLAY_PLANE_ENABLE))
  9187.                 return;
  9188.  
  9189.         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  9190.         if (!intel_fb) {
  9191.                 DRM_DEBUG_KMS("failed to alloc fb\n");
  9192.                 return;
  9193.         }
  9194.  
  9195.         fb = &intel_fb->base;
  9196.  
  9197.         if (INTEL_INFO(dev)->gen >= 4) {
  9198.                 if (val & DISPPLANE_TILED) {
  9199.                         plane_config->tiling = I915_TILING_X;
  9200.                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
  9201.                 }
  9202.         }
  9203.  
  9204.         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
  9205.         fourcc = i9xx_format_to_fourcc(pixel_format);
  9206.         fb->pixel_format = fourcc;
  9207.         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
  9208.  
  9209.         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
  9210.         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  9211.                 offset = I915_READ(DSPOFFSET(pipe));
  9212.         } else {
  9213.                 if (plane_config->tiling)
  9214.                         offset = I915_READ(DSPTILEOFF(pipe));
  9215.                 else
  9216.                         offset = I915_READ(DSPLINOFF(pipe));
  9217.         }
  9218.         plane_config->base = base;
  9219.  
  9220.         val = I915_READ(PIPESRC(pipe));
  9221.         fb->width = ((val >> 16) & 0xfff) + 1;
  9222.         fb->height = ((val >> 0) & 0xfff) + 1;
  9223.  
  9224.         val = I915_READ(DSPSTRIDE(pipe));
  9225. //   fb->pitches[0] = val & 0xffffffc0;
  9226.     fb->pitches[0] = 2560*4;
  9227.  
  9228.         aligned_height = intel_fb_align_height(dev, fb->height,
  9229.                                                fb->pixel_format,
  9230.                                                fb->modifier[0]);
  9231.  
  9232. //   plane_config->size = fb->pitches[0] * aligned_height;
  9233.     plane_config->size = i915.fbsize*1024*1024;
  9234.  
  9235.         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
  9236.                       pipe_name(pipe), fb->width, fb->height,
  9237.                       fb->bits_per_pixel, base, fb->pitches[0],
  9238.                       plane_config->size);
  9239.  
  9240.         plane_config->fb = intel_fb;
  9241. }
  9242.  
  9243. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  9244.                                      struct intel_crtc_state *pipe_config)
  9245. {
  9246.         struct drm_device *dev = crtc->base.dev;
  9247.         struct drm_i915_private *dev_priv = dev->dev_private;
  9248.         uint32_t tmp;
  9249.  
  9250.         if (!intel_display_power_is_enabled(dev_priv,
  9251.                                             POWER_DOMAIN_PIPE(crtc->pipe)))
  9252.                 return false;
  9253.  
  9254.         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  9255.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  9256.  
  9257.         tmp = I915_READ(PIPECONF(crtc->pipe));
  9258.         if (!(tmp & PIPECONF_ENABLE))
  9259.                 return false;
  9260.  
  9261.         switch (tmp & PIPECONF_BPC_MASK) {
  9262.         case PIPECONF_6BPC:
  9263.                 pipe_config->pipe_bpp = 18;
  9264.                 break;
  9265.         case PIPECONF_8BPC:
  9266.                 pipe_config->pipe_bpp = 24;
  9267.                 break;
  9268.         case PIPECONF_10BPC:
  9269.                 pipe_config->pipe_bpp = 30;
  9270.                 break;
  9271.         case PIPECONF_12BPC:
  9272.                 pipe_config->pipe_bpp = 36;
  9273.                 break;
  9274.         default:
  9275.                 break;
  9276.         }
  9277.  
  9278.         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
  9279.                 pipe_config->limited_color_range = true;
  9280.  
  9281.         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  9282.                 struct intel_shared_dpll *pll;
  9283.  
  9284.                 pipe_config->has_pch_encoder = true;
  9285.  
  9286.                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  9287.                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  9288.                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
  9289.  
  9290.                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
  9291.  
  9292.                 if (HAS_PCH_IBX(dev_priv->dev)) {
  9293.                         pipe_config->shared_dpll =
  9294.                                 (enum intel_dpll_id) crtc->pipe;
  9295.                 } else {
  9296.                         tmp = I915_READ(PCH_DPLL_SEL);
  9297.                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  9298.                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
  9299.                         else
  9300.                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
  9301.                 }
  9302.  
  9303.                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  9304.  
  9305.                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
  9306.                                            &pipe_config->dpll_hw_state));
  9307.  
  9308.                 tmp = pipe_config->dpll_hw_state.dpll;
  9309.                 pipe_config->pixel_multiplier =
  9310.                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  9311.                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  9312.  
  9313.                 ironlake_pch_clock_get(crtc, pipe_config);
  9314.         } else {
  9315.                 pipe_config->pixel_multiplier = 1;
  9316.         }
  9317.  
  9318.         intel_get_pipe_timings(crtc, pipe_config);
  9319.  
  9320.         ironlake_get_pfit_config(crtc, pipe_config);
  9321.  
  9322.         return true;
  9323. }
  9324.  
  9325. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  9326. {
  9327.         struct drm_device *dev = dev_priv->dev;
  9328.         struct intel_crtc *crtc;
  9329.  
  9330.         for_each_intel_crtc(dev, crtc)
  9331.                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
  9332.                      pipe_name(crtc->pipe));
  9333.  
  9334.         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  9335.         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
  9336.         I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
  9337.         I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
  9338.         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  9339.         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  9340.              "CPU PWM1 enabled\n");
  9341.         if (IS_HASWELL(dev))
  9342.                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  9343.                      "CPU PWM2 enabled\n");
  9344.         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  9345.              "PCH PWM1 enabled\n");
  9346.         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  9347.              "Utility pin enabled\n");
  9348.         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  9349.  
  9350.         /*
  9351.          * In theory we can still leave IRQs enabled, as long as only the HPD
  9352.          * interrupts remain enabled. We used to check for that, but since it's
  9353.          * gen-specific and since we only disable LCPLL after we fully disable
  9354.          * the interrupts, the check below should be enough.
  9355.          */
  9356.         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
  9357. }
  9358.  
  9359. static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
  9360. {
  9361.         struct drm_device *dev = dev_priv->dev;
  9362.  
  9363.         if (IS_HASWELL(dev))
  9364.                 return I915_READ(D_COMP_HSW);
  9365.         else
  9366.                 return I915_READ(D_COMP_BDW);
  9367. }
  9368.  
  9369. static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
  9370. {
  9371.         struct drm_device *dev = dev_priv->dev;
  9372.  
  9373.         if (IS_HASWELL(dev)) {
  9374.                 mutex_lock(&dev_priv->rps.hw_lock);
  9375.                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
  9376.                                             val))
  9377.                         DRM_ERROR("Failed to write to D_COMP\n");
  9378.                 mutex_unlock(&dev_priv->rps.hw_lock);
  9379.         } else {
  9380.                 I915_WRITE(D_COMP_BDW, val);
  9381.                 POSTING_READ(D_COMP_BDW);
  9382.         }
  9383. }
  9384.  
  9385. /*
  9386.  * This function implements pieces of two sequences from BSpec:
  9387.  * - Sequence for display software to disable LCPLL
  9388.  * - Sequence for display software to allow package C8+
  9389.  * The steps implemented here are just the steps that actually touch the LCPLL
  9390.  * register. Callers should take care of disabling all the display engine
  9391.  * functions, doing the mode unset, fixing interrupts, etc.
  9392.  */
  9393. static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  9394.                               bool switch_to_fclk, bool allow_power_down)
  9395. {
  9396.         uint32_t val;
  9397.  
  9398.         assert_can_disable_lcpll(dev_priv);
  9399.  
  9400.         val = I915_READ(LCPLL_CTL);
  9401.  
  9402.         if (switch_to_fclk) {
  9403.                 val |= LCPLL_CD_SOURCE_FCLK;
  9404.                 I915_WRITE(LCPLL_CTL, val);
  9405.  
  9406.                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  9407.                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
  9408.                         DRM_ERROR("Switching to FCLK failed\n");
  9409.  
  9410.                 val = I915_READ(LCPLL_CTL);
  9411.         }
  9412.  
  9413.         val |= LCPLL_PLL_DISABLE;
  9414.         I915_WRITE(LCPLL_CTL, val);
  9415.         POSTING_READ(LCPLL_CTL);
  9416.  
  9417.         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  9418.                 DRM_ERROR("LCPLL still locked\n");
  9419.  
  9420.         val = hsw_read_dcomp(dev_priv);
  9421.         val |= D_COMP_COMP_DISABLE;
  9422.         hsw_write_dcomp(dev_priv, val);
  9423.         ndelay(100);
  9424.  
  9425.         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
  9426.                      1))
  9427.                 DRM_ERROR("D_COMP RCOMP still in progress\n");
  9428.  
  9429.         if (allow_power_down) {
  9430.                 val = I915_READ(LCPLL_CTL);
  9431.                 val |= LCPLL_POWER_DOWN_ALLOW;
  9432.                 I915_WRITE(LCPLL_CTL, val);
  9433.                 POSTING_READ(LCPLL_CTL);
  9434.         }
  9435. }
  9436.  
  9437. /*
  9438.  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  9439.  * source.
  9440.  */
  9441. static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  9442. {
  9443.         uint32_t val;
  9444.  
  9445.         val = I915_READ(LCPLL_CTL);
  9446.  
  9447.         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  9448.                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  9449.                 return;
  9450.  
  9451.         /*
  9452.          * Make sure we're not on PC8 state before disabling PC8, otherwise
  9453.          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
  9454.          */
  9455.         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  9456.  
  9457.         if (val & LCPLL_POWER_DOWN_ALLOW) {
  9458.                 val &= ~LCPLL_POWER_DOWN_ALLOW;
  9459.                 I915_WRITE(LCPLL_CTL, val);
  9460.                 POSTING_READ(LCPLL_CTL);
  9461.         }
  9462.  
  9463.         val = hsw_read_dcomp(dev_priv);
  9464.         val |= D_COMP_COMP_FORCE;
  9465.         val &= ~D_COMP_COMP_DISABLE;
  9466.         hsw_write_dcomp(dev_priv, val);
  9467.  
  9468.         val = I915_READ(LCPLL_CTL);
  9469.         val &= ~LCPLL_PLL_DISABLE;
  9470.         I915_WRITE(LCPLL_CTL, val);
  9471.  
  9472.         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  9473.                 DRM_ERROR("LCPLL not locked yet\n");
  9474.  
  9475.         if (val & LCPLL_CD_SOURCE_FCLK) {
  9476.                 val = I915_READ(LCPLL_CTL);
  9477.                 val &= ~LCPLL_CD_SOURCE_FCLK;
  9478.                 I915_WRITE(LCPLL_CTL, val);
  9479.  
  9480.                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  9481.                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  9482.                         DRM_ERROR("Switching back to LCPLL failed\n");
  9483.         }
  9484.  
  9485.         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  9486.         intel_update_cdclk(dev_priv->dev);
  9487. }
  9488.  
  9489. /*
  9490.  * Package states C8 and deeper are really deep PC states that can only be
  9491.  * reached when all the devices on the system allow it, so even if the graphics
  9492.  * device allows PC8+, it doesn't mean the system will actually get to these
  9493.  * states. Our driver only allows PC8+ when going into runtime PM.
  9494.  *
  9495.  * The requirements for PC8+ are that all the outputs are disabled, the power
  9496.  * well is disabled and most interrupts are disabled, and these are also
  9497.  * requirements for runtime PM. When these conditions are met, we manually do
  9498.  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
  9499.  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
  9500.  * hang the machine.
  9501.  *
  9502.  * When we really reach PC8 or deeper states (not just when we allow it) we lose
  9503.  * the state of some registers, so when we come back from PC8+ we need to
  9504.  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
  9505.  * need to take care of the registers kept by RC6. Notice that this happens even
  9506.  * if we don't put the device in PCI D3 state (which is what currently happens
  9507.  * because of the runtime PM support).
  9508.  *
  9509.  * For more, read "Display Sequences for Package C8" on the hardware
  9510.  * documentation.
  9511.  */
  9512. void hsw_enable_pc8(struct drm_i915_private *dev_priv)
  9513. {
  9514.         struct drm_device *dev = dev_priv->dev;
  9515.         uint32_t val;
  9516.  
  9517.         DRM_DEBUG_KMS("Enabling package C8+\n");
  9518.  
  9519.         if (HAS_PCH_LPT_LP(dev)) {
  9520.                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
  9521.                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
  9522.                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  9523.         }
  9524.  
  9525.         lpt_disable_clkout_dp(dev);
  9526.         hsw_disable_lcpll(dev_priv, true, true);
  9527. }
  9528.  
  9529. void hsw_disable_pc8(struct drm_i915_private *dev_priv)
  9530. {
  9531.         struct drm_device *dev = dev_priv->dev;
  9532.         uint32_t val;
  9533.  
  9534.         DRM_DEBUG_KMS("Disabling package C8+\n");
  9535.  
  9536.         hsw_restore_lcpll(dev_priv);
  9537.         lpt_init_pch_refclk(dev);
  9538.  
  9539.         if (HAS_PCH_LPT_LP(dev)) {
  9540.                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
  9541.                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
  9542.                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
  9543.         }
  9544.  
  9545.         intel_prepare_ddi(dev);
  9546. }
  9547.  
  9548. static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
  9549. {
  9550.         struct drm_device *dev = old_state->dev;
  9551.         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
  9552.  
  9553.         broxton_set_cdclk(dev, req_cdclk);
  9554. }
  9555.  
  9556. /* compute the max rate for new configuration */
  9557. static int ilk_max_pixel_rate(struct drm_atomic_state *state)
  9558. {
  9559.         struct intel_crtc *intel_crtc;
  9560.         struct intel_crtc_state *crtc_state;
  9561.         int max_pixel_rate = 0;
  9562.  
  9563.         for_each_intel_crtc(state->dev, intel_crtc) {
  9564.                 int pixel_rate;
  9565.  
  9566.                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
  9567.                 if (IS_ERR(crtc_state))
  9568.                         return PTR_ERR(crtc_state);
  9569.  
  9570.                 if (!crtc_state->base.enable)
  9571.                         continue;
  9572.  
  9573.                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
  9574.  
  9575.                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
  9576.                 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
  9577.                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
  9578.  
  9579.                 max_pixel_rate = max(max_pixel_rate, pixel_rate);
  9580.         }
  9581.  
  9582.         return max_pixel_rate;
  9583. }
  9584.  
  9585. static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
  9586. {
  9587.         struct drm_i915_private *dev_priv = dev->dev_private;
  9588.         uint32_t val, data;
  9589.         int ret;
  9590.  
  9591.         if (WARN((I915_READ(LCPLL_CTL) &
  9592.                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
  9593.                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
  9594.                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
  9595.                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
  9596.                  "trying to change cdclk frequency with cdclk not enabled\n"))
  9597.                 return;
  9598.  
  9599.         mutex_lock(&dev_priv->rps.hw_lock);
  9600.         ret = sandybridge_pcode_write(dev_priv,
  9601.                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
  9602.         mutex_unlock(&dev_priv->rps.hw_lock);
  9603.         if (ret) {
  9604.                 DRM_ERROR("failed to inform pcode about cdclk change\n");
  9605.                 return;
  9606.         }
  9607.  
  9608.         val = I915_READ(LCPLL_CTL);
  9609.         val |= LCPLL_CD_SOURCE_FCLK;
  9610.         I915_WRITE(LCPLL_CTL, val);
  9611.  
  9612.         if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  9613.                                LCPLL_CD_SOURCE_FCLK_DONE, 1))
  9614.                 DRM_ERROR("Switching to FCLK failed\n");
  9615.  
  9616.         val = I915_READ(LCPLL_CTL);
  9617.         val &= ~LCPLL_CLK_FREQ_MASK;
  9618.  
  9619.         switch (cdclk) {
  9620.         case 450000:
  9621.                 val |= LCPLL_CLK_FREQ_450;
  9622.                 data = 0;
  9623.                 break;
  9624.         case 540000:
  9625.                 val |= LCPLL_CLK_FREQ_54O_BDW;
  9626.                 data = 1;
  9627.                 break;
  9628.         case 337500:
  9629.                 val |= LCPLL_CLK_FREQ_337_5_BDW;
  9630.                 data = 2;
  9631.                 break;
  9632.         case 675000:
  9633.                 val |= LCPLL_CLK_FREQ_675_BDW;
  9634.                 data = 3;
  9635.                 break;
  9636.         default:
  9637.                 WARN(1, "invalid cdclk frequency\n");
  9638.                 return;
  9639.         }
  9640.  
  9641.         I915_WRITE(LCPLL_CTL, val);
  9642.  
  9643.         val = I915_READ(LCPLL_CTL);
  9644.         val &= ~LCPLL_CD_SOURCE_FCLK;
  9645.         I915_WRITE(LCPLL_CTL, val);
  9646.  
  9647.         if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  9648.                                 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  9649.                 DRM_ERROR("Switching back to LCPLL failed\n");
  9650.  
  9651.         mutex_lock(&dev_priv->rps.hw_lock);
  9652.         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
  9653.         mutex_unlock(&dev_priv->rps.hw_lock);
  9654.  
  9655.         intel_update_cdclk(dev);
  9656.  
  9657.         WARN(cdclk != dev_priv->cdclk_freq,
  9658.              "cdclk requested %d kHz but got %d kHz\n",
  9659.              cdclk, dev_priv->cdclk_freq);
  9660. }
  9661.  
  9662. static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
  9663. {
  9664.         struct drm_i915_private *dev_priv = to_i915(state->dev);
  9665.         int max_pixclk = ilk_max_pixel_rate(state);
  9666.         int cdclk;
  9667.  
  9668.         /*
  9669.          * FIXME should also account for plane ratio
  9670.          * once 64bpp pixel formats are supported.
  9671.          */
  9672.         if (max_pixclk > 540000)
  9673.                 cdclk = 675000;
  9674.         else if (max_pixclk > 450000)
  9675.                 cdclk = 540000;
  9676.         else if (max_pixclk > 337500)
  9677.                 cdclk = 450000;
  9678.         else
  9679.                 cdclk = 337500;
  9680.  
  9681.         /*
  9682.          * FIXME move the cdclk caclulation to
  9683.          * compute_config() so we can fail gracegully.
  9684.          */
  9685.         if (cdclk > dev_priv->max_cdclk_freq) {
  9686.                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
  9687.                           cdclk, dev_priv->max_cdclk_freq);
  9688.                 cdclk = dev_priv->max_cdclk_freq;
  9689.         }
  9690.  
  9691.         to_intel_atomic_state(state)->cdclk = cdclk;
  9692.  
  9693.         return 0;
  9694. }
  9695.  
  9696. static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
  9697. {
  9698.         struct drm_device *dev = old_state->dev;
  9699.         unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
  9700.  
  9701.         broadwell_set_cdclk(dev, req_cdclk);
  9702. }
  9703.  
  9704. static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
  9705.                                       struct intel_crtc_state *crtc_state)
  9706. {
  9707.         if (!intel_ddi_pll_select(crtc, crtc_state))
  9708.                 return -EINVAL;
  9709.  
  9710.         crtc->lowfreq_avail = false;
  9711.  
  9712.         return 0;
  9713. }
  9714.  
  9715. static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
  9716.                                 enum port port,
  9717.                                 struct intel_crtc_state *pipe_config)
  9718. {
  9719.         switch (port) {
  9720.         case PORT_A:
  9721.                 pipe_config->ddi_pll_sel = SKL_DPLL0;
  9722.                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
  9723.                 break;
  9724.         case PORT_B:
  9725.                 pipe_config->ddi_pll_sel = SKL_DPLL1;
  9726.                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
  9727.                 break;
  9728.         case PORT_C:
  9729.                 pipe_config->ddi_pll_sel = SKL_DPLL2;
  9730.                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
  9731.                 break;
  9732.         default:
  9733.                 DRM_ERROR("Incorrect port type\n");
  9734.         }
  9735. }
  9736.  
  9737. static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
  9738.                                 enum port port,
  9739.                                 struct intel_crtc_state *pipe_config)
  9740. {
  9741.         u32 temp, dpll_ctl1;
  9742.  
  9743.         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
  9744.         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
  9745.  
  9746.         switch (pipe_config->ddi_pll_sel) {
  9747.         case SKL_DPLL0:
  9748.                 /*
  9749.                  * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
  9750.                  * of the shared DPLL framework and thus needs to be read out
  9751.                  * separately
  9752.                  */
  9753.                 dpll_ctl1 = I915_READ(DPLL_CTRL1);
  9754.                 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
  9755.                 break;
  9756.         case SKL_DPLL1:
  9757.                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
  9758.                 break;
  9759.         case SKL_DPLL2:
  9760.                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
  9761.                 break;
  9762.         case SKL_DPLL3:
  9763.                 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
  9764.                 break;
  9765.         }
  9766. }
  9767.  
  9768. static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
  9769.                                 enum port port,
  9770.                                 struct intel_crtc_state *pipe_config)
  9771. {
  9772.         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
  9773.  
  9774.         switch (pipe_config->ddi_pll_sel) {
  9775.         case PORT_CLK_SEL_WRPLL1:
  9776.                 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
  9777.                 break;
  9778.         case PORT_CLK_SEL_WRPLL2:
  9779.                 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
  9780.                 break;
  9781.         case PORT_CLK_SEL_SPLL:
  9782.                 pipe_config->shared_dpll = DPLL_ID_SPLL;
  9783.         }
  9784. }
  9785.  
  9786. static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
  9787.                                        struct intel_crtc_state *pipe_config)
  9788. {
  9789.         struct drm_device *dev = crtc->base.dev;
  9790.         struct drm_i915_private *dev_priv = dev->dev_private;
  9791.         struct intel_shared_dpll *pll;
  9792.         enum port port;
  9793.         uint32_t tmp;
  9794.  
  9795.         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  9796.  
  9797.         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
  9798.  
  9799.         if (IS_SKYLAKE(dev))
  9800.                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
  9801.         else if (IS_BROXTON(dev))
  9802.                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
  9803.         else
  9804.                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
  9805.  
  9806.         if (pipe_config->shared_dpll >= 0) {
  9807.                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  9808.  
  9809.                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
  9810.                                            &pipe_config->dpll_hw_state));
  9811.         }
  9812.  
  9813.         /*
  9814.          * Haswell has only FDI/PCH transcoder A. It is which is connected to
  9815.          * DDI E. So just check whether this pipe is wired to DDI E and whether
  9816.          * the PCH transcoder is on.
  9817.          */
  9818.         if (INTEL_INFO(dev)->gen < 9 &&
  9819.             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  9820.                 pipe_config->has_pch_encoder = true;
  9821.  
  9822.                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  9823.                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  9824.                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
  9825.  
  9826.                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
  9827.         }
  9828. }
  9829.  
  9830. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  9831.                                     struct intel_crtc_state *pipe_config)
  9832. {
  9833.         struct drm_device *dev = crtc->base.dev;
  9834.         struct drm_i915_private *dev_priv = dev->dev_private;
  9835.         enum intel_display_power_domain pfit_domain;
  9836.         uint32_t tmp;
  9837.  
  9838.         if (!intel_display_power_is_enabled(dev_priv,
  9839.                                          POWER_DOMAIN_PIPE(crtc->pipe)))
  9840.                 return false;
  9841.  
  9842.         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  9843.         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  9844.  
  9845.         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  9846.         if (tmp & TRANS_DDI_FUNC_ENABLE) {
  9847.                 enum pipe trans_edp_pipe;
  9848.                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  9849.                 default:
  9850.                         WARN(1, "unknown pipe linked to edp transcoder\n");
  9851.                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
  9852.                 case TRANS_DDI_EDP_INPUT_A_ON:
  9853.                         trans_edp_pipe = PIPE_A;
  9854.                         break;
  9855.                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
  9856.                         trans_edp_pipe = PIPE_B;
  9857.                         break;
  9858.                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
  9859.                         trans_edp_pipe = PIPE_C;
  9860.                         break;
  9861.                 }
  9862.  
  9863.                 if (trans_edp_pipe == crtc->pipe)
  9864.                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
  9865.         }
  9866.  
  9867.         if (!intel_display_power_is_enabled(dev_priv,
  9868.                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
  9869.                 return false;
  9870.  
  9871.         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  9872.         if (!(tmp & PIPECONF_ENABLE))
  9873.                 return false;
  9874.  
  9875.         haswell_get_ddi_port_state(crtc, pipe_config);
  9876.  
  9877.         intel_get_pipe_timings(crtc, pipe_config);
  9878.  
  9879.         if (INTEL_INFO(dev)->gen >= 9) {
  9880.                 skl_init_scalers(dev, crtc, pipe_config);
  9881.         }
  9882.  
  9883.         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  9884.  
  9885.         if (INTEL_INFO(dev)->gen >= 9) {
  9886.                 pipe_config->scaler_state.scaler_id = -1;
  9887.                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
  9888.         }
  9889.  
  9890.         if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
  9891.                 if (INTEL_INFO(dev)->gen >= 9)
  9892.                         skylake_get_pfit_config(crtc, pipe_config);
  9893.                 else
  9894.                         ironlake_get_pfit_config(crtc, pipe_config);
  9895.         }
  9896.  
  9897.         if (IS_HASWELL(dev))
  9898.                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  9899.                         (I915_READ(IPS_CTL) & IPS_ENABLE);
  9900.  
  9901.         if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
  9902.                 pipe_config->pixel_multiplier =
  9903.                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
  9904.         } else {
  9905.                 pipe_config->pixel_multiplier = 1;
  9906.         }
  9907.  
  9908.         return true;
  9909. }
  9910.  
  9911. static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
  9912. {
  9913.         struct drm_device *dev = crtc->dev;
  9914.         struct drm_i915_private *dev_priv = dev->dev_private;
  9915.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9916.         uint32_t cntl = 0, size = 0;
  9917.  
  9918.         if (on) {
  9919.                 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
  9920.                 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
  9921.                 unsigned int stride = roundup_pow_of_two(width) * 4;
  9922.  
  9923.                 switch (stride) {
  9924.                 default:
  9925.                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
  9926.                                   width, stride);
  9927.                         stride = 256;
  9928.                         /* fallthrough */
  9929.                 case 256:
  9930.                 case 512:
  9931.                 case 1024:
  9932.                 case 2048:
  9933.                         break;
  9934.                 }
  9935.  
  9936.                 cntl |= CURSOR_ENABLE |
  9937.                         CURSOR_GAMMA_ENABLE |
  9938.                         CURSOR_FORMAT_ARGB |
  9939.                         CURSOR_STRIDE(stride);
  9940.  
  9941.                 size = (height << 12) | width;
  9942.         }
  9943.  
  9944.         if (intel_crtc->cursor_cntl != 0 &&
  9945.             (intel_crtc->cursor_base != base ||
  9946.              intel_crtc->cursor_size != size ||
  9947.              intel_crtc->cursor_cntl != cntl)) {
  9948.                 /* On these chipsets we can only modify the base/size/stride
  9949.                  * whilst the cursor is disabled.
  9950.                  */
  9951.                 I915_WRITE(CURCNTR(PIPE_A), 0);
  9952.                 POSTING_READ(CURCNTR(PIPE_A));
  9953.                 intel_crtc->cursor_cntl = 0;
  9954.         }
  9955.  
  9956.         if (intel_crtc->cursor_base != base) {
  9957.                 I915_WRITE(CURBASE(PIPE_A), base);
  9958.                 intel_crtc->cursor_base = base;
  9959.         }
  9960.  
  9961.         if (intel_crtc->cursor_size != size) {
  9962.                 I915_WRITE(CURSIZE, size);
  9963.                 intel_crtc->cursor_size = size;
  9964.         }
  9965.  
  9966.         if (intel_crtc->cursor_cntl != cntl) {
  9967.                 I915_WRITE(CURCNTR(PIPE_A), cntl);
  9968.                 POSTING_READ(CURCNTR(PIPE_A));
  9969.                 intel_crtc->cursor_cntl = cntl;
  9970.         }
  9971. }
  9972.  
  9973. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on)
  9974. {
  9975.         struct drm_device *dev = crtc->dev;
  9976.         struct drm_i915_private *dev_priv = dev->dev_private;
  9977.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  9978.         int pipe = intel_crtc->pipe;
  9979.         uint32_t cntl = 0;
  9980.  
  9981.         if (on) {
  9982.                 cntl = MCURSOR_GAMMA_ENABLE;
  9983.                 switch (intel_crtc->base.cursor->state->crtc_w) {
  9984.                         case 64:
  9985.                                 cntl |= CURSOR_MODE_64_ARGB_AX;
  9986.                                 break;
  9987.                         case 128:
  9988.                                 cntl |= CURSOR_MODE_128_ARGB_AX;
  9989.                                 break;
  9990.                         case 256:
  9991.                                 cntl |= CURSOR_MODE_256_ARGB_AX;
  9992.                                 break;
  9993.                         default:
  9994.                                 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
  9995.                                 return;
  9996.                 }
  9997.                 cntl |= pipe << 28; /* Connect to correct pipe */
  9998.  
  9999.                 if (HAS_DDI(dev))
  10000.                         cntl |= CURSOR_PIPE_CSC_ENABLE;
  10001.         }
  10002.  
  10003.         if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
  10004.                 cntl |= CURSOR_ROTATE_180;
  10005.  
  10006.         if (intel_crtc->cursor_cntl != cntl) {
  10007.                 I915_WRITE(CURCNTR(pipe), cntl);
  10008.                 POSTING_READ(CURCNTR(pipe));
  10009.                 intel_crtc->cursor_cntl = cntl;
  10010.         }
  10011.  
  10012.         /* and commit changes on next vblank */
  10013.         I915_WRITE(CURBASE(pipe), base);
  10014.         POSTING_READ(CURBASE(pipe));
  10015.  
  10016.         intel_crtc->cursor_base = base;
  10017. }
  10018.  
  10019. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  10020. void intel_crtc_update_cursor(struct drm_crtc *crtc,
  10021.                                      bool on)
  10022. {
  10023.         struct drm_device *dev = crtc->dev;
  10024.         struct drm_i915_private *dev_priv = dev->dev_private;
  10025.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10026.         int pipe = intel_crtc->pipe;
  10027.         struct drm_plane_state *cursor_state = crtc->cursor->state;
  10028.         int x = cursor_state->crtc_x;
  10029.         int y = cursor_state->crtc_y;
  10030.         u32 base = 0, pos = 0;
  10031.  
  10032.         base = intel_crtc->cursor_addr;
  10033.  
  10034.         if (x >= intel_crtc->config->pipe_src_w)
  10035.                 on = false;
  10036.  
  10037.         if (y >= intel_crtc->config->pipe_src_h)
  10038.                 on = false;
  10039.  
  10040.         if (x < 0) {
  10041.                 if (x + cursor_state->crtc_w <= 0)
  10042.                         on = false;
  10043.  
  10044.                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  10045.                 x = -x;
  10046.         }
  10047.         pos |= x << CURSOR_X_SHIFT;
  10048.  
  10049.         if (y < 0) {
  10050.                 if (y + cursor_state->crtc_h <= 0)
  10051.                         on = false;
  10052.  
  10053.                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  10054.                 y = -y;
  10055.         }
  10056.         pos |= y << CURSOR_Y_SHIFT;
  10057.  
  10058.         I915_WRITE(CURPOS(pipe), pos);
  10059.  
  10060.         /* ILK+ do this automagically */
  10061.         if (HAS_GMCH_DISPLAY(dev) &&
  10062.             crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
  10063.                 base += (cursor_state->crtc_h *
  10064.                          cursor_state->crtc_w - 1) * 4;
  10065.         }
  10066.  
  10067.         if (IS_845G(dev) || IS_I865G(dev))
  10068.                 i845_update_cursor(crtc, base, on);
  10069.         else
  10070.                 i9xx_update_cursor(crtc, base, on);
  10071. }
  10072.  
  10073. static bool cursor_size_ok(struct drm_device *dev,
  10074.                            uint32_t width, uint32_t height)
  10075. {
  10076.         if (width == 0 || height == 0)
  10077.                 return false;
  10078.  
  10079.         /*
  10080.          * 845g/865g are special in that they are only limited by
  10081.          * the width of their cursors, the height is arbitrary up to
  10082.          * the precision of the register. Everything else requires
  10083.          * square cursors, limited to a few power-of-two sizes.
  10084.          */
  10085.         if (IS_845G(dev) || IS_I865G(dev)) {
  10086.                 if ((width & 63) != 0)
  10087.                         return false;
  10088.  
  10089.                 if (width > (IS_845G(dev) ? 64 : 512))
  10090.                         return false;
  10091.  
  10092.                 if (height > 1023)
  10093.                         return false;
  10094.         } else {
  10095.                 switch (width | height) {
  10096.                 case 256:
  10097.                 case 128:
  10098.                         if (IS_GEN2(dev))
  10099.                                 return false;
  10100.                 case 64:
  10101.                         break;
  10102.                 default:
  10103.                         return false;
  10104.                 }
  10105.         }
  10106.  
  10107.         return true;
  10108. }
  10109.  
  10110. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  10111.                                  u16 *blue, uint32_t start, uint32_t size)
  10112. {
  10113.         int end = (start + size > 256) ? 256 : start + size, i;
  10114.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10115.  
  10116.         for (i = start; i < end; i++) {
  10117.                 intel_crtc->lut_r[i] = red[i] >> 8;
  10118.                 intel_crtc->lut_g[i] = green[i] >> 8;
  10119.                 intel_crtc->lut_b[i] = blue[i] >> 8;
  10120.         }
  10121.  
  10122.         intel_crtc_load_lut(crtc);
  10123. }
  10124.  
  10125. /* VESA 640x480x72Hz mode to set on the pipe */
  10126. static struct drm_display_mode load_detect_mode = {
  10127.         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  10128.                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  10129. };
  10130.  
  10131. struct drm_framebuffer *
  10132. __intel_framebuffer_create(struct drm_device *dev,
  10133.                            struct drm_mode_fb_cmd2 *mode_cmd,
  10134.                            struct drm_i915_gem_object *obj)
  10135. {
  10136.         struct intel_framebuffer *intel_fb;
  10137.         int ret;
  10138.  
  10139.         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  10140.         if (!intel_fb) {
  10141.                 drm_gem_object_unreference(&obj->base);
  10142.                 return ERR_PTR(-ENOMEM);
  10143.         }
  10144.  
  10145.         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  10146.         if (ret)
  10147.                 goto err;
  10148.  
  10149.         return &intel_fb->base;
  10150. err:
  10151.         drm_gem_object_unreference(&obj->base);
  10152.         kfree(intel_fb);
  10153.  
  10154.         return ERR_PTR(ret);
  10155. }
  10156.  
  10157. static struct drm_framebuffer *
  10158. intel_framebuffer_create(struct drm_device *dev,
  10159.                          struct drm_mode_fb_cmd2 *mode_cmd,
  10160.                          struct drm_i915_gem_object *obj)
  10161. {
  10162.         struct drm_framebuffer *fb;
  10163.         int ret;
  10164.  
  10165.         ret = i915_mutex_lock_interruptible(dev);
  10166.         if (ret)
  10167.                 return ERR_PTR(ret);
  10168.         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
  10169.         mutex_unlock(&dev->struct_mutex);
  10170.  
  10171.         return fb;
  10172. }
  10173.  
  10174. static u32
  10175. intel_framebuffer_pitch_for_width(int width, int bpp)
  10176. {
  10177.         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  10178.         return ALIGN(pitch, 64);
  10179. }
  10180.  
  10181. static u32
  10182. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  10183. {
  10184.         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  10185.         return PAGE_ALIGN(pitch * mode->vdisplay);
  10186. }
  10187.  
  10188. static struct drm_framebuffer *
  10189. intel_framebuffer_create_for_mode(struct drm_device *dev,
  10190.                                   struct drm_display_mode *mode,
  10191.                                   int depth, int bpp)
  10192. {
  10193.         struct drm_i915_gem_object *obj;
  10194.         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  10195.  
  10196.         obj = i915_gem_alloc_object(dev,
  10197.                                     intel_framebuffer_size_for_mode(mode, bpp));
  10198.         if (obj == NULL)
  10199.                 return ERR_PTR(-ENOMEM);
  10200.  
  10201.         mode_cmd.width = mode->hdisplay;
  10202.         mode_cmd.height = mode->vdisplay;
  10203.         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  10204.                                                                 bpp);
  10205.         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  10206.  
  10207.         return intel_framebuffer_create(dev, &mode_cmd, obj);
  10208. }
  10209.  
  10210. static struct drm_framebuffer *
  10211. mode_fits_in_fbdev(struct drm_device *dev,
  10212.                    struct drm_display_mode *mode)
  10213. {
  10214. #ifdef CONFIG_DRM_FBDEV_EMULATION
  10215.         struct drm_i915_private *dev_priv = dev->dev_private;
  10216.         struct drm_i915_gem_object *obj;
  10217.         struct drm_framebuffer *fb;
  10218.  
  10219.         if (!dev_priv->fbdev)
  10220.                 return NULL;
  10221.  
  10222.         if (!dev_priv->fbdev->fb)
  10223.                 return NULL;
  10224.  
  10225.         obj = dev_priv->fbdev->fb->obj;
  10226.         BUG_ON(!obj);
  10227.  
  10228.         fb = &dev_priv->fbdev->fb->base;
  10229.         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  10230.                                                                fb->bits_per_pixel))
  10231.                 return NULL;
  10232.  
  10233.         if (obj->base.size < mode->vdisplay * fb->pitches[0])
  10234.                 return NULL;
  10235.  
  10236.         return fb;
  10237. #else
  10238.         return NULL;
  10239. #endif
  10240. }
  10241.  
  10242. static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
  10243.                                            struct drm_crtc *crtc,
  10244.                                            struct drm_display_mode *mode,
  10245.                                            struct drm_framebuffer *fb,
  10246.                                            int x, int y)
  10247. {
  10248.         struct drm_plane_state *plane_state;
  10249.         int hdisplay, vdisplay;
  10250.         int ret;
  10251.  
  10252.         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
  10253.         if (IS_ERR(plane_state))
  10254.                 return PTR_ERR(plane_state);
  10255.  
  10256.         if (mode)
  10257.                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
  10258.         else
  10259.                 hdisplay = vdisplay = 0;
  10260.  
  10261.         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
  10262.         if (ret)
  10263.                 return ret;
  10264.         drm_atomic_set_fb_for_plane(plane_state, fb);
  10265.         plane_state->crtc_x = 0;
  10266.         plane_state->crtc_y = 0;
  10267.         plane_state->crtc_w = hdisplay;
  10268.         plane_state->crtc_h = vdisplay;
  10269.         plane_state->src_x = x << 16;
  10270.         plane_state->src_y = y << 16;
  10271.         plane_state->src_w = hdisplay << 16;
  10272.         plane_state->src_h = vdisplay << 16;
  10273.  
  10274.         return 0;
  10275. }
  10276.  
  10277. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  10278.                                 struct drm_display_mode *mode,
  10279.                                 struct intel_load_detect_pipe *old,
  10280.                                 struct drm_modeset_acquire_ctx *ctx)
  10281. {
  10282.         struct intel_crtc *intel_crtc;
  10283.         struct intel_encoder *intel_encoder =
  10284.                 intel_attached_encoder(connector);
  10285.         struct drm_crtc *possible_crtc;
  10286.         struct drm_encoder *encoder = &intel_encoder->base;
  10287.         struct drm_crtc *crtc = NULL;
  10288.         struct drm_device *dev = encoder->dev;
  10289.         struct drm_framebuffer *fb;
  10290.         struct drm_mode_config *config = &dev->mode_config;
  10291.         struct drm_atomic_state *state = NULL;
  10292.         struct drm_connector_state *connector_state;
  10293.         struct intel_crtc_state *crtc_state;
  10294.         int ret, i = -1;
  10295.  
  10296.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  10297.                       connector->base.id, connector->name,
  10298.                       encoder->base.id, encoder->name);
  10299.  
  10300. retry:
  10301.         ret = drm_modeset_lock(&config->connection_mutex, ctx);
  10302.         if (ret)
  10303.                 goto fail;
  10304.  
  10305.         /*
  10306.          * Algorithm gets a little messy:
  10307.          *
  10308.          *   - if the connector already has an assigned crtc, use it (but make
  10309.          *     sure it's on first)
  10310.          *
  10311.          *   - try to find the first unused crtc that can drive this connector,
  10312.          *     and use that if we find one
  10313.          */
  10314.  
  10315.         /* See if we already have a CRTC for this connector */
  10316.         if (encoder->crtc) {
  10317.                 crtc = encoder->crtc;
  10318.  
  10319.                 ret = drm_modeset_lock(&crtc->mutex, ctx);
  10320.                 if (ret)
  10321.                         goto fail;
  10322.                 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
  10323.                 if (ret)
  10324.                         goto fail;
  10325.  
  10326.                 old->dpms_mode = connector->dpms;
  10327.                 old->load_detect_temp = false;
  10328.  
  10329.                 /* Make sure the crtc and connector are running */
  10330.                 if (connector->dpms != DRM_MODE_DPMS_ON)
  10331.                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  10332.  
  10333.                 return true;
  10334.         }
  10335.  
  10336.         /* Find an unused one (if possible) */
  10337.         for_each_crtc(dev, possible_crtc) {
  10338.                 i++;
  10339.                 if (!(encoder->possible_crtcs & (1 << i)))
  10340.                         continue;
  10341.                 if (possible_crtc->state->enable)
  10342.                         continue;
  10343.  
  10344.                 crtc = possible_crtc;
  10345.                 break;
  10346.         }
  10347.  
  10348.         /*
  10349.          * If we didn't find an unused CRTC, don't use any.
  10350.          */
  10351.         if (!crtc) {
  10352.                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
  10353.                 goto fail;
  10354.         }
  10355.  
  10356.         ret = drm_modeset_lock(&crtc->mutex, ctx);
  10357.         if (ret)
  10358.                 goto fail;
  10359.         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
  10360.         if (ret)
  10361.                 goto fail;
  10362.  
  10363.         intel_crtc = to_intel_crtc(crtc);
  10364.         old->dpms_mode = connector->dpms;
  10365.         old->load_detect_temp = true;
  10366.         old->release_fb = NULL;
  10367.  
  10368.         state = drm_atomic_state_alloc(dev);
  10369.         if (!state)
  10370.                 return false;
  10371.  
  10372.         state->acquire_ctx = ctx;
  10373.  
  10374.         connector_state = drm_atomic_get_connector_state(state, connector);
  10375.         if (IS_ERR(connector_state)) {
  10376.                 ret = PTR_ERR(connector_state);
  10377.                 goto fail;
  10378.         }
  10379.  
  10380.         connector_state->crtc = crtc;
  10381.         connector_state->best_encoder = &intel_encoder->base;
  10382.  
  10383.         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
  10384.         if (IS_ERR(crtc_state)) {
  10385.                 ret = PTR_ERR(crtc_state);
  10386.                 goto fail;
  10387.         }
  10388.  
  10389.         crtc_state->base.active = crtc_state->base.enable = true;
  10390.  
  10391.         if (!mode)
  10392.                 mode = &load_detect_mode;
  10393.  
  10394.         /* We need a framebuffer large enough to accommodate all accesses
  10395.          * that the plane may generate whilst we perform load detection.
  10396.          * We can not rely on the fbcon either being present (we get called
  10397.          * during its initialisation to detect all boot displays, or it may
  10398.          * not even exist) or that it is large enough to satisfy the
  10399.          * requested mode.
  10400.          */
  10401.         fb = mode_fits_in_fbdev(dev, mode);
  10402.         if (fb == NULL) {
  10403.                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  10404.                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  10405.                 old->release_fb = fb;
  10406.         } else
  10407.                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  10408.         if (IS_ERR(fb)) {
  10409.                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  10410.                 goto fail;
  10411.         }
  10412.  
  10413.         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
  10414.         if (ret)
  10415.                 goto fail;
  10416.  
  10417.         drm_mode_copy(&crtc_state->base.mode, mode);
  10418.  
  10419.         if (drm_atomic_commit(state)) {
  10420.                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  10421.                 if (old->release_fb)
  10422.                         old->release_fb->funcs->destroy(old->release_fb);
  10423.                 goto fail;
  10424.         }
  10425.         crtc->primary->crtc = crtc;
  10426.  
  10427.         /* let the connector get through one full cycle before testing */
  10428.         intel_wait_for_vblank(dev, intel_crtc->pipe);
  10429.         return true;
  10430.  
  10431. fail:
  10432.         drm_atomic_state_free(state);
  10433.         state = NULL;
  10434.  
  10435.         if (ret == -EDEADLK) {
  10436.                 drm_modeset_backoff(ctx);
  10437.                 goto retry;
  10438.         }
  10439.  
  10440.         return false;
  10441. }
  10442.  
  10443. void intel_release_load_detect_pipe(struct drm_connector *connector,
  10444.                                     struct intel_load_detect_pipe *old,
  10445.                                     struct drm_modeset_acquire_ctx *ctx)
  10446. {
  10447.         struct drm_device *dev = connector->dev;
  10448.         struct intel_encoder *intel_encoder =
  10449.                 intel_attached_encoder(connector);
  10450.         struct drm_encoder *encoder = &intel_encoder->base;
  10451.         struct drm_crtc *crtc = encoder->crtc;
  10452.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10453.         struct drm_atomic_state *state;
  10454.         struct drm_connector_state *connector_state;
  10455.         struct intel_crtc_state *crtc_state;
  10456.         int ret;
  10457.  
  10458.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  10459.                       connector->base.id, connector->name,
  10460.                       encoder->base.id, encoder->name);
  10461.  
  10462.         if (old->load_detect_temp) {
  10463.                 state = drm_atomic_state_alloc(dev);
  10464.                 if (!state)
  10465.                         goto fail;
  10466.  
  10467.                 state->acquire_ctx = ctx;
  10468.  
  10469.                 connector_state = drm_atomic_get_connector_state(state, connector);
  10470.                 if (IS_ERR(connector_state))
  10471.                         goto fail;
  10472.  
  10473.                 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
  10474.                 if (IS_ERR(crtc_state))
  10475.                         goto fail;
  10476.  
  10477.                 connector_state->best_encoder = NULL;
  10478.                 connector_state->crtc = NULL;
  10479.  
  10480.                 crtc_state->base.enable = crtc_state->base.active = false;
  10481.  
  10482.                 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
  10483.                                                       0, 0);
  10484.                 if (ret)
  10485.                         goto fail;
  10486.  
  10487.                 ret = drm_atomic_commit(state);
  10488.                 if (ret)
  10489.                         goto fail;
  10490.  
  10491.                 if (old->release_fb) {
  10492.                         drm_framebuffer_unregister_private(old->release_fb);
  10493.                         drm_framebuffer_unreference(old->release_fb);
  10494.                 }
  10495.  
  10496.                 return;
  10497.         }
  10498.  
  10499.         /* Switch crtc and encoder back off if necessary */
  10500.         if (old->dpms_mode != DRM_MODE_DPMS_ON)
  10501.                 connector->funcs->dpms(connector, old->dpms_mode);
  10502.  
  10503.         return;
  10504. fail:
  10505.         DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
  10506.         drm_atomic_state_free(state);
  10507. }
  10508.  
  10509. static int i9xx_pll_refclk(struct drm_device *dev,
  10510.                            const struct intel_crtc_state *pipe_config)
  10511. {
  10512.         struct drm_i915_private *dev_priv = dev->dev_private;
  10513.         u32 dpll = pipe_config->dpll_hw_state.dpll;
  10514.  
  10515.         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
  10516.                 return dev_priv->vbt.lvds_ssc_freq;
  10517.         else if (HAS_PCH_SPLIT(dev))
  10518.                 return 120000;
  10519.         else if (!IS_GEN2(dev))
  10520.                 return 96000;
  10521.         else
  10522.                 return 48000;
  10523. }
  10524.  
  10525. /* Returns the clock of the currently programmed mode of the given pipe. */
  10526. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  10527.                                 struct intel_crtc_state *pipe_config)
  10528. {
  10529.         struct drm_device *dev = crtc->base.dev;
  10530.         struct drm_i915_private *dev_priv = dev->dev_private;
  10531.         int pipe = pipe_config->cpu_transcoder;
  10532.         u32 dpll = pipe_config->dpll_hw_state.dpll;
  10533.         u32 fp;
  10534.         intel_clock_t clock;
  10535.         int port_clock;
  10536.         int refclk = i9xx_pll_refclk(dev, pipe_config);
  10537.  
  10538.         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  10539.                 fp = pipe_config->dpll_hw_state.fp0;
  10540.         else
  10541.                 fp = pipe_config->dpll_hw_state.fp1;
  10542.  
  10543.         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  10544.         if (IS_PINEVIEW(dev)) {
  10545.                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  10546.                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  10547.         } else {
  10548.                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  10549.                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  10550.         }
  10551.  
  10552.         if (!IS_GEN2(dev)) {
  10553.                 if (IS_PINEVIEW(dev))
  10554.                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  10555.                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  10556.                 else
  10557.                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  10558.                                DPLL_FPA01_P1_POST_DIV_SHIFT);
  10559.  
  10560.                 switch (dpll & DPLL_MODE_MASK) {
  10561.                 case DPLLB_MODE_DAC_SERIAL:
  10562.                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  10563.                                 5 : 10;
  10564.                         break;
  10565.                 case DPLLB_MODE_LVDS:
  10566.                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  10567.                                 7 : 14;
  10568.                         break;
  10569.                 default:
  10570.                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  10571.                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
  10572.                         return;
  10573.                 }
  10574.  
  10575.                 if (IS_PINEVIEW(dev))
  10576.                         port_clock = pnv_calc_dpll_params(refclk, &clock);
  10577.                 else
  10578.                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
  10579.         } else {
  10580.                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
  10581.                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
  10582.  
  10583.                 if (is_lvds) {
  10584.                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  10585.                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
  10586.  
  10587.                         if (lvds & LVDS_CLKB_POWER_UP)
  10588.                                 clock.p2 = 7;
  10589.                         else
  10590.                                 clock.p2 = 14;
  10591.                 } else {
  10592.                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
  10593.                                 clock.p1 = 2;
  10594.                         else {
  10595.                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  10596.                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  10597.                         }
  10598.                         if (dpll & PLL_P2_DIVIDE_BY_4)
  10599.                                 clock.p2 = 4;
  10600.                         else
  10601.                                 clock.p2 = 2;
  10602.                 }
  10603.  
  10604.                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
  10605.         }
  10606.  
  10607.         /*
  10608.          * This value includes pixel_multiplier. We will use
  10609.          * port_clock to compute adjusted_mode.crtc_clock in the
  10610.          * encoder's get_config() function.
  10611.          */
  10612.         pipe_config->port_clock = port_clock;
  10613. }
  10614.  
  10615. int intel_dotclock_calculate(int link_freq,
  10616.                              const struct intel_link_m_n *m_n)
  10617. {
  10618.         /*
  10619.          * The calculation for the data clock is:
  10620.          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
  10621.          * But we want to avoid losing precison if possible, so:
  10622.          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
  10623.          *
  10624.          * and the link clock is simpler:
  10625.          * link_clock = (m * link_clock) / n
  10626.          */
  10627.  
  10628.         if (!m_n->link_n)
  10629.                 return 0;
  10630.  
  10631.         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
  10632. }
  10633.  
  10634. static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  10635.                                    struct intel_crtc_state *pipe_config)
  10636. {
  10637.         struct drm_device *dev = crtc->base.dev;
  10638.  
  10639.         /* read out port_clock from the DPLL */
  10640.         i9xx_crtc_clock_get(crtc, pipe_config);
  10641.  
  10642.         /*
  10643.          * This value does not include pixel_multiplier.
  10644.          * We will check that port_clock and adjusted_mode.crtc_clock
  10645.          * agree once we know their relationship in the encoder's
  10646.          * get_config() function.
  10647.          */
  10648.         pipe_config->base.adjusted_mode.crtc_clock =
  10649.                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
  10650.                                          &pipe_config->fdi_m_n);
  10651. }
  10652.  
  10653. /** Returns the currently programmed mode of the given pipe. */
  10654. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  10655.                                              struct drm_crtc *crtc)
  10656. {
  10657.         struct drm_i915_private *dev_priv = dev->dev_private;
  10658.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10659.         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
  10660.         struct drm_display_mode *mode;
  10661.         struct intel_crtc_state pipe_config;
  10662.         int htot = I915_READ(HTOTAL(cpu_transcoder));
  10663.         int hsync = I915_READ(HSYNC(cpu_transcoder));
  10664.         int vtot = I915_READ(VTOTAL(cpu_transcoder));
  10665.         int vsync = I915_READ(VSYNC(cpu_transcoder));
  10666.         enum pipe pipe = intel_crtc->pipe;
  10667.  
  10668.         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  10669.         if (!mode)
  10670.                 return NULL;
  10671.  
  10672.         /*
  10673.          * Construct a pipe_config sufficient for getting the clock info
  10674.          * back out of crtc_clock_get.
  10675.          *
  10676.          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  10677.          * to use a real value here instead.
  10678.          */
  10679.         pipe_config.cpu_transcoder = (enum transcoder) pipe;
  10680.         pipe_config.pixel_multiplier = 1;
  10681.         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
  10682.         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
  10683.         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
  10684.         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
  10685.  
  10686.         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
  10687.         mode->hdisplay = (htot & 0xffff) + 1;
  10688.         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  10689.         mode->hsync_start = (hsync & 0xffff) + 1;
  10690.         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  10691.         mode->vdisplay = (vtot & 0xffff) + 1;
  10692.         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  10693.         mode->vsync_start = (vsync & 0xffff) + 1;
  10694.         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  10695.  
  10696.         drm_mode_set_name(mode);
  10697.  
  10698.         return mode;
  10699. }
  10700.  
  10701. void intel_mark_busy(struct drm_device *dev)
  10702. {
  10703.         struct drm_i915_private *dev_priv = dev->dev_private;
  10704.  
  10705.         if (dev_priv->mm.busy)
  10706.                 return;
  10707.  
  10708.         intel_runtime_pm_get(dev_priv);
  10709.         i915_update_gfx_val(dev_priv);
  10710.         if (INTEL_INFO(dev)->gen >= 6)
  10711.                 gen6_rps_busy(dev_priv);
  10712.         dev_priv->mm.busy = true;
  10713. }
  10714.  
  10715. void intel_mark_idle(struct drm_device *dev)
  10716. {
  10717.         struct drm_i915_private *dev_priv = dev->dev_private;
  10718.  
  10719.         if (!dev_priv->mm.busy)
  10720.                 return;
  10721.  
  10722.         dev_priv->mm.busy = false;
  10723.  
  10724.         if (INTEL_INFO(dev)->gen >= 6)
  10725.                 gen6_rps_idle(dev->dev_private);
  10726.  
  10727.         intel_runtime_pm_put(dev_priv);
  10728. }
  10729.  
  10730. static void intel_crtc_destroy(struct drm_crtc *crtc)
  10731. {
  10732.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10733.         struct drm_device *dev = crtc->dev;
  10734.         struct intel_unpin_work *work;
  10735.  
  10736.         spin_lock_irq(&dev->event_lock);
  10737.         work = intel_crtc->unpin_work;
  10738.         intel_crtc->unpin_work = NULL;
  10739.         spin_unlock_irq(&dev->event_lock);
  10740.  
  10741.         if (work) {
  10742.                 cancel_work_sync(&work->work);
  10743.                 kfree(work);
  10744.         }
  10745.  
  10746.         drm_crtc_cleanup(crtc);
  10747.  
  10748.         kfree(intel_crtc);
  10749. }
  10750.  
  10751. #if 0
  10752. static void intel_unpin_work_fn(struct work_struct *__work)
  10753. {
  10754.         struct intel_unpin_work *work =
  10755.                 container_of(__work, struct intel_unpin_work, work);
  10756.         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
  10757.         struct drm_device *dev = crtc->base.dev;
  10758.         struct drm_plane *primary = crtc->base.primary;
  10759.  
  10760.         mutex_lock(&dev->struct_mutex);
  10761.         intel_unpin_fb_obj(work->old_fb, primary->state);
  10762.         drm_gem_object_unreference(&work->pending_flip_obj->base);
  10763.  
  10764.         if (work->flip_queued_req)
  10765.                 i915_gem_request_assign(&work->flip_queued_req, NULL);
  10766.         mutex_unlock(&dev->struct_mutex);
  10767.  
  10768.         intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
  10769.         drm_framebuffer_unreference(work->old_fb);
  10770.  
  10771.         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
  10772.         atomic_dec(&crtc->unpin_work_count);
  10773.  
  10774.         kfree(work);
  10775. }
  10776.  
  10777. static void do_intel_finish_page_flip(struct drm_device *dev,
  10778.                                       struct drm_crtc *crtc)
  10779. {
  10780.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10781.         struct intel_unpin_work *work;
  10782.         unsigned long flags;
  10783.  
  10784.         /* Ignore early vblank irqs */
  10785.         if (intel_crtc == NULL)
  10786.                 return;
  10787.  
  10788.         /*
  10789.          * This is called both by irq handlers and the reset code (to complete
  10790.          * lost pageflips) so needs the full irqsave spinlocks.
  10791.          */
  10792.         spin_lock_irqsave(&dev->event_lock, flags);
  10793.         work = intel_crtc->unpin_work;
  10794.  
  10795.         /* Ensure we don't miss a work->pending update ... */
  10796.         smp_rmb();
  10797.  
  10798.         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  10799.                 spin_unlock_irqrestore(&dev->event_lock, flags);
  10800.                 return;
  10801.         }
  10802.  
  10803.         page_flip_completed(intel_crtc);
  10804.  
  10805.         spin_unlock_irqrestore(&dev->event_lock, flags);
  10806. }
  10807.  
  10808. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  10809. {
  10810.         struct drm_i915_private *dev_priv = dev->dev_private;
  10811.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  10812.  
  10813.         do_intel_finish_page_flip(dev, crtc);
  10814. }
  10815.  
  10816. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  10817. {
  10818.         struct drm_i915_private *dev_priv = dev->dev_private;
  10819.         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  10820.  
  10821.         do_intel_finish_page_flip(dev, crtc);
  10822. }
  10823.  
  10824. /* Is 'a' after or equal to 'b'? */
  10825. static bool g4x_flip_count_after_eq(u32 a, u32 b)
  10826. {
  10827.         return !((a - b) & 0x80000000);
  10828. }
  10829.  
  10830. static bool page_flip_finished(struct intel_crtc *crtc)
  10831. {
  10832.         struct drm_device *dev = crtc->base.dev;
  10833.         struct drm_i915_private *dev_priv = dev->dev_private;
  10834.  
  10835.         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  10836.             crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  10837.                 return true;
  10838.  
  10839.         /*
  10840.          * The relevant registers doen't exist on pre-ctg.
  10841.          * As the flip done interrupt doesn't trigger for mmio
  10842.          * flips on gmch platforms, a flip count check isn't
  10843.          * really needed there. But since ctg has the registers,
  10844.          * include it in the check anyway.
  10845.          */
  10846.         if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
  10847.                 return true;
  10848.  
  10849.         /*
  10850.          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
  10851.          * used the same base address. In that case the mmio flip might
  10852.          * have completed, but the CS hasn't even executed the flip yet.
  10853.          *
  10854.          * A flip count check isn't enough as the CS might have updated
  10855.          * the base address just after start of vblank, but before we
  10856.          * managed to process the interrupt. This means we'd complete the
  10857.          * CS flip too soon.
  10858.          *
  10859.          * Combining both checks should get us a good enough result. It may
  10860.          * still happen that the CS flip has been executed, but has not
  10861.          * yet actually completed. But in case the base address is the same
  10862.          * anyway, we don't really care.
  10863.          */
  10864.         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
  10865.                 crtc->unpin_work->gtt_offset &&
  10866.                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
  10867.                                     crtc->unpin_work->flip_count);
  10868. }
  10869.  
  10870. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  10871. {
  10872.         struct drm_i915_private *dev_priv = dev->dev_private;
  10873.         struct intel_crtc *intel_crtc =
  10874.                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  10875.         unsigned long flags;
  10876.  
  10877.  
  10878.         /*
  10879.          * This is called both by irq handlers and the reset code (to complete
  10880.          * lost pageflips) so needs the full irqsave spinlocks.
  10881.          *
  10882.          * NB: An MMIO update of the plane base pointer will also
  10883.          * generate a page-flip completion irq, i.e. every modeset
  10884.          * is also accompanied by a spurious intel_prepare_page_flip().
  10885.          */
  10886.         spin_lock_irqsave(&dev->event_lock, flags);
  10887.         if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
  10888.                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  10889.         spin_unlock_irqrestore(&dev->event_lock, flags);
  10890. }
  10891.  
  10892. static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
  10893. {
  10894.         /* Ensure that the work item is consistent when activating it ... */
  10895.         smp_wmb();
  10896.         atomic_set(&work->pending, INTEL_FLIP_PENDING);
  10897.         /* and that it is marked active as soon as the irq could fire. */
  10898.         smp_wmb();
  10899. }
  10900.  
  10901. static int intel_gen2_queue_flip(struct drm_device *dev,
  10902.                                  struct drm_crtc *crtc,
  10903.                                  struct drm_framebuffer *fb,
  10904.                                  struct drm_i915_gem_object *obj,
  10905.                                  struct drm_i915_gem_request *req,
  10906.                                  uint32_t flags)
  10907. {
  10908.         struct intel_engine_cs *ring = req->ring;
  10909.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10910.         u32 flip_mask;
  10911.         int ret;
  10912.  
  10913.         ret = intel_ring_begin(req, 6);
  10914.         if (ret)
  10915.                 return ret;
  10916.  
  10917.         /* Can't queue multiple flips, so wait for the previous
  10918.          * one to finish before executing the next.
  10919.          */
  10920.         if (intel_crtc->plane)
  10921.                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  10922.         else
  10923.                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  10924.         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  10925.         intel_ring_emit(ring, MI_NOOP);
  10926.         intel_ring_emit(ring, MI_DISPLAY_FLIP |
  10927.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  10928.         intel_ring_emit(ring, fb->pitches[0]);
  10929.         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
  10930.         intel_ring_emit(ring, 0); /* aux display base address, unused */
  10931.  
  10932.         intel_mark_page_flip_active(intel_crtc->unpin_work);
  10933.         return 0;
  10934. }
  10935.  
  10936. static int intel_gen3_queue_flip(struct drm_device *dev,
  10937.                                  struct drm_crtc *crtc,
  10938.                                  struct drm_framebuffer *fb,
  10939.                                  struct drm_i915_gem_object *obj,
  10940.                                  struct drm_i915_gem_request *req,
  10941.                                  uint32_t flags)
  10942. {
  10943.         struct intel_engine_cs *ring = req->ring;
  10944.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10945.         u32 flip_mask;
  10946.         int ret;
  10947.  
  10948.         ret = intel_ring_begin(req, 6);
  10949.         if (ret)
  10950.                 return ret;
  10951.  
  10952.         if (intel_crtc->plane)
  10953.                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  10954.         else
  10955.                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  10956.         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  10957.         intel_ring_emit(ring, MI_NOOP);
  10958.         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  10959.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  10960.         intel_ring_emit(ring, fb->pitches[0]);
  10961.         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
  10962.         intel_ring_emit(ring, MI_NOOP);
  10963.  
  10964.         intel_mark_page_flip_active(intel_crtc->unpin_work);
  10965.         return 0;
  10966. }
  10967.  
  10968. static int intel_gen4_queue_flip(struct drm_device *dev,
  10969.                                  struct drm_crtc *crtc,
  10970.                                  struct drm_framebuffer *fb,
  10971.                                  struct drm_i915_gem_object *obj,
  10972.                                  struct drm_i915_gem_request *req,
  10973.                                  uint32_t flags)
  10974. {
  10975.         struct intel_engine_cs *ring = req->ring;
  10976.         struct drm_i915_private *dev_priv = dev->dev_private;
  10977.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  10978.         uint32_t pf, pipesrc;
  10979.         int ret;
  10980.  
  10981.         ret = intel_ring_begin(req, 4);
  10982.         if (ret)
  10983.                 return ret;
  10984.  
  10985.         /* i965+ uses the linear or tiled offsets from the
  10986.          * Display Registers (which do not change across a page-flip)
  10987.          * so we need only reprogram the base address.
  10988.          */
  10989.         intel_ring_emit(ring, MI_DISPLAY_FLIP |
  10990.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  10991.         intel_ring_emit(ring, fb->pitches[0]);
  10992.         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
  10993.                         obj->tiling_mode);
  10994.  
  10995.         /* XXX Enabling the panel-fitter across page-flip is so far
  10996.          * untested on non-native modes, so ignore it for now.
  10997.          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  10998.          */
  10999.         pf = 0;
  11000.         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  11001.         intel_ring_emit(ring, pf | pipesrc);
  11002.  
  11003.         intel_mark_page_flip_active(intel_crtc->unpin_work);
  11004.         return 0;
  11005. }
  11006.  
  11007. static int intel_gen6_queue_flip(struct drm_device *dev,
  11008.                                  struct drm_crtc *crtc,
  11009.                                  struct drm_framebuffer *fb,
  11010.                                  struct drm_i915_gem_object *obj,
  11011.                                  struct drm_i915_gem_request *req,
  11012.                                  uint32_t flags)
  11013. {
  11014.         struct intel_engine_cs *ring = req->ring;
  11015.         struct drm_i915_private *dev_priv = dev->dev_private;
  11016.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11017.         uint32_t pf, pipesrc;
  11018.         int ret;
  11019.  
  11020.         ret = intel_ring_begin(req, 4);
  11021.         if (ret)
  11022.                 return ret;
  11023.  
  11024.         intel_ring_emit(ring, MI_DISPLAY_FLIP |
  11025.                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  11026.         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  11027.         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
  11028.  
  11029.         /* Contrary to the suggestions in the documentation,
  11030.          * "Enable Panel Fitter" does not seem to be required when page
  11031.          * flipping with a non-native mode, and worse causes a normal
  11032.          * modeset to fail.
  11033.          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  11034.          */
  11035.         pf = 0;
  11036.         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  11037.         intel_ring_emit(ring, pf | pipesrc);
  11038.  
  11039.         intel_mark_page_flip_active(intel_crtc->unpin_work);
  11040.         return 0;
  11041. }
  11042.  
  11043. static int intel_gen7_queue_flip(struct drm_device *dev,
  11044.                                  struct drm_crtc *crtc,
  11045.                                  struct drm_framebuffer *fb,
  11046.                                  struct drm_i915_gem_object *obj,
  11047.                                  struct drm_i915_gem_request *req,
  11048.                                  uint32_t flags)
  11049. {
  11050.         struct intel_engine_cs *ring = req->ring;
  11051.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11052.         uint32_t plane_bit = 0;
  11053.         int len, ret;
  11054.  
  11055.         switch (intel_crtc->plane) {
  11056.         case PLANE_A:
  11057.                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  11058.                 break;
  11059.         case PLANE_B:
  11060.                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  11061.                 break;
  11062.         case PLANE_C:
  11063.                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  11064.                 break;
  11065.         default:
  11066.                 WARN_ONCE(1, "unknown plane in flip command\n");
  11067.                 return -ENODEV;
  11068.         }
  11069.  
  11070.         len = 4;
  11071.         if (ring->id == RCS) {
  11072.                 len += 6;
  11073.                 /*
  11074.                  * On Gen 8, SRM is now taking an extra dword to accommodate
  11075.                  * 48bits addresses, and we need a NOOP for the batch size to
  11076.                  * stay even.
  11077.                  */
  11078.                 if (IS_GEN8(dev))
  11079.                         len += 2;
  11080.         }
  11081.  
  11082.         /*
  11083.          * BSpec MI_DISPLAY_FLIP for IVB:
  11084.          * "The full packet must be contained within the same cache line."
  11085.          *
  11086.          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
  11087.          * cacheline, if we ever start emitting more commands before
  11088.          * the MI_DISPLAY_FLIP we may need to first emit everything else,
  11089.          * then do the cacheline alignment, and finally emit the
  11090.          * MI_DISPLAY_FLIP.
  11091.          */
  11092.         ret = intel_ring_cacheline_align(req);
  11093.         if (ret)
  11094.                 return ret;
  11095.  
  11096.         ret = intel_ring_begin(req, len);
  11097.         if (ret)
  11098.                 return ret;
  11099.  
  11100.         /* Unmask the flip-done completion message. Note that the bspec says that
  11101.          * we should do this for both the BCS and RCS, and that we must not unmask
  11102.          * more than one flip event at any time (or ensure that one flip message
  11103.          * can be sent by waiting for flip-done prior to queueing new flips).
  11104.          * Experimentation says that BCS works despite DERRMR masking all
  11105.          * flip-done completion events and that unmasking all planes at once
  11106.          * for the RCS also doesn't appear to drop events. Setting the DERRMR
  11107.          * to zero does lead to lockups within MI_DISPLAY_FLIP.
  11108.          */
  11109.         if (ring->id == RCS) {
  11110.                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
  11111.                 intel_ring_emit(ring, DERRMR);
  11112.                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
  11113.                                         DERRMR_PIPEB_PRI_FLIP_DONE |
  11114.                                         DERRMR_PIPEC_PRI_FLIP_DONE));
  11115.                 if (IS_GEN8(dev))
  11116.                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
  11117.                                               MI_SRM_LRM_GLOBAL_GTT);
  11118.                 else
  11119.                         intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
  11120.                                               MI_SRM_LRM_GLOBAL_GTT);
  11121.                 intel_ring_emit(ring, DERRMR);
  11122.                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
  11123.                 if (IS_GEN8(dev)) {
  11124.                         intel_ring_emit(ring, 0);
  11125.                         intel_ring_emit(ring, MI_NOOP);
  11126.                 }
  11127.         }
  11128.  
  11129.         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  11130.         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  11131.         intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
  11132.         intel_ring_emit(ring, (MI_NOOP));
  11133.  
  11134.         intel_mark_page_flip_active(intel_crtc->unpin_work);
  11135.         return 0;
  11136. }
  11137.  
  11138. static bool use_mmio_flip(struct intel_engine_cs *ring,
  11139.                           struct drm_i915_gem_object *obj)
  11140. {
  11141.         /*
  11142.          * This is not being used for older platforms, because
  11143.          * non-availability of flip done interrupt forces us to use
  11144.          * CS flips. Older platforms derive flip done using some clever
  11145.          * tricks involving the flip_pending status bits and vblank irqs.
  11146.          * So using MMIO flips there would disrupt this mechanism.
  11147.          */
  11148.  
  11149.         if (ring == NULL)
  11150.                 return true;
  11151.  
  11152.         if (INTEL_INFO(ring->dev)->gen < 5)
  11153.                 return false;
  11154.  
  11155.         if (i915.use_mmio_flip < 0)
  11156.                 return false;
  11157.         else if (i915.use_mmio_flip > 0)
  11158.                 return true;
  11159.         else if (i915.enable_execlists)
  11160.                 return true;
  11161.         else
  11162.                 return ring != i915_gem_request_get_ring(obj->last_write_req);
  11163. }
  11164.  
  11165. static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
  11166.                              struct intel_unpin_work *work)
  11167. {
  11168.         struct drm_device *dev = intel_crtc->base.dev;
  11169.         struct drm_i915_private *dev_priv = dev->dev_private;
  11170.         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
  11171.         const enum pipe pipe = intel_crtc->pipe;
  11172.         u32 ctl, stride;
  11173.  
  11174.         ctl = I915_READ(PLANE_CTL(pipe, 0));
  11175.         ctl &= ~PLANE_CTL_TILED_MASK;
  11176.         switch (fb->modifier[0]) {
  11177.         case DRM_FORMAT_MOD_NONE:
  11178.                 break;
  11179.         case I915_FORMAT_MOD_X_TILED:
  11180.                 ctl |= PLANE_CTL_TILED_X;
  11181.                 break;
  11182.         case I915_FORMAT_MOD_Y_TILED:
  11183.                 ctl |= PLANE_CTL_TILED_Y;
  11184.                 break;
  11185.         case I915_FORMAT_MOD_Yf_TILED:
  11186.                 ctl |= PLANE_CTL_TILED_YF;
  11187.                 break;
  11188.         default:
  11189.                 MISSING_CASE(fb->modifier[0]);
  11190.         }
  11191.  
  11192.         /*
  11193.          * The stride is either expressed as a multiple of 64 bytes chunks for
  11194.          * linear buffers or in number of tiles for tiled buffers.
  11195.          */
  11196.         stride = fb->pitches[0] /
  11197.                  intel_fb_stride_alignment(dev, fb->modifier[0],
  11198.                                            fb->pixel_format);
  11199.  
  11200.         /*
  11201.          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
  11202.          * PLANE_SURF updates, the update is then guaranteed to be atomic.
  11203.          */
  11204.         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
  11205.         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
  11206.  
  11207.         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
  11208.         POSTING_READ(PLANE_SURF(pipe, 0));
  11209. }
  11210.  
  11211. static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
  11212.                              struct intel_unpin_work *work)
  11213. {
  11214.         struct drm_device *dev = intel_crtc->base.dev;
  11215.         struct drm_i915_private *dev_priv = dev->dev_private;
  11216.         struct intel_framebuffer *intel_fb =
  11217.                 to_intel_framebuffer(intel_crtc->base.primary->fb);
  11218.         struct drm_i915_gem_object *obj = intel_fb->obj;
  11219.         u32 dspcntr;
  11220.         u32 reg;
  11221.  
  11222.         reg = DSPCNTR(intel_crtc->plane);
  11223.         dspcntr = I915_READ(reg);
  11224.  
  11225.         if (obj->tiling_mode != I915_TILING_NONE)
  11226.                 dspcntr |= DISPPLANE_TILED;
  11227.         else
  11228.                 dspcntr &= ~DISPPLANE_TILED;
  11229.  
  11230.         I915_WRITE(reg, dspcntr);
  11231.  
  11232.         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
  11233.         POSTING_READ(DSPSURF(intel_crtc->plane));
  11234. }
  11235.  
  11236. /*
  11237.  * XXX: This is the temporary way to update the plane registers until we get
  11238.  * around to using the usual plane update functions for MMIO flips
  11239.  */
  11240. static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
  11241. {
  11242.         struct intel_crtc *crtc = mmio_flip->crtc;
  11243.         struct intel_unpin_work *work;
  11244.  
  11245.         spin_lock_irq(&crtc->base.dev->event_lock);
  11246.         work = crtc->unpin_work;
  11247.         spin_unlock_irq(&crtc->base.dev->event_lock);
  11248.         if (work == NULL)
  11249.                 return;
  11250.  
  11251.         intel_mark_page_flip_active(work);
  11252.  
  11253.         intel_pipe_update_start(crtc);
  11254.  
  11255.         if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
  11256.                 skl_do_mmio_flip(crtc, work);
  11257.         else
  11258.                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
  11259.                 ilk_do_mmio_flip(crtc, work);
  11260.  
  11261.         intel_pipe_update_end(crtc);
  11262. }
  11263.  
  11264. static void intel_mmio_flip_work_func(struct work_struct *work)
  11265. {
  11266.         struct intel_mmio_flip *mmio_flip =
  11267.                 container_of(work, struct intel_mmio_flip, work);
  11268.  
  11269.         if (mmio_flip->req) {
  11270.                 WARN_ON(__i915_wait_request(mmio_flip->req,
  11271.                                             mmio_flip->crtc->reset_counter,
  11272.                                             false, NULL,
  11273.                                             &mmio_flip->i915->rps.mmioflips));
  11274.                 i915_gem_request_unreference__unlocked(mmio_flip->req);
  11275.         }
  11276.  
  11277.         intel_do_mmio_flip(mmio_flip);
  11278.         kfree(mmio_flip);
  11279. }
  11280.  
  11281. static int intel_queue_mmio_flip(struct drm_device *dev,
  11282.                                  struct drm_crtc *crtc,
  11283.                                  struct drm_framebuffer *fb,
  11284.                                  struct drm_i915_gem_object *obj,
  11285.                                  struct intel_engine_cs *ring,
  11286.                                  uint32_t flags)
  11287. {
  11288.         struct intel_mmio_flip *mmio_flip;
  11289.  
  11290.         mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
  11291.         if (mmio_flip == NULL)
  11292.                 return -ENOMEM;
  11293.  
  11294.         mmio_flip->i915 = to_i915(dev);
  11295.         mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
  11296.         mmio_flip->crtc = to_intel_crtc(crtc);
  11297.  
  11298.         INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
  11299.         schedule_work(&mmio_flip->work);
  11300.  
  11301.         return 0;
  11302. }
  11303.  
  11304. static int intel_default_queue_flip(struct drm_device *dev,
  11305.                                     struct drm_crtc *crtc,
  11306.                                     struct drm_framebuffer *fb,
  11307.                                     struct drm_i915_gem_object *obj,
  11308.                                     struct drm_i915_gem_request *req,
  11309.                                     uint32_t flags)
  11310. {
  11311.         return -ENODEV;
  11312. }
  11313.  
  11314. static bool __intel_pageflip_stall_check(struct drm_device *dev,
  11315.                                          struct drm_crtc *crtc)
  11316. {
  11317.         struct drm_i915_private *dev_priv = dev->dev_private;
  11318.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11319.         struct intel_unpin_work *work = intel_crtc->unpin_work;
  11320.         u32 addr;
  11321.  
  11322.         if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
  11323.                 return true;
  11324.  
  11325.         if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
  11326.                 return false;
  11327.  
  11328.         if (!work->enable_stall_check)
  11329.                 return false;
  11330.  
  11331.         if (work->flip_ready_vblank == 0) {
  11332.                 if (work->flip_queued_req &&
  11333.                     !i915_gem_request_completed(work->flip_queued_req, true))
  11334.                         return false;
  11335.  
  11336.                 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
  11337.         }
  11338.  
  11339.         if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
  11340.                 return false;
  11341.  
  11342.         /* Potential stall - if we see that the flip has happened,
  11343.          * assume a missed interrupt. */
  11344.         if (INTEL_INFO(dev)->gen >= 4)
  11345.                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
  11346.         else
  11347.                 addr = I915_READ(DSPADDR(intel_crtc->plane));
  11348.  
  11349.         /* There is a potential issue here with a false positive after a flip
  11350.          * to the same address. We could address this by checking for a
  11351.          * non-incrementing frame counter.
  11352.          */
  11353.         return addr == work->gtt_offset;
  11354. }
  11355.  
  11356. void intel_check_page_flip(struct drm_device *dev, int pipe)
  11357. {
  11358.         struct drm_i915_private *dev_priv = dev->dev_private;
  11359.         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  11360.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11361.         struct intel_unpin_work *work;
  11362.  
  11363.         WARN_ON(!in_interrupt());
  11364.  
  11365.         if (crtc == NULL)
  11366.                 return;
  11367.  
  11368.         spin_lock(&dev->event_lock);
  11369.         work = intel_crtc->unpin_work;
  11370.         if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
  11371.                 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
  11372.                          work->flip_queued_vblank, drm_vblank_count(dev, pipe));
  11373.                 page_flip_completed(intel_crtc);
  11374.                 work = NULL;
  11375.         }
  11376.         if (work != NULL &&
  11377.             drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
  11378.                 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
  11379.         spin_unlock(&dev->event_lock);
  11380. }
  11381.  
  11382. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  11383.                                 struct drm_framebuffer *fb,
  11384.                                 struct drm_pending_vblank_event *event,
  11385.                                 uint32_t page_flip_flags)
  11386. {
  11387.         struct drm_device *dev = crtc->dev;
  11388.         struct drm_i915_private *dev_priv = dev->dev_private;
  11389.         struct drm_framebuffer *old_fb = crtc->primary->fb;
  11390.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  11391.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11392.         struct drm_plane *primary = crtc->primary;
  11393.         enum pipe pipe = intel_crtc->pipe;
  11394.         struct intel_unpin_work *work;
  11395.         struct intel_engine_cs *ring;
  11396.         bool mmio_flip;
  11397.         struct drm_i915_gem_request *request = NULL;
  11398.         int ret;
  11399.  
  11400.         /*
  11401.          * drm_mode_page_flip_ioctl() should already catch this, but double
  11402.          * check to be safe.  In the future we may enable pageflipping from
  11403.          * a disabled primary plane.
  11404.          */
  11405.         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
  11406.                 return -EBUSY;
  11407.  
  11408.         /* Can't change pixel format via MI display flips. */
  11409.         if (fb->pixel_format != crtc->primary->fb->pixel_format)
  11410.                 return -EINVAL;
  11411.  
  11412.         /*
  11413.          * TILEOFF/LINOFF registers can't be changed via MI display flips.
  11414.          * Note that pitch changes could also affect these register.
  11415.          */
  11416.         if (INTEL_INFO(dev)->gen > 3 &&
  11417.             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
  11418.              fb->pitches[0] != crtc->primary->fb->pitches[0]))
  11419.                 return -EINVAL;
  11420.  
  11421.         if (i915_terminally_wedged(&dev_priv->gpu_error))
  11422.                 goto out_hang;
  11423.  
  11424.         work = kzalloc(sizeof(*work), GFP_KERNEL);
  11425.         if (work == NULL)
  11426.                 return -ENOMEM;
  11427.  
  11428.         work->event = event;
  11429.         work->crtc = crtc;
  11430.         work->old_fb = old_fb;
  11431.         INIT_WORK(&work->work, intel_unpin_work_fn);
  11432.  
  11433.         ret = drm_crtc_vblank_get(crtc);
  11434.         if (ret)
  11435.                 goto free_work;
  11436.  
  11437.         /* We borrow the event spin lock for protecting unpin_work */
  11438.         spin_lock_irq(&dev->event_lock);
  11439.         if (intel_crtc->unpin_work) {
  11440.                 /* Before declaring the flip queue wedged, check if
  11441.                  * the hardware completed the operation behind our backs.
  11442.                  */
  11443.                 if (__intel_pageflip_stall_check(dev, crtc)) {
  11444.                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
  11445.                         page_flip_completed(intel_crtc);
  11446.                 } else {
  11447.                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  11448.                         spin_unlock_irq(&dev->event_lock);
  11449.  
  11450.                         drm_crtc_vblank_put(crtc);
  11451.                         kfree(work);
  11452.                         return -EBUSY;
  11453.                 }
  11454.         }
  11455.         intel_crtc->unpin_work = work;
  11456.         spin_unlock_irq(&dev->event_lock);
  11457.  
  11458.         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  11459.                 flush_workqueue(dev_priv->wq);
  11460.  
  11461.         /* Reference the objects for the scheduled work. */
  11462.         drm_framebuffer_reference(work->old_fb);
  11463.         drm_gem_object_reference(&obj->base);
  11464.  
  11465.         crtc->primary->fb = fb;
  11466.         update_state_fb(crtc->primary);
  11467.  
  11468.         work->pending_flip_obj = obj;
  11469.  
  11470.         ret = i915_mutex_lock_interruptible(dev);
  11471.         if (ret)
  11472.                 goto cleanup;
  11473.  
  11474.         atomic_inc(&intel_crtc->unpin_work_count);
  11475.         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  11476.  
  11477.         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
  11478.                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
  11479.  
  11480.         if (IS_VALLEYVIEW(dev)) {
  11481.                 ring = &dev_priv->ring[BCS];
  11482.                 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
  11483.                         /* vlv: DISPLAY_FLIP fails to change tiling */
  11484.                         ring = NULL;
  11485.         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  11486.                 ring = &dev_priv->ring[BCS];
  11487.         } else if (INTEL_INFO(dev)->gen >= 7) {
  11488.                 ring = i915_gem_request_get_ring(obj->last_write_req);
  11489.                 if (ring == NULL || ring->id != RCS)
  11490.                         ring = &dev_priv->ring[BCS];
  11491.         } else {
  11492.                 ring = &dev_priv->ring[RCS];
  11493.         }
  11494.  
  11495.         mmio_flip = use_mmio_flip(ring, obj);
  11496.  
  11497.         /* When using CS flips, we want to emit semaphores between rings.
  11498.          * However, when using mmio flips we will create a task to do the
  11499.          * synchronisation, so all we want here is to pin the framebuffer
  11500.          * into the display plane and skip any waits.
  11501.          */
  11502.         ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
  11503.                                          crtc->primary->state,
  11504.                                          mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
  11505.         if (ret)
  11506.                 goto cleanup_pending;
  11507.  
  11508.         work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
  11509.                                                   obj, 0);
  11510.         work->gtt_offset += intel_crtc->dspaddr_offset;
  11511.  
  11512.         if (mmio_flip) {
  11513.                 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
  11514.                                             page_flip_flags);
  11515.                 if (ret)
  11516.                         goto cleanup_unpin;
  11517.  
  11518.                 i915_gem_request_assign(&work->flip_queued_req,
  11519.                                         obj->last_write_req);
  11520.         } else {
  11521.                 if (!request) {
  11522.                         ret = i915_gem_request_alloc(ring, ring->default_context, &request);
  11523.                         if (ret)
  11524.                                 goto cleanup_unpin;
  11525.                 }
  11526.  
  11527.                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
  11528.                                                    page_flip_flags);
  11529.                 if (ret)
  11530.                         goto cleanup_unpin;
  11531.  
  11532.                 i915_gem_request_assign(&work->flip_queued_req, request);
  11533.         }
  11534.  
  11535.         if (request)
  11536.                 i915_add_request_no_flush(request);
  11537.  
  11538.         work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
  11539.         work->enable_stall_check = true;
  11540.  
  11541.         i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
  11542.                           to_intel_plane(primary)->frontbuffer_bit);
  11543.         mutex_unlock(&dev->struct_mutex);
  11544.  
  11545.         intel_fbc_disable_crtc(intel_crtc);
  11546.         intel_frontbuffer_flip_prepare(dev,
  11547.                                        to_intel_plane(primary)->frontbuffer_bit);
  11548.  
  11549.         trace_i915_flip_request(intel_crtc->plane, obj);
  11550.  
  11551.         return 0;
  11552.  
  11553. cleanup_unpin:
  11554.         intel_unpin_fb_obj(fb, crtc->primary->state);
  11555. cleanup_pending:
  11556.         if (request)
  11557.                 i915_gem_request_cancel(request);
  11558.         atomic_dec(&intel_crtc->unpin_work_count);
  11559.         mutex_unlock(&dev->struct_mutex);
  11560. cleanup:
  11561.         crtc->primary->fb = old_fb;
  11562.         update_state_fb(crtc->primary);
  11563.  
  11564.         drm_gem_object_unreference_unlocked(&obj->base);
  11565.         drm_framebuffer_unreference(work->old_fb);
  11566.  
  11567.         spin_lock_irq(&dev->event_lock);
  11568.         intel_crtc->unpin_work = NULL;
  11569.         spin_unlock_irq(&dev->event_lock);
  11570.  
  11571.         drm_crtc_vblank_put(crtc);
  11572. free_work:
  11573.         kfree(work);
  11574.  
  11575.         if (ret == -EIO) {
  11576.                 struct drm_atomic_state *state;
  11577.                 struct drm_plane_state *plane_state;
  11578.  
  11579. out_hang:
  11580.                 state = drm_atomic_state_alloc(dev);
  11581.                 if (!state)
  11582.                         return -ENOMEM;
  11583.                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
  11584.  
  11585. retry:
  11586.                 plane_state = drm_atomic_get_plane_state(state, primary);
  11587.                 ret = PTR_ERR_OR_ZERO(plane_state);
  11588.                 if (!ret) {
  11589.                         drm_atomic_set_fb_for_plane(plane_state, fb);
  11590.  
  11591.                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
  11592.                         if (!ret)
  11593.                                 ret = drm_atomic_commit(state);
  11594.                 }
  11595.  
  11596.                 if (ret == -EDEADLK) {
  11597.                         drm_modeset_backoff(state->acquire_ctx);
  11598.                         drm_atomic_state_clear(state);
  11599.                         goto retry;
  11600.                 }
  11601.  
  11602.                 if (ret)
  11603.                         drm_atomic_state_free(state);
  11604.  
  11605.                 if (ret == 0 && event) {
  11606.                         spin_lock_irq(&dev->event_lock);
  11607.                         drm_send_vblank_event(dev, pipe, event);
  11608.                         spin_unlock_irq(&dev->event_lock);
  11609.                 }
  11610.         }
  11611.         return ret;
  11612. }
  11613. #endif
  11614.  
  11615.  
  11616. /**
  11617.  * intel_wm_need_update - Check whether watermarks need updating
  11618.  * @plane: drm plane
  11619.  * @state: new plane state
  11620.  *
  11621.  * Check current plane state versus the new one to determine whether
  11622.  * watermarks need to be recalculated.
  11623.  *
  11624.  * Returns true or false.
  11625.  */
  11626. static bool intel_wm_need_update(struct drm_plane *plane,
  11627.                                  struct drm_plane_state *state)
  11628. {
  11629.         /* Update watermarks on tiling changes. */
  11630.         if (!plane->state->fb || !state->fb ||
  11631.             plane->state->fb->modifier[0] != state->fb->modifier[0] ||
  11632.             plane->state->rotation != state->rotation)
  11633.                 return true;
  11634.  
  11635.         if (plane->state->crtc_w != state->crtc_w)
  11636.                 return true;
  11637.  
  11638.         return false;
  11639. }
  11640.  
  11641. int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
  11642.                                     struct drm_plane_state *plane_state)
  11643. {
  11644.         struct drm_crtc *crtc = crtc_state->crtc;
  11645.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11646.         struct drm_plane *plane = plane_state->plane;
  11647.         struct drm_device *dev = crtc->dev;
  11648.         struct drm_i915_private *dev_priv = dev->dev_private;
  11649.         struct intel_plane_state *old_plane_state =
  11650.                 to_intel_plane_state(plane->state);
  11651.         int idx = intel_crtc->base.base.id, ret;
  11652.         int i = drm_plane_index(plane);
  11653.         bool mode_changed = needs_modeset(crtc_state);
  11654.         bool was_crtc_enabled = crtc->state->active;
  11655.         bool is_crtc_enabled = crtc_state->active;
  11656.  
  11657.         bool turn_off, turn_on, visible, was_visible;
  11658.         struct drm_framebuffer *fb = plane_state->fb;
  11659.  
  11660.         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
  11661.             plane->type != DRM_PLANE_TYPE_CURSOR) {
  11662.                 ret = skl_update_scaler_plane(
  11663.                         to_intel_crtc_state(crtc_state),
  11664.                         to_intel_plane_state(plane_state));
  11665.                 if (ret)
  11666.                         return ret;
  11667.         }
  11668.  
  11669.         /*
  11670.          * Disabling a plane is always okay; we just need to update
  11671.          * fb tracking in a special way since cleanup_fb() won't
  11672.          * get called by the plane helpers.
  11673.          */
  11674.         if (old_plane_state->base.fb && !fb)
  11675.                 intel_crtc->atomic.disabled_planes |= 1 << i;
  11676.  
  11677.         was_visible = old_plane_state->visible;
  11678.         visible = to_intel_plane_state(plane_state)->visible;
  11679.  
  11680.         if (!was_crtc_enabled && WARN_ON(was_visible))
  11681.                 was_visible = false;
  11682.  
  11683.         if (!is_crtc_enabled && WARN_ON(visible))
  11684.                 visible = false;
  11685.  
  11686.         if (!was_visible && !visible)
  11687.                 return 0;
  11688.  
  11689.         turn_off = was_visible && (!visible || mode_changed);
  11690.         turn_on = visible && (!was_visible || mode_changed);
  11691.  
  11692.         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
  11693.                          plane->base.id, fb ? fb->base.id : -1);
  11694.  
  11695.         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
  11696.                          plane->base.id, was_visible, visible,
  11697.                          turn_off, turn_on, mode_changed);
  11698.  
  11699.         if (turn_on) {
  11700.                 intel_crtc->atomic.update_wm_pre = true;
  11701.                 /* must disable cxsr around plane enable/disable */
  11702.                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  11703.                         intel_crtc->atomic.disable_cxsr = true;
  11704.                         /* to potentially re-enable cxsr */
  11705.                         intel_crtc->atomic.wait_vblank = true;
  11706.                         intel_crtc->atomic.update_wm_post = true;
  11707.                 }
  11708.         } else if (turn_off) {
  11709.                 intel_crtc->atomic.update_wm_post = true;
  11710.                 /* must disable cxsr around plane enable/disable */
  11711.                 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  11712.                         if (is_crtc_enabled)
  11713.                                 intel_crtc->atomic.wait_vblank = true;
  11714.                         intel_crtc->atomic.disable_cxsr = true;
  11715.                 }
  11716.         } else if (intel_wm_need_update(plane, plane_state)) {
  11717.                 intel_crtc->atomic.update_wm_pre = true;
  11718.         }
  11719.  
  11720.         if (visible || was_visible)
  11721.                 intel_crtc->atomic.fb_bits |=
  11722.                         to_intel_plane(plane)->frontbuffer_bit;
  11723.  
  11724.         switch (plane->type) {
  11725.         case DRM_PLANE_TYPE_PRIMARY:
  11726.                 intel_crtc->atomic.wait_for_flips = true;
  11727.                 intel_crtc->atomic.pre_disable_primary = turn_off;
  11728.                 intel_crtc->atomic.post_enable_primary = turn_on;
  11729.  
  11730.                 if (turn_off) {
  11731.                         /*
  11732.                          * FIXME: Actually if we will still have any other
  11733.                          * plane enabled on the pipe we could let IPS enabled
  11734.                          * still, but for now lets consider that when we make
  11735.                          * primary invisible by setting DSPCNTR to 0 on
  11736.                          * update_primary_plane function IPS needs to be
  11737.                          * disable.
  11738.                          */
  11739.                         intel_crtc->atomic.disable_ips = true;
  11740.  
  11741.                         intel_crtc->atomic.disable_fbc = true;
  11742.                 }
  11743.  
  11744.                 /*
  11745.                  * FBC does not work on some platforms for rotated
  11746.                  * planes, so disable it when rotation is not 0 and
  11747.                  * update it when rotation is set back to 0.
  11748.                  *
  11749.                  * FIXME: This is redundant with the fbc update done in
  11750.                  * the primary plane enable function except that that
  11751.                  * one is done too late. We eventually need to unify
  11752.                  * this.
  11753.                  */
  11754.  
  11755.                 if (visible &&
  11756.                     INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
  11757.                     dev_priv->fbc.crtc == intel_crtc &&
  11758.                     plane_state->rotation != BIT(DRM_ROTATE_0))
  11759.                         intel_crtc->atomic.disable_fbc = true;
  11760.  
  11761.                 /*
  11762.                  * BDW signals flip done immediately if the plane
  11763.                  * is disabled, even if the plane enable is already
  11764.                  * armed to occur at the next vblank :(
  11765.                  */
  11766.                 if (turn_on && IS_BROADWELL(dev))
  11767.                         intel_crtc->atomic.wait_vblank = true;
  11768.  
  11769.                 intel_crtc->atomic.update_fbc |= visible || mode_changed;
  11770.                 break;
  11771.         case DRM_PLANE_TYPE_CURSOR:
  11772.                 break;
  11773.         case DRM_PLANE_TYPE_OVERLAY:
  11774.                 if (turn_off && !mode_changed) {
  11775.                         intel_crtc->atomic.wait_vblank = true;
  11776.                         intel_crtc->atomic.update_sprite_watermarks |=
  11777.                                 1 << i;
  11778.                 }
  11779.         }
  11780.         return 0;
  11781. }
  11782.  
  11783. static bool encoders_cloneable(const struct intel_encoder *a,
  11784.                                const struct intel_encoder *b)
  11785. {
  11786.         /* masks could be asymmetric, so check both ways */
  11787.         return a == b || (a->cloneable & (1 << b->type) &&
  11788.                           b->cloneable & (1 << a->type));
  11789. }
  11790.  
  11791. static bool check_single_encoder_cloning(struct drm_atomic_state *state,
  11792.                                          struct intel_crtc *crtc,
  11793.                                          struct intel_encoder *encoder)
  11794. {
  11795.         struct intel_encoder *source_encoder;
  11796.         struct drm_connector *connector;
  11797.         struct drm_connector_state *connector_state;
  11798.         int i;
  11799.  
  11800.         for_each_connector_in_state(state, connector, connector_state, i) {
  11801.                 if (connector_state->crtc != &crtc->base)
  11802.                         continue;
  11803.  
  11804.                 source_encoder =
  11805.                         to_intel_encoder(connector_state->best_encoder);
  11806.                 if (!encoders_cloneable(encoder, source_encoder))
  11807.                         return false;
  11808.         }
  11809.  
  11810.         return true;
  11811. }
  11812.  
  11813. static bool check_encoder_cloning(struct drm_atomic_state *state,
  11814.                                   struct intel_crtc *crtc)
  11815. {
  11816.         struct intel_encoder *encoder;
  11817.         struct drm_connector *connector;
  11818.         struct drm_connector_state *connector_state;
  11819.         int i;
  11820.  
  11821.         for_each_connector_in_state(state, connector, connector_state, i) {
  11822.                 if (connector_state->crtc != &crtc->base)
  11823.                         continue;
  11824.  
  11825.                 encoder = to_intel_encoder(connector_state->best_encoder);
  11826.                 if (!check_single_encoder_cloning(state, crtc, encoder))
  11827.                         return false;
  11828.         }
  11829.  
  11830.         return true;
  11831. }
  11832.  
  11833. static int intel_crtc_atomic_check(struct drm_crtc *crtc,
  11834.                                    struct drm_crtc_state *crtc_state)
  11835. {
  11836.         struct drm_device *dev = crtc->dev;
  11837.         struct drm_i915_private *dev_priv = dev->dev_private;
  11838.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  11839.         struct intel_crtc_state *pipe_config =
  11840.                 to_intel_crtc_state(crtc_state);
  11841.         struct drm_atomic_state *state = crtc_state->state;
  11842.         int ret;
  11843.         bool mode_changed = needs_modeset(crtc_state);
  11844.  
  11845.         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
  11846.                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  11847.                 return -EINVAL;
  11848.         }
  11849.  
  11850.         if (mode_changed && !crtc_state->active)
  11851.                 intel_crtc->atomic.update_wm_post = true;
  11852.  
  11853.         if (mode_changed && crtc_state->enable &&
  11854.             dev_priv->display.crtc_compute_clock &&
  11855.             !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
  11856.                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
  11857.                                                            pipe_config);
  11858.                 if (ret)
  11859.                         return ret;
  11860.         }
  11861.  
  11862.         ret = 0;
  11863.         if (INTEL_INFO(dev)->gen >= 9) {
  11864.                 if (mode_changed)
  11865.                         ret = skl_update_scaler_crtc(pipe_config);
  11866.  
  11867.                 if (!ret)
  11868.                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
  11869.                                                          pipe_config);
  11870.         }
  11871.  
  11872.         return ret;
  11873. }
  11874.  
  11875. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  11876.         .mode_set_base_atomic = intel_pipe_set_base_atomic,
  11877.         .load_lut = intel_crtc_load_lut,
  11878.         .atomic_begin = intel_begin_crtc_commit,
  11879.         .atomic_flush = intel_finish_crtc_commit,
  11880.         .atomic_check = intel_crtc_atomic_check,
  11881. };
  11882.  
  11883. static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
  11884. {
  11885.         struct intel_connector *connector;
  11886.  
  11887.         for_each_intel_connector(dev, connector) {
  11888.                 if (connector->base.encoder) {
  11889.                         connector->base.state->best_encoder =
  11890.                                 connector->base.encoder;
  11891.                         connector->base.state->crtc =
  11892.                                 connector->base.encoder->crtc;
  11893.                 } else {
  11894.                         connector->base.state->best_encoder = NULL;
  11895.                         connector->base.state->crtc = NULL;
  11896.                 }
  11897.         }
  11898. }
  11899.  
  11900. static void
  11901. connected_sink_compute_bpp(struct intel_connector *connector,
  11902.                            struct intel_crtc_state *pipe_config)
  11903. {
  11904.         int bpp = pipe_config->pipe_bpp;
  11905.  
  11906.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  11907.                 connector->base.base.id,
  11908.                 connector->base.name);
  11909.  
  11910.         /* Don't use an invalid EDID bpc value */
  11911.         if (connector->base.display_info.bpc &&
  11912.             connector->base.display_info.bpc * 3 < bpp) {
  11913.                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  11914.                               bpp, connector->base.display_info.bpc*3);
  11915.                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  11916.         }
  11917.  
  11918.         /* Clamp bpp to 8 on screens without EDID 1.4 */
  11919.         if (connector->base.display_info.bpc == 0 && bpp > 24) {
  11920.                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  11921.                               bpp);
  11922.                 pipe_config->pipe_bpp = 24;
  11923.         }
  11924. }
  11925.  
  11926. static int
  11927. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  11928.                           struct intel_crtc_state *pipe_config)
  11929. {
  11930.         struct drm_device *dev = crtc->base.dev;
  11931.         struct drm_atomic_state *state;
  11932.         struct drm_connector *connector;
  11933.         struct drm_connector_state *connector_state;
  11934.         int bpp, i;
  11935.  
  11936.         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
  11937.                 bpp = 10*3;
  11938.         else if (INTEL_INFO(dev)->gen >= 5)
  11939.                 bpp = 12*3;
  11940.         else
  11941.                 bpp = 8*3;
  11942.  
  11943.  
  11944.         pipe_config->pipe_bpp = bpp;
  11945.  
  11946.         state = pipe_config->base.state;
  11947.  
  11948.         /* Clamp display bpp to EDID value */
  11949.         for_each_connector_in_state(state, connector, connector_state, i) {
  11950.                 if (connector_state->crtc != &crtc->base)
  11951.                         continue;
  11952.  
  11953.                 connected_sink_compute_bpp(to_intel_connector(connector),
  11954.                                            pipe_config);
  11955.         }
  11956.  
  11957.         return bpp;
  11958. }
  11959.  
  11960. static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
  11961. {
  11962.         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
  11963.                         "type: 0x%x flags: 0x%x\n",
  11964.                 mode->crtc_clock,
  11965.                 mode->crtc_hdisplay, mode->crtc_hsync_start,
  11966.                 mode->crtc_hsync_end, mode->crtc_htotal,
  11967.                 mode->crtc_vdisplay, mode->crtc_vsync_start,
  11968.                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
  11969. }
  11970.  
  11971. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  11972.                                    struct intel_crtc_state *pipe_config,
  11973.                                    const char *context)
  11974. {
  11975.         struct drm_device *dev = crtc->base.dev;
  11976.         struct drm_plane *plane;
  11977.         struct intel_plane *intel_plane;
  11978.         struct intel_plane_state *state;
  11979.         struct drm_framebuffer *fb;
  11980.  
  11981.         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
  11982.                       context, pipe_config, pipe_name(crtc->pipe));
  11983.  
  11984.         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
  11985.         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  11986.                       pipe_config->pipe_bpp, pipe_config->dither);
  11987.         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  11988.                       pipe_config->has_pch_encoder,
  11989.                       pipe_config->fdi_lanes,
  11990.                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  11991.                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  11992.                       pipe_config->fdi_m_n.tu);
  11993.         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  11994.                       pipe_config->has_dp_encoder,
  11995.                       pipe_config->lane_count,
  11996.                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
  11997.                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
  11998.                       pipe_config->dp_m_n.tu);
  11999.  
  12000.         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
  12001.                       pipe_config->has_dp_encoder,
  12002.                       pipe_config->lane_count,
  12003.                       pipe_config->dp_m2_n2.gmch_m,
  12004.                       pipe_config->dp_m2_n2.gmch_n,
  12005.                       pipe_config->dp_m2_n2.link_m,
  12006.                       pipe_config->dp_m2_n2.link_n,
  12007.                       pipe_config->dp_m2_n2.tu);
  12008.  
  12009.         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
  12010.                       pipe_config->has_audio,
  12011.                       pipe_config->has_infoframe);
  12012.  
  12013.         DRM_DEBUG_KMS("requested mode:\n");
  12014.         drm_mode_debug_printmodeline(&pipe_config->base.mode);
  12015.         DRM_DEBUG_KMS("adjusted mode:\n");
  12016.         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
  12017.         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
  12018.         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
  12019.         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
  12020.                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
  12021.         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
  12022.                       crtc->num_scalers,
  12023.                       pipe_config->scaler_state.scaler_users,
  12024.                       pipe_config->scaler_state.scaler_id);
  12025.         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  12026.                       pipe_config->gmch_pfit.control,
  12027.                       pipe_config->gmch_pfit.pgm_ratios,
  12028.                       pipe_config->gmch_pfit.lvds_border_bits);
  12029.         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
  12030.                       pipe_config->pch_pfit.pos,
  12031.                       pipe_config->pch_pfit.size,
  12032.                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
  12033.         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  12034.         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
  12035.  
  12036.         if (IS_BROXTON(dev)) {
  12037.                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
  12038.                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
  12039.                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
  12040.                               pipe_config->ddi_pll_sel,
  12041.                               pipe_config->dpll_hw_state.ebb0,
  12042.                               pipe_config->dpll_hw_state.ebb4,
  12043.                               pipe_config->dpll_hw_state.pll0,
  12044.                               pipe_config->dpll_hw_state.pll1,
  12045.                               pipe_config->dpll_hw_state.pll2,
  12046.                               pipe_config->dpll_hw_state.pll3,
  12047.                               pipe_config->dpll_hw_state.pll6,
  12048.                               pipe_config->dpll_hw_state.pll8,
  12049.                               pipe_config->dpll_hw_state.pll9,
  12050.                               pipe_config->dpll_hw_state.pll10,
  12051.                               pipe_config->dpll_hw_state.pcsdw12);
  12052.         } else if (IS_SKYLAKE(dev)) {
  12053.                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
  12054.                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
  12055.                               pipe_config->ddi_pll_sel,
  12056.                               pipe_config->dpll_hw_state.ctrl1,
  12057.                               pipe_config->dpll_hw_state.cfgcr1,
  12058.                               pipe_config->dpll_hw_state.cfgcr2);
  12059.         } else if (HAS_DDI(dev)) {
  12060.                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
  12061.                               pipe_config->ddi_pll_sel,
  12062.                               pipe_config->dpll_hw_state.wrpll,
  12063.                               pipe_config->dpll_hw_state.spll);
  12064.         } else {
  12065.                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
  12066.                               "fp0: 0x%x, fp1: 0x%x\n",
  12067.                               pipe_config->dpll_hw_state.dpll,
  12068.                               pipe_config->dpll_hw_state.dpll_md,
  12069.                               pipe_config->dpll_hw_state.fp0,
  12070.                               pipe_config->dpll_hw_state.fp1);
  12071.         }
  12072.  
  12073.         DRM_DEBUG_KMS("planes on this crtc\n");
  12074.         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
  12075.                 intel_plane = to_intel_plane(plane);
  12076.                 if (intel_plane->pipe != crtc->pipe)
  12077.                         continue;
  12078.  
  12079.                 state = to_intel_plane_state(plane->state);
  12080.                 fb = state->base.fb;
  12081.                 if (!fb) {
  12082.                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
  12083.                                 "disabled, scaler_id = %d\n",
  12084.                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
  12085.                                 plane->base.id, intel_plane->pipe,
  12086.                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
  12087.                                 drm_plane_index(plane), state->scaler_id);
  12088.                         continue;
  12089.                 }
  12090.  
  12091.                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
  12092.                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
  12093.                         plane->base.id, intel_plane->pipe,
  12094.                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
  12095.                         drm_plane_index(plane));
  12096.                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
  12097.                         fb->base.id, fb->width, fb->height, fb->pixel_format);
  12098.                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
  12099.                         state->scaler_id,
  12100.                         state->src.x1 >> 16, state->src.y1 >> 16,
  12101.                         drm_rect_width(&state->src) >> 16,
  12102.                         drm_rect_height(&state->src) >> 16,
  12103.                         state->dst.x1, state->dst.y1,
  12104.                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
  12105.         }
  12106. }
  12107.  
  12108. static bool check_digital_port_conflicts(struct drm_atomic_state *state)
  12109. {
  12110.         struct drm_device *dev = state->dev;
  12111.         struct drm_connector *connector;
  12112.         unsigned int used_ports = 0;
  12113.  
  12114.         /*
  12115.          * Walk the connector list instead of the encoder
  12116.          * list to detect the problem on ddi platforms
  12117.          * where there's just one encoder per digital port.
  12118.          */
  12119.         drm_for_each_connector(connector, dev) {
  12120.                 struct drm_connector_state *connector_state;
  12121.                 struct intel_encoder *encoder;
  12122.  
  12123.                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
  12124.                 if (!connector_state)
  12125.                         connector_state = connector->state;
  12126.  
  12127.                 if (!connector_state->best_encoder)
  12128.                         continue;
  12129.  
  12130.                 encoder = to_intel_encoder(connector_state->best_encoder);
  12131.  
  12132.                 WARN_ON(!connector_state->crtc);
  12133.  
  12134.                 switch (encoder->type) {
  12135.                         unsigned int port_mask;
  12136.                 case INTEL_OUTPUT_UNKNOWN:
  12137.                         if (WARN_ON(!HAS_DDI(dev)))
  12138.                                 break;
  12139.                 case INTEL_OUTPUT_DISPLAYPORT:
  12140.                 case INTEL_OUTPUT_HDMI:
  12141.                 case INTEL_OUTPUT_EDP:
  12142.                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
  12143.  
  12144.                         /* the same port mustn't appear more than once */
  12145.                         if (used_ports & port_mask)
  12146.                                 return false;
  12147.  
  12148.                         used_ports |= port_mask;
  12149.                 default:
  12150.                         break;
  12151.                 }
  12152.         }
  12153.  
  12154.         return true;
  12155. }
  12156.  
  12157. static void
  12158. clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
  12159. {
  12160.         struct drm_crtc_state tmp_state;
  12161.         struct intel_crtc_scaler_state scaler_state;
  12162.         struct intel_dpll_hw_state dpll_hw_state;
  12163.         enum intel_dpll_id shared_dpll;
  12164.         uint32_t ddi_pll_sel;
  12165.         bool force_thru;
  12166.  
  12167.         /* FIXME: before the switch to atomic started, a new pipe_config was
  12168.          * kzalloc'd. Code that depends on any field being zero should be
  12169.          * fixed, so that the crtc_state can be safely duplicated. For now,
  12170.          * only fields that are know to not cause problems are preserved. */
  12171.  
  12172.         tmp_state = crtc_state->base;
  12173.         scaler_state = crtc_state->scaler_state;
  12174.         shared_dpll = crtc_state->shared_dpll;
  12175.         dpll_hw_state = crtc_state->dpll_hw_state;
  12176.         ddi_pll_sel = crtc_state->ddi_pll_sel;
  12177.         force_thru = crtc_state->pch_pfit.force_thru;
  12178.  
  12179.         memset(crtc_state, 0, sizeof *crtc_state);
  12180.  
  12181.         crtc_state->base = tmp_state;
  12182.         crtc_state->scaler_state = scaler_state;
  12183.         crtc_state->shared_dpll = shared_dpll;
  12184.         crtc_state->dpll_hw_state = dpll_hw_state;
  12185.         crtc_state->ddi_pll_sel = ddi_pll_sel;
  12186.         crtc_state->pch_pfit.force_thru = force_thru;
  12187. }
  12188.  
  12189. static int
  12190. intel_modeset_pipe_config(struct drm_crtc *crtc,
  12191.                           struct intel_crtc_state *pipe_config)
  12192. {
  12193.         struct drm_atomic_state *state = pipe_config->base.state;
  12194.         struct intel_encoder *encoder;
  12195.         struct drm_connector *connector;
  12196.         struct drm_connector_state *connector_state;
  12197.         int base_bpp, ret = -EINVAL;
  12198.         int i;
  12199.         bool retry = true;
  12200.  
  12201.         clear_intel_crtc_state(pipe_config);
  12202.  
  12203.         pipe_config->cpu_transcoder =
  12204.                 (enum transcoder) to_intel_crtc(crtc)->pipe;
  12205.  
  12206.         /*
  12207.          * Sanitize sync polarity flags based on requested ones. If neither
  12208.          * positive or negative polarity is requested, treat this as meaning
  12209.          * negative polarity.
  12210.          */
  12211.         if (!(pipe_config->base.adjusted_mode.flags &
  12212.               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
  12213.                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
  12214.  
  12215.         if (!(pipe_config->base.adjusted_mode.flags &
  12216.               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
  12217.                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
  12218.  
  12219.         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  12220.                                              pipe_config);
  12221.         if (base_bpp < 0)
  12222.                 goto fail;
  12223.  
  12224.         /*
  12225.          * Determine the real pipe dimensions. Note that stereo modes can
  12226.          * increase the actual pipe size due to the frame doubling and
  12227.          * insertion of additional space for blanks between the frame. This
  12228.          * is stored in the crtc timings. We use the requested mode to do this
  12229.          * computation to clearly distinguish it from the adjusted mode, which
  12230.          * can be changed by the connectors in the below retry loop.
  12231.          */
  12232.         drm_crtc_get_hv_timing(&pipe_config->base.mode,
  12233.                                &pipe_config->pipe_src_w,
  12234.                                &pipe_config->pipe_src_h);
  12235.  
  12236. encoder_retry:
  12237.         /* Ensure the port clock defaults are reset when retrying. */
  12238.         pipe_config->port_clock = 0;
  12239.         pipe_config->pixel_multiplier = 1;
  12240.  
  12241.         /* Fill in default crtc timings, allow encoders to overwrite them. */
  12242.         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
  12243.                               CRTC_STEREO_DOUBLE);
  12244.  
  12245.         /* Pass our mode to the connectors and the CRTC to give them a chance to
  12246.          * adjust it according to limitations or connector properties, and also
  12247.          * a chance to reject the mode entirely.
  12248.          */
  12249.         for_each_connector_in_state(state, connector, connector_state, i) {
  12250.                 if (connector_state->crtc != crtc)
  12251.                         continue;
  12252.  
  12253.                 encoder = to_intel_encoder(connector_state->best_encoder);
  12254.  
  12255.                 if (!(encoder->compute_config(encoder, pipe_config))) {
  12256.                         DRM_DEBUG_KMS("Encoder config failure\n");
  12257.                         goto fail;
  12258.                 }
  12259.         }
  12260.  
  12261.         /* Set default port clock if not overwritten by the encoder. Needs to be
  12262.          * done afterwards in case the encoder adjusts the mode. */
  12263.         if (!pipe_config->port_clock)
  12264.                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
  12265.                         * pipe_config->pixel_multiplier;
  12266.  
  12267.         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  12268.         if (ret < 0) {
  12269.                 DRM_DEBUG_KMS("CRTC fixup failed\n");
  12270.                 goto fail;
  12271.         }
  12272.  
  12273.         if (ret == RETRY) {
  12274.                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
  12275.                         ret = -EINVAL;
  12276.                         goto fail;
  12277.                 }
  12278.  
  12279.                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  12280.                 retry = false;
  12281.                 goto encoder_retry;
  12282.         }
  12283.  
  12284.         /* Dithering seems to not pass-through bits correctly when it should, so
  12285.          * only enable it on 6bpc panels. */
  12286.         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
  12287.         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
  12288.                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  12289.  
  12290. fail:
  12291.         return ret;
  12292. }
  12293.  
  12294. static void
  12295. intel_modeset_update_crtc_state(struct drm_atomic_state *state)
  12296. {
  12297.         struct drm_crtc *crtc;
  12298.         struct drm_crtc_state *crtc_state;
  12299.         int i;
  12300.  
  12301.         /* Double check state. */
  12302.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  12303.                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
  12304.  
  12305.                 /* Update hwmode for vblank functions */
  12306.                 if (crtc->state->active)
  12307.                         crtc->hwmode = crtc->state->adjusted_mode;
  12308.                 else
  12309.                         crtc->hwmode.crtc_clock = 0;
  12310.         }
  12311. }
  12312.  
  12313. static bool intel_fuzzy_clock_check(int clock1, int clock2)
  12314. {
  12315.         int diff;
  12316.  
  12317.         if (clock1 == clock2)
  12318.                 return true;
  12319.  
  12320.         if (!clock1 || !clock2)
  12321.                 return false;
  12322.  
  12323.         diff = abs(clock1 - clock2);
  12324.  
  12325.         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  12326.                 return true;
  12327.  
  12328.         return false;
  12329. }
  12330.  
  12331. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  12332.         list_for_each_entry((intel_crtc), \
  12333.                             &(dev)->mode_config.crtc_list, \
  12334.                             base.head) \
  12335.                 if (mask & (1 <<(intel_crtc)->pipe))
  12336.  
  12337. static bool
  12338. intel_compare_m_n(unsigned int m, unsigned int n,
  12339.                   unsigned int m2, unsigned int n2,
  12340.                   bool exact)
  12341. {
  12342.         if (m == m2 && n == n2)
  12343.                 return true;
  12344.  
  12345.         if (exact || !m || !n || !m2 || !n2)
  12346.                 return false;
  12347.  
  12348.         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
  12349.  
  12350.         if (m > m2) {
  12351.                 while (m > m2) {
  12352.                         m2 <<= 1;
  12353.                         n2 <<= 1;
  12354.                 }
  12355.         } else if (m < m2) {
  12356.                 while (m < m2) {
  12357.                         m <<= 1;
  12358.                         n <<= 1;
  12359.                 }
  12360.         }
  12361.  
  12362.         return m == m2 && n == n2;
  12363. }
  12364.  
  12365. static bool
  12366. intel_compare_link_m_n(const struct intel_link_m_n *m_n,
  12367.                        struct intel_link_m_n *m2_n2,
  12368.                        bool adjust)
  12369. {
  12370.         if (m_n->tu == m2_n2->tu &&
  12371.             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
  12372.                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
  12373.             intel_compare_m_n(m_n->link_m, m_n->link_n,
  12374.                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
  12375.                 if (adjust)
  12376.                         *m2_n2 = *m_n;
  12377.  
  12378.                 return true;
  12379.         }
  12380.  
  12381.         return false;
  12382. }
  12383.  
  12384. static bool
  12385. intel_pipe_config_compare(struct drm_device *dev,
  12386.                           struct intel_crtc_state *current_config,
  12387.                           struct intel_crtc_state *pipe_config,
  12388.                           bool adjust)
  12389. {
  12390.         bool ret = true;
  12391.  
  12392. #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
  12393.         do { \
  12394.                 if (!adjust) \
  12395.                         DRM_ERROR(fmt, ##__VA_ARGS__); \
  12396.                 else \
  12397.                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
  12398.         } while (0)
  12399.  
  12400. #define PIPE_CONF_CHECK_X(name) \
  12401.         if (current_config->name != pipe_config->name) { \
  12402.                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  12403.                           "(expected 0x%08x, found 0x%08x)\n", \
  12404.                           current_config->name, \
  12405.                           pipe_config->name); \
  12406.                 ret = false; \
  12407.         }
  12408.  
  12409. #define PIPE_CONF_CHECK_I(name) \
  12410.         if (current_config->name != pipe_config->name) { \
  12411.                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  12412.                           "(expected %i, found %i)\n", \
  12413.                           current_config->name, \
  12414.                           pipe_config->name); \
  12415.                 ret = false; \
  12416.         }
  12417.  
  12418. #define PIPE_CONF_CHECK_M_N(name) \
  12419.         if (!intel_compare_link_m_n(&current_config->name, \
  12420.                                     &pipe_config->name,\
  12421.                                     adjust)) { \
  12422.                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  12423.                           "(expected tu %i gmch %i/%i link %i/%i, " \
  12424.                           "found tu %i, gmch %i/%i link %i/%i)\n", \
  12425.                           current_config->name.tu, \
  12426.                           current_config->name.gmch_m, \
  12427.                           current_config->name.gmch_n, \
  12428.                           current_config->name.link_m, \
  12429.                           current_config->name.link_n, \
  12430.                           pipe_config->name.tu, \
  12431.                           pipe_config->name.gmch_m, \
  12432.                           pipe_config->name.gmch_n, \
  12433.                           pipe_config->name.link_m, \
  12434.                           pipe_config->name.link_n); \
  12435.                 ret = false; \
  12436.         }
  12437.  
  12438. #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
  12439.         if (!intel_compare_link_m_n(&current_config->name, \
  12440.                                     &pipe_config->name, adjust) && \
  12441.             !intel_compare_link_m_n(&current_config->alt_name, \
  12442.                                     &pipe_config->name, adjust)) { \
  12443.                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  12444.                           "(expected tu %i gmch %i/%i link %i/%i, " \
  12445.                           "or tu %i gmch %i/%i link %i/%i, " \
  12446.                           "found tu %i, gmch %i/%i link %i/%i)\n", \
  12447.                           current_config->name.tu, \
  12448.                           current_config->name.gmch_m, \
  12449.                           current_config->name.gmch_n, \
  12450.                           current_config->name.link_m, \
  12451.                           current_config->name.link_n, \
  12452.                           current_config->alt_name.tu, \
  12453.                           current_config->alt_name.gmch_m, \
  12454.                           current_config->alt_name.gmch_n, \
  12455.                           current_config->alt_name.link_m, \
  12456.                           current_config->alt_name.link_n, \
  12457.                           pipe_config->name.tu, \
  12458.                           pipe_config->name.gmch_m, \
  12459.                           pipe_config->name.gmch_n, \
  12460.                           pipe_config->name.link_m, \
  12461.                           pipe_config->name.link_n); \
  12462.                 ret = false; \
  12463.         }
  12464.  
  12465. /* This is required for BDW+ where there is only one set of registers for
  12466.  * switching between high and low RR.
  12467.  * This macro can be used whenever a comparison has to be made between one
  12468.  * hw state and multiple sw state variables.
  12469.  */
  12470. #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
  12471.         if ((current_config->name != pipe_config->name) && \
  12472.                 (current_config->alt_name != pipe_config->name)) { \
  12473.                         INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  12474.                                   "(expected %i or %i, found %i)\n", \
  12475.                                   current_config->name, \
  12476.                                   current_config->alt_name, \
  12477.                                   pipe_config->name); \
  12478.                         ret = false; \
  12479.         }
  12480.  
  12481. #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
  12482.         if ((current_config->name ^ pipe_config->name) & (mask)) { \
  12483.                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
  12484.                           "(expected %i, found %i)\n", \
  12485.                           current_config->name & (mask), \
  12486.                           pipe_config->name & (mask)); \
  12487.                 ret = false; \
  12488.         }
  12489.  
  12490. #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
  12491.         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
  12492.                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
  12493.                           "(expected %i, found %i)\n", \
  12494.                           current_config->name, \
  12495.                           pipe_config->name); \
  12496.                 ret = false; \
  12497.         }
  12498.  
  12499. #define PIPE_CONF_QUIRK(quirk)  \
  12500.         ((current_config->quirks | pipe_config->quirks) & (quirk))
  12501.  
  12502.         PIPE_CONF_CHECK_I(cpu_transcoder);
  12503.  
  12504.         PIPE_CONF_CHECK_I(has_pch_encoder);
  12505.         PIPE_CONF_CHECK_I(fdi_lanes);
  12506.         PIPE_CONF_CHECK_M_N(fdi_m_n);
  12507.  
  12508.         PIPE_CONF_CHECK_I(has_dp_encoder);
  12509.         PIPE_CONF_CHECK_I(lane_count);
  12510.  
  12511.         if (INTEL_INFO(dev)->gen < 8) {
  12512.                 PIPE_CONF_CHECK_M_N(dp_m_n);
  12513.  
  12514.                 if (current_config->has_drrs)
  12515.                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
  12516.         } else
  12517.                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
  12518.  
  12519.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
  12520.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
  12521.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
  12522.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
  12523.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
  12524.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
  12525.  
  12526.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
  12527.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
  12528.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
  12529.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
  12530.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
  12531.         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
  12532.  
  12533.         PIPE_CONF_CHECK_I(pixel_multiplier);
  12534.         PIPE_CONF_CHECK_I(has_hdmi_sink);
  12535.         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
  12536.             IS_VALLEYVIEW(dev))
  12537.                 PIPE_CONF_CHECK_I(limited_color_range);
  12538.         PIPE_CONF_CHECK_I(has_infoframe);
  12539.  
  12540.         PIPE_CONF_CHECK_I(has_audio);
  12541.  
  12542.         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  12543.                               DRM_MODE_FLAG_INTERLACE);
  12544.  
  12545.         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  12546.                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  12547.                                       DRM_MODE_FLAG_PHSYNC);
  12548.                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  12549.                                       DRM_MODE_FLAG_NHSYNC);
  12550.                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  12551.                                       DRM_MODE_FLAG_PVSYNC);
  12552.                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
  12553.                                       DRM_MODE_FLAG_NVSYNC);
  12554.         }
  12555.  
  12556.         PIPE_CONF_CHECK_X(gmch_pfit.control);
  12557.         /* pfit ratios are autocomputed by the hw on gen4+ */
  12558.         if (INTEL_INFO(dev)->gen < 4)
  12559.                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
  12560.         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
  12561.  
  12562.         if (!adjust) {
  12563.                 PIPE_CONF_CHECK_I(pipe_src_w);
  12564.                 PIPE_CONF_CHECK_I(pipe_src_h);
  12565.  
  12566.                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
  12567.                 if (current_config->pch_pfit.enabled) {
  12568.                         PIPE_CONF_CHECK_X(pch_pfit.pos);
  12569.                         PIPE_CONF_CHECK_X(pch_pfit.size);
  12570.                 }
  12571.  
  12572.                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
  12573.         }
  12574.  
  12575.         /* BDW+ don't expose a synchronous way to read the state */
  12576.         if (IS_HASWELL(dev))
  12577.                 PIPE_CONF_CHECK_I(ips_enabled);
  12578.  
  12579.         PIPE_CONF_CHECK_I(double_wide);
  12580.  
  12581.         PIPE_CONF_CHECK_X(ddi_pll_sel);
  12582.  
  12583.         PIPE_CONF_CHECK_I(shared_dpll);
  12584.         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  12585.         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  12586.         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  12587.         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  12588.         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
  12589.         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
  12590.         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
  12591.         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
  12592.         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
  12593.  
  12594.         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
  12595.                 PIPE_CONF_CHECK_I(pipe_bpp);
  12596.  
  12597.         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
  12598.         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
  12599.  
  12600. #undef PIPE_CONF_CHECK_X
  12601. #undef PIPE_CONF_CHECK_I
  12602. #undef PIPE_CONF_CHECK_I_ALT
  12603. #undef PIPE_CONF_CHECK_FLAGS
  12604. #undef PIPE_CONF_CHECK_CLOCK_FUZZY
  12605. #undef PIPE_CONF_QUIRK
  12606. #undef INTEL_ERR_OR_DBG_KMS
  12607.  
  12608.         return ret;
  12609. }
  12610.  
  12611. static void check_wm_state(struct drm_device *dev)
  12612. {
  12613.         struct drm_i915_private *dev_priv = dev->dev_private;
  12614.         struct skl_ddb_allocation hw_ddb, *sw_ddb;
  12615.         struct intel_crtc *intel_crtc;
  12616.         int plane;
  12617.  
  12618.         if (INTEL_INFO(dev)->gen < 9)
  12619.                 return;
  12620.  
  12621.         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
  12622.         sw_ddb = &dev_priv->wm.skl_hw.ddb;
  12623.  
  12624.         for_each_intel_crtc(dev, intel_crtc) {
  12625.                 struct skl_ddb_entry *hw_entry, *sw_entry;
  12626.                 const enum pipe pipe = intel_crtc->pipe;
  12627.  
  12628.                 if (!intel_crtc->active)
  12629.                         continue;
  12630.  
  12631.                 /* planes */
  12632.                 for_each_plane(dev_priv, pipe, plane) {
  12633.                         hw_entry = &hw_ddb.plane[pipe][plane];
  12634.                         sw_entry = &sw_ddb->plane[pipe][plane];
  12635.  
  12636.                         if (skl_ddb_entry_equal(hw_entry, sw_entry))
  12637.                                 continue;
  12638.  
  12639.                         DRM_ERROR("mismatch in DDB state pipe %c plane %d "
  12640.                                   "(expected (%u,%u), found (%u,%u))\n",
  12641.                                   pipe_name(pipe), plane + 1,
  12642.                                   sw_entry->start, sw_entry->end,
  12643.                                   hw_entry->start, hw_entry->end);
  12644.                 }
  12645.  
  12646.                 /* cursor */
  12647.                 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
  12648.                 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
  12649.  
  12650.                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
  12651.                         continue;
  12652.  
  12653.                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
  12654.                           "(expected (%u,%u), found (%u,%u))\n",
  12655.                           pipe_name(pipe),
  12656.                           sw_entry->start, sw_entry->end,
  12657.                           hw_entry->start, hw_entry->end);
  12658.         }
  12659. }
  12660.  
  12661. static void
  12662. check_connector_state(struct drm_device *dev,
  12663.                       struct drm_atomic_state *old_state)
  12664. {
  12665.         struct drm_connector_state *old_conn_state;
  12666.         struct drm_connector *connector;
  12667.         int i;
  12668.  
  12669.         for_each_connector_in_state(old_state, connector, old_conn_state, i) {
  12670.                 struct drm_encoder *encoder = connector->encoder;
  12671.                 struct drm_connector_state *state = connector->state;
  12672.  
  12673.                 /* This also checks the encoder/connector hw state with the
  12674.                  * ->get_hw_state callbacks. */
  12675.                 intel_connector_check_state(to_intel_connector(connector));
  12676.  
  12677.                 I915_STATE_WARN(state->best_encoder != encoder,
  12678.                      "connector's atomic encoder doesn't match legacy encoder\n");
  12679.         }
  12680. }
  12681.  
  12682. static void
  12683. check_encoder_state(struct drm_device *dev)
  12684. {
  12685.         struct intel_encoder *encoder;
  12686.         struct intel_connector *connector;
  12687.  
  12688.         for_each_intel_encoder(dev, encoder) {
  12689.                 bool enabled = false;
  12690.                 enum pipe pipe;
  12691.  
  12692.                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  12693.                               encoder->base.base.id,
  12694.                               encoder->base.name);
  12695.  
  12696.                 for_each_intel_connector(dev, connector) {
  12697.                         if (connector->base.state->best_encoder != &encoder->base)
  12698.                                 continue;
  12699.                         enabled = true;
  12700.  
  12701.                         I915_STATE_WARN(connector->base.state->crtc !=
  12702.                                         encoder->base.crtc,
  12703.                              "connector's crtc doesn't match encoder crtc\n");
  12704.                 }
  12705.  
  12706.                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
  12707.                      "encoder's enabled state mismatch "
  12708.                      "(expected %i, found %i)\n",
  12709.                      !!encoder->base.crtc, enabled);
  12710.  
  12711.                 if (!encoder->base.crtc) {
  12712.                         bool active;
  12713.  
  12714.                         active = encoder->get_hw_state(encoder, &pipe);
  12715.                         I915_STATE_WARN(active,
  12716.                              "encoder detached but still enabled on pipe %c.\n",
  12717.                              pipe_name(pipe));
  12718.                 }
  12719.         }
  12720. }
  12721.  
  12722. static void
  12723. check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
  12724. {
  12725.         struct drm_i915_private *dev_priv = dev->dev_private;
  12726.         struct intel_encoder *encoder;
  12727.         struct drm_crtc_state *old_crtc_state;
  12728.         struct drm_crtc *crtc;
  12729.         int i;
  12730.  
  12731.         for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  12732.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  12733.                 struct intel_crtc_state *pipe_config, *sw_config;
  12734.                 bool active;
  12735.  
  12736.                 if (!needs_modeset(crtc->state) &&
  12737.                     !to_intel_crtc_state(crtc->state)->update_pipe)
  12738.                         continue;
  12739.  
  12740.                 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
  12741.                 pipe_config = to_intel_crtc_state(old_crtc_state);
  12742.                 memset(pipe_config, 0, sizeof(*pipe_config));
  12743.                 pipe_config->base.crtc = crtc;
  12744.                 pipe_config->base.state = old_state;
  12745.  
  12746.                 DRM_DEBUG_KMS("[CRTC:%d]\n",
  12747.                               crtc->base.id);
  12748.  
  12749.                 active = dev_priv->display.get_pipe_config(intel_crtc,
  12750.                                                            pipe_config);
  12751.  
  12752.                 /* hw state is inconsistent with the pipe quirk */
  12753.                 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
  12754.                     (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
  12755.                         active = crtc->state->active;
  12756.  
  12757.                 I915_STATE_WARN(crtc->state->active != active,
  12758.                      "crtc active state doesn't match with hw state "
  12759.                      "(expected %i, found %i)\n", crtc->state->active, active);
  12760.  
  12761.                 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
  12762.                      "transitional active state does not match atomic hw state "
  12763.                      "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
  12764.  
  12765.                 for_each_encoder_on_crtc(dev, crtc, encoder) {
  12766.                         enum pipe pipe;
  12767.  
  12768.                         active = encoder->get_hw_state(encoder, &pipe);
  12769.                         I915_STATE_WARN(active != crtc->state->active,
  12770.                                 "[ENCODER:%i] active %i with crtc active %i\n",
  12771.                                 encoder->base.base.id, active, crtc->state->active);
  12772.  
  12773.                         I915_STATE_WARN(active && intel_crtc->pipe != pipe,
  12774.                                         "Encoder connected to wrong pipe %c\n",
  12775.                                         pipe_name(pipe));
  12776.  
  12777.                         if (active)
  12778.                                 encoder->get_config(encoder, pipe_config);
  12779.                 }
  12780.  
  12781.                 if (!crtc->state->active)
  12782.                         continue;
  12783.  
  12784.                 sw_config = to_intel_crtc_state(crtc->state);
  12785.                 if (!intel_pipe_config_compare(dev, sw_config,
  12786.                                                pipe_config, false)) {
  12787.                         I915_STATE_WARN(1, "pipe state doesn't match!\n");
  12788.                         intel_dump_pipe_config(intel_crtc, pipe_config,
  12789.                                                "[hw state]");
  12790.                         intel_dump_pipe_config(intel_crtc, sw_config,
  12791.                                                "[sw state]");
  12792.                 }
  12793.         }
  12794. }
  12795.  
  12796. static void
  12797. check_shared_dpll_state(struct drm_device *dev)
  12798. {
  12799.         struct drm_i915_private *dev_priv = dev->dev_private;
  12800.         struct intel_crtc *crtc;
  12801.         struct intel_dpll_hw_state dpll_hw_state;
  12802.         int i;
  12803.  
  12804.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  12805.                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  12806.                 int enabled_crtcs = 0, active_crtcs = 0;
  12807.                 bool active;
  12808.  
  12809.                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  12810.  
  12811.                 DRM_DEBUG_KMS("%s\n", pll->name);
  12812.  
  12813.                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
  12814.  
  12815.                 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
  12816.                      "more active pll users than references: %i vs %i\n",
  12817.                      pll->active, hweight32(pll->config.crtc_mask));
  12818.                 I915_STATE_WARN(pll->active && !pll->on,
  12819.                      "pll in active use but not on in sw tracking\n");
  12820.                 I915_STATE_WARN(pll->on && !pll->active,
  12821.                      "pll in on but not on in use in sw tracking\n");
  12822.                 I915_STATE_WARN(pll->on != active,
  12823.                      "pll on state mismatch (expected %i, found %i)\n",
  12824.                      pll->on, active);
  12825.  
  12826.                 for_each_intel_crtc(dev, crtc) {
  12827.                         if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
  12828.                                 enabled_crtcs++;
  12829.                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  12830.                                 active_crtcs++;
  12831.                 }
  12832.                 I915_STATE_WARN(pll->active != active_crtcs,
  12833.                      "pll active crtcs mismatch (expected %i, found %i)\n",
  12834.                      pll->active, active_crtcs);
  12835.                 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
  12836.                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
  12837.                      hweight32(pll->config.crtc_mask), enabled_crtcs);
  12838.  
  12839.                 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
  12840.                                        sizeof(dpll_hw_state)),
  12841.                      "pll hw state mismatch\n");
  12842.         }
  12843. }
  12844.  
  12845. static void
  12846. intel_modeset_check_state(struct drm_device *dev,
  12847.                           struct drm_atomic_state *old_state)
  12848. {
  12849.         check_wm_state(dev);
  12850.         check_connector_state(dev, old_state);
  12851.         check_encoder_state(dev);
  12852.         check_crtc_state(dev, old_state);
  12853.         check_shared_dpll_state(dev);
  12854. }
  12855.  
  12856. void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
  12857.                                      int dotclock)
  12858. {
  12859.         /*
  12860.          * FDI already provided one idea for the dotclock.
  12861.          * Yell if the encoder disagrees.
  12862.          */
  12863.         WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
  12864.              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
  12865.              pipe_config->base.adjusted_mode.crtc_clock, dotclock);
  12866. }
  12867.  
  12868. static void update_scanline_offset(struct intel_crtc *crtc)
  12869. {
  12870.         struct drm_device *dev = crtc->base.dev;
  12871.  
  12872.         /*
  12873.          * The scanline counter increments at the leading edge of hsync.
  12874.          *
  12875.          * On most platforms it starts counting from vtotal-1 on the
  12876.          * first active line. That means the scanline counter value is
  12877.          * always one less than what we would expect. Ie. just after
  12878.          * start of vblank, which also occurs at start of hsync (on the
  12879.          * last active line), the scanline counter will read vblank_start-1.
  12880.          *
  12881.          * On gen2 the scanline counter starts counting from 1 instead
  12882.          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
  12883.          * to keep the value positive), instead of adding one.
  12884.          *
  12885.          * On HSW+ the behaviour of the scanline counter depends on the output
  12886.          * type. For DP ports it behaves like most other platforms, but on HDMI
  12887.          * there's an extra 1 line difference. So we need to add two instead of
  12888.          * one to the value.
  12889.          */
  12890.         if (IS_GEN2(dev)) {
  12891.                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  12892.                 int vtotal;
  12893.  
  12894.                 vtotal = adjusted_mode->crtc_vtotal;
  12895.                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  12896.                         vtotal /= 2;
  12897.  
  12898.                 crtc->scanline_offset = vtotal - 1;
  12899.         } else if (HAS_DDI(dev) &&
  12900.                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
  12901.                 crtc->scanline_offset = 2;
  12902.         } else
  12903.                 crtc->scanline_offset = 1;
  12904. }
  12905.  
  12906. static void intel_modeset_clear_plls(struct drm_atomic_state *state)
  12907. {
  12908.         struct drm_device *dev = state->dev;
  12909.         struct drm_i915_private *dev_priv = to_i915(dev);
  12910.         struct intel_shared_dpll_config *shared_dpll = NULL;
  12911.         struct intel_crtc *intel_crtc;
  12912.         struct intel_crtc_state *intel_crtc_state;
  12913.         struct drm_crtc *crtc;
  12914.         struct drm_crtc_state *crtc_state;
  12915.         int i;
  12916.  
  12917.         if (!dev_priv->display.crtc_compute_clock)
  12918.                 return;
  12919.  
  12920.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  12921.                 int dpll;
  12922.  
  12923.                 intel_crtc = to_intel_crtc(crtc);
  12924.                 intel_crtc_state = to_intel_crtc_state(crtc_state);
  12925.                 dpll = intel_crtc_state->shared_dpll;
  12926.  
  12927.                 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
  12928.                         continue;
  12929.  
  12930.                 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
  12931.  
  12932.                 if (!shared_dpll)
  12933.                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
  12934.  
  12935.                 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
  12936.         }
  12937. }
  12938.  
  12939. /*
  12940.  * This implements the workaround described in the "notes" section of the mode
  12941.  * set sequence documentation. When going from no pipes or single pipe to
  12942.  * multiple pipes, and planes are enabled after the pipe, we need to wait at
  12943.  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
  12944.  */
  12945. static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
  12946. {
  12947.         struct drm_crtc_state *crtc_state;
  12948.         struct intel_crtc *intel_crtc;
  12949.         struct drm_crtc *crtc;
  12950.         struct intel_crtc_state *first_crtc_state = NULL;
  12951.         struct intel_crtc_state *other_crtc_state = NULL;
  12952.         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
  12953.         int i;
  12954.  
  12955.         /* look at all crtc's that are going to be enabled in during modeset */
  12956.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  12957.                 intel_crtc = to_intel_crtc(crtc);
  12958.  
  12959.                 if (!crtc_state->active || !needs_modeset(crtc_state))
  12960.                         continue;
  12961.  
  12962.                 if (first_crtc_state) {
  12963.                         other_crtc_state = to_intel_crtc_state(crtc_state);
  12964.                         break;
  12965.                 } else {
  12966.                         first_crtc_state = to_intel_crtc_state(crtc_state);
  12967.                         first_pipe = intel_crtc->pipe;
  12968.                 }
  12969.         }
  12970.  
  12971.         /* No workaround needed? */
  12972.         if (!first_crtc_state)
  12973.                 return 0;
  12974.  
  12975.         /* w/a possibly needed, check how many crtc's are already enabled. */
  12976.         for_each_intel_crtc(state->dev, intel_crtc) {
  12977.                 struct intel_crtc_state *pipe_config;
  12978.  
  12979.                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
  12980.                 if (IS_ERR(pipe_config))
  12981.                         return PTR_ERR(pipe_config);
  12982.  
  12983.                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
  12984.  
  12985.                 if (!pipe_config->base.active ||
  12986.                     needs_modeset(&pipe_config->base))
  12987.                         continue;
  12988.  
  12989.                 /* 2 or more enabled crtcs means no need for w/a */
  12990.                 if (enabled_pipe != INVALID_PIPE)
  12991.                         return 0;
  12992.  
  12993.                 enabled_pipe = intel_crtc->pipe;
  12994.         }
  12995.  
  12996.         if (enabled_pipe != INVALID_PIPE)
  12997.                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
  12998.         else if (other_crtc_state)
  12999.                 other_crtc_state->hsw_workaround_pipe = first_pipe;
  13000.  
  13001.         return 0;
  13002. }
  13003.  
  13004. static int intel_modeset_all_pipes(struct drm_atomic_state *state)
  13005. {
  13006.         struct drm_crtc *crtc;
  13007.         struct drm_crtc_state *crtc_state;
  13008.         int ret = 0;
  13009.  
  13010.         /* add all active pipes to the state */
  13011.         for_each_crtc(state->dev, crtc) {
  13012.                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
  13013.                 if (IS_ERR(crtc_state))
  13014.                         return PTR_ERR(crtc_state);
  13015.  
  13016.                 if (!crtc_state->active || needs_modeset(crtc_state))
  13017.                         continue;
  13018.  
  13019.                 crtc_state->mode_changed = true;
  13020.  
  13021.                 ret = drm_atomic_add_affected_connectors(state, crtc);
  13022.                 if (ret)
  13023.                         break;
  13024.  
  13025.                 ret = drm_atomic_add_affected_planes(state, crtc);
  13026.                 if (ret)
  13027.                         break;
  13028.         }
  13029.  
  13030.         return ret;
  13031. }
  13032.  
  13033. static int intel_modeset_checks(struct drm_atomic_state *state)
  13034. {
  13035.         struct drm_device *dev = state->dev;
  13036.         struct drm_i915_private *dev_priv = dev->dev_private;
  13037.         int ret;
  13038.  
  13039.         if (!check_digital_port_conflicts(state)) {
  13040.                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
  13041.                 return -EINVAL;
  13042.         }
  13043.  
  13044.         /*
  13045.          * See if the config requires any additional preparation, e.g.
  13046.          * to adjust global state with pipes off.  We need to do this
  13047.          * here so we can get the modeset_pipe updated config for the new
  13048.          * mode set on this crtc.  For other crtcs we need to use the
  13049.          * adjusted_mode bits in the crtc directly.
  13050.          */
  13051.         if (dev_priv->display.modeset_calc_cdclk) {
  13052.                 unsigned int cdclk;
  13053.  
  13054.                 ret = dev_priv->display.modeset_calc_cdclk(state);
  13055.  
  13056.                 cdclk = to_intel_atomic_state(state)->cdclk;
  13057.                 if (!ret && cdclk != dev_priv->cdclk_freq)
  13058.                         ret = intel_modeset_all_pipes(state);
  13059.  
  13060.                 if (ret < 0)
  13061.                         return ret;
  13062.         } else
  13063.                 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
  13064.  
  13065.         intel_modeset_clear_plls(state);
  13066.  
  13067.         if (IS_HASWELL(dev))
  13068.                 return haswell_mode_set_planes_workaround(state);
  13069.  
  13070.         return 0;
  13071. }
  13072.  
  13073. /**
  13074.  * intel_atomic_check - validate state object
  13075.  * @dev: drm device
  13076.  * @state: state to validate
  13077.  */
  13078. static int intel_atomic_check(struct drm_device *dev,
  13079.                               struct drm_atomic_state *state)
  13080. {
  13081.         struct drm_crtc *crtc;
  13082.         struct drm_crtc_state *crtc_state;
  13083.         int ret, i;
  13084.         bool any_ms = false;
  13085.  
  13086.         ret = drm_atomic_helper_check_modeset(dev, state);
  13087.         if (ret)
  13088.                 return ret;
  13089.  
  13090.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  13091.                 struct intel_crtc_state *pipe_config =
  13092.                         to_intel_crtc_state(crtc_state);
  13093.  
  13094.                 memset(&to_intel_crtc(crtc)->atomic, 0,
  13095.                        sizeof(struct intel_crtc_atomic_commit));
  13096.  
  13097.                 /* Catch I915_MODE_FLAG_INHERITED */
  13098.                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
  13099.                         crtc_state->mode_changed = true;
  13100.  
  13101.                 if (!crtc_state->enable) {
  13102.                         if (needs_modeset(crtc_state))
  13103.                                 any_ms = true;
  13104.                         continue;
  13105.                 }
  13106.  
  13107.                 if (!needs_modeset(crtc_state))
  13108.                         continue;
  13109.  
  13110.                 /* FIXME: For only active_changed we shouldn't need to do any
  13111.                  * state recomputation at all. */
  13112.  
  13113.                 ret = drm_atomic_add_affected_connectors(state, crtc);
  13114.                 if (ret)
  13115.                         return ret;
  13116.  
  13117.                 ret = intel_modeset_pipe_config(crtc, pipe_config);
  13118.                 if (ret)
  13119.                         return ret;
  13120.  
  13121.                 if (i915.fastboot &&
  13122.                     intel_pipe_config_compare(state->dev,
  13123.                                         to_intel_crtc_state(crtc->state),
  13124.                                         pipe_config, true)) {
  13125.                         crtc_state->mode_changed = false;
  13126.                         to_intel_crtc_state(crtc_state)->update_pipe = true;
  13127.                 }
  13128.  
  13129.                 if (needs_modeset(crtc_state)) {
  13130.                         any_ms = true;
  13131.  
  13132.                         ret = drm_atomic_add_affected_planes(state, crtc);
  13133.                         if (ret)
  13134.                                 return ret;
  13135.                 }
  13136.  
  13137.                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  13138.                                        needs_modeset(crtc_state) ?
  13139.                                        "[modeset]" : "[fastset]");
  13140.         }
  13141.  
  13142.         if (any_ms) {
  13143.                 ret = intel_modeset_checks(state);
  13144.  
  13145.                 if (ret)
  13146.                         return ret;
  13147.         } else
  13148.                 to_intel_atomic_state(state)->cdclk =
  13149.                         to_i915(state->dev)->cdclk_freq;
  13150.  
  13151.         return drm_atomic_helper_check_planes(state->dev, state);
  13152. }
  13153.  
  13154. /**
  13155.  * intel_atomic_commit - commit validated state object
  13156.  * @dev: DRM device
  13157.  * @state: the top-level driver state object
  13158.  * @async: asynchronous commit
  13159.  *
  13160.  * This function commits a top-level state object that has been validated
  13161.  * with drm_atomic_helper_check().
  13162.  *
  13163.  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
  13164.  * we can only handle plane-related operations and do not yet support
  13165.  * asynchronous commit.
  13166.  *
  13167.  * RETURNS
  13168.  * Zero for success or -errno.
  13169.  */
  13170. static int intel_atomic_commit(struct drm_device *dev,
  13171.                                struct drm_atomic_state *state,
  13172.                                bool async)
  13173. {
  13174.         struct drm_i915_private *dev_priv = dev->dev_private;
  13175.         struct drm_crtc *crtc;
  13176.         struct drm_crtc_state *crtc_state;
  13177.         int ret = 0;
  13178.         int i;
  13179.         bool any_ms = false;
  13180.  
  13181.         if (async) {
  13182.                 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
  13183.                 return -EINVAL;
  13184.         }
  13185.  
  13186.         ret = drm_atomic_helper_prepare_planes(dev, state);
  13187.         if (ret)
  13188.                 return ret;
  13189.  
  13190.         drm_atomic_helper_swap_state(dev, state);
  13191.  
  13192.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  13193.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  13194.  
  13195.                 if (!needs_modeset(crtc->state))
  13196.                         continue;
  13197.  
  13198.                 any_ms = true;
  13199.                 intel_pre_plane_update(intel_crtc);
  13200.  
  13201.                 if (crtc_state->active) {
  13202.                         intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
  13203.                         dev_priv->display.crtc_disable(crtc);
  13204.                         intel_crtc->active = false;
  13205.                         intel_disable_shared_dpll(intel_crtc);
  13206.                 }
  13207.         }
  13208.  
  13209.         /* Only after disabling all output pipelines that will be changed can we
  13210.          * update the the output configuration. */
  13211.         intel_modeset_update_crtc_state(state);
  13212.  
  13213.         if (any_ms) {
  13214.                 intel_shared_dpll_commit(state);
  13215.  
  13216.                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
  13217.                 modeset_update_crtc_power_domains(state);
  13218.         }
  13219.  
  13220.         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  13221.         for_each_crtc_in_state(state, crtc, crtc_state, i) {
  13222.                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  13223.                 bool modeset = needs_modeset(crtc->state);
  13224.                 bool update_pipe = !modeset &&
  13225.                         to_intel_crtc_state(crtc->state)->update_pipe;
  13226.                 unsigned long put_domains = 0;
  13227.  
  13228.                 if (modeset && crtc->state->active) {
  13229.                         update_scanline_offset(to_intel_crtc(crtc));
  13230.                         dev_priv->display.crtc_enable(crtc);
  13231.                 }
  13232.  
  13233.                 if (update_pipe) {
  13234.                         put_domains = modeset_get_crtc_power_domains(crtc);
  13235.  
  13236.                         /* make sure intel_modeset_check_state runs */
  13237.                         any_ms = true;
  13238.                 }
  13239.  
  13240.                 if (!modeset)
  13241.                         intel_pre_plane_update(intel_crtc);
  13242.  
  13243.                 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
  13244.  
  13245.                 if (put_domains)
  13246.                         modeset_put_power_domains(dev_priv, put_domains);
  13247.  
  13248.                 intel_post_plane_update(intel_crtc);
  13249.         }
  13250.  
  13251.         /* FIXME: add subpixel order */
  13252.  
  13253.         drm_atomic_helper_wait_for_vblanks(dev, state);
  13254.         drm_atomic_helper_cleanup_planes(dev, state);
  13255.  
  13256.         if (any_ms)
  13257.                 intel_modeset_check_state(dev, state);
  13258.  
  13259.         drm_atomic_state_free(state);
  13260.  
  13261.         return 0;
  13262. }
  13263.  
  13264. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  13265. {
  13266.         struct drm_device *dev = crtc->dev;
  13267.         struct drm_atomic_state *state;
  13268.         struct drm_crtc_state *crtc_state;
  13269.         int ret;
  13270.  
  13271.         state = drm_atomic_state_alloc(dev);
  13272.         if (!state) {
  13273.                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
  13274.                               crtc->base.id);
  13275.                 return;
  13276.         }
  13277.  
  13278.         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
  13279.  
  13280. retry:
  13281.         crtc_state = drm_atomic_get_crtc_state(state, crtc);
  13282.         ret = PTR_ERR_OR_ZERO(crtc_state);
  13283.         if (!ret) {
  13284.                 if (!crtc_state->active)
  13285.                         goto out;
  13286.  
  13287.                 crtc_state->mode_changed = true;
  13288.                 ret = drm_atomic_commit(state);
  13289.         }
  13290.  
  13291.         if (ret == -EDEADLK) {
  13292.                 drm_atomic_state_clear(state);
  13293.                 drm_modeset_backoff(state->acquire_ctx);
  13294.                 goto retry;
  13295.         }
  13296.  
  13297.         if (ret)
  13298. out:
  13299.                 drm_atomic_state_free(state);
  13300. }
  13301.  
  13302. #undef for_each_intel_crtc_masked
  13303.  
  13304. static const struct drm_crtc_funcs intel_crtc_funcs = {
  13305.         .gamma_set = intel_crtc_gamma_set,
  13306.         .set_config = drm_atomic_helper_set_config,
  13307.         .destroy = intel_crtc_destroy,
  13308. //      .page_flip = intel_crtc_page_flip,
  13309.         .atomic_duplicate_state = intel_crtc_duplicate_state,
  13310.         .atomic_destroy_state = intel_crtc_destroy_state,
  13311. };
  13312.  
  13313. static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
  13314.                                       struct intel_shared_dpll *pll,
  13315.                                       struct intel_dpll_hw_state *hw_state)
  13316. {
  13317.         uint32_t val;
  13318.  
  13319.         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
  13320.                 return false;
  13321.  
  13322.         val = I915_READ(PCH_DPLL(pll->id));
  13323.         hw_state->dpll = val;
  13324.         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
  13325.         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
  13326.  
  13327.         return val & DPLL_VCO_ENABLE;
  13328. }
  13329.  
  13330. static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
  13331.                                   struct intel_shared_dpll *pll)
  13332. {
  13333.         I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
  13334.         I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
  13335. }
  13336.  
  13337. static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
  13338.                                 struct intel_shared_dpll *pll)
  13339. {
  13340.         /* PCH refclock must be enabled first */
  13341.         ibx_assert_pch_refclk_enabled(dev_priv);
  13342.  
  13343.         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
  13344.  
  13345.         /* Wait for the clocks to stabilize. */
  13346.         POSTING_READ(PCH_DPLL(pll->id));
  13347.         udelay(150);
  13348.  
  13349.         /* The pixel multiplier can only be updated once the
  13350.          * DPLL is enabled and the clocks are stable.
  13351.          *
  13352.          * So write it again.
  13353.          */
  13354.         I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
  13355.         POSTING_READ(PCH_DPLL(pll->id));
  13356.         udelay(200);
  13357. }
  13358.  
  13359. static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
  13360.                                  struct intel_shared_dpll *pll)
  13361. {
  13362.         struct drm_device *dev = dev_priv->dev;
  13363.         struct intel_crtc *crtc;
  13364.  
  13365.         /* Make sure no transcoder isn't still depending on us. */
  13366.         for_each_intel_crtc(dev, crtc) {
  13367.                 if (intel_crtc_to_shared_dpll(crtc) == pll)
  13368.                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
  13369.         }
  13370.  
  13371.         I915_WRITE(PCH_DPLL(pll->id), 0);
  13372.         POSTING_READ(PCH_DPLL(pll->id));
  13373.         udelay(200);
  13374. }
  13375.  
  13376. static char *ibx_pch_dpll_names[] = {
  13377.         "PCH DPLL A",
  13378.         "PCH DPLL B",
  13379. };
  13380.  
  13381. static void ibx_pch_dpll_init(struct drm_device *dev)
  13382. {
  13383.         struct drm_i915_private *dev_priv = dev->dev_private;
  13384.         int i;
  13385.  
  13386.         dev_priv->num_shared_dpll = 2;
  13387.  
  13388.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  13389.                 dev_priv->shared_dplls[i].id = i;
  13390.                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
  13391.                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
  13392.                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
  13393.                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
  13394.                 dev_priv->shared_dplls[i].get_hw_state =
  13395.                         ibx_pch_dpll_get_hw_state;
  13396.         }
  13397. }
  13398.  
  13399. static void intel_shared_dpll_init(struct drm_device *dev)
  13400. {
  13401.         struct drm_i915_private *dev_priv = dev->dev_private;
  13402.  
  13403.         if (HAS_DDI(dev))
  13404.                 intel_ddi_pll_init(dev);
  13405.         else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  13406.                 ibx_pch_dpll_init(dev);
  13407.         else
  13408.                 dev_priv->num_shared_dpll = 0;
  13409.  
  13410.         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
  13411. }
  13412.  
  13413. /**
  13414.  * intel_prepare_plane_fb - Prepare fb for usage on plane
  13415.  * @plane: drm plane to prepare for
  13416.  * @fb: framebuffer to prepare for presentation
  13417.  *
  13418.  * Prepares a framebuffer for usage on a display plane.  Generally this
  13419.  * involves pinning the underlying object and updating the frontbuffer tracking
  13420.  * bits.  Some older platforms need special physical address handling for
  13421.  * cursor planes.
  13422.  *
  13423.  * Returns 0 on success, negative error code on failure.
  13424.  */
  13425. int
  13426. intel_prepare_plane_fb(struct drm_plane *plane,
  13427.                        const struct drm_plane_state *new_state)
  13428. {
  13429.         struct drm_device *dev = plane->dev;
  13430.         struct drm_framebuffer *fb = new_state->fb;
  13431.         struct intel_plane *intel_plane = to_intel_plane(plane);
  13432.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  13433.         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
  13434.         int ret = 0;
  13435.  
  13436.         if (!obj)
  13437.                 return 0;
  13438.  
  13439.         mutex_lock(&dev->struct_mutex);
  13440.  
  13441.         if (plane->type == DRM_PLANE_TYPE_CURSOR &&
  13442.             INTEL_INFO(dev)->cursor_needs_physical) {
  13443.                 int align = IS_I830(dev) ? 16 * 1024 : 256;
  13444.         ret = 1;
  13445.                 if (ret)
  13446.                         DRM_DEBUG_KMS("failed to attach phys object\n");
  13447.         } else {
  13448.                 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
  13449.         }
  13450.  
  13451.         if (ret == 0)
  13452.                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
  13453.  
  13454.         mutex_unlock(&dev->struct_mutex);
  13455.  
  13456.         return ret;
  13457. }
  13458.  
  13459. /**
  13460.  * intel_cleanup_plane_fb - Cleans up an fb after plane use
  13461.  * @plane: drm plane to clean up for
  13462.  * @fb: old framebuffer that was on plane
  13463.  *
  13464.  * Cleans up a framebuffer that has just been removed from a plane.
  13465.  */
  13466. void
  13467. intel_cleanup_plane_fb(struct drm_plane *plane,
  13468.                        const struct drm_plane_state *old_state)
  13469. {
  13470.         struct drm_device *dev = plane->dev;
  13471.         struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
  13472.  
  13473.         if (!obj)
  13474.                 return;
  13475.  
  13476.         if (plane->type != DRM_PLANE_TYPE_CURSOR ||
  13477.             !INTEL_INFO(dev)->cursor_needs_physical) {
  13478.                 mutex_lock(&dev->struct_mutex);
  13479.                 intel_unpin_fb_obj(old_state->fb, old_state);
  13480.                 mutex_unlock(&dev->struct_mutex);
  13481.         }
  13482. }
  13483.  
  13484. int
  13485. skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
  13486. {
  13487.         int max_scale;
  13488.         struct drm_device *dev;
  13489.         struct drm_i915_private *dev_priv;
  13490.         int crtc_clock, cdclk;
  13491.  
  13492.         if (!intel_crtc || !crtc_state)
  13493.                 return DRM_PLANE_HELPER_NO_SCALING;
  13494.  
  13495.         dev = intel_crtc->base.dev;
  13496.         dev_priv = dev->dev_private;
  13497.         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
  13498.         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
  13499.  
  13500.         if (!crtc_clock || !cdclk)
  13501.                 return DRM_PLANE_HELPER_NO_SCALING;
  13502.  
  13503.         /*
  13504.          * skl max scale is lower of:
  13505.          *    close to 3 but not 3, -1 is for that purpose
  13506.          *            or
  13507.          *    cdclk/crtc_clock
  13508.          */
  13509.         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
  13510.  
  13511.         return max_scale;
  13512. }
  13513.  
  13514. static int
  13515. intel_check_primary_plane(struct drm_plane *plane,
  13516.                           struct intel_crtc_state *crtc_state,
  13517.                           struct intel_plane_state *state)
  13518. {
  13519.         struct drm_crtc *crtc = state->base.crtc;
  13520.         struct drm_framebuffer *fb = state->base.fb;
  13521.         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
  13522.         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
  13523.         bool can_position = false;
  13524.  
  13525.         /* use scaler when colorkey is not required */
  13526.         if (INTEL_INFO(plane->dev)->gen >= 9 &&
  13527.             state->ckey.flags == I915_SET_COLORKEY_NONE) {
  13528.                 min_scale = 1;
  13529.                 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
  13530.                 can_position = true;
  13531.         }
  13532.  
  13533.         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
  13534.                                              &state->dst, &state->clip,
  13535.                                              min_scale, max_scale,
  13536.                                              can_position, true,
  13537.                                              &state->visible);
  13538. }
  13539.  
  13540. static void
  13541. intel_commit_primary_plane(struct drm_plane *plane,
  13542.                            struct intel_plane_state *state)
  13543. {
  13544.         struct drm_crtc *crtc = state->base.crtc;
  13545.         struct drm_framebuffer *fb = state->base.fb;
  13546.         struct drm_device *dev = plane->dev;
  13547.         struct drm_i915_private *dev_priv = dev->dev_private;
  13548.         struct intel_crtc *intel_crtc;
  13549.         struct drm_rect *src = &state->src;
  13550.  
  13551.         crtc = crtc ? crtc : plane->crtc;
  13552.         intel_crtc = to_intel_crtc(crtc);
  13553.  
  13554.         plane->fb = fb;
  13555.         crtc->x = src->x1 >> 16;
  13556.         crtc->y = src->y1 >> 16;
  13557.  
  13558.         if (!crtc->state->active)
  13559.                 return;
  13560.  
  13561.         dev_priv->display.update_primary_plane(crtc, fb,
  13562.                                                state->src.x1 >> 16,
  13563.                                                state->src.y1 >> 16);
  13564. }
  13565.  
  13566. static void
  13567. intel_disable_primary_plane(struct drm_plane *plane,
  13568.                             struct drm_crtc *crtc)
  13569. {
  13570.         struct drm_device *dev = plane->dev;
  13571.         struct drm_i915_private *dev_priv = dev->dev_private;
  13572.  
  13573.         dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
  13574. }
  13575.  
  13576. static void intel_begin_crtc_commit(struct drm_crtc *crtc,
  13577.                                     struct drm_crtc_state *old_crtc_state)
  13578. {
  13579.         struct drm_device *dev = crtc->dev;
  13580.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  13581.         struct intel_crtc_state *old_intel_state =
  13582.                 to_intel_crtc_state(old_crtc_state);
  13583.         bool modeset = needs_modeset(crtc->state);
  13584.  
  13585.         if (intel_crtc->atomic.update_wm_pre)
  13586.                 intel_update_watermarks(crtc);
  13587.  
  13588.         /* Perform vblank evasion around commit operation */
  13589.         if (crtc->state->active)
  13590.                 intel_pipe_update_start(intel_crtc);
  13591.  
  13592.         if (modeset)
  13593.                 return;
  13594.  
  13595.         if (to_intel_crtc_state(crtc->state)->update_pipe)
  13596.                 intel_update_pipe_config(intel_crtc, old_intel_state);
  13597.         else if (INTEL_INFO(dev)->gen >= 9)
  13598.                 skl_detach_scalers(intel_crtc);
  13599. }
  13600.  
  13601. static void intel_finish_crtc_commit(struct drm_crtc *crtc,
  13602.                                      struct drm_crtc_state *old_crtc_state)
  13603. {
  13604.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  13605.  
  13606.         if (crtc->state->active)
  13607.                 intel_pipe_update_end(intel_crtc);
  13608. }
  13609.  
  13610. /**
  13611.  * intel_plane_destroy - destroy a plane
  13612.  * @plane: plane to destroy
  13613.  *
  13614.  * Common destruction function for all types of planes (primary, cursor,
  13615.  * sprite).
  13616.  */
  13617. void intel_plane_destroy(struct drm_plane *plane)
  13618. {
  13619.         struct intel_plane *intel_plane = to_intel_plane(plane);
  13620.         drm_plane_cleanup(plane);
  13621.         kfree(intel_plane);
  13622. }
  13623.  
  13624. const struct drm_plane_funcs intel_plane_funcs = {
  13625.         .update_plane = drm_atomic_helper_update_plane,
  13626.         .disable_plane = drm_atomic_helper_disable_plane,
  13627.         .destroy = intel_plane_destroy,
  13628.         .set_property = drm_atomic_helper_plane_set_property,
  13629.         .atomic_get_property = intel_plane_atomic_get_property,
  13630.         .atomic_set_property = intel_plane_atomic_set_property,
  13631.         .atomic_duplicate_state = intel_plane_duplicate_state,
  13632.         .atomic_destroy_state = intel_plane_destroy_state,
  13633.  
  13634. };
  13635.  
  13636. static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
  13637.                                                     int pipe)
  13638. {
  13639.         struct intel_plane *primary;
  13640.         struct intel_plane_state *state;
  13641.         const uint32_t *intel_primary_formats;
  13642.         unsigned int num_formats;
  13643.  
  13644.         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
  13645.         if (primary == NULL)
  13646.                 return NULL;
  13647.  
  13648.         state = intel_create_plane_state(&primary->base);
  13649.         if (!state) {
  13650.                 kfree(primary);
  13651.                 return NULL;
  13652.         }
  13653.         primary->base.state = &state->base;
  13654.  
  13655.         primary->can_scale = false;
  13656.         primary->max_downscale = 1;
  13657.         if (INTEL_INFO(dev)->gen >= 9) {
  13658.                 primary->can_scale = true;
  13659.                 state->scaler_id = -1;
  13660.         }
  13661.         primary->pipe = pipe;
  13662.         primary->plane = pipe;
  13663.         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
  13664.         primary->check_plane = intel_check_primary_plane;
  13665.         primary->commit_plane = intel_commit_primary_plane;
  13666.         primary->disable_plane = intel_disable_primary_plane;
  13667.         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
  13668.                 primary->plane = !pipe;
  13669.  
  13670.         if (INTEL_INFO(dev)->gen >= 9) {
  13671.                 intel_primary_formats = skl_primary_formats;
  13672.                 num_formats = ARRAY_SIZE(skl_primary_formats);
  13673.         } else if (INTEL_INFO(dev)->gen >= 4) {
  13674.                 intel_primary_formats = i965_primary_formats;
  13675.                 num_formats = ARRAY_SIZE(i965_primary_formats);
  13676.         } else {
  13677.                 intel_primary_formats = i8xx_primary_formats;
  13678.                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
  13679.         }
  13680.  
  13681.         drm_universal_plane_init(dev, &primary->base, 0,
  13682.                                  &intel_plane_funcs,
  13683.                                  intel_primary_formats, num_formats,
  13684.                                  DRM_PLANE_TYPE_PRIMARY);
  13685.  
  13686.         if (INTEL_INFO(dev)->gen >= 4)
  13687.                 intel_create_rotation_property(dev, primary);
  13688.  
  13689.         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
  13690.  
  13691.         return &primary->base;
  13692. }
  13693.  
  13694. void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
  13695. {
  13696.         if (!dev->mode_config.rotation_property) {
  13697.                 unsigned long flags = BIT(DRM_ROTATE_0) |
  13698.                         BIT(DRM_ROTATE_180);
  13699.  
  13700.                 if (INTEL_INFO(dev)->gen >= 9)
  13701.                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
  13702.  
  13703.                 dev->mode_config.rotation_property =
  13704.                         drm_mode_create_rotation_property(dev, flags);
  13705.         }
  13706.         if (dev->mode_config.rotation_property)
  13707.                 drm_object_attach_property(&plane->base.base,
  13708.                                 dev->mode_config.rotation_property,
  13709.                                 plane->base.state->rotation);
  13710. }
  13711.  
  13712. static int
  13713. intel_check_cursor_plane(struct drm_plane *plane,
  13714.                          struct intel_crtc_state *crtc_state,
  13715.                          struct intel_plane_state *state)
  13716. {
  13717.         struct drm_crtc *crtc = crtc_state->base.crtc;
  13718.         struct drm_framebuffer *fb = state->base.fb;
  13719.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  13720.         enum pipe pipe = to_intel_plane(plane)->pipe;
  13721.         unsigned stride;
  13722.         int ret;
  13723.  
  13724.         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
  13725.                                             &state->dst, &state->clip,
  13726.                                             DRM_PLANE_HELPER_NO_SCALING,
  13727.                                             DRM_PLANE_HELPER_NO_SCALING,
  13728.                                             true, true, &state->visible);
  13729.         if (ret)
  13730.                 return ret;
  13731.  
  13732.         /* if we want to turn off the cursor ignore width and height */
  13733.         if (!obj)
  13734.                 return 0;
  13735.  
  13736.         /* Check for which cursor types we support */
  13737.         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
  13738.                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
  13739.                           state->base.crtc_w, state->base.crtc_h);
  13740.                 return -EINVAL;
  13741.         }
  13742.  
  13743.         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
  13744.         if (obj->base.size < stride * state->base.crtc_h) {
  13745.                 DRM_DEBUG_KMS("buffer is too small\n");
  13746.                 return -ENOMEM;
  13747.         }
  13748.  
  13749.         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
  13750.                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
  13751.                 return -EINVAL;
  13752.         }
  13753.  
  13754.         /*
  13755.          * There's something wrong with the cursor on CHV pipe C.
  13756.          * If it straddles the left edge of the screen then
  13757.          * moving it away from the edge or disabling it often
  13758.          * results in a pipe underrun, and often that can lead to
  13759.          * dead pipe (constant underrun reported, and it scans
  13760.          * out just a solid color). To recover from that, the
  13761.          * display power well must be turned off and on again.
  13762.          * Refuse the put the cursor into that compromised position.
  13763.          */
  13764.         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
  13765.             state->visible && state->base.crtc_x < 0) {
  13766.                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
  13767.                 return -EINVAL;
  13768.         }
  13769.  
  13770.         return 0;
  13771. }
  13772.  
  13773. static void
  13774. intel_disable_cursor_plane(struct drm_plane *plane,
  13775.                            struct drm_crtc *crtc)
  13776. {
  13777.         intel_crtc_update_cursor(crtc, false);
  13778. }
  13779.  
  13780. static void
  13781. intel_commit_cursor_plane(struct drm_plane *plane,
  13782.                           struct intel_plane_state *state)
  13783. {
  13784.         struct drm_crtc *crtc = state->base.crtc;
  13785.         struct drm_device *dev = plane->dev;
  13786.         struct intel_crtc *intel_crtc;
  13787.         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
  13788.         uint32_t addr;
  13789.  
  13790.         crtc = crtc ? crtc : plane->crtc;
  13791.         intel_crtc = to_intel_crtc(crtc);
  13792.  
  13793.         if (!obj)
  13794.                 addr = 0;
  13795.         else if (!INTEL_INFO(dev)->cursor_needs_physical)
  13796.                 addr = i915_gem_obj_ggtt_offset(obj);
  13797.         else
  13798.                 addr = obj->phys_handle->busaddr;
  13799.  
  13800.         intel_crtc->cursor_addr = addr;
  13801.  
  13802.         if (crtc->state->active)
  13803.                 intel_crtc_update_cursor(crtc, state->visible);
  13804. }
  13805.  
  13806. static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
  13807.                                                    int pipe)
  13808. {
  13809.         struct intel_plane *cursor;
  13810.         struct intel_plane_state *state;
  13811.  
  13812.         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
  13813.         if (cursor == NULL)
  13814.                 return NULL;
  13815.  
  13816.         state = intel_create_plane_state(&cursor->base);
  13817.         if (!state) {
  13818.                 kfree(cursor);
  13819.                 return NULL;
  13820.         }
  13821.         cursor->base.state = &state->base;
  13822.  
  13823.         cursor->can_scale = false;
  13824.         cursor->max_downscale = 1;
  13825.         cursor->pipe = pipe;
  13826.         cursor->plane = pipe;
  13827.         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
  13828.         cursor->check_plane = intel_check_cursor_plane;
  13829.         cursor->commit_plane = intel_commit_cursor_plane;
  13830.         cursor->disable_plane = intel_disable_cursor_plane;
  13831.  
  13832.         drm_universal_plane_init(dev, &cursor->base, 0,
  13833.                                  &intel_plane_funcs,
  13834.                                  intel_cursor_formats,
  13835.                                  ARRAY_SIZE(intel_cursor_formats),
  13836.                                  DRM_PLANE_TYPE_CURSOR);
  13837.  
  13838.         if (INTEL_INFO(dev)->gen >= 4) {
  13839.                 if (!dev->mode_config.rotation_property)
  13840.                         dev->mode_config.rotation_property =
  13841.                                 drm_mode_create_rotation_property(dev,
  13842.                                                         BIT(DRM_ROTATE_0) |
  13843.                                                         BIT(DRM_ROTATE_180));
  13844.                 if (dev->mode_config.rotation_property)
  13845.                         drm_object_attach_property(&cursor->base.base,
  13846.                                 dev->mode_config.rotation_property,
  13847.                                 state->base.rotation);
  13848.         }
  13849.  
  13850.         if (INTEL_INFO(dev)->gen >=9)
  13851.                 state->scaler_id = -1;
  13852.  
  13853.         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
  13854.  
  13855.         return &cursor->base;
  13856. }
  13857.  
  13858. static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
  13859.         struct intel_crtc_state *crtc_state)
  13860. {
  13861.         int i;
  13862.         struct intel_scaler *intel_scaler;
  13863.         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
  13864.  
  13865.         for (i = 0; i < intel_crtc->num_scalers; i++) {
  13866.                 intel_scaler = &scaler_state->scalers[i];
  13867.                 intel_scaler->in_use = 0;
  13868.                 intel_scaler->mode = PS_SCALER_MODE_DYN;
  13869.         }
  13870.  
  13871.         scaler_state->scaler_id = -1;
  13872. }
  13873.  
  13874. static void intel_crtc_init(struct drm_device *dev, int pipe)
  13875. {
  13876.         struct drm_i915_private *dev_priv = dev->dev_private;
  13877.         struct intel_crtc *intel_crtc;
  13878.         struct intel_crtc_state *crtc_state = NULL;
  13879.         struct drm_plane *primary = NULL;
  13880.         struct drm_plane *cursor = NULL;
  13881.         int i, ret;
  13882.  
  13883.         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
  13884.         if (intel_crtc == NULL)
  13885.                 return;
  13886.  
  13887.         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
  13888.         if (!crtc_state)
  13889.                 goto fail;
  13890.         intel_crtc->config = crtc_state;
  13891.         intel_crtc->base.state = &crtc_state->base;
  13892.         crtc_state->base.crtc = &intel_crtc->base;
  13893.  
  13894.         /* initialize shared scalers */
  13895.         if (INTEL_INFO(dev)->gen >= 9) {
  13896.                 if (pipe == PIPE_C)
  13897.                         intel_crtc->num_scalers = 1;
  13898.                 else
  13899.                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
  13900.  
  13901.                 skl_init_scalers(dev, intel_crtc, crtc_state);
  13902.         }
  13903.  
  13904.         primary = intel_primary_plane_create(dev, pipe);
  13905.         if (!primary)
  13906.                 goto fail;
  13907.  
  13908.         cursor = intel_cursor_plane_create(dev, pipe);
  13909.         if (!cursor)
  13910.                 goto fail;
  13911.  
  13912.         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
  13913.                                         cursor, &intel_crtc_funcs);
  13914.         if (ret)
  13915.                 goto fail;
  13916.  
  13917.         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  13918.         for (i = 0; i < 256; i++) {
  13919.                 intel_crtc->lut_r[i] = i;
  13920.                 intel_crtc->lut_g[i] = i;
  13921.                 intel_crtc->lut_b[i] = i;
  13922.         }
  13923.  
  13924.         /*
  13925.          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
  13926.          * is hooked to pipe B. Hence we want plane A feeding pipe B.
  13927.          */
  13928.         intel_crtc->pipe = pipe;
  13929.         intel_crtc->plane = pipe;
  13930.         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
  13931.                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  13932.                 intel_crtc->plane = !pipe;
  13933.         }
  13934.  
  13935.         intel_crtc->cursor_base = ~0;
  13936.         intel_crtc->cursor_cntl = ~0;
  13937.         intel_crtc->cursor_size = ~0;
  13938.  
  13939.         intel_crtc->wm.cxsr_allowed = true;
  13940.  
  13941.         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  13942.                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  13943.         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  13944.         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  13945.  
  13946.         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  13947.  
  13948.         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
  13949.         return;
  13950.  
  13951. fail:
  13952.         if (primary)
  13953.                 drm_plane_cleanup(primary);
  13954.         if (cursor)
  13955.                 drm_plane_cleanup(cursor);
  13956.         kfree(crtc_state);
  13957.         kfree(intel_crtc);
  13958. }
  13959.  
  13960. enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
  13961. {
  13962.         struct drm_encoder *encoder = connector->base.encoder;
  13963.         struct drm_device *dev = connector->base.dev;
  13964.  
  13965.         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
  13966.  
  13967.         if (!encoder || WARN_ON(!encoder->crtc))
  13968.                 return INVALID_PIPE;
  13969.  
  13970.         return to_intel_crtc(encoder->crtc)->pipe;
  13971. }
  13972.  
  13973. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  13974.                                 struct drm_file *file)
  13975. {
  13976.         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  13977.         struct drm_crtc *drmmode_crtc;
  13978.         struct intel_crtc *crtc;
  13979.  
  13980.         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
  13981.  
  13982.         if (!drmmode_crtc) {
  13983.                 DRM_ERROR("no such CRTC id\n");
  13984.                 return -ENOENT;
  13985.         }
  13986.  
  13987.         crtc = to_intel_crtc(drmmode_crtc);
  13988.         pipe_from_crtc_id->pipe = crtc->pipe;
  13989.  
  13990.         return 0;
  13991. }
  13992.  
  13993. static int intel_encoder_clones(struct intel_encoder *encoder)
  13994. {
  13995.         struct drm_device *dev = encoder->base.dev;
  13996.         struct intel_encoder *source_encoder;
  13997.         int index_mask = 0;
  13998.         int entry = 0;
  13999.  
  14000.         for_each_intel_encoder(dev, source_encoder) {
  14001.                 if (encoders_cloneable(encoder, source_encoder))
  14002.                         index_mask |= (1 << entry);
  14003.  
  14004.                 entry++;
  14005.         }
  14006.  
  14007.         return index_mask;
  14008. }
  14009.  
  14010. static bool has_edp_a(struct drm_device *dev)
  14011. {
  14012.         struct drm_i915_private *dev_priv = dev->dev_private;
  14013.  
  14014.         if (!IS_MOBILE(dev))
  14015.                 return false;
  14016.  
  14017.         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  14018.                 return false;
  14019.  
  14020.         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
  14021.                 return false;
  14022.  
  14023.         return true;
  14024. }
  14025.  
  14026. static bool intel_crt_present(struct drm_device *dev)
  14027. {
  14028.         struct drm_i915_private *dev_priv = dev->dev_private;
  14029.  
  14030.         if (INTEL_INFO(dev)->gen >= 9)
  14031.                 return false;
  14032.  
  14033.         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
  14034.                 return false;
  14035.  
  14036.         if (IS_CHERRYVIEW(dev))
  14037.                 return false;
  14038.  
  14039.         if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
  14040.                 return false;
  14041.  
  14042.         return true;
  14043. }
  14044.  
  14045. static void intel_setup_outputs(struct drm_device *dev)
  14046. {
  14047.         struct drm_i915_private *dev_priv = dev->dev_private;
  14048.         struct intel_encoder *encoder;
  14049.         bool dpd_is_edp = false;
  14050.  
  14051.         intel_lvds_init(dev);
  14052.  
  14053.         if (intel_crt_present(dev))
  14054.                 intel_crt_init(dev);
  14055.  
  14056.         if (IS_BROXTON(dev)) {
  14057.                 /*
  14058.                  * FIXME: Broxton doesn't support port detection via the
  14059.                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
  14060.                  * detect the ports.
  14061.                  */
  14062.                 intel_ddi_init(dev, PORT_A);
  14063.                 intel_ddi_init(dev, PORT_B);
  14064.                 intel_ddi_init(dev, PORT_C);
  14065.         } else if (HAS_DDI(dev)) {
  14066.                 int found;
  14067.  
  14068.                 /*
  14069.                  * Haswell uses DDI functions to detect digital outputs.
  14070.                  * On SKL pre-D0 the strap isn't connected, so we assume
  14071.                  * it's there.
  14072.                  */
  14073.                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
  14074.                 /* WaIgnoreDDIAStrap: skl */
  14075.                 if (found || IS_SKYLAKE(dev))
  14076.                         intel_ddi_init(dev, PORT_A);
  14077.  
  14078.                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  14079.                  * register */
  14080.                 found = I915_READ(SFUSE_STRAP);
  14081.  
  14082.                 if (found & SFUSE_STRAP_DDIB_DETECTED)
  14083.                         intel_ddi_init(dev, PORT_B);
  14084.                 if (found & SFUSE_STRAP_DDIC_DETECTED)
  14085.                         intel_ddi_init(dev, PORT_C);
  14086.                 if (found & SFUSE_STRAP_DDID_DETECTED)
  14087.                         intel_ddi_init(dev, PORT_D);
  14088.                 /*
  14089.                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
  14090.                  */
  14091.                 if (IS_SKYLAKE(dev) &&
  14092.                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
  14093.                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
  14094.                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
  14095.                         intel_ddi_init(dev, PORT_E);
  14096.  
  14097.         } else if (HAS_PCH_SPLIT(dev)) {
  14098.                 int found;
  14099.                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
  14100.  
  14101.                 if (has_edp_a(dev))
  14102.                         intel_dp_init(dev, DP_A, PORT_A);
  14103.  
  14104.                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  14105.                         /* PCH SDVOB multiplex with HDMIB */
  14106.                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
  14107.                         if (!found)
  14108.                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  14109.                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  14110.                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
  14111.                 }
  14112.  
  14113.                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  14114.                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  14115.  
  14116.                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  14117.                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  14118.  
  14119.                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
  14120.                         intel_dp_init(dev, PCH_DP_C, PORT_C);
  14121.  
  14122.                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
  14123.                         intel_dp_init(dev, PCH_DP_D, PORT_D);
  14124.         } else if (IS_VALLEYVIEW(dev)) {
  14125.                 /*
  14126.                  * The DP_DETECTED bit is the latched state of the DDC
  14127.                  * SDA pin at boot. However since eDP doesn't require DDC
  14128.                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
  14129.                  * eDP ports may have been muxed to an alternate function.
  14130.                  * Thus we can't rely on the DP_DETECTED bit alone to detect
  14131.                  * eDP ports. Consult the VBT as well as DP_DETECTED to
  14132.                  * detect eDP ports.
  14133.                  */
  14134.                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
  14135.                     !intel_dp_is_edp(dev, PORT_B))
  14136.                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
  14137.                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
  14138.                     intel_dp_is_edp(dev, PORT_B))
  14139.                         intel_dp_init(dev, VLV_DP_B, PORT_B);
  14140.  
  14141.                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
  14142.                     !intel_dp_is_edp(dev, PORT_C))
  14143.                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
  14144.                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
  14145.                     intel_dp_is_edp(dev, PORT_C))
  14146.                         intel_dp_init(dev, VLV_DP_C, PORT_C);
  14147.  
  14148.                 if (IS_CHERRYVIEW(dev)) {
  14149.                         /* eDP not supported on port D, so don't check VBT */
  14150.                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
  14151.                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
  14152.                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
  14153.                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
  14154.                 }
  14155.  
  14156.                 intel_dsi_init(dev);
  14157.         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
  14158.                 bool found = false;
  14159.  
  14160.                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  14161.                         DRM_DEBUG_KMS("probing SDVOB\n");
  14162.                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  14163.                         if (!found && IS_G4X(dev)) {
  14164.                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  14165.                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  14166.                         }
  14167.  
  14168.                         if (!found && IS_G4X(dev))
  14169.                                 intel_dp_init(dev, DP_B, PORT_B);
  14170.                 }
  14171.  
  14172.                 /* Before G4X SDVOC doesn't have its own detect register */
  14173.  
  14174.                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  14175.                         DRM_DEBUG_KMS("probing SDVOC\n");
  14176.                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  14177.                 }
  14178.  
  14179.                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  14180.  
  14181.                         if (IS_G4X(dev)) {
  14182.                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  14183.                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  14184.                         }
  14185.                         if (IS_G4X(dev))
  14186.                                 intel_dp_init(dev, DP_C, PORT_C);
  14187.                 }
  14188.  
  14189.                 if (IS_G4X(dev) &&
  14190.                     (I915_READ(DP_D) & DP_DETECTED))
  14191.                         intel_dp_init(dev, DP_D, PORT_D);
  14192.         } else if (IS_GEN2(dev))
  14193.                 intel_dvo_init(dev);
  14194.  
  14195.         intel_psr_init(dev);
  14196.  
  14197.         for_each_intel_encoder(dev, encoder) {
  14198.                 encoder->base.possible_crtcs = encoder->crtc_mask;
  14199.                 encoder->base.possible_clones =
  14200.                         intel_encoder_clones(encoder);
  14201.         }
  14202.  
  14203.         intel_init_pch_refclk(dev);
  14204.  
  14205.         drm_helper_move_panel_connectors_to_head(dev);
  14206. }
  14207.  
  14208. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  14209. {
  14210.         struct drm_device *dev = fb->dev;
  14211.         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  14212.  
  14213.         drm_framebuffer_cleanup(fb);
  14214.         mutex_lock(&dev->struct_mutex);
  14215.         WARN_ON(!intel_fb->obj->framebuffer_references--);
  14216.         drm_gem_object_unreference(&intel_fb->obj->base);
  14217.         mutex_unlock(&dev->struct_mutex);
  14218.         kfree(intel_fb);
  14219. }
  14220.  
  14221. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  14222.                                                 struct drm_file *file,
  14223.                                                 unsigned int *handle)
  14224. {
  14225.         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  14226.         struct drm_i915_gem_object *obj = intel_fb->obj;
  14227.  
  14228.         if (obj->userptr.mm) {
  14229.                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
  14230.                 return -EINVAL;
  14231.         }
  14232.  
  14233.         return drm_gem_handle_create(file, &obj->base, handle);
  14234. }
  14235.  
  14236. static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
  14237.                                         struct drm_file *file,
  14238.                                         unsigned flags, unsigned color,
  14239.                                         struct drm_clip_rect *clips,
  14240.                                         unsigned num_clips)
  14241. {
  14242.         struct drm_device *dev = fb->dev;
  14243.         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  14244.         struct drm_i915_gem_object *obj = intel_fb->obj;
  14245.  
  14246.         mutex_lock(&dev->struct_mutex);
  14247.         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
  14248.         mutex_unlock(&dev->struct_mutex);
  14249.  
  14250.         return 0;
  14251. }
  14252.  
  14253. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  14254.         .destroy = intel_user_framebuffer_destroy,
  14255.         .create_handle = intel_user_framebuffer_create_handle,
  14256.         .dirty = intel_user_framebuffer_dirty,
  14257. };
  14258.  
  14259. static
  14260. u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
  14261.                          uint32_t pixel_format)
  14262. {
  14263.         u32 gen = INTEL_INFO(dev)->gen;
  14264.  
  14265.         if (gen >= 9) {
  14266.                 /* "The stride in bytes must not exceed the of the size of 8K
  14267.                  *  pixels and 32K bytes."
  14268.                  */
  14269.                  return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
  14270.         } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
  14271.                 return 32*1024;
  14272.         } else if (gen >= 4) {
  14273.                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
  14274.                         return 16*1024;
  14275.                 else
  14276.                         return 32*1024;
  14277.         } else if (gen >= 3) {
  14278.                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
  14279.                         return 8*1024;
  14280.                 else
  14281.                         return 16*1024;
  14282.         } else {
  14283.                 /* XXX DSPC is limited to 4k tiled */
  14284.                 return 8*1024;
  14285.         }
  14286. }
  14287.  
  14288. static int intel_framebuffer_init(struct drm_device *dev,
  14289.                                   struct intel_framebuffer *intel_fb,
  14290.                                   struct drm_mode_fb_cmd2 *mode_cmd,
  14291.                                   struct drm_i915_gem_object *obj)
  14292. {
  14293.         unsigned int aligned_height;
  14294.         int ret;
  14295.         u32 pitch_limit, stride_alignment;
  14296.  
  14297.         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  14298.  
  14299.         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
  14300.                 /* Enforce that fb modifier and tiling mode match, but only for
  14301.                  * X-tiled. This is needed for FBC. */
  14302.                 if (!!(obj->tiling_mode == I915_TILING_X) !=
  14303.                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
  14304.                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
  14305.                         return -EINVAL;
  14306.                 }
  14307.         } else {
  14308.                 if (obj->tiling_mode == I915_TILING_X)
  14309.                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
  14310.                 else if (obj->tiling_mode == I915_TILING_Y) {
  14311.                         DRM_DEBUG("No Y tiling for legacy addfb\n");
  14312.                         return -EINVAL;
  14313.                 }
  14314.         }
  14315.  
  14316.         /* Passed in modifier sanity checking. */
  14317.         switch (mode_cmd->modifier[0]) {
  14318.         case I915_FORMAT_MOD_Y_TILED:
  14319.         case I915_FORMAT_MOD_Yf_TILED:
  14320.                 if (INTEL_INFO(dev)->gen < 9) {
  14321.                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
  14322.                                   mode_cmd->modifier[0]);
  14323.                         return -EINVAL;
  14324.                 }
  14325.         case DRM_FORMAT_MOD_NONE:
  14326.         case I915_FORMAT_MOD_X_TILED:
  14327.                 break;
  14328.         default:
  14329.                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
  14330.                           mode_cmd->modifier[0]);
  14331.                 return -EINVAL;
  14332.         }
  14333.  
  14334.         stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
  14335.                                                      mode_cmd->pixel_format);
  14336.         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
  14337.                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
  14338.                           mode_cmd->pitches[0], stride_alignment);
  14339.                 return -EINVAL;
  14340.         }
  14341.  
  14342.         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
  14343.                                            mode_cmd->pixel_format);
  14344.         if (mode_cmd->pitches[0] > pitch_limit) {
  14345.                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
  14346.                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
  14347.                           "tiled" : "linear",
  14348.                           mode_cmd->pitches[0], pitch_limit);
  14349.                 return -EINVAL;
  14350.         }
  14351.  
  14352.         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
  14353.             mode_cmd->pitches[0] != obj->stride) {
  14354.                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  14355.                           mode_cmd->pitches[0], obj->stride);
  14356.                 return -EINVAL;
  14357.         }
  14358.  
  14359.         /* Reject formats not supported by any plane early. */
  14360.         switch (mode_cmd->pixel_format) {
  14361.         case DRM_FORMAT_C8:
  14362.         case DRM_FORMAT_RGB565:
  14363.         case DRM_FORMAT_XRGB8888:
  14364.         case DRM_FORMAT_ARGB8888:
  14365.                 break;
  14366.         case DRM_FORMAT_XRGB1555:
  14367.                 if (INTEL_INFO(dev)->gen > 3) {
  14368.                         DRM_DEBUG("unsupported pixel format: %s\n",
  14369.                                   drm_get_format_name(mode_cmd->pixel_format));
  14370.                         return -EINVAL;
  14371.                 }
  14372.                 break;
  14373.         case DRM_FORMAT_ABGR8888:
  14374.                 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
  14375.                         DRM_DEBUG("unsupported pixel format: %s\n",
  14376.                                   drm_get_format_name(mode_cmd->pixel_format));
  14377.                         return -EINVAL;
  14378.                 }
  14379.                 break;
  14380.         case DRM_FORMAT_XBGR8888:
  14381.         case DRM_FORMAT_XRGB2101010:
  14382.         case DRM_FORMAT_XBGR2101010:
  14383.                 if (INTEL_INFO(dev)->gen < 4) {
  14384.                         DRM_DEBUG("unsupported pixel format: %s\n",
  14385.                                   drm_get_format_name(mode_cmd->pixel_format));
  14386.                         return -EINVAL;
  14387.                 }
  14388.                 break;
  14389.         case DRM_FORMAT_ABGR2101010:
  14390.                 if (!IS_VALLEYVIEW(dev)) {
  14391.                         DRM_DEBUG("unsupported pixel format: %s\n",
  14392.                                   drm_get_format_name(mode_cmd->pixel_format));
  14393.                         return -EINVAL;
  14394.                 }
  14395.                 break;
  14396.         case DRM_FORMAT_YUYV:
  14397.         case DRM_FORMAT_UYVY:
  14398.         case DRM_FORMAT_YVYU:
  14399.         case DRM_FORMAT_VYUY:
  14400.                 if (INTEL_INFO(dev)->gen < 5) {
  14401.                         DRM_DEBUG("unsupported pixel format: %s\n",
  14402.                                   drm_get_format_name(mode_cmd->pixel_format));
  14403.                         return -EINVAL;
  14404.                 }
  14405.                 break;
  14406.         default:
  14407.                 DRM_DEBUG("unsupported pixel format: %s\n",
  14408.                           drm_get_format_name(mode_cmd->pixel_format));
  14409.                 return -EINVAL;
  14410.         }
  14411.  
  14412.         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  14413.         if (mode_cmd->offsets[0] != 0)
  14414.                 return -EINVAL;
  14415.  
  14416.         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
  14417.                                                mode_cmd->pixel_format,
  14418.                                                mode_cmd->modifier[0]);
  14419.         /* FIXME drm helper for size checks (especially planar formats)? */
  14420.         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
  14421.                 return -EINVAL;
  14422.  
  14423.         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  14424.         intel_fb->obj = obj;
  14425.         intel_fb->obj->framebuffer_references++;
  14426.  
  14427.         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  14428.         if (ret) {
  14429.                 DRM_ERROR("framebuffer init failed %d\n", ret);
  14430.                 return ret;
  14431.         }
  14432.  
  14433.         return 0;
  14434. }
  14435.  
  14436. static struct drm_framebuffer *
  14437. intel_user_framebuffer_create(struct drm_device *dev,
  14438.                               struct drm_file *filp,
  14439.                               struct drm_mode_fb_cmd2 *user_mode_cmd)
  14440. {
  14441.         struct drm_i915_gem_object *obj;
  14442.         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
  14443.  
  14444.         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  14445.                                                 mode_cmd.handles[0]));
  14446.         if (&obj->base == NULL)
  14447.                 return ERR_PTR(-ENOENT);
  14448.  
  14449.         return intel_framebuffer_create(dev, &mode_cmd, obj);
  14450. }
  14451.  
  14452. #ifndef CONFIG_DRM_FBDEV_EMULATION
  14453. static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
  14454. {
  14455. }
  14456. #endif
  14457.  
  14458. static const struct drm_mode_config_funcs intel_mode_funcs = {
  14459.         .fb_create = intel_user_framebuffer_create,
  14460.         .output_poll_changed = intel_fbdev_output_poll_changed,
  14461.         .atomic_check = intel_atomic_check,
  14462.         .atomic_commit = intel_atomic_commit,
  14463.         .atomic_state_alloc = intel_atomic_state_alloc,
  14464.         .atomic_state_clear = intel_atomic_state_clear,
  14465. };
  14466.  
  14467. /* Set up chip specific display functions */
  14468. static void intel_init_display(struct drm_device *dev)
  14469. {
  14470.         struct drm_i915_private *dev_priv = dev->dev_private;
  14471.  
  14472.         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
  14473.                 dev_priv->display.find_dpll = g4x_find_best_dpll;
  14474.         else if (IS_CHERRYVIEW(dev))
  14475.                 dev_priv->display.find_dpll = chv_find_best_dpll;
  14476.         else if (IS_VALLEYVIEW(dev))
  14477.                 dev_priv->display.find_dpll = vlv_find_best_dpll;
  14478.         else if (IS_PINEVIEW(dev))
  14479.                 dev_priv->display.find_dpll = pnv_find_best_dpll;
  14480.         else
  14481.                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
  14482.  
  14483.         if (INTEL_INFO(dev)->gen >= 9) {
  14484.                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  14485.                 dev_priv->display.get_initial_plane_config =
  14486.                         skylake_get_initial_plane_config;
  14487.                 dev_priv->display.crtc_compute_clock =
  14488.                         haswell_crtc_compute_clock;
  14489.                 dev_priv->display.crtc_enable = haswell_crtc_enable;
  14490.                 dev_priv->display.crtc_disable = haswell_crtc_disable;
  14491.                 dev_priv->display.update_primary_plane =
  14492.                         skylake_update_primary_plane;
  14493.         } else if (HAS_DDI(dev)) {
  14494.                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  14495.                 dev_priv->display.get_initial_plane_config =
  14496.                         ironlake_get_initial_plane_config;
  14497.                 dev_priv->display.crtc_compute_clock =
  14498.                         haswell_crtc_compute_clock;
  14499.                 dev_priv->display.crtc_enable = haswell_crtc_enable;
  14500.                 dev_priv->display.crtc_disable = haswell_crtc_disable;
  14501.                 dev_priv->display.update_primary_plane =
  14502.                         ironlake_update_primary_plane;
  14503.         } else if (HAS_PCH_SPLIT(dev)) {
  14504.                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  14505.                 dev_priv->display.get_initial_plane_config =
  14506.                         ironlake_get_initial_plane_config;
  14507.                 dev_priv->display.crtc_compute_clock =
  14508.                         ironlake_crtc_compute_clock;
  14509.                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
  14510.                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
  14511.                 dev_priv->display.update_primary_plane =
  14512.                         ironlake_update_primary_plane;
  14513.         } else if (IS_VALLEYVIEW(dev)) {
  14514.                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  14515.                 dev_priv->display.get_initial_plane_config =
  14516.                         i9xx_get_initial_plane_config;
  14517.                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
  14518.                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
  14519.                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
  14520.                 dev_priv->display.update_primary_plane =
  14521.                         i9xx_update_primary_plane;
  14522.         } else {
  14523.                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  14524.                 dev_priv->display.get_initial_plane_config =
  14525.                         i9xx_get_initial_plane_config;
  14526.                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
  14527.                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
  14528.                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
  14529.                 dev_priv->display.update_primary_plane =
  14530.                         i9xx_update_primary_plane;
  14531.         }
  14532.  
  14533.         /* Returns the core display clock speed */
  14534.         if (IS_SKYLAKE(dev))
  14535.                 dev_priv->display.get_display_clock_speed =
  14536.                         skylake_get_display_clock_speed;
  14537.         else if (IS_BROXTON(dev))
  14538.                 dev_priv->display.get_display_clock_speed =
  14539.                         broxton_get_display_clock_speed;
  14540.         else if (IS_BROADWELL(dev))
  14541.                 dev_priv->display.get_display_clock_speed =
  14542.                         broadwell_get_display_clock_speed;
  14543.         else if (IS_HASWELL(dev))
  14544.                 dev_priv->display.get_display_clock_speed =
  14545.                         haswell_get_display_clock_speed;
  14546.         else if (IS_VALLEYVIEW(dev))
  14547.                 dev_priv->display.get_display_clock_speed =
  14548.                         valleyview_get_display_clock_speed;
  14549.         else if (IS_GEN5(dev))
  14550.                 dev_priv->display.get_display_clock_speed =
  14551.                         ilk_get_display_clock_speed;
  14552.         else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
  14553.                  IS_GEN6(dev) || IS_IVYBRIDGE(dev))
  14554.                 dev_priv->display.get_display_clock_speed =
  14555.                         i945_get_display_clock_speed;
  14556.         else if (IS_GM45(dev))
  14557.                 dev_priv->display.get_display_clock_speed =
  14558.                         gm45_get_display_clock_speed;
  14559.         else if (IS_CRESTLINE(dev))
  14560.                 dev_priv->display.get_display_clock_speed =
  14561.                         i965gm_get_display_clock_speed;
  14562.         else if (IS_PINEVIEW(dev))
  14563.                 dev_priv->display.get_display_clock_speed =
  14564.                         pnv_get_display_clock_speed;
  14565.         else if (IS_G33(dev) || IS_G4X(dev))
  14566.                 dev_priv->display.get_display_clock_speed =
  14567.                         g33_get_display_clock_speed;
  14568.         else if (IS_I915G(dev))
  14569.                 dev_priv->display.get_display_clock_speed =
  14570.                         i915_get_display_clock_speed;
  14571.         else if (IS_I945GM(dev) || IS_845G(dev))
  14572.                 dev_priv->display.get_display_clock_speed =
  14573.                         i9xx_misc_get_display_clock_speed;
  14574.         else if (IS_PINEVIEW(dev))
  14575.                 dev_priv->display.get_display_clock_speed =
  14576.                         pnv_get_display_clock_speed;
  14577.         else if (IS_I915GM(dev))
  14578.                 dev_priv->display.get_display_clock_speed =
  14579.                         i915gm_get_display_clock_speed;
  14580.         else if (IS_I865G(dev))
  14581.                 dev_priv->display.get_display_clock_speed =
  14582.                         i865_get_display_clock_speed;
  14583.         else if (IS_I85X(dev))
  14584.                 dev_priv->display.get_display_clock_speed =
  14585.                         i85x_get_display_clock_speed;
  14586.         else { /* 830 */
  14587.                 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
  14588.                 dev_priv->display.get_display_clock_speed =
  14589.                         i830_get_display_clock_speed;
  14590.         }
  14591.  
  14592.         if (IS_GEN5(dev)) {
  14593.                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  14594.         } else if (IS_GEN6(dev)) {
  14595.                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  14596.         } else if (IS_IVYBRIDGE(dev)) {
  14597.                 /* FIXME: detect B0+ stepping and use auto training */
  14598.                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  14599.         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
  14600.                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  14601.                 if (IS_BROADWELL(dev)) {
  14602.                         dev_priv->display.modeset_commit_cdclk =
  14603.                                 broadwell_modeset_commit_cdclk;
  14604.                         dev_priv->display.modeset_calc_cdclk =
  14605.                                 broadwell_modeset_calc_cdclk;
  14606.                 }
  14607.         } else if (IS_VALLEYVIEW(dev)) {
  14608.                 dev_priv->display.modeset_commit_cdclk =
  14609.                         valleyview_modeset_commit_cdclk;
  14610.                 dev_priv->display.modeset_calc_cdclk =
  14611.                         valleyview_modeset_calc_cdclk;
  14612.         } else if (IS_BROXTON(dev)) {
  14613.                 dev_priv->display.modeset_commit_cdclk =
  14614.                         broxton_modeset_commit_cdclk;
  14615.                 dev_priv->display.modeset_calc_cdclk =
  14616.                         broxton_modeset_calc_cdclk;
  14617.         }
  14618.  
  14619.  
  14620.  
  14621.  
  14622.  
  14623.  
  14624.         mutex_init(&dev_priv->pps_mutex);
  14625. }
  14626.  
  14627. /*
  14628.  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  14629.  * resume, or other times.  This quirk makes sure that's the case for
  14630.  * affected systems.
  14631.  */
  14632. static void quirk_pipea_force(struct drm_device *dev)
  14633. {
  14634.         struct drm_i915_private *dev_priv = dev->dev_private;
  14635.  
  14636.         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  14637.         DRM_INFO("applying pipe a force quirk\n");
  14638. }
  14639.  
  14640. static void quirk_pipeb_force(struct drm_device *dev)
  14641. {
  14642.         struct drm_i915_private *dev_priv = dev->dev_private;
  14643.  
  14644.         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
  14645.         DRM_INFO("applying pipe b force quirk\n");
  14646. }
  14647.  
  14648. /*
  14649.  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  14650.  */
  14651. static void quirk_ssc_force_disable(struct drm_device *dev)
  14652. {
  14653.         struct drm_i915_private *dev_priv = dev->dev_private;
  14654.         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  14655.         DRM_INFO("applying lvds SSC disable quirk\n");
  14656. }
  14657.  
  14658. /*
  14659.  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  14660.  * brightness value
  14661.  */
  14662. static void quirk_invert_brightness(struct drm_device *dev)
  14663. {
  14664.         struct drm_i915_private *dev_priv = dev->dev_private;
  14665.         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  14666.         DRM_INFO("applying inverted panel brightness quirk\n");
  14667. }
  14668.  
  14669. /* Some VBT's incorrectly indicate no backlight is present */
  14670. static void quirk_backlight_present(struct drm_device *dev)
  14671. {
  14672.         struct drm_i915_private *dev_priv = dev->dev_private;
  14673.         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
  14674.         DRM_INFO("applying backlight present quirk\n");
  14675. }
  14676.  
  14677. struct intel_quirk {
  14678.         int device;
  14679.         int subsystem_vendor;
  14680.         int subsystem_device;
  14681.         void (*hook)(struct drm_device *dev);
  14682. };
  14683.  
  14684. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  14685. struct intel_dmi_quirk {
  14686.         void (*hook)(struct drm_device *dev);
  14687.         const struct dmi_system_id (*dmi_id_list)[];
  14688. };
  14689.  
  14690. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  14691. {
  14692.         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  14693.         return 1;
  14694. }
  14695.  
  14696. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  14697.         {
  14698.                 .dmi_id_list = &(const struct dmi_system_id[]) {
  14699.                         {
  14700.                                 .callback = intel_dmi_reverse_brightness,
  14701.                                 .ident = "NCR Corporation",
  14702.                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  14703.                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
  14704.                                 },
  14705.                         },
  14706.                         { }  /* terminating entry */
  14707.                 },
  14708.                 .hook = quirk_invert_brightness,
  14709.         },
  14710. };
  14711.  
  14712. static struct intel_quirk intel_quirks[] = {
  14713.         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  14714.         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  14715.  
  14716.         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  14717.         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  14718.  
  14719.         /* 830 needs to leave pipe A & dpll A up */
  14720.         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  14721.  
  14722.         /* 830 needs to leave pipe B & dpll B up */
  14723.         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
  14724.  
  14725.         /* Lenovo U160 cannot use SSC on LVDS */
  14726.         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  14727.  
  14728.         /* Sony Vaio Y cannot use SSC on LVDS */
  14729.         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  14730.  
  14731.         /* Acer Aspire 5734Z must invert backlight brightness */
  14732.         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  14733.  
  14734.         /* Acer/eMachines G725 */
  14735.         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  14736.  
  14737.         /* Acer/eMachines e725 */
  14738.         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  14739.  
  14740.         /* Acer/Packard Bell NCL20 */
  14741.         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  14742.  
  14743.         /* Acer Aspire 4736Z */
  14744.         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
  14745.  
  14746.         /* Acer Aspire 5336 */
  14747.         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
  14748.  
  14749.         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
  14750.         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
  14751.  
  14752.         /* Acer C720 Chromebook (Core i3 4005U) */
  14753.         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
  14754.  
  14755.         /* Apple Macbook 2,1 (Core 2 T7400) */
  14756.         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
  14757.  
  14758.         /* Apple Macbook 4,1 */
  14759.         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
  14760.  
  14761.         /* Toshiba CB35 Chromebook (Celeron 2955U) */
  14762.         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
  14763.  
  14764.         /* HP Chromebook 14 (Celeron 2955U) */
  14765.         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
  14766.  
  14767.         /* Dell Chromebook 11 */
  14768.         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
  14769.  
  14770.         /* Dell Chromebook 11 (2015 version) */
  14771.         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
  14772. };
  14773.  
  14774. static void intel_init_quirks(struct drm_device *dev)
  14775. {
  14776.         struct pci_dev *d = dev->pdev;
  14777.         int i;
  14778.  
  14779.         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  14780.                 struct intel_quirk *q = &intel_quirks[i];
  14781.  
  14782.                 if (d->device == q->device &&
  14783.                     (d->subsystem_vendor == q->subsystem_vendor ||
  14784.                      q->subsystem_vendor == PCI_ANY_ID) &&
  14785.                     (d->subsystem_device == q->subsystem_device ||
  14786.                      q->subsystem_device == PCI_ANY_ID))
  14787.                         q->hook(dev);
  14788.         }
  14789.         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  14790.                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  14791.                         intel_dmi_quirks[i].hook(dev);
  14792.         }
  14793. }
  14794.  
  14795. /* Disable the VGA plane that we never use */
  14796. static void i915_disable_vga(struct drm_device *dev)
  14797. {
  14798.         struct drm_i915_private *dev_priv = dev->dev_private;
  14799.         u8 sr1;
  14800.         u32 vga_reg = i915_vgacntrl_reg(dev);
  14801.  
  14802.         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
  14803. //      vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  14804.         outb(SR01, VGA_SR_INDEX);
  14805.         sr1 = inb(VGA_SR_DATA);
  14806.         outb(sr1 | 1<<5, VGA_SR_DATA);
  14807. //      vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  14808.         udelay(300);
  14809.  
  14810.         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  14811.         POSTING_READ(vga_reg);
  14812. }
  14813.  
  14814. void intel_modeset_init_hw(struct drm_device *dev)
  14815. {
  14816.         intel_update_cdclk(dev);
  14817.         intel_prepare_ddi(dev);
  14818.         intel_init_clock_gating(dev);
  14819.         intel_enable_gt_powersave(dev);
  14820. }
  14821.  
  14822. void intel_modeset_init(struct drm_device *dev)
  14823. {
  14824.         struct drm_i915_private *dev_priv = dev->dev_private;
  14825.         int sprite, ret;
  14826.         enum pipe pipe;
  14827.         struct intel_crtc *crtc;
  14828.  
  14829.         drm_mode_config_init(dev);
  14830.  
  14831.         dev->mode_config.min_width = 0;
  14832.         dev->mode_config.min_height = 0;
  14833.  
  14834.         dev->mode_config.preferred_depth = 24;
  14835.         dev->mode_config.prefer_shadow = 1;
  14836.  
  14837.         dev->mode_config.allow_fb_modifiers = true;
  14838.  
  14839.         dev->mode_config.funcs = &intel_mode_funcs;
  14840.  
  14841.         intel_init_quirks(dev);
  14842.  
  14843.         intel_init_pm(dev);
  14844.  
  14845.         if (INTEL_INFO(dev)->num_pipes == 0)
  14846.                 return;
  14847.  
  14848.         /*
  14849.          * There may be no VBT; and if the BIOS enabled SSC we can
  14850.          * just keep using it to avoid unnecessary flicker.  Whereas if the
  14851.          * BIOS isn't using it, don't assume it will work even if the VBT
  14852.          * indicates as much.
  14853.          */
  14854.         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
  14855.                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
  14856.                                             DREF_SSC1_ENABLE);
  14857.  
  14858.                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
  14859.                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
  14860.                                      bios_lvds_use_ssc ? "en" : "dis",
  14861.                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
  14862.                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
  14863.                 }
  14864.         }
  14865.  
  14866.         intel_init_display(dev);
  14867.  
  14868.         if (IS_GEN2(dev)) {
  14869.                 dev->mode_config.max_width = 2048;
  14870.                 dev->mode_config.max_height = 2048;
  14871.         } else if (IS_GEN3(dev)) {
  14872.                 dev->mode_config.max_width = 4096;
  14873.                 dev->mode_config.max_height = 4096;
  14874.         } else {
  14875.                 dev->mode_config.max_width = 8192;
  14876.                 dev->mode_config.max_height = 8192;
  14877.         }
  14878.  
  14879.         if (IS_GEN2(dev)) {
  14880.                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
  14881.                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
  14882.         } else {
  14883.                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
  14884.                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
  14885.         }
  14886.  
  14887.         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  14888.  
  14889.         DRM_DEBUG_KMS("%d display pipe%s available.\n",
  14890.                       INTEL_INFO(dev)->num_pipes,
  14891.                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  14892.  
  14893.         for_each_pipe(dev_priv, pipe) {
  14894.                 intel_crtc_init(dev, pipe);
  14895.                 for_each_sprite(dev_priv, pipe, sprite) {
  14896.                         ret = intel_plane_init(dev, pipe, sprite);
  14897.                         if (ret)
  14898.                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  14899.                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
  14900.                 }
  14901.         }
  14902.  
  14903.         intel_update_czclk(dev_priv);
  14904.         intel_update_cdclk(dev);
  14905.  
  14906.         intel_shared_dpll_init(dev);
  14907.  
  14908.         /* Just disable it once at startup */
  14909.         i915_disable_vga(dev);
  14910.         intel_setup_outputs(dev);
  14911.  
  14912.         /* Just in case the BIOS is doing something questionable. */
  14913.         intel_fbc_disable(dev_priv);
  14914.  
  14915.         drm_modeset_lock_all(dev);
  14916.         intel_modeset_setup_hw_state(dev);
  14917.         drm_modeset_unlock_all(dev);
  14918.  
  14919.         for_each_intel_crtc(dev, crtc) {
  14920.                 struct intel_initial_plane_config plane_config = {};
  14921.  
  14922.                 if (!crtc->active)
  14923.                         continue;
  14924.  
  14925.                 /*
  14926.                  * Note that reserving the BIOS fb up front prevents us
  14927.                  * from stuffing other stolen allocations like the ring
  14928.                  * on top.  This prevents some ugliness at boot time, and
  14929.                  * can even allow for smooth boot transitions if the BIOS
  14930.                  * fb is large enough for the active pipe configuration.
  14931.                  */
  14932.                 dev_priv->display.get_initial_plane_config(crtc,
  14933.                                                            &plane_config);
  14934.  
  14935.                 /*
  14936.                  * If the fb is shared between multiple heads, we'll
  14937.                  * just get the first one.
  14938.                  */
  14939.                 intel_find_initial_plane_obj(crtc, &plane_config);
  14940.                 if(!main_fb_obj)
  14941.                 {
  14942.                         struct drm_framebuffer *fb;
  14943.  
  14944.                         fb = crtc->base.primary->fb;
  14945.                         main_fb_obj = intel_fb_obj(fb);
  14946.                         main_fb_obj->map_and_fenceable=true;
  14947.                         DRM_DEBUG_KMS("main_fb_obj %p gtt_offset 0x%08lx\n", main_fb_obj, i915_gem_obj_ggtt_offset(main_fb_obj));
  14948.                 }
  14949.  
  14950.         }
  14951. }
  14952.  
  14953. static void intel_enable_pipe_a(struct drm_device *dev)
  14954. {
  14955.         struct intel_connector *connector;
  14956.         struct drm_connector *crt = NULL;
  14957.         struct intel_load_detect_pipe load_detect_temp;
  14958.         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
  14959.  
  14960.         /* We can't just switch on the pipe A, we need to set things up with a
  14961.          * proper mode and output configuration. As a gross hack, enable pipe A
  14962.          * by enabling the load detect pipe once. */
  14963.         for_each_intel_connector(dev, connector) {
  14964.                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  14965.                         crt = &connector->base;
  14966.                         break;
  14967.                 }
  14968.         }
  14969.  
  14970.         if (!crt)
  14971.                 return;
  14972.  
  14973.         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
  14974.                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
  14975. }
  14976.  
  14977. static bool
  14978. intel_check_plane_mapping(struct intel_crtc *crtc)
  14979. {
  14980.         struct drm_device *dev = crtc->base.dev;
  14981.         struct drm_i915_private *dev_priv = dev->dev_private;
  14982.         u32 val;
  14983.  
  14984.         if (INTEL_INFO(dev)->num_pipes == 1)
  14985.                 return true;
  14986.  
  14987.         val = I915_READ(DSPCNTR(!crtc->plane));
  14988.  
  14989.         if ((val & DISPLAY_PLANE_ENABLE) &&
  14990.             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  14991.                 return false;
  14992.  
  14993.         return true;
  14994. }
  14995.  
  14996. static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
  14997. {
  14998.         struct drm_device *dev = crtc->base.dev;
  14999.         struct intel_encoder *encoder;
  15000.  
  15001.         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  15002.                 return true;
  15003.  
  15004.         return false;
  15005. }
  15006.  
  15007. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  15008. {
  15009.         struct drm_device *dev = crtc->base.dev;
  15010.         struct drm_i915_private *dev_priv = dev->dev_private;
  15011.         u32 reg;
  15012.  
  15013.         /* Clear any frame start delays used for debugging left by the BIOS */
  15014.         reg = PIPECONF(crtc->config->cpu_transcoder);
  15015.         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  15016.  
  15017.         /* restore vblank interrupts to correct state */
  15018.         drm_crtc_vblank_reset(&crtc->base);
  15019.         if (crtc->active) {
  15020.                 struct intel_plane *plane;
  15021.  
  15022.                 drm_crtc_vblank_on(&crtc->base);
  15023.  
  15024.                 /* Disable everything but the primary plane */
  15025.                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
  15026.                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
  15027.                                 continue;
  15028.  
  15029.                         plane->disable_plane(&plane->base, &crtc->base);
  15030.                 }
  15031.         }
  15032.  
  15033.         /* We need to sanitize the plane -> pipe mapping first because this will
  15034.          * disable the crtc (and hence change the state) if it is wrong. Note
  15035.          * that gen4+ has a fixed plane -> pipe mapping.  */
  15036.         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  15037.                 bool plane;
  15038.  
  15039.                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  15040.                               crtc->base.base.id);
  15041.  
  15042.                 /* Pipe has the wrong plane attached and the plane is active.
  15043.                  * Temporarily change the plane mapping and disable everything
  15044.                  * ...  */
  15045.                 plane = crtc->plane;
  15046.                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
  15047.                 crtc->plane = !plane;
  15048.                 intel_crtc_disable_noatomic(&crtc->base);
  15049.                 crtc->plane = plane;
  15050.         }
  15051.  
  15052.         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  15053.             crtc->pipe == PIPE_A && !crtc->active) {
  15054.                 /* BIOS forgot to enable pipe A, this mostly happens after
  15055.                  * resume. Force-enable the pipe to fix this, the update_dpms
  15056.                  * call below we restore the pipe to the right state, but leave
  15057.                  * the required bits on. */
  15058.                 intel_enable_pipe_a(dev);
  15059.         }
  15060.  
  15061.         /* Adjust the state of the output pipe according to whether we
  15062.          * have active connectors/encoders. */
  15063.         if (!intel_crtc_has_encoders(crtc))
  15064.                 intel_crtc_disable_noatomic(&crtc->base);
  15065.  
  15066.         if (crtc->active != crtc->base.state->active) {
  15067.                 struct intel_encoder *encoder;
  15068.  
  15069.                 /* This can happen either due to bugs in the get_hw_state
  15070.                  * functions or because of calls to intel_crtc_disable_noatomic,
  15071.                  * or because the pipe is force-enabled due to the
  15072.                  * pipe A quirk. */
  15073.                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  15074.                               crtc->base.base.id,
  15075.                               crtc->base.state->enable ? "enabled" : "disabled",
  15076.                               crtc->active ? "enabled" : "disabled");
  15077.  
  15078.                 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
  15079.                 crtc->base.state->active = crtc->active;
  15080.                 crtc->base.enabled = crtc->active;
  15081.  
  15082.                 /* Because we only establish the connector -> encoder ->
  15083.                  * crtc links if something is active, this means the
  15084.                  * crtc is now deactivated. Break the links. connector
  15085.                  * -> encoder links are only establish when things are
  15086.                  *  actually up, hence no need to break them. */
  15087.                 WARN_ON(crtc->active);
  15088.  
  15089.                 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  15090.                         encoder->base.crtc = NULL;
  15091.         }
  15092.  
  15093.         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
  15094.                 /*
  15095.                  * We start out with underrun reporting disabled to avoid races.
  15096.                  * For correct bookkeeping mark this on active crtcs.
  15097.                  *
  15098.                  * Also on gmch platforms we dont have any hardware bits to
  15099.                  * disable the underrun reporting. Which means we need to start
  15100.                  * out with underrun reporting disabled also on inactive pipes,
  15101.                  * since otherwise we'll complain about the garbage we read when
  15102.                  * e.g. coming up after runtime pm.
  15103.                  *
  15104.                  * No protection against concurrent access is required - at
  15105.                  * worst a fifo underrun happens which also sets this to false.
  15106.                  */
  15107.                 crtc->cpu_fifo_underrun_disabled = true;
  15108.                 crtc->pch_fifo_underrun_disabled = true;
  15109.         }
  15110. }
  15111.  
  15112. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  15113. {
  15114.         struct intel_connector *connector;
  15115.         struct drm_device *dev = encoder->base.dev;
  15116.         bool active = false;
  15117.  
  15118.         /* We need to check both for a crtc link (meaning that the
  15119.          * encoder is active and trying to read from a pipe) and the
  15120.          * pipe itself being active. */
  15121.         bool has_active_crtc = encoder->base.crtc &&
  15122.                 to_intel_crtc(encoder->base.crtc)->active;
  15123.  
  15124.         for_each_intel_connector(dev, connector) {
  15125.                 if (connector->base.encoder != &encoder->base)
  15126.                         continue;
  15127.  
  15128.                 active = true;
  15129.                 break;
  15130.         }
  15131.  
  15132.         if (active && !has_active_crtc) {
  15133.                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  15134.                               encoder->base.base.id,
  15135.                               encoder->base.name);
  15136.  
  15137.                 /* Connector is active, but has no active pipe. This is
  15138.                  * fallout from our resume register restoring. Disable
  15139.                  * the encoder manually again. */
  15140.                 if (encoder->base.crtc) {
  15141.                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  15142.                                       encoder->base.base.id,
  15143.                                       encoder->base.name);
  15144.                         encoder->disable(encoder);
  15145.                         if (encoder->post_disable)
  15146.                                 encoder->post_disable(encoder);
  15147.                 }
  15148.                 encoder->base.crtc = NULL;
  15149.  
  15150.                 /* Inconsistent output/port/pipe state happens presumably due to
  15151.                  * a bug in one of the get_hw_state functions. Or someplace else
  15152.                  * in our code, like the register restore mess on resume. Clamp
  15153.                  * things to off as a safer default. */
  15154.                 for_each_intel_connector(dev, connector) {
  15155.                         if (connector->encoder != encoder)
  15156.                                 continue;
  15157.                         connector->base.dpms = DRM_MODE_DPMS_OFF;
  15158.                         connector->base.encoder = NULL;
  15159.                 }
  15160.         }
  15161.         /* Enabled encoders without active connectors will be fixed in
  15162.          * the crtc fixup. */
  15163. }
  15164.  
  15165. void i915_redisable_vga_power_on(struct drm_device *dev)
  15166. {
  15167.         struct drm_i915_private *dev_priv = dev->dev_private;
  15168.         u32 vga_reg = i915_vgacntrl_reg(dev);
  15169.  
  15170.         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
  15171.                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  15172.                 i915_disable_vga(dev);
  15173.         }
  15174. }
  15175.  
  15176. void i915_redisable_vga(struct drm_device *dev)
  15177. {
  15178.         struct drm_i915_private *dev_priv = dev->dev_private;
  15179.  
  15180.         /* This function can be called both from intel_modeset_setup_hw_state or
  15181.          * at a very early point in our resume sequence, where the power well
  15182.          * structures are not yet restored. Since this function is at a very
  15183.          * paranoid "someone might have enabled VGA while we were not looking"
  15184.          * level, just check if the power well is enabled instead of trying to
  15185.          * follow the "don't touch the power well if we don't need it" policy
  15186.          * the rest of the driver uses. */
  15187.         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
  15188.                 return;
  15189.  
  15190.         i915_redisable_vga_power_on(dev);
  15191. }
  15192.  
  15193. static bool primary_get_hw_state(struct intel_plane *plane)
  15194. {
  15195.         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
  15196.  
  15197.         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
  15198. }
  15199.  
  15200. /* FIXME read out full plane state for all planes */
  15201. static void readout_plane_state(struct intel_crtc *crtc)
  15202. {
  15203.         struct drm_plane *primary = crtc->base.primary;
  15204.         struct intel_plane_state *plane_state =
  15205.                 to_intel_plane_state(primary->state);
  15206.  
  15207.         plane_state->visible =
  15208.                 primary_get_hw_state(to_intel_plane(primary));
  15209.  
  15210.         if (plane_state->visible)
  15211.                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
  15212. }
  15213.  
  15214. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  15215. {
  15216.         struct drm_i915_private *dev_priv = dev->dev_private;
  15217.         enum pipe pipe;
  15218.         struct intel_crtc *crtc;
  15219.         struct intel_encoder *encoder;
  15220.         struct intel_connector *connector;
  15221.         int i;
  15222.  
  15223.         for_each_intel_crtc(dev, crtc) {
  15224.                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
  15225.                 memset(crtc->config, 0, sizeof(*crtc->config));
  15226.                 crtc->config->base.crtc = &crtc->base;
  15227.  
  15228.                 crtc->active = dev_priv->display.get_pipe_config(crtc,
  15229.                                                                  crtc->config);
  15230.  
  15231.                 crtc->base.state->active = crtc->active;
  15232.                 crtc->base.enabled = crtc->active;
  15233.  
  15234.                 readout_plane_state(crtc);
  15235.  
  15236.                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  15237.                               crtc->base.base.id,
  15238.                               crtc->active ? "enabled" : "disabled");
  15239.         }
  15240.  
  15241.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  15242.                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  15243.  
  15244.                 pll->on = pll->get_hw_state(dev_priv, pll,
  15245.                                             &pll->config.hw_state);
  15246.                 pll->active = 0;
  15247.                 pll->config.crtc_mask = 0;
  15248.                 for_each_intel_crtc(dev, crtc) {
  15249.                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
  15250.                                 pll->active++;
  15251.                                 pll->config.crtc_mask |= 1 << crtc->pipe;
  15252.                         }
  15253.                 }
  15254.  
  15255.                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
  15256.                               pll->name, pll->config.crtc_mask, pll->on);
  15257.  
  15258.                 if (pll->config.crtc_mask)
  15259.                         intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
  15260.         }
  15261.  
  15262.         for_each_intel_encoder(dev, encoder) {
  15263.                 pipe = 0;
  15264.  
  15265.                 if (encoder->get_hw_state(encoder, &pipe)) {
  15266.                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  15267.                         encoder->base.crtc = &crtc->base;
  15268.                         encoder->get_config(encoder, crtc->config);
  15269.                 } else {
  15270.                         encoder->base.crtc = NULL;
  15271.                 }
  15272.  
  15273.                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
  15274.                               encoder->base.base.id,
  15275.                               encoder->base.name,
  15276.                               encoder->base.crtc ? "enabled" : "disabled",
  15277.                               pipe_name(pipe));
  15278.         }
  15279.  
  15280.         for_each_intel_connector(dev, connector) {
  15281.                 if (connector->get_hw_state(connector)) {
  15282.                         connector->base.dpms = DRM_MODE_DPMS_ON;
  15283.                         connector->base.encoder = &connector->encoder->base;
  15284.                 } else {
  15285.                         connector->base.dpms = DRM_MODE_DPMS_OFF;
  15286.                         connector->base.encoder = NULL;
  15287.                 }
  15288.                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  15289.                               connector->base.base.id,
  15290.                               connector->base.name,
  15291.                               connector->base.encoder ? "enabled" : "disabled");
  15292.         }
  15293.  
  15294.         for_each_intel_crtc(dev, crtc) {
  15295.                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
  15296.  
  15297.                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
  15298.                 if (crtc->base.state->active) {
  15299.                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
  15300.                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
  15301.                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
  15302.  
  15303.                         /*
  15304.                          * The initial mode needs to be set in order to keep
  15305.                          * the atomic core happy. It wants a valid mode if the
  15306.                          * crtc's enabled, so we do the above call.
  15307.                          *
  15308.                          * At this point some state updated by the connectors
  15309.                          * in their ->detect() callback has not run yet, so
  15310.                          * no recalculation can be done yet.
  15311.                          *
  15312.                          * Even if we could do a recalculation and modeset
  15313.                          * right now it would cause a double modeset if
  15314.                          * fbdev or userspace chooses a different initial mode.
  15315.                          *
  15316.                          * If that happens, someone indicated they wanted a
  15317.                          * mode change, which means it's safe to do a full
  15318.                          * recalculation.
  15319.                          */
  15320.                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
  15321.  
  15322.                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
  15323.                         update_scanline_offset(crtc);
  15324.                 }
  15325.         }
  15326. }
  15327.  
  15328. /* Scan out the current hw modeset state,
  15329.  * and sanitizes it to the current state
  15330.  */
  15331. static void
  15332. intel_modeset_setup_hw_state(struct drm_device *dev)
  15333. {
  15334.         struct drm_i915_private *dev_priv = dev->dev_private;
  15335.         enum pipe pipe;
  15336.         struct intel_crtc *crtc;
  15337.         struct intel_encoder *encoder;
  15338.         int i;
  15339.  
  15340.         intel_modeset_readout_hw_state(dev);
  15341.  
  15342.         /* HW state is read out, now we need to sanitize this mess. */
  15343.         for_each_intel_encoder(dev, encoder) {
  15344.                 intel_sanitize_encoder(encoder);
  15345.         }
  15346.  
  15347.         for_each_pipe(dev_priv, pipe) {
  15348.                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  15349.                 intel_sanitize_crtc(crtc);
  15350.                 intel_dump_pipe_config(crtc, crtc->config,
  15351.                                        "[setup_hw_state]");
  15352.         }
  15353.  
  15354.         intel_modeset_update_connector_atomic_state(dev);
  15355.  
  15356.         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  15357.                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  15358.  
  15359.                 if (!pll->on || pll->active)
  15360.                         continue;
  15361.  
  15362.                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  15363.  
  15364.                 pll->disable(dev_priv, pll);
  15365.                 pll->on = false;
  15366.         }
  15367.  
  15368.         if (IS_VALLEYVIEW(dev))
  15369.                 vlv_wm_get_hw_state(dev);
  15370.         else if (IS_GEN9(dev))
  15371.                 skl_wm_get_hw_state(dev);
  15372.         else if (HAS_PCH_SPLIT(dev))
  15373.                 ilk_wm_get_hw_state(dev);
  15374.  
  15375.         for_each_intel_crtc(dev, crtc) {
  15376.                 unsigned long put_domains;
  15377.  
  15378.                 put_domains = modeset_get_crtc_power_domains(&crtc->base);
  15379.                 if (WARN_ON(put_domains))
  15380.                         modeset_put_power_domains(dev_priv, put_domains);
  15381.         }
  15382.         intel_display_set_init_power(dev_priv, false);
  15383. }
  15384.  
  15385. void intel_display_resume(struct drm_device *dev)
  15386. {
  15387.         struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
  15388.         struct intel_connector *conn;
  15389.         struct intel_plane *plane;
  15390.         struct drm_crtc *crtc;
  15391.         int ret;
  15392.  
  15393.         if (!state)
  15394.                 return;
  15395.  
  15396.         state->acquire_ctx = dev->mode_config.acquire_ctx;
  15397.  
  15398.         /* preserve complete old state, including dpll */
  15399.         intel_atomic_get_shared_dpll_state(state);
  15400.  
  15401.         for_each_crtc(dev, crtc) {
  15402.                 struct drm_crtc_state *crtc_state =
  15403.                         drm_atomic_get_crtc_state(state, crtc);
  15404.  
  15405.                 ret = PTR_ERR_OR_ZERO(crtc_state);
  15406.                 if (ret)
  15407.                         goto err;
  15408.  
  15409.                 /* force a restore */
  15410.                 crtc_state->mode_changed = true;
  15411.         }
  15412.  
  15413.         for_each_intel_plane(dev, plane) {
  15414.                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
  15415.                 if (ret)
  15416.                         goto err;
  15417.         }
  15418.  
  15419.         for_each_intel_connector(dev, conn) {
  15420.                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
  15421.                 if (ret)
  15422.                         goto err;
  15423.         }
  15424.  
  15425.         intel_modeset_setup_hw_state(dev);
  15426.  
  15427.         i915_redisable_vga(dev);
  15428.         ret = drm_atomic_commit(state);
  15429.         if (!ret)
  15430.                 return;
  15431.  
  15432. err:
  15433.         DRM_ERROR("Restoring old state failed with %i\n", ret);
  15434.         drm_atomic_state_free(state);
  15435. }
  15436.  
  15437. void intel_modeset_gem_init(struct drm_device *dev)
  15438. {
  15439.         struct drm_crtc *c;
  15440.         struct drm_i915_gem_object *obj;
  15441.         int ret;
  15442.  
  15443.         mutex_lock(&dev->struct_mutex);
  15444.         intel_init_gt_powersave(dev);
  15445.         mutex_unlock(&dev->struct_mutex);
  15446.  
  15447.         intel_modeset_init_hw(dev);
  15448.  
  15449. //   intel_setup_overlay(dev);
  15450.  
  15451.         /*
  15452.          * Make sure any fbs we allocated at startup are properly
  15453.          * pinned & fenced.  When we do the allocation it's too early
  15454.          * for this.
  15455.          */
  15456.         for_each_crtc(dev, c) {
  15457.                 obj = intel_fb_obj(c->primary->fb);
  15458.                 if (obj == NULL)
  15459.                         continue;
  15460.  
  15461.                 mutex_lock(&dev->struct_mutex);
  15462.                 ret = intel_pin_and_fence_fb_obj(c->primary,
  15463.                                                  c->primary->fb,
  15464.                                                  c->primary->state,
  15465.                                                  NULL, NULL);
  15466.                 mutex_unlock(&dev->struct_mutex);
  15467.                 if (ret) {
  15468.                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
  15469.                                   to_intel_crtc(c)->pipe);
  15470.                         drm_framebuffer_unreference(c->primary->fb);
  15471.                         c->primary->fb = NULL;
  15472.                         c->primary->crtc = c->primary->state->crtc = NULL;
  15473.                         update_state_fb(c->primary);
  15474.                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
  15475.                 }
  15476.         }
  15477.  
  15478.         intel_backlight_register(dev);
  15479. }
  15480.  
  15481. void intel_connector_unregister(struct intel_connector *intel_connector)
  15482. {
  15483.         struct drm_connector *connector = &intel_connector->base;
  15484.  
  15485.         intel_panel_destroy_backlight(connector);
  15486.         drm_connector_unregister(connector);
  15487. }
  15488.  
  15489. void intel_modeset_cleanup(struct drm_device *dev)
  15490. {
  15491. #if 0
  15492.         struct drm_i915_private *dev_priv = dev->dev_private;
  15493.         struct drm_connector *connector;
  15494.  
  15495.         intel_disable_gt_powersave(dev);
  15496.  
  15497.         intel_backlight_unregister(dev);
  15498.  
  15499.         /*
  15500.          * Interrupts and polling as the first thing to avoid creating havoc.
  15501.          * Too much stuff here (turning of connectors, ...) would
  15502.          * experience fancy races otherwise.
  15503.          */
  15504.         intel_irq_uninstall(dev_priv);
  15505.  
  15506.         /*
  15507.          * Due to the hpd irq storm handling the hotplug work can re-arm the
  15508.          * poll handlers. Hence disable polling after hpd handling is shut down.
  15509.          */
  15510.         drm_kms_helper_poll_fini(dev);
  15511.  
  15512.         intel_unregister_dsm_handler();
  15513.  
  15514.         intel_fbc_disable(dev_priv);
  15515.  
  15516.         /* flush any delayed tasks or pending work */
  15517.         flush_scheduled_work();
  15518.  
  15519.         /* destroy the backlight and sysfs files before encoders/connectors */
  15520.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  15521.                 struct intel_connector *intel_connector;
  15522.  
  15523.                 intel_connector = to_intel_connector(connector);
  15524.                 intel_connector->unregister(intel_connector);
  15525.         }
  15526.  
  15527.         drm_mode_config_cleanup(dev);
  15528.  
  15529.         intel_cleanup_overlay(dev);
  15530.  
  15531.         mutex_lock(&dev->struct_mutex);
  15532.         intel_cleanup_gt_powersave(dev);
  15533.         mutex_unlock(&dev->struct_mutex);
  15534. #endif
  15535. }
  15536.  
  15537. /*
  15538.  * Return which encoder is currently attached for connector.
  15539.  */
  15540. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  15541. {
  15542.         return &intel_attached_encoder(connector)->base;
  15543. }
  15544.  
  15545. void intel_connector_attach_encoder(struct intel_connector *connector,
  15546.                                     struct intel_encoder *encoder)
  15547. {
  15548.         connector->encoder = encoder;
  15549.         drm_mode_connector_attach_encoder(&connector->base,
  15550.                                           &encoder->base);
  15551. }
  15552.  
  15553. /*
  15554.  * set vga decode state - true == enable VGA decode
  15555.  */
  15556. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  15557. {
  15558.         struct drm_i915_private *dev_priv = dev->dev_private;
  15559.         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
  15560.         u16 gmch_ctrl;
  15561.  
  15562.         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
  15563.                 DRM_ERROR("failed to read control word\n");
  15564.                 return -EIO;
  15565.         }
  15566.  
  15567.         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
  15568.                 return 0;
  15569.  
  15570.         if (state)
  15571.                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  15572.         else
  15573.                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  15574.  
  15575.         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
  15576.                 DRM_ERROR("failed to write control word\n");
  15577.                 return -EIO;
  15578.         }
  15579.  
  15580.         return 0;
  15581. }
  15582.  
  15583. #ifdef CONFIG_DEBUG_FS
  15584.  
  15585. struct intel_display_error_state {
  15586.  
  15587.         u32 power_well_driver;
  15588.  
  15589.         int num_transcoders;
  15590.  
  15591.         struct intel_cursor_error_state {
  15592.                 u32 control;
  15593.                 u32 position;
  15594.                 u32 base;
  15595.                 u32 size;
  15596.         } cursor[I915_MAX_PIPES];
  15597.  
  15598.         struct intel_pipe_error_state {
  15599.                 bool power_domain_on;
  15600.                 u32 source;
  15601.                 u32 stat;
  15602.         } pipe[I915_MAX_PIPES];
  15603.  
  15604.         struct intel_plane_error_state {
  15605.                 u32 control;
  15606.                 u32 stride;
  15607.                 u32 size;
  15608.                 u32 pos;
  15609.                 u32 addr;
  15610.                 u32 surface;
  15611.                 u32 tile_offset;
  15612.         } plane[I915_MAX_PIPES];
  15613.  
  15614.         struct intel_transcoder_error_state {
  15615.                 bool power_domain_on;
  15616.                 enum transcoder cpu_transcoder;
  15617.  
  15618.                 u32 conf;
  15619.  
  15620.                 u32 htotal;
  15621.                 u32 hblank;
  15622.                 u32 hsync;
  15623.                 u32 vtotal;
  15624.                 u32 vblank;
  15625.                 u32 vsync;
  15626.         } transcoder[4];
  15627. };
  15628.  
  15629. struct intel_display_error_state *
  15630. intel_display_capture_error_state(struct drm_device *dev)
  15631. {
  15632.         struct drm_i915_private *dev_priv = dev->dev_private;
  15633.         struct intel_display_error_state *error;
  15634.         int transcoders[] = {
  15635.                 TRANSCODER_A,
  15636.                 TRANSCODER_B,
  15637.                 TRANSCODER_C,
  15638.                 TRANSCODER_EDP,
  15639.         };
  15640.         int i;
  15641.  
  15642.         if (INTEL_INFO(dev)->num_pipes == 0)
  15643.                 return NULL;
  15644.  
  15645.         error = kzalloc(sizeof(*error), GFP_ATOMIC);
  15646.         if (error == NULL)
  15647.                 return NULL;
  15648.  
  15649.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  15650.                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  15651.  
  15652.         for_each_pipe(dev_priv, i) {
  15653.                 error->pipe[i].power_domain_on =
  15654.                         __intel_display_power_is_enabled(dev_priv,
  15655.                                                          POWER_DOMAIN_PIPE(i));
  15656.                 if (!error->pipe[i].power_domain_on)
  15657.                         continue;
  15658.  
  15659.                 error->cursor[i].control = I915_READ(CURCNTR(i));
  15660.                 error->cursor[i].position = I915_READ(CURPOS(i));
  15661.                 error->cursor[i].base = I915_READ(CURBASE(i));
  15662.  
  15663.                 error->plane[i].control = I915_READ(DSPCNTR(i));
  15664.                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  15665.                 if (INTEL_INFO(dev)->gen <= 3) {
  15666.                         error->plane[i].size = I915_READ(DSPSIZE(i));
  15667.                         error->plane[i].pos = I915_READ(DSPPOS(i));
  15668.                 }
  15669.                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  15670.                         error->plane[i].addr = I915_READ(DSPADDR(i));
  15671.                 if (INTEL_INFO(dev)->gen >= 4) {
  15672.                         error->plane[i].surface = I915_READ(DSPSURF(i));
  15673.                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  15674.                 }
  15675.  
  15676.                 error->pipe[i].source = I915_READ(PIPESRC(i));
  15677.  
  15678.                 if (HAS_GMCH_DISPLAY(dev))
  15679.                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
  15680.         }
  15681.  
  15682.         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
  15683.         if (HAS_DDI(dev_priv->dev))
  15684.                 error->num_transcoders++; /* Account for eDP. */
  15685.  
  15686.         for (i = 0; i < error->num_transcoders; i++) {
  15687.                 enum transcoder cpu_transcoder = transcoders[i];
  15688.  
  15689.                 error->transcoder[i].power_domain_on =
  15690.                         __intel_display_power_is_enabled(dev_priv,
  15691.                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
  15692.                 if (!error->transcoder[i].power_domain_on)
  15693.                         continue;
  15694.  
  15695.                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
  15696.  
  15697.                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  15698.                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  15699.                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  15700.                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  15701.                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  15702.                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  15703.                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  15704.         }
  15705.  
  15706.         return error;
  15707. }
  15708.  
  15709. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  15710.  
  15711. void
  15712. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  15713.                                 struct drm_device *dev,
  15714.                                 struct intel_display_error_state *error)
  15715. {
  15716.         struct drm_i915_private *dev_priv = dev->dev_private;
  15717.         int i;
  15718.  
  15719.         if (!error)
  15720.                 return;
  15721.  
  15722.         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  15723.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  15724.                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
  15725.                            error->power_well_driver);
  15726.         for_each_pipe(dev_priv, i) {
  15727.                 err_printf(m, "Pipe [%d]:\n", i);
  15728.                 err_printf(m, "  Power: %s\n",
  15729.                            error->pipe[i].power_domain_on ? "on" : "off");
  15730.                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
  15731.                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
  15732.  
  15733.                 err_printf(m, "Plane [%d]:\n", i);
  15734.                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
  15735.                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
  15736.                 if (INTEL_INFO(dev)->gen <= 3) {
  15737.                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
  15738.                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
  15739.                 }
  15740.                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  15741.                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
  15742.                 if (INTEL_INFO(dev)->gen >= 4) {
  15743.                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
  15744.                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
  15745.                 }
  15746.  
  15747.                 err_printf(m, "Cursor [%d]:\n", i);
  15748.                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
  15749.                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
  15750.                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
  15751.         }
  15752.  
  15753.         for (i = 0; i < error->num_transcoders; i++) {
  15754.                 err_printf(m, "CPU transcoder: %c\n",
  15755.                            transcoder_name(error->transcoder[i].cpu_transcoder));
  15756.                 err_printf(m, "  Power: %s\n",
  15757.                            error->transcoder[i].power_domain_on ? "on" : "off");
  15758.                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
  15759.                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
  15760.                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
  15761.                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
  15762.                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
  15763.                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
  15764.                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
  15765.         }
  15766. }
  15767. #endif
  15768.  
  15769. void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
  15770. {
  15771.         struct intel_crtc *crtc;
  15772.  
  15773.         for_each_intel_crtc(dev, crtc) {
  15774.                 struct intel_unpin_work *work;
  15775.  
  15776.                 spin_lock_irq(&dev->event_lock);
  15777.  
  15778.                 work = crtc->unpin_work;
  15779.  
  15780.                 if (work && work->event &&
  15781.                     work->event->base.file_priv == file) {
  15782.                         kfree(work->event);
  15783.                         work->event = NULL;
  15784.                 }
  15785.  
  15786.                 spin_unlock_irq(&dev->event_lock);
  15787.         }
  15788. }
  15789.