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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  */
  24. #include <linux/firmware.h>
  25. #include "i915_drv.h"
  26. #include "i915_reg.h"
  27.  
  28. /**
  29.  * DOC: csr support for dmc
  30.  *
  31.  * Display Context Save and Restore (CSR) firmware support added from gen9
  32.  * onwards to drive newly added DMC (Display microcontroller) in display
  33.  * engine to save and restore the state of display engine when it enter into
  34.  * low-power state and comes back to normal.
  35.  *
  36.  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
  37.  * FW_LOADED, FW_FAILED.
  38.  *
  39.  * Once the firmware is written into the registers status will be moved from
  40.  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
  41.  * be moved to FW_FAILED.
  42.  */
  43.  
  44. #define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
  45. #define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
  46.  
  47. MODULE_FIRMWARE(I915_CSR_SKL);
  48. MODULE_FIRMWARE(I915_CSR_BXT);
  49.  
  50. /*
  51. * SKL CSR registers for DC5 and DC6
  52. */
  53. #define CSR_PROGRAM(i)                  (0x80000 + (i) * 4)
  54. #define CSR_SSP_BASE_ADDR_GEN9          0x00002FC0
  55. #define CSR_HTP_ADDR_SKL                0x00500034
  56. #define CSR_SSP_BASE                    0x8F074
  57. #define CSR_HTP_SKL                     0x8F004
  58. #define CSR_LAST_WRITE                  0x8F034
  59. #define CSR_LAST_WRITE_VALUE            0xc003b400
  60. /* MMIO address range for CSR program (0x80000 - 0x82FFF) */
  61. #define CSR_MAX_FW_SIZE                 0x2FFF
  62. #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  63. #define CSR_MMIO_START_RANGE    0x80000
  64. #define CSR_MMIO_END_RANGE              0x8FFFF
  65.  
  66. struct intel_css_header {
  67.         /* 0x09 for DMC */
  68.         uint32_t module_type;
  69.  
  70.         /* Includes the DMC specific header in dwords */
  71.         uint32_t header_len;
  72.  
  73.         /* always value would be 0x10000 */
  74.         uint32_t header_ver;
  75.  
  76.         /* Not used */
  77.         uint32_t module_id;
  78.  
  79.         /* Not used */
  80.         uint32_t module_vendor;
  81.  
  82.         /* in YYYYMMDD format */
  83.         uint32_t date;
  84.  
  85.         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  86.         uint32_t size;
  87.  
  88.         /* Not used */
  89.         uint32_t key_size;
  90.  
  91.         /* Not used */
  92.         uint32_t modulus_size;
  93.  
  94.         /* Not used */
  95.         uint32_t exponent_size;
  96.  
  97.         /* Not used */
  98.         uint32_t reserved1[12];
  99.  
  100.         /* Major Minor */
  101.         uint32_t version;
  102.  
  103.         /* Not used */
  104.         uint32_t reserved2[8];
  105.  
  106.         /* Not used */
  107.         uint32_t kernel_header_info;
  108. } __packed;
  109.  
  110. struct intel_fw_info {
  111.         uint16_t reserved1;
  112.  
  113.         /* Stepping (A, B, C, ..., *). * is a wildcard */
  114.         char stepping;
  115.  
  116.         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
  117.         char substepping;
  118.  
  119.         uint32_t offset;
  120.         uint32_t reserved2;
  121. } __packed;
  122.  
  123. struct intel_package_header {
  124.         /* DMC container header length in dwords */
  125.         unsigned char header_len;
  126.  
  127.         /* always value would be 0x01 */
  128.         unsigned char header_ver;
  129.  
  130.         unsigned char reserved[10];
  131.  
  132.         /* Number of valid entries in the FWInfo array below */
  133.         uint32_t num_entries;
  134.  
  135.         struct intel_fw_info fw_info[20];
  136. } __packed;
  137.  
  138. struct intel_dmc_header {
  139.         /* always value would be 0x40403E3E */
  140.         uint32_t signature;
  141.  
  142.         /* DMC binary header length */
  143.         unsigned char header_len;
  144.  
  145.         /* 0x01 */
  146.         unsigned char header_ver;
  147.  
  148.         /* Reserved */
  149.         uint16_t dmcc_ver;
  150.  
  151.         /* Major, Minor */
  152.         uint32_t        project;
  153.  
  154.         /* Firmware program size (excluding header) in dwords */
  155.         uint32_t        fw_size;
  156.  
  157.         /* Major Minor version */
  158.         uint32_t fw_version;
  159.  
  160.         /* Number of valid MMIO cycles present. */
  161.         uint32_t mmio_count;
  162.  
  163.         /* MMIO address */
  164.         uint32_t mmioaddr[8];
  165.  
  166.         /* MMIO data */
  167.         uint32_t mmiodata[8];
  168.  
  169.         /* FW filename  */
  170.         unsigned char dfile[32];
  171.  
  172.         uint32_t reserved1[2];
  173. } __packed;
  174.  
  175. struct stepping_info {
  176.         char stepping;
  177.         char substepping;
  178. };
  179.  
  180. static const struct stepping_info skl_stepping_info[] = {
  181.                 {'A', '0'}, {'B', '0'}, {'C', '0'},
  182.                 {'D', '0'}, {'E', '0'}, {'F', '0'},
  183.                 {'G', '0'}, {'H', '0'}, {'I', '0'}
  184. };
  185.  
  186. static struct stepping_info bxt_stepping_info[] = {
  187.         {'A', '0'}, {'A', '1'}, {'A', '2'},
  188.         {'B', '0'}, {'B', '1'}, {'B', '2'}
  189. };
  190.  
  191. static char intel_get_stepping(struct drm_device *dev)
  192. {
  193.         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
  194.                         ARRAY_SIZE(skl_stepping_info)))
  195.                 return skl_stepping_info[dev->pdev->revision].stepping;
  196.         else if (IS_BROXTON(dev) && (dev->pdev->revision <
  197.                                 ARRAY_SIZE(bxt_stepping_info)))
  198.                 return bxt_stepping_info[dev->pdev->revision].stepping;
  199.         else
  200.                 return -ENODATA;
  201. }
  202.  
  203. static char intel_get_substepping(struct drm_device *dev)
  204. {
  205.         if (IS_SKYLAKE(dev) && (dev->pdev->revision <
  206.                         ARRAY_SIZE(skl_stepping_info)))
  207.                 return skl_stepping_info[dev->pdev->revision].substepping;
  208.         else if (IS_BROXTON(dev) && (dev->pdev->revision <
  209.                         ARRAY_SIZE(bxt_stepping_info)))
  210.                 return bxt_stepping_info[dev->pdev->revision].substepping;
  211.         else
  212.                 return -ENODATA;
  213. }
  214.  
  215. /**
  216.  * intel_csr_load_status_get() - to get firmware loading status.
  217.  * @dev_priv: i915 device.
  218.  *
  219.  * This function helps to get the firmware loading status.
  220.  *
  221.  * Return: Firmware loading status.
  222.  */
  223. enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv)
  224. {
  225.         enum csr_state state;
  226.  
  227.         mutex_lock(&dev_priv->csr_lock);
  228.         state = dev_priv->csr.state;
  229.         mutex_unlock(&dev_priv->csr_lock);
  230.  
  231.         return state;
  232. }
  233.  
  234. /**
  235.  * intel_csr_load_status_set() - help to set firmware loading status.
  236.  * @dev_priv: i915 device.
  237.  * @state: enumeration of firmware loading status.
  238.  *
  239.  * Set the firmware loading status.
  240.  */
  241. void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
  242.                         enum csr_state state)
  243. {
  244.         mutex_lock(&dev_priv->csr_lock);
  245.         dev_priv->csr.state = state;
  246.         mutex_unlock(&dev_priv->csr_lock);
  247. }
  248.  
  249. /**
  250.  * intel_csr_load_program() - write the firmware from memory to register.
  251.  * @dev: drm device.
  252.  *
  253.  * CSR firmware is read from a .bin file and kept in internal memory one time.
  254.  * Everytime display comes back from low power state this function is called to
  255.  * copy the firmware from internal memory to registers.
  256.  */
  257. void intel_csr_load_program(struct drm_device *dev)
  258. {
  259.         struct drm_i915_private *dev_priv = dev->dev_private;
  260.         u32 *payload = dev_priv->csr.dmc_payload;
  261.         uint32_t i, fw_size;
  262.  
  263.         if (!IS_GEN9(dev)) {
  264.                 DRM_ERROR("No CSR support available for this platform\n");
  265.                 return;
  266.         }
  267.  
  268.         /*
  269.          * FIXME: Firmware gets lost on S3/S4, but not when entering system
  270.          * standby or suspend-to-idle (which is just like forced runtime pm).
  271.          * Unfortunately the ACPI subsystem doesn't yet give us a way to
  272.          * differentiate this, hence figure it out with this hack.
  273.          */
  274.         if (I915_READ(CSR_PROGRAM(0)))
  275.                 return;
  276.  
  277.         mutex_lock(&dev_priv->csr_lock);
  278.         fw_size = dev_priv->csr.dmc_fw_size;
  279.         for (i = 0; i < fw_size; i++)
  280.                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
  281.  
  282.         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
  283.                 I915_WRITE(dev_priv->csr.mmioaddr[i],
  284.                         dev_priv->csr.mmiodata[i]);
  285.         }
  286.  
  287.         dev_priv->csr.state = FW_LOADED;
  288.         mutex_unlock(&dev_priv->csr_lock);
  289. }
  290.  
  291. static void finish_csr_load(const struct firmware *fw, void *context)
  292. {
  293.         struct drm_i915_private *dev_priv = context;
  294.         struct drm_device *dev = dev_priv->dev;
  295.         struct intel_css_header *css_header;
  296.         struct intel_package_header *package_header;
  297.         struct intel_dmc_header *dmc_header;
  298.         struct intel_csr *csr = &dev_priv->csr;
  299.         char stepping = intel_get_stepping(dev);
  300.         char substepping = intel_get_substepping(dev);
  301.         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
  302.         uint32_t i;
  303.         uint32_t *dmc_payload;
  304.         bool fw_loaded = false;
  305.  
  306.         if (!fw) {
  307.                 i915_firmware_load_error_print(csr->fw_path, 0);
  308.                 goto out;
  309.         }
  310.  
  311.         if ((stepping == -ENODATA) || (substepping == -ENODATA)) {
  312.                 DRM_ERROR("Unknown stepping info, firmware loading failed\n");
  313.                 goto out;
  314.         }
  315.  
  316.         /* Extract CSS Header information*/
  317.         css_header = (struct intel_css_header *)fw->data;
  318.         if (sizeof(struct intel_css_header) !=
  319.                 (css_header->header_len * 4)) {
  320.                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
  321.                         (css_header->header_len * 4));
  322.                 goto out;
  323.         }
  324.         readcount += sizeof(struct intel_css_header);
  325.  
  326.         /* Extract Package Header information*/
  327.         package_header = (struct intel_package_header *)
  328.                                         &fw->data[readcount];
  329.         if (sizeof(struct intel_package_header) !=
  330.                 (package_header->header_len * 4)) {
  331.                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
  332.                         (package_header->header_len * 4));
  333.                 goto out;
  334.         }
  335.         readcount += sizeof(struct intel_package_header);
  336.  
  337.         /* Search for dmc_offset to find firware binary. */
  338.         for (i = 0; i < package_header->num_entries; i++) {
  339.                 if (package_header->fw_info[i].substepping == '*' &&
  340.                         stepping == package_header->fw_info[i].stepping) {
  341.                         dmc_offset = package_header->fw_info[i].offset;
  342.                         break;
  343.                 } else if (stepping == package_header->fw_info[i].stepping &&
  344.                         substepping == package_header->fw_info[i].substepping) {
  345.                         dmc_offset = package_header->fw_info[i].offset;
  346.                         break;
  347.                 } else if (package_header->fw_info[i].stepping == '*' &&
  348.                         package_header->fw_info[i].substepping == '*')
  349.                         dmc_offset = package_header->fw_info[i].offset;
  350.         }
  351.         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
  352.                 DRM_ERROR("Firmware not supported for %c stepping\n", stepping);
  353.                 goto out;
  354.         }
  355.         readcount += dmc_offset;
  356.  
  357.         /* Extract dmc_header information. */
  358.         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
  359.         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
  360.                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
  361.                                 (dmc_header->header_len));
  362.                 goto out;
  363.         }
  364.         readcount += sizeof(struct intel_dmc_header);
  365.  
  366.         /* Cache the dmc header info. */
  367.         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
  368.                 DRM_ERROR("Firmware has wrong mmio count %u\n",
  369.                                                 dmc_header->mmio_count);
  370.                 goto out;
  371.         }
  372.         csr->mmio_count = dmc_header->mmio_count;
  373.         for (i = 0; i < dmc_header->mmio_count; i++) {
  374.                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
  375.                         dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
  376.                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
  377.                                                 dmc_header->mmioaddr[i]);
  378.                         goto out;
  379.                 }
  380.                 csr->mmioaddr[i] = dmc_header->mmioaddr[i];
  381.                 csr->mmiodata[i] = dmc_header->mmiodata[i];
  382.         }
  383.  
  384.         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
  385.         nbytes = dmc_header->fw_size * 4;
  386.         if (nbytes > CSR_MAX_FW_SIZE) {
  387.                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
  388.                 goto out;
  389.         }
  390.         csr->dmc_fw_size = dmc_header->fw_size;
  391.  
  392.         csr->dmc_payload = kmalloc(nbytes, GFP_KERNEL);
  393.         if (!csr->dmc_payload) {
  394.                 DRM_ERROR("Memory allocation failed for dmc payload\n");
  395.                 goto out;
  396.         }
  397.  
  398.         dmc_payload = csr->dmc_payload;
  399.         memcpy(dmc_payload, &fw->data[readcount], nbytes);
  400.  
  401.         /* load csr program during system boot, as needed for DC states */
  402.         intel_csr_load_program(dev);
  403.         fw_loaded = true;
  404.  
  405.         DRM_DEBUG_KMS("Finished loading %s\n", dev_priv->csr.fw_path);
  406. out:
  407.         if (fw_loaded)
  408.                 intel_runtime_pm_put(dev_priv);
  409.         else
  410.                 intel_csr_load_status_set(dev_priv, FW_FAILED);
  411.  
  412.         release_firmware(fw);
  413. }
  414.  
  415. /**
  416.  * intel_csr_ucode_init() - initialize the firmware loading.
  417.  * @dev: drm device.
  418.  *
  419.  * This function is called at the time of loading the display driver to read
  420.  * firmware from a .bin file and copied into a internal memory.
  421.  */
  422. void intel_csr_ucode_init(struct drm_device *dev)
  423. {
  424.         struct drm_i915_private *dev_priv = dev->dev_private;
  425.         struct intel_csr *csr = &dev_priv->csr;
  426.         int ret;
  427.  
  428.         if (!HAS_CSR(dev))
  429.                 return;
  430.  
  431.         if (IS_SKYLAKE(dev))
  432.                 csr->fw_path = I915_CSR_SKL;
  433.         else if (IS_BROXTON(dev_priv))
  434.                 csr->fw_path = I915_CSR_BXT;
  435.         else {
  436.                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
  437.                 intel_csr_load_status_set(dev_priv, FW_FAILED);
  438.                 return;
  439.         }
  440. #if 0
  441.         /*
  442.          * Obtain a runtime pm reference, until CSR is loaded,
  443.          * to avoid entering runtime-suspend.
  444.          */
  445.         intel_runtime_pm_get(dev_priv);
  446.  
  447.         /* CSR supported for platform, load firmware */
  448.         ret = request_firmware_nowait(THIS_MODULE, true, csr->fw_path,
  449.                                 &dev_priv->dev->pdev->dev,
  450.                                 GFP_KERNEL, dev_priv,
  451.                                 finish_csr_load);
  452.         if (ret) {
  453.                 i915_firmware_load_error_print(csr->fw_path, ret);
  454.                 intel_csr_load_status_set(dev_priv, FW_FAILED);
  455.         }
  456. #endif
  457. }
  458.  
  459. /**
  460.  * intel_csr_ucode_fini() - unload the CSR firmware.
  461.  * @dev: drm device.
  462.  *
  463.  * Firmmware unloading includes freeing the internal momory and reset the
  464.  * firmware loading status.
  465.  */
  466. void intel_csr_ucode_fini(struct drm_device *dev)
  467. {
  468.         struct drm_i915_private *dev_priv = dev->dev_private;
  469.  
  470.         if (!HAS_CSR(dev))
  471.                 return;
  472.  
  473.         intel_csr_load_status_set(dev_priv, FW_FAILED);
  474.         kfree(dev_priv->csr.dmc_payload);
  475. }
  476.  
  477. void assert_csr_loaded(struct drm_i915_private *dev_priv)
  478. {
  479.         WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
  480.                   "CSR is not loaded.\n");
  481.         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
  482.                   "CSR program storage start is NULL\n");
  483.         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
  484.         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
  485. }
  486.