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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/dmi.h>
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_atomic_helper.h>
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_crtc_helper.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38.  
  39. /* Here's the desired hotplug mode */
  40. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  41.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  42.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  43.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  44.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  45.                            ADPA_CRT_HOTPLUG_ENABLE)
  46.  
  47. struct intel_crt {
  48.         struct intel_encoder base;
  49.         /* DPMS state is stored in the connector, which we need in the
  50.          * encoder's enable/disable callbacks */
  51.         struct intel_connector *connector;
  52.         bool force_hotplug_required;
  53.         i915_reg_t adpa_reg;
  54. };
  55.  
  56. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  57. {
  58.         return container_of(encoder, struct intel_crt, base);
  59. }
  60.  
  61. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  62. {
  63.         return intel_encoder_to_crt(intel_attached_encoder(connector));
  64. }
  65.  
  66. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  67.                                    enum pipe *pipe)
  68. {
  69.         struct drm_device *dev = encoder->base.dev;
  70.         struct drm_i915_private *dev_priv = dev->dev_private;
  71.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  72.         enum intel_display_power_domain power_domain;
  73.         u32 tmp;
  74.         bool ret;
  75.  
  76.         power_domain = intel_display_port_power_domain(encoder);
  77.         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
  78.                 return false;
  79.  
  80.         ret = false;
  81.  
  82.         tmp = I915_READ(crt->adpa_reg);
  83.  
  84.         if (!(tmp & ADPA_DAC_ENABLE))
  85.                 goto out;
  86.  
  87.         if (HAS_PCH_CPT(dev))
  88.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  89.         else
  90.                 *pipe = PORT_TO_PIPE(tmp);
  91.  
  92.         ret = true;
  93. out:
  94.         intel_display_power_put(dev_priv, power_domain);
  95.  
  96.         return ret;
  97. }
  98.  
  99. static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  100. {
  101.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  102.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  103.         u32 tmp, flags = 0;
  104.  
  105.         tmp = I915_READ(crt->adpa_reg);
  106.  
  107.         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  108.                 flags |= DRM_MODE_FLAG_PHSYNC;
  109.         else
  110.                 flags |= DRM_MODE_FLAG_NHSYNC;
  111.  
  112.         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
  113.                 flags |= DRM_MODE_FLAG_PVSYNC;
  114.         else
  115.                 flags |= DRM_MODE_FLAG_NVSYNC;
  116.  
  117.         return flags;
  118. }
  119.  
  120. static void intel_crt_get_config(struct intel_encoder *encoder,
  121.                                  struct intel_crtc_state *pipe_config)
  122. {
  123.         struct drm_device *dev = encoder->base.dev;
  124.         int dotclock;
  125.  
  126.         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
  127.  
  128.         dotclock = pipe_config->port_clock;
  129.  
  130.         if (HAS_PCH_SPLIT(dev))
  131.                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
  132.  
  133.         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
  134. }
  135.  
  136. static void hsw_crt_get_config(struct intel_encoder *encoder,
  137.                                struct intel_crtc_state *pipe_config)
  138. {
  139.         intel_ddi_get_config(encoder, pipe_config);
  140.  
  141.         pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
  142.                                               DRM_MODE_FLAG_NHSYNC |
  143.                                               DRM_MODE_FLAG_PVSYNC |
  144.                                               DRM_MODE_FLAG_NVSYNC);
  145.         pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
  146. }
  147.  
  148. /* Note: The caller is required to filter out dpms modes not supported by the
  149.  * platform. */
  150. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  151. {
  152.         struct drm_device *dev = encoder->base.dev;
  153.         struct drm_i915_private *dev_priv = dev->dev_private;
  154.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  155.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  156.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  157.         u32 adpa;
  158.  
  159.         if (INTEL_INFO(dev)->gen >= 5)
  160.                 adpa = ADPA_HOTPLUG_BITS;
  161.         else
  162.                 adpa = 0;
  163.  
  164.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  165.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  166.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  167.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  168.  
  169.         /* For CPT allow 3 pipe config, for others just use A or B */
  170.         if (HAS_PCH_LPT(dev))
  171.                 ; /* Those bits don't exist here */
  172.         else if (HAS_PCH_CPT(dev))
  173.                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
  174.         else if (crtc->pipe == 0)
  175.                 adpa |= ADPA_PIPE_A_SELECT;
  176.         else
  177.                 adpa |= ADPA_PIPE_B_SELECT;
  178.  
  179.         if (!HAS_PCH_SPLIT(dev))
  180.                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
  181.  
  182.         switch (mode) {
  183.         case DRM_MODE_DPMS_ON:
  184.                 adpa |= ADPA_DAC_ENABLE;
  185.                 break;
  186.         case DRM_MODE_DPMS_STANDBY:
  187.                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  188.                 break;
  189.         case DRM_MODE_DPMS_SUSPEND:
  190.                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  191.                 break;
  192.         case DRM_MODE_DPMS_OFF:
  193.                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  194.                 break;
  195.         }
  196.  
  197.         I915_WRITE(crt->adpa_reg, adpa);
  198. }
  199.  
  200. static void intel_disable_crt(struct intel_encoder *encoder)
  201. {
  202.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  203. }
  204.  
  205. static void pch_disable_crt(struct intel_encoder *encoder)
  206. {
  207. }
  208.  
  209. static void pch_post_disable_crt(struct intel_encoder *encoder)
  210. {
  211.         intel_disable_crt(encoder);
  212. }
  213.  
  214. static void intel_enable_crt(struct intel_encoder *encoder)
  215. {
  216.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  217.  
  218.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  219. }
  220.  
  221. static enum drm_mode_status
  222. intel_crt_mode_valid(struct drm_connector *connector,
  223.                      struct drm_display_mode *mode)
  224. {
  225.         struct drm_device *dev = connector->dev;
  226.  
  227.         int max_clock = 0;
  228.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  229.                 return MODE_NO_DBLESCAN;
  230.  
  231.         if (mode->clock < 25000)
  232.                 return MODE_CLOCK_LOW;
  233.  
  234.         if (IS_GEN2(dev))
  235.                 max_clock = 350000;
  236.         else
  237.                 max_clock = 400000;
  238.         if (mode->clock > max_clock)
  239.                 return MODE_CLOCK_HIGH;
  240.  
  241.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  242.         if (HAS_PCH_LPT(dev) &&
  243.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  244.                 return MODE_CLOCK_HIGH;
  245.  
  246.         return MODE_OK;
  247. }
  248.  
  249. static bool intel_crt_compute_config(struct intel_encoder *encoder,
  250.                                      struct intel_crtc_state *pipe_config)
  251. {
  252.         struct drm_device *dev = encoder->base.dev;
  253.  
  254.         if (HAS_PCH_SPLIT(dev))
  255.                 pipe_config->has_pch_encoder = true;
  256.  
  257.         /* LPT FDI RX only supports 8bpc. */
  258.         if (HAS_PCH_LPT(dev)) {
  259.                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
  260.                         DRM_DEBUG_KMS("LPT only supports 24bpp\n");
  261.                         return false;
  262.                 }
  263.  
  264.                 pipe_config->pipe_bpp = 24;
  265.         }
  266.  
  267.         /* FDI must always be 2.7 GHz */
  268.         if (HAS_DDI(dev)) {
  269.                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
  270.                 pipe_config->port_clock = 135000 * 2;
  271.  
  272.                 pipe_config->dpll_hw_state.wrpll = 0;
  273.                 pipe_config->dpll_hw_state.spll =
  274.                         SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
  275.         }
  276.  
  277.         return true;
  278. }
  279.  
  280. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  281. {
  282.         struct drm_device *dev = connector->dev;
  283.         struct intel_crt *crt = intel_attached_crt(connector);
  284.         struct drm_i915_private *dev_priv = dev->dev_private;
  285.         u32 adpa;
  286.         bool ret;
  287.  
  288.         /* The first time through, trigger an explicit detection cycle */
  289.         if (crt->force_hotplug_required) {
  290.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  291.                 u32 save_adpa;
  292.  
  293.                 crt->force_hotplug_required = 0;
  294.  
  295.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  296.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  297.  
  298.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  299.                 if (turn_off_dac)
  300.                         adpa &= ~ADPA_DAC_ENABLE;
  301.  
  302.                 I915_WRITE(crt->adpa_reg, adpa);
  303.  
  304.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  305.                              1000))
  306.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  307.  
  308.                 if (turn_off_dac) {
  309.                         I915_WRITE(crt->adpa_reg, save_adpa);
  310.                         POSTING_READ(crt->adpa_reg);
  311.                 }
  312.         }
  313.  
  314.         /* Check the status to see if both blue and green are on now */
  315.         adpa = I915_READ(crt->adpa_reg);
  316.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  317.                 ret = true;
  318.         else
  319.                 ret = false;
  320.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  321.  
  322.         return ret;
  323. }
  324.  
  325. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  326. {
  327.         struct drm_device *dev = connector->dev;
  328.         struct intel_crt *crt = intel_attached_crt(connector);
  329.         struct drm_i915_private *dev_priv = dev->dev_private;
  330.         u32 adpa;
  331.         bool ret;
  332.         u32 save_adpa;
  333.  
  334.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  335.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  336.  
  337.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  338.  
  339.         I915_WRITE(crt->adpa_reg, adpa);
  340.  
  341.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  342.                      1000)) {
  343.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  344.                 I915_WRITE(crt->adpa_reg, save_adpa);
  345.         }
  346.  
  347.         /* Check the status to see if both blue and green are on now */
  348.         adpa = I915_READ(crt->adpa_reg);
  349.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  350.                 ret = true;
  351.         else
  352.                 ret = false;
  353.  
  354.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  355.  
  356.         return ret;
  357. }
  358.  
  359. /**
  360.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  361.  *
  362.  * Not for i915G/i915GM
  363.  *
  364.  * \return true if CRT is connected.
  365.  * \return false if CRT is disconnected.
  366.  */
  367. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  368. {
  369.         struct drm_device *dev = connector->dev;
  370.         struct drm_i915_private *dev_priv = dev->dev_private;
  371.         u32 stat;
  372.         bool ret = false;
  373.         int i, tries = 0;
  374.  
  375.         if (HAS_PCH_SPLIT(dev))
  376.                 return intel_ironlake_crt_detect_hotplug(connector);
  377.  
  378.         if (IS_VALLEYVIEW(dev))
  379.                 return valleyview_crt_detect_hotplug(connector);
  380.  
  381.         /*
  382.          * On 4 series desktop, CRT detect sequence need to be done twice
  383.          * to get a reliable result.
  384.          */
  385.  
  386.         if (IS_G4X(dev) && !IS_GM45(dev))
  387.                 tries = 2;
  388.         else
  389.                 tries = 1;
  390.  
  391.         for (i = 0; i < tries ; i++) {
  392.                 /* turn on the FORCE_DETECT */
  393.                 i915_hotplug_interrupt_update(dev_priv,
  394.                                               CRT_HOTPLUG_FORCE_DETECT,
  395.                                               CRT_HOTPLUG_FORCE_DETECT);
  396.                 /* wait for FORCE_DETECT to go off */
  397.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  398.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  399.                              1000))
  400.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  401.         }
  402.  
  403.         stat = I915_READ(PORT_HOTPLUG_STAT);
  404.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  405.                 ret = true;
  406.  
  407.         /* clear the interrupt we just generated, if any */
  408.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  409.  
  410.         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
  411.  
  412.         return ret;
  413. }
  414.  
  415. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  416.                                 struct i2c_adapter *i2c)
  417. {
  418.         struct edid *edid;
  419.  
  420.         edid = drm_get_edid(connector, i2c);
  421.  
  422.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  423.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  424.                 intel_gmbus_force_bit(i2c, true);
  425.                 edid = drm_get_edid(connector, i2c);
  426.                 intel_gmbus_force_bit(i2c, false);
  427.         }
  428.  
  429.         return edid;
  430. }
  431.  
  432. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  433. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  434.                                 struct i2c_adapter *adapter)
  435. {
  436.         struct edid *edid;
  437.         int ret;
  438.  
  439.         edid = intel_crt_get_edid(connector, adapter);
  440.         if (!edid)
  441.                 return 0;
  442.  
  443.         ret = intel_connector_update_modes(connector, edid);
  444.         kfree(edid);
  445.  
  446.         return ret;
  447. }
  448.  
  449. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  450. {
  451.         struct intel_crt *crt = intel_attached_crt(connector);
  452.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  453.         struct edid *edid;
  454.         struct i2c_adapter *i2c;
  455.  
  456.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  457.  
  458.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  459.         edid = intel_crt_get_edid(connector, i2c);
  460.  
  461.         if (edid) {
  462.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  463.  
  464.                 /*
  465.                  * This may be a DVI-I connector with a shared DDC
  466.                  * link between analog and digital outputs, so we
  467.                  * have to check the EDID input spec of the attached device.
  468.                  */
  469.                 if (!is_digital) {
  470.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  471.                         return true;
  472.                 }
  473.  
  474.                         DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  475.         } else {
  476.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  477.         }
  478.  
  479.         kfree(edid);
  480.  
  481.         return false;
  482. }
  483.  
  484. static enum drm_connector_status
  485. intel_crt_load_detect(struct intel_crt *crt)
  486. {
  487.         struct drm_device *dev = crt->base.base.dev;
  488.         struct drm_i915_private *dev_priv = dev->dev_private;
  489.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  490.         uint32_t save_bclrpat;
  491.         uint32_t save_vtotal;
  492.         uint32_t vtotal, vactive;
  493.         uint32_t vsample;
  494.         uint32_t vblank, vblank_start, vblank_end;
  495.         uint32_t dsl;
  496.         i915_reg_t bclrpat_reg, vtotal_reg,
  497.                 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg;
  498.         uint8_t st00;
  499.         enum drm_connector_status status;
  500.  
  501.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  502.  
  503.         bclrpat_reg = BCLRPAT(pipe);
  504.         vtotal_reg = VTOTAL(pipe);
  505.         vblank_reg = VBLANK(pipe);
  506.         vsync_reg = VSYNC(pipe);
  507.         pipeconf_reg = PIPECONF(pipe);
  508.         pipe_dsl_reg = PIPEDSL(pipe);
  509.  
  510.         save_bclrpat = I915_READ(bclrpat_reg);
  511.         save_vtotal = I915_READ(vtotal_reg);
  512.         vblank = I915_READ(vblank_reg);
  513.  
  514.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  515.         vactive = (save_vtotal & 0x7ff) + 1;
  516.  
  517.         vblank_start = (vblank & 0xfff) + 1;
  518.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  519.  
  520.         /* Set the border color to purple. */
  521.         I915_WRITE(bclrpat_reg, 0x500050);
  522.  
  523.         if (!IS_GEN2(dev)) {
  524.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  525.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  526.                 POSTING_READ(pipeconf_reg);
  527.                 /* Wait for next Vblank to substitue
  528.                  * border color for Color info */
  529.                 intel_wait_for_vblank(dev, pipe);
  530.                 st00 = I915_READ8(_VGA_MSR_WRITE);
  531.                 status = ((st00 & (1 << 4)) != 0) ?
  532.                         connector_status_connected :
  533.                         connector_status_disconnected;
  534.  
  535.                 I915_WRITE(pipeconf_reg, pipeconf);
  536.         } else {
  537.                 bool restore_vblank = false;
  538.                 int count, detect;
  539.  
  540.                 /*
  541.                 * If there isn't any border, add some.
  542.                 * Yes, this will flicker
  543.                 */
  544.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  545.                         uint32_t vsync = I915_READ(vsync_reg);
  546.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  547.  
  548.                         vblank_start = vsync_start;
  549.                         I915_WRITE(vblank_reg,
  550.                                    (vblank_start - 1) |
  551.                                    ((vblank_end - 1) << 16));
  552.                         restore_vblank = true;
  553.                 }
  554.                 /* sample in the vertical border, selecting the larger one */
  555.                 if (vblank_start - vactive >= vtotal - vblank_end)
  556.                         vsample = (vblank_start + vactive) >> 1;
  557.                 else
  558.                         vsample = (vtotal + vblank_end) >> 1;
  559.  
  560.                 /*
  561.                  * Wait for the border to be displayed
  562.                  */
  563.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  564.                         ;
  565.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  566.                         ;
  567.                 /*
  568.                  * Watch ST00 for an entire scanline
  569.                  */
  570.                 detect = 0;
  571.                 count = 0;
  572.                 do {
  573.                         count++;
  574.                         /* Read the ST00 VGA status register */
  575.                         st00 = I915_READ8(_VGA_MSR_WRITE);
  576.                         if (st00 & (1 << 4))
  577.                                 detect++;
  578.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  579.  
  580.                 /* restore vblank if necessary */
  581.                 if (restore_vblank)
  582.                         I915_WRITE(vblank_reg, vblank);
  583.                 /*
  584.                  * If more than 3/4 of the scanline detected a monitor,
  585.                  * then it is assumed to be present. This works even on i830,
  586.                  * where there isn't any way to force the border color across
  587.                  * the screen
  588.                  */
  589.                 status = detect * 4 > count * 3 ?
  590.                          connector_status_connected :
  591.                          connector_status_disconnected;
  592.         }
  593.  
  594.         /* Restore previous settings */
  595.         I915_WRITE(bclrpat_reg, save_bclrpat);
  596.  
  597.         return status;
  598. }
  599.  
  600. static enum drm_connector_status
  601. intel_crt_detect(struct drm_connector *connector, bool force)
  602. {
  603.         struct drm_device *dev = connector->dev;
  604.         struct drm_i915_private *dev_priv = dev->dev_private;
  605.         struct intel_crt *crt = intel_attached_crt(connector);
  606.         struct intel_encoder *intel_encoder = &crt->base;
  607.         enum intel_display_power_domain power_domain;
  608.         enum drm_connector_status status;
  609.         struct intel_load_detect_pipe tmp;
  610.         struct drm_modeset_acquire_ctx ctx;
  611.  
  612.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
  613.                       connector->base.id, connector->name,
  614.                       force);
  615.  
  616.         power_domain = intel_display_port_power_domain(intel_encoder);
  617.         intel_display_power_get(dev_priv, power_domain);
  618.  
  619.         if (I915_HAS_HOTPLUG(dev)) {
  620.                 /* We can not rely on the HPD pin always being correctly wired
  621.                  * up, for example many KVM do not pass it through, and so
  622.                  * only trust an assertion that the monitor is connected.
  623.                  */
  624.                 if (intel_crt_detect_hotplug(connector)) {
  625.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  626.                         status = connector_status_connected;
  627.                         goto out;
  628.                 } else
  629.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  630.         }
  631.  
  632.         if (intel_crt_detect_ddc(connector)) {
  633.                 status = connector_status_connected;
  634.                 goto out;
  635.         }
  636.  
  637.         /* Load detection is broken on HPD capable machines. Whoever wants a
  638.          * broken monitor (without edid) to work behind a broken kvm (that fails
  639.          * to have the right resistors for HP detection) needs to fix this up.
  640.          * For now just bail out. */
  641.         if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) {
  642.                 status = connector_status_disconnected;
  643.                 goto out;
  644.         }
  645.  
  646.         if (!force) {
  647.                 status = connector->status;
  648.                 goto out;
  649.         }
  650.  
  651.         drm_modeset_acquire_init(&ctx, 0);
  652.  
  653.         /* for pre-945g platforms use load detect */
  654.         if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) {
  655.                 if (intel_crt_detect_ddc(connector))
  656.                         status = connector_status_connected;
  657.                 else if (INTEL_INFO(dev)->gen < 4)
  658.                         status = intel_crt_load_detect(crt);
  659.                 else
  660.                         status = connector_status_unknown;
  661.                 intel_release_load_detect_pipe(connector, &tmp, &ctx);
  662.         } else
  663.                 status = connector_status_unknown;
  664.  
  665.         drm_modeset_drop_locks(&ctx);
  666.         drm_modeset_acquire_fini(&ctx);
  667.  
  668. out:
  669.         intel_display_power_put(dev_priv, power_domain);
  670.         return status;
  671. }
  672.  
  673. static void intel_crt_destroy(struct drm_connector *connector)
  674. {
  675.         drm_connector_cleanup(connector);
  676.         kfree(connector);
  677. }
  678.  
  679. static int intel_crt_get_modes(struct drm_connector *connector)
  680. {
  681.         struct drm_device *dev = connector->dev;
  682.         struct drm_i915_private *dev_priv = dev->dev_private;
  683.         struct intel_crt *crt = intel_attached_crt(connector);
  684.         struct intel_encoder *intel_encoder = &crt->base;
  685.         enum intel_display_power_domain power_domain;
  686.         int ret;
  687.         struct i2c_adapter *i2c;
  688.  
  689.         power_domain = intel_display_port_power_domain(intel_encoder);
  690.         intel_display_power_get(dev_priv, power_domain);
  691.  
  692.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  693.         ret = intel_crt_ddc_get_modes(connector, i2c);
  694.         if (ret || !IS_G4X(dev))
  695.                 goto out;
  696.  
  697.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  698.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
  699.         ret = intel_crt_ddc_get_modes(connector, i2c);
  700.  
  701. out:
  702.         intel_display_power_put(dev_priv, power_domain);
  703.  
  704.         return ret;
  705. }
  706.  
  707. static int intel_crt_set_property(struct drm_connector *connector,
  708.                                   struct drm_property *property,
  709.                                   uint64_t value)
  710. {
  711.         return 0;
  712. }
  713.  
  714. static void intel_crt_reset(struct drm_connector *connector)
  715. {
  716.         struct drm_device *dev = connector->dev;
  717.         struct drm_i915_private *dev_priv = dev->dev_private;
  718.         struct intel_crt *crt = intel_attached_crt(connector);
  719.  
  720.         if (INTEL_INFO(dev)->gen >= 5) {
  721.                 u32 adpa;
  722.  
  723.                 adpa = I915_READ(crt->adpa_reg);
  724.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  725.                 adpa |= ADPA_HOTPLUG_BITS;
  726.                 I915_WRITE(crt->adpa_reg, adpa);
  727.                 POSTING_READ(crt->adpa_reg);
  728.  
  729.                 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa);
  730.                 crt->force_hotplug_required = 1;
  731.         }
  732.  
  733. }
  734.  
  735. /*
  736.  * Routines for controlling stuff on the analog port
  737.  */
  738.  
  739. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  740.         .reset = intel_crt_reset,
  741.         .dpms = drm_atomic_helper_connector_dpms,
  742.         .detect = intel_crt_detect,
  743.         .fill_modes = drm_helper_probe_single_connector_modes,
  744.         .destroy = intel_crt_destroy,
  745.         .set_property = intel_crt_set_property,
  746.         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  747.         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  748.         .atomic_get_property = intel_connector_atomic_get_property,
  749. };
  750.  
  751. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  752.         .mode_valid = intel_crt_mode_valid,
  753.         .get_modes = intel_crt_get_modes,
  754.         .best_encoder = intel_best_encoder,
  755. };
  756.  
  757. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  758.         .destroy = intel_encoder_destroy,
  759. };
  760.  
  761. static int intel_no_crt_dmi_callback(const struct dmi_system_id *id)
  762. {
  763.         DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
  764.         return 1;
  765. }
  766.  
  767. static const struct dmi_system_id intel_no_crt[] = {
  768.         {
  769.                 .callback = intel_no_crt_dmi_callback,
  770.                 .ident = "ACER ZGB",
  771.                 .matches = {
  772.                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
  773.                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
  774.                 },
  775.         },
  776.         {
  777.                 .callback = intel_no_crt_dmi_callback,
  778.                 .ident = "DELL XPS 8700",
  779.                 .matches = {
  780.                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  781.                         DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"),
  782.                 },
  783.         },
  784.         { }
  785. };
  786.  
  787. void intel_crt_init(struct drm_device *dev)
  788. {
  789.         struct drm_connector *connector;
  790.         struct intel_crt *crt;
  791.         struct intel_connector *intel_connector;
  792.         struct drm_i915_private *dev_priv = dev->dev_private;
  793.         i915_reg_t adpa_reg;
  794.         u32 adpa;
  795.  
  796.         /* Skip machines without VGA that falsely report hotplug events */
  797.         if (dmi_check_system(intel_no_crt))
  798.                 return;
  799.  
  800.         if (HAS_PCH_SPLIT(dev))
  801.                 adpa_reg = PCH_ADPA;
  802.         else if (IS_VALLEYVIEW(dev))
  803.                 adpa_reg = VLV_ADPA;
  804.         else
  805.                 adpa_reg = ADPA;
  806.  
  807.         adpa = I915_READ(adpa_reg);
  808.         if ((adpa & ADPA_DAC_ENABLE) == 0) {
  809.                 /*
  810.                  * On some machines (some IVB at least) CRT can be
  811.                  * fused off, but there's no known fuse bit to
  812.                  * indicate that. On these machine the ADPA register
  813.                  * works normally, except the DAC enable bit won't
  814.                  * take. So the only way to tell is attempt to enable
  815.                  * it and see what happens.
  816.                  */
  817.                 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE |
  818.                            ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  819.                 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0)
  820.                         return;
  821.                 I915_WRITE(adpa_reg, adpa);
  822.         }
  823.  
  824.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  825.         if (!crt)
  826.                 return;
  827.  
  828.         intel_connector = intel_connector_alloc();
  829.         if (!intel_connector) {
  830.                 kfree(crt);
  831.                 return;
  832.         }
  833.  
  834.         connector = &intel_connector->base;
  835.         crt->connector = intel_connector;
  836.         drm_connector_init(dev, &intel_connector->base,
  837.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  838.  
  839.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  840.                          DRM_MODE_ENCODER_DAC, NULL);
  841.  
  842.         intel_connector_attach_encoder(intel_connector, &crt->base);
  843.  
  844.         crt->base.type = INTEL_OUTPUT_ANALOG;
  845.         crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI);
  846.         if (IS_I830(dev))
  847.                 crt->base.crtc_mask = (1 << 0);
  848.         else
  849.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  850.  
  851.         if (IS_GEN2(dev))
  852.                 connector->interlace_allowed = 0;
  853.         else
  854.                 connector->interlace_allowed = 1;
  855.         connector->doublescan_allowed = 0;
  856.  
  857.         crt->adpa_reg = adpa_reg;
  858.  
  859.         crt->base.compute_config = intel_crt_compute_config;
  860.         if (HAS_PCH_SPLIT(dev)) {
  861.                 crt->base.disable = pch_disable_crt;
  862.                 crt->base.post_disable = pch_post_disable_crt;
  863.         } else {
  864.                 crt->base.disable = intel_disable_crt;
  865.         }
  866.         crt->base.enable = intel_enable_crt;
  867.         if (I915_HAS_HOTPLUG(dev))
  868.                 crt->base.hpd_pin = HPD_CRT;
  869.         if (HAS_DDI(dev)) {
  870.                 crt->base.get_config = hsw_crt_get_config;
  871.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  872.         } else {
  873.                 crt->base.get_config = intel_crt_get_config;
  874.                 crt->base.get_hw_state = intel_crt_get_hw_state;
  875.         }
  876.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  877.         intel_connector->unregister = intel_connector_unregister;
  878.  
  879.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  880.  
  881.         drm_connector_register(connector);
  882.  
  883.         if (!I915_HAS_HOTPLUG(dev))
  884.                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  885.  
  886.         /*
  887.          * Configure the automatic hotplug detection stuff
  888.          */
  889.         crt->force_hotplug_required = 0;
  890.  
  891.         /*
  892.          * TODO: find a proper way to discover whether we need to set the the
  893.          * polarity and link reversal bits or not, instead of relying on the
  894.          * BIOS.
  895.          */
  896.         if (HAS_PCH_LPT(dev)) {
  897.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  898.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  899.  
  900.                 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config;
  901.         }
  902.  
  903.         intel_crt_reset(connector);
  904. }
  905.