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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43.                            ADPA_CRT_HOTPLUG_ENABLE)
  44.  
  45. struct intel_crt {
  46.         struct intel_encoder base;
  47.         /* DPMS state is stored in the connector, which we need in the
  48.          * encoder's enable/disable callbacks */
  49.         struct intel_connector *connector;
  50.         bool force_hotplug_required;
  51.         u32 adpa_reg;
  52. };
  53.  
  54. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  55. {
  56.         return container_of(encoder, struct intel_crt, base);
  57. }
  58.  
  59. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  60. {
  61.         return intel_encoder_to_crt(intel_attached_encoder(connector));
  62. }
  63.  
  64. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  65.                                    enum pipe *pipe)
  66. {
  67.         struct drm_device *dev = encoder->base.dev;
  68.         struct drm_i915_private *dev_priv = dev->dev_private;
  69.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  70.         u32 tmp;
  71.  
  72.         tmp = I915_READ(crt->adpa_reg);
  73.  
  74.         if (!(tmp & ADPA_DAC_ENABLE))
  75.                 return false;
  76.  
  77.         if (HAS_PCH_CPT(dev))
  78.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  79.         else
  80.                 *pipe = PORT_TO_PIPE(tmp);
  81.  
  82.         return true;
  83. }
  84.  
  85. static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
  86. {
  87.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  88.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  89.         u32 tmp, flags = 0;
  90.  
  91.         tmp = I915_READ(crt->adpa_reg);
  92.  
  93.         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  94.                 flags |= DRM_MODE_FLAG_PHSYNC;
  95.         else
  96.                 flags |= DRM_MODE_FLAG_NHSYNC;
  97.  
  98.         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
  99.                 flags |= DRM_MODE_FLAG_PVSYNC;
  100.         else
  101.                 flags |= DRM_MODE_FLAG_NVSYNC;
  102.  
  103.         return flags;
  104. }
  105.  
  106. static void intel_crt_get_config(struct intel_encoder *encoder,
  107.                                  struct intel_crtc_config *pipe_config)
  108. {
  109.         struct drm_device *dev = encoder->base.dev;
  110.         int dotclock;
  111.  
  112.         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
  113.  
  114.         dotclock = pipe_config->port_clock;
  115.  
  116.         if (HAS_PCH_SPLIT(dev))
  117.                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
  118.  
  119.         pipe_config->adjusted_mode.crtc_clock = dotclock;
  120. }
  121.  
  122. static void hsw_crt_get_config(struct intel_encoder *encoder,
  123.                                struct intel_crtc_config *pipe_config)
  124. {
  125.         intel_ddi_get_config(encoder, pipe_config);
  126.  
  127.         pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
  128.                                               DRM_MODE_FLAG_NHSYNC |
  129.                                               DRM_MODE_FLAG_PVSYNC |
  130.                                               DRM_MODE_FLAG_NVSYNC);
  131.         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
  132. }
  133.  
  134. /* Note: The caller is required to filter out dpms modes not supported by the
  135.  * platform. */
  136. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  137. {
  138.         struct drm_device *dev = encoder->base.dev;
  139.         struct drm_i915_private *dev_priv = dev->dev_private;
  140.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  141.         u32 temp;
  142.  
  143.         temp = I915_READ(crt->adpa_reg);
  144.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  145.         temp &= ~ADPA_DAC_ENABLE;
  146.  
  147.         switch (mode) {
  148.         case DRM_MODE_DPMS_ON:
  149.                 temp |= ADPA_DAC_ENABLE;
  150.                 break;
  151.         case DRM_MODE_DPMS_STANDBY:
  152.                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  153.                 break;
  154.         case DRM_MODE_DPMS_SUSPEND:
  155.                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  156.                 break;
  157.         case DRM_MODE_DPMS_OFF:
  158.                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  159.                 break;
  160.         }
  161.  
  162.         I915_WRITE(crt->adpa_reg, temp);
  163. }
  164.  
  165. static void intel_disable_crt(struct intel_encoder *encoder)
  166. {
  167.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  168. }
  169.  
  170. static void intel_enable_crt(struct intel_encoder *encoder)
  171. {
  172.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  173.  
  174.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  175. }
  176.  
  177. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  178. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  179. {
  180.         struct drm_device *dev = connector->dev;
  181.         struct intel_encoder *encoder = intel_attached_encoder(connector);
  182.         struct drm_crtc *crtc;
  183.         int old_dpms;
  184.  
  185.         /* PCH platforms and VLV only support on/off. */
  186.         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  187.                 mode = DRM_MODE_DPMS_OFF;
  188.  
  189.         if (mode == connector->dpms)
  190.                 return;
  191.  
  192.         old_dpms = connector->dpms;
  193.         connector->dpms = mode;
  194.  
  195.         /* Only need to change hw state when actually enabled */
  196.         crtc = encoder->base.crtc;
  197.         if (!crtc) {
  198.                 encoder->connectors_active = false;
  199.                 return;
  200.         }
  201.  
  202.         /* We need the pipe to run for anything but OFF. */
  203.         if (mode == DRM_MODE_DPMS_OFF)
  204.                 encoder->connectors_active = false;
  205.         else
  206.                 encoder->connectors_active = true;
  207.  
  208.         /* We call connector dpms manually below in case pipe dpms doesn't
  209.          * change due to cloning. */
  210.         if (mode < old_dpms) {
  211.                 /* From off to on, enable the pipe first. */
  212.                 intel_crtc_update_dpms(crtc);
  213.  
  214.                 intel_crt_set_dpms(encoder, mode);
  215.         } else {
  216.                 intel_crt_set_dpms(encoder, mode);
  217.  
  218.                 intel_crtc_update_dpms(crtc);
  219.         }
  220.  
  221.         intel_modeset_check_state(connector->dev);
  222. }
  223.  
  224. static enum drm_mode_status
  225. intel_crt_mode_valid(struct drm_connector *connector,
  226.                                 struct drm_display_mode *mode)
  227. {
  228.         struct drm_device *dev = connector->dev;
  229.  
  230.         int max_clock = 0;
  231.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  232.                 return MODE_NO_DBLESCAN;
  233.  
  234.         if (mode->clock < 25000)
  235.                 return MODE_CLOCK_LOW;
  236.  
  237.         if (IS_GEN2(dev))
  238.                 max_clock = 350000;
  239.         else
  240.                 max_clock = 400000;
  241.         if (mode->clock > max_clock)
  242.                 return MODE_CLOCK_HIGH;
  243.  
  244.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  245.         if (HAS_PCH_LPT(dev) &&
  246.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  247.                 return MODE_CLOCK_HIGH;
  248.  
  249.         return MODE_OK;
  250. }
  251.  
  252. static bool intel_crt_compute_config(struct intel_encoder *encoder,
  253.                                      struct intel_crtc_config *pipe_config)
  254. {
  255.         struct drm_device *dev = encoder->base.dev;
  256.  
  257.         if (HAS_PCH_SPLIT(dev))
  258.                 pipe_config->has_pch_encoder = true;
  259.  
  260.         /* LPT FDI RX only supports 8bpc. */
  261.         if (HAS_PCH_LPT(dev))
  262.                 pipe_config->pipe_bpp = 24;
  263.  
  264.         return true;
  265. }
  266.  
  267. static void intel_crt_mode_set(struct intel_encoder *encoder)
  268. {
  269.  
  270.         struct drm_device *dev = encoder->base.dev;
  271.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  272.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  273.         struct drm_i915_private *dev_priv = dev->dev_private;
  274.         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  275.         u32 adpa;
  276.  
  277.         if (INTEL_INFO(dev)->gen >= 5)
  278.         adpa = ADPA_HOTPLUG_BITS;
  279.         else
  280.                 adpa = 0;
  281.  
  282.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  283.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  284.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  285.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  286.  
  287.         /* For CPT allow 3 pipe config, for others just use A or B */
  288.         if (HAS_PCH_LPT(dev))
  289.                 ; /* Those bits don't exist here */
  290.         else if (HAS_PCH_CPT(dev))
  291.                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
  292.         else if (crtc->pipe == 0)
  293.                         adpa |= ADPA_PIPE_A_SELECT;
  294.                 else
  295.                         adpa |= ADPA_PIPE_B_SELECT;
  296.  
  297.         if (!HAS_PCH_SPLIT(dev))
  298.                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
  299.  
  300.         I915_WRITE(crt->adpa_reg, adpa);
  301. }
  302.  
  303. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  304. {
  305.         struct drm_device *dev = connector->dev;
  306.         struct intel_crt *crt = intel_attached_crt(connector);
  307.         struct drm_i915_private *dev_priv = dev->dev_private;
  308.         u32 adpa;
  309.         bool ret;
  310.  
  311.         /* The first time through, trigger an explicit detection cycle */
  312.         if (crt->force_hotplug_required) {
  313.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  314.                 u32 save_adpa;
  315.  
  316.                 crt->force_hotplug_required = 0;
  317.  
  318.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  319.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  320.  
  321.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  322.                 if (turn_off_dac)
  323.                         adpa &= ~ADPA_DAC_ENABLE;
  324.  
  325.                 I915_WRITE(crt->adpa_reg, adpa);
  326.  
  327.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  328.                              1000))
  329.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  330.  
  331.                 if (turn_off_dac) {
  332.                         I915_WRITE(crt->adpa_reg, save_adpa);
  333.                         POSTING_READ(crt->adpa_reg);
  334.                 }
  335.         }
  336.  
  337.         /* Check the status to see if both blue and green are on now */
  338.         adpa = I915_READ(crt->adpa_reg);
  339.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  340.                 ret = true;
  341.         else
  342.                 ret = false;
  343.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  344.  
  345.         return ret;
  346. }
  347.  
  348. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  349. {
  350.         struct drm_device *dev = connector->dev;
  351.         struct intel_crt *crt = intel_attached_crt(connector);
  352.         struct drm_i915_private *dev_priv = dev->dev_private;
  353.         u32 adpa;
  354.         bool ret;
  355.         u32 save_adpa;
  356.  
  357.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  358.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  359.  
  360.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  361.  
  362.         I915_WRITE(crt->adpa_reg, adpa);
  363.  
  364.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  365.                      1000)) {
  366.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  367.                 I915_WRITE(crt->adpa_reg, save_adpa);
  368.         }
  369.  
  370.         /* Check the status to see if both blue and green are on now */
  371.         adpa = I915_READ(crt->adpa_reg);
  372.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  373.                 ret = true;
  374.         else
  375.                 ret = false;
  376.  
  377.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  378.  
  379.         return ret;
  380. }
  381.  
  382. /**
  383.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  384.  *
  385.  * Not for i915G/i915GM
  386.  *
  387.  * \return true if CRT is connected.
  388.  * \return false if CRT is disconnected.
  389.  */
  390. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  391. {
  392.         struct drm_device *dev = connector->dev;
  393.         struct drm_i915_private *dev_priv = dev->dev_private;
  394.         u32 hotplug_en, orig, stat;
  395.         bool ret = false;
  396.         int i, tries = 0;
  397.  
  398.         if (HAS_PCH_SPLIT(dev))
  399.                 return intel_ironlake_crt_detect_hotplug(connector);
  400.  
  401.         if (IS_VALLEYVIEW(dev))
  402.                 return valleyview_crt_detect_hotplug(connector);
  403.  
  404.         /*
  405.          * On 4 series desktop, CRT detect sequence need to be done twice
  406.          * to get a reliable result.
  407.          */
  408.  
  409.         if (IS_G4X(dev) && !IS_GM45(dev))
  410.                 tries = 2;
  411.         else
  412.                 tries = 1;
  413.         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  414.         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  415.  
  416.         for (i = 0; i < tries ; i++) {
  417.                 /* turn on the FORCE_DETECT */
  418.                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  419.                 /* wait for FORCE_DETECT to go off */
  420.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  421.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  422.                              1000))
  423.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  424.         }
  425.  
  426.         stat = I915_READ(PORT_HOTPLUG_STAT);
  427.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  428.                 ret = true;
  429.  
  430.         /* clear the interrupt we just generated, if any */
  431.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  432.  
  433.         /* and put the bits back */
  434.         I915_WRITE(PORT_HOTPLUG_EN, orig);
  435.  
  436.         return ret;
  437. }
  438.  
  439. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  440.                                 struct i2c_adapter *i2c)
  441. {
  442.         struct edid *edid;
  443.  
  444.         edid = drm_get_edid(connector, i2c);
  445.  
  446.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  447.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  448.                 intel_gmbus_force_bit(i2c, true);
  449.                 edid = drm_get_edid(connector, i2c);
  450.                 intel_gmbus_force_bit(i2c, false);
  451.         }
  452.  
  453.         return edid;
  454. }
  455.  
  456. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  457. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  458.                                 struct i2c_adapter *adapter)
  459. {
  460.         struct edid *edid;
  461.         int ret;
  462.  
  463.         edid = intel_crt_get_edid(connector, adapter);
  464.         if (!edid)
  465.                 return 0;
  466.  
  467.         ret = intel_connector_update_modes(connector, edid);
  468.         kfree(edid);
  469.  
  470.         return ret;
  471. }
  472.  
  473. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  474. {
  475.         struct intel_crt *crt = intel_attached_crt(connector);
  476.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  477.         struct edid *edid;
  478.         struct i2c_adapter *i2c;
  479.  
  480.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  481.  
  482.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  483.         edid = intel_crt_get_edid(connector, i2c);
  484.  
  485.         if (edid) {
  486.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  487.  
  488.                 /*
  489.                  * This may be a DVI-I connector with a shared DDC
  490.                  * link between analog and digital outputs, so we
  491.                  * have to check the EDID input spec of the attached device.
  492.                  */
  493.                 if (!is_digital) {
  494.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  495.                         return true;
  496.                 }
  497.  
  498.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  499.                 } else {
  500.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  501.                 }
  502.  
  503.         kfree(edid);
  504.  
  505.         return false;
  506. }
  507.  
  508. static enum drm_connector_status
  509. intel_crt_load_detect(struct intel_crt *crt)
  510. {
  511.         struct drm_device *dev = crt->base.base.dev;
  512.         struct drm_i915_private *dev_priv = dev->dev_private;
  513.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  514.         uint32_t save_bclrpat;
  515.         uint32_t save_vtotal;
  516.         uint32_t vtotal, vactive;
  517.         uint32_t vsample;
  518.         uint32_t vblank, vblank_start, vblank_end;
  519.         uint32_t dsl;
  520.         uint32_t bclrpat_reg;
  521.         uint32_t vtotal_reg;
  522.         uint32_t vblank_reg;
  523.         uint32_t vsync_reg;
  524.         uint32_t pipeconf_reg;
  525.         uint32_t pipe_dsl_reg;
  526.         uint8_t st00;
  527.         enum drm_connector_status status;
  528.  
  529.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  530.  
  531.         bclrpat_reg = BCLRPAT(pipe);
  532.         vtotal_reg = VTOTAL(pipe);
  533.         vblank_reg = VBLANK(pipe);
  534.         vsync_reg = VSYNC(pipe);
  535.         pipeconf_reg = PIPECONF(pipe);
  536.         pipe_dsl_reg = PIPEDSL(pipe);
  537.  
  538.         save_bclrpat = I915_READ(bclrpat_reg);
  539.         save_vtotal = I915_READ(vtotal_reg);
  540.         vblank = I915_READ(vblank_reg);
  541.  
  542.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  543.         vactive = (save_vtotal & 0x7ff) + 1;
  544.  
  545.         vblank_start = (vblank & 0xfff) + 1;
  546.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  547.  
  548.         /* Set the border color to purple. */
  549.         I915_WRITE(bclrpat_reg, 0x500050);
  550.  
  551.         if (!IS_GEN2(dev)) {
  552.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  553.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  554.                 POSTING_READ(pipeconf_reg);
  555.                 /* Wait for next Vblank to substitue
  556.                  * border color for Color info */
  557.                 intel_wait_for_vblank(dev, pipe);
  558.                 st00 = I915_READ8(VGA_MSR_WRITE);
  559.                 status = ((st00 & (1 << 4)) != 0) ?
  560.                         connector_status_connected :
  561.                         connector_status_disconnected;
  562.  
  563.                 I915_WRITE(pipeconf_reg, pipeconf);
  564.         } else {
  565.                 bool restore_vblank = false;
  566.                 int count, detect;
  567.  
  568.                 /*
  569.                 * If there isn't any border, add some.
  570.                 * Yes, this will flicker
  571.                 */
  572.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  573.                         uint32_t vsync = I915_READ(vsync_reg);
  574.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  575.  
  576.                         vblank_start = vsync_start;
  577.                         I915_WRITE(vblank_reg,
  578.                                    (vblank_start - 1) |
  579.                                    ((vblank_end - 1) << 16));
  580.                         restore_vblank = true;
  581.                 }
  582.                 /* sample in the vertical border, selecting the larger one */
  583.                 if (vblank_start - vactive >= vtotal - vblank_end)
  584.                         vsample = (vblank_start + vactive) >> 1;
  585.                 else
  586.                         vsample = (vtotal + vblank_end) >> 1;
  587.  
  588.                 /*
  589.                  * Wait for the border to be displayed
  590.                  */
  591.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  592.                         ;
  593.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  594.                         ;
  595.                 /*
  596.                  * Watch ST00 for an entire scanline
  597.                  */
  598.                 detect = 0;
  599.                 count = 0;
  600.                 do {
  601.                         count++;
  602.                         /* Read the ST00 VGA status register */
  603.                         st00 = I915_READ8(VGA_MSR_WRITE);
  604.                         if (st00 & (1 << 4))
  605.                                 detect++;
  606.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  607.  
  608.                 /* restore vblank if necessary */
  609.                 if (restore_vblank)
  610.                         I915_WRITE(vblank_reg, vblank);
  611.                 /*
  612.                  * If more than 3/4 of the scanline detected a monitor,
  613.                  * then it is assumed to be present. This works even on i830,
  614.                  * where there isn't any way to force the border color across
  615.                  * the screen
  616.                  */
  617.                 status = detect * 4 > count * 3 ?
  618.                          connector_status_connected :
  619.                          connector_status_disconnected;
  620.         }
  621.  
  622.         /* Restore previous settings */
  623.         I915_WRITE(bclrpat_reg, save_bclrpat);
  624.  
  625.         return status;
  626. }
  627.  
  628. static enum drm_connector_status
  629. intel_crt_detect(struct drm_connector *connector, bool force)
  630. {
  631.         struct drm_device *dev = connector->dev;
  632.         struct intel_crt *crt = intel_attached_crt(connector);
  633.         enum drm_connector_status status;
  634.         struct intel_load_detect_pipe tmp;
  635.  
  636.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
  637.                       connector->base.id, drm_get_connector_name(connector),
  638.                       force);
  639.  
  640.         if (I915_HAS_HOTPLUG(dev)) {
  641.                 /* We can not rely on the HPD pin always being correctly wired
  642.                  * up, for example many KVM do not pass it through, and so
  643.                  * only trust an assertion that the monitor is connected.
  644.                  */
  645.                 if (intel_crt_detect_hotplug(connector)) {
  646.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  647.                         return connector_status_connected;
  648.                 } else
  649.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  650.         }
  651.  
  652.         if (intel_crt_detect_ddc(connector))
  653.                 return connector_status_connected;
  654.  
  655.         /* Load detection is broken on HPD capable machines. Whoever wants a
  656.          * broken monitor (without edid) to work behind a broken kvm (that fails
  657.          * to have the right resistors for HP detection) needs to fix this up.
  658.          * For now just bail out. */
  659.         if (I915_HAS_HOTPLUG(dev))
  660.                 return connector_status_disconnected;
  661.  
  662.         if (!force)
  663.                 return connector->status;
  664.  
  665.         /* for pre-945g platforms use load detect */
  666.         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  667.                         if (intel_crt_detect_ddc(connector))
  668.                                 status = connector_status_connected;
  669.                         else
  670.                                 status = intel_crt_load_detect(crt);
  671.                 intel_release_load_detect_pipe(connector, &tmp);
  672.                 } else
  673.                         status = connector_status_unknown;
  674.  
  675.         return status;
  676. }
  677.  
  678. static void intel_crt_destroy(struct drm_connector *connector)
  679. {
  680.         drm_connector_cleanup(connector);
  681.         kfree(connector);
  682. }
  683.  
  684. static int intel_crt_get_modes(struct drm_connector *connector)
  685. {
  686.         struct drm_device *dev = connector->dev;
  687.         struct drm_i915_private *dev_priv = dev->dev_private;
  688.         int ret;
  689.         struct i2c_adapter *i2c;
  690.  
  691.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  692.         ret = intel_crt_ddc_get_modes(connector, i2c);
  693.         if (ret || !IS_G4X(dev))
  694.                 return ret;
  695.  
  696.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  697.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  698.         return intel_crt_ddc_get_modes(connector, i2c);
  699. }
  700.  
  701. static int intel_crt_set_property(struct drm_connector *connector,
  702.                                   struct drm_property *property,
  703.                                   uint64_t value)
  704. {
  705.         return 0;
  706. }
  707.  
  708. static void intel_crt_reset(struct drm_connector *connector)
  709. {
  710.         struct drm_device *dev = connector->dev;
  711.         struct drm_i915_private *dev_priv = dev->dev_private;
  712.         struct intel_crt *crt = intel_attached_crt(connector);
  713.  
  714.         if (INTEL_INFO(dev)->gen >= 5) {
  715.                 u32 adpa;
  716.  
  717.                 adpa = I915_READ(crt->adpa_reg);
  718.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  719.                 adpa |= ADPA_HOTPLUG_BITS;
  720.                 I915_WRITE(crt->adpa_reg, adpa);
  721.                 POSTING_READ(crt->adpa_reg);
  722.  
  723.                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  724.                 crt->force_hotplug_required = 1;
  725.         }
  726.  
  727. }
  728.  
  729. /*
  730.  * Routines for controlling stuff on the analog port
  731.  */
  732.  
  733. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  734.         .reset = intel_crt_reset,
  735.         .dpms = intel_crt_dpms,
  736.         .detect = intel_crt_detect,
  737.         .fill_modes = drm_helper_probe_single_connector_modes,
  738.         .destroy = intel_crt_destroy,
  739.         .set_property = intel_crt_set_property,
  740. };
  741.  
  742. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  743.         .mode_valid = intel_crt_mode_valid,
  744.         .get_modes = intel_crt_get_modes,
  745.         .best_encoder = intel_best_encoder,
  746. };
  747.  
  748. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  749.         .destroy = intel_encoder_destroy,
  750. };
  751.  
  752. void intel_crt_init(struct drm_device *dev)
  753. {
  754.         struct drm_connector *connector;
  755.         struct intel_crt *crt;
  756.         struct intel_connector *intel_connector;
  757.         struct drm_i915_private *dev_priv = dev->dev_private;
  758.  
  759.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  760.         if (!crt)
  761.                 return;
  762.  
  763.         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
  764.         if (!intel_connector) {
  765.                 kfree(crt);
  766.                 return;
  767.         }
  768.  
  769.         connector = &intel_connector->base;
  770.         crt->connector = intel_connector;
  771.         drm_connector_init(dev, &intel_connector->base,
  772.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  773.  
  774.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  775.                          DRM_MODE_ENCODER_DAC);
  776.  
  777.         intel_connector_attach_encoder(intel_connector, &crt->base);
  778.  
  779.         crt->base.type = INTEL_OUTPUT_ANALOG;
  780.         crt->base.cloneable = true;
  781.         if (IS_I830(dev))
  782.                 crt->base.crtc_mask = (1 << 0);
  783.         else
  784.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  785.  
  786.         if (IS_GEN2(dev))
  787.                 connector->interlace_allowed = 0;
  788.         else
  789.         connector->interlace_allowed = 1;
  790.         connector->doublescan_allowed = 0;
  791.  
  792.         if (HAS_PCH_SPLIT(dev))
  793.                 crt->adpa_reg = PCH_ADPA;
  794.         else if (IS_VALLEYVIEW(dev))
  795.                 crt->adpa_reg = VLV_ADPA;
  796.         else
  797.                 crt->adpa_reg = ADPA;
  798.  
  799.         crt->base.compute_config = intel_crt_compute_config;
  800.         crt->base.mode_set = intel_crt_mode_set;
  801.         crt->base.disable = intel_disable_crt;
  802.         crt->base.enable = intel_enable_crt;
  803.         if (I915_HAS_HOTPLUG(dev))
  804.                 crt->base.hpd_pin = HPD_CRT;
  805.         if (HAS_DDI(dev)) {
  806.                 crt->base.get_config = hsw_crt_get_config;
  807.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  808.         } else {
  809.                 crt->base.get_config = intel_crt_get_config;
  810.         crt->base.get_hw_state = intel_crt_get_hw_state;
  811.         }
  812.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  813.  
  814.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  815.  
  816.         drm_sysfs_connector_add(connector);
  817.  
  818.         if (!I915_HAS_HOTPLUG(dev))
  819.                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  820.  
  821.         /*
  822.          * Configure the automatic hotplug detection stuff
  823.          */
  824.         crt->force_hotplug_required = 0;
  825.  
  826.         /*
  827.          * TODO: find a proper way to discover whether we need to set the the
  828.          * polarity and link reversal bits or not, instead of relying on the
  829.          * BIOS.
  830.          */
  831.         if (HAS_PCH_LPT(dev)) {
  832.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  833.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  834.  
  835.                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
  836.         }
  837. }
  838.