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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43.                            ADPA_CRT_HOTPLUG_ENABLE)
  44.  
  45. struct intel_crt {
  46.         struct intel_encoder base;
  47.         /* DPMS state is stored in the connector, which we need in the
  48.          * encoder's enable/disable callbacks */
  49.         struct intel_connector *connector;
  50.         bool force_hotplug_required;
  51.         u32 adpa_reg;
  52. };
  53.  
  54. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  55. {
  56.         return container_of(encoder, struct intel_crt, base);
  57. }
  58.  
  59. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  60. {
  61.         return intel_encoder_to_crt(intel_attached_encoder(connector));
  62. }
  63.  
  64. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  65.                                    enum pipe *pipe)
  66. {
  67.         struct drm_device *dev = encoder->base.dev;
  68.         struct drm_i915_private *dev_priv = dev->dev_private;
  69.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  70.         u32 tmp;
  71.  
  72.         tmp = I915_READ(crt->adpa_reg);
  73.  
  74.         if (!(tmp & ADPA_DAC_ENABLE))
  75.                 return false;
  76.  
  77.         if (HAS_PCH_CPT(dev))
  78.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  79.         else
  80.                 *pipe = PORT_TO_PIPE(tmp);
  81.  
  82.         return true;
  83. }
  84.  
  85. static void intel_crt_get_config(struct intel_encoder *encoder,
  86.                                  struct intel_crtc_config *pipe_config)
  87. {
  88.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  89.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  90.         u32 tmp, flags = 0;
  91.  
  92.         tmp = I915_READ(crt->adpa_reg);
  93.  
  94.         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
  95.                 flags |= DRM_MODE_FLAG_PHSYNC;
  96.         else
  97.                 flags |= DRM_MODE_FLAG_NHSYNC;
  98.  
  99.         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
  100.                 flags |= DRM_MODE_FLAG_PVSYNC;
  101.         else
  102.                 flags |= DRM_MODE_FLAG_NVSYNC;
  103.  
  104.         pipe_config->adjusted_mode.flags |= flags;
  105. }
  106.  
  107. /* Note: The caller is required to filter out dpms modes not supported by the
  108.  * platform. */
  109. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  110. {
  111.         struct drm_device *dev = encoder->base.dev;
  112.         struct drm_i915_private *dev_priv = dev->dev_private;
  113.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  114.         u32 temp;
  115.  
  116.         temp = I915_READ(crt->adpa_reg);
  117.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  118.         temp &= ~ADPA_DAC_ENABLE;
  119.  
  120.         switch (mode) {
  121.         case DRM_MODE_DPMS_ON:
  122.                 temp |= ADPA_DAC_ENABLE;
  123.                 break;
  124.         case DRM_MODE_DPMS_STANDBY:
  125.                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  126.                 break;
  127.         case DRM_MODE_DPMS_SUSPEND:
  128.                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  129.                 break;
  130.         case DRM_MODE_DPMS_OFF:
  131.                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  132.                 break;
  133.         }
  134.  
  135.         I915_WRITE(crt->adpa_reg, temp);
  136. }
  137.  
  138. static void intel_disable_crt(struct intel_encoder *encoder)
  139. {
  140.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  141. }
  142.  
  143. static void intel_enable_crt(struct intel_encoder *encoder)
  144. {
  145.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  146.  
  147.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  148. }
  149.  
  150. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  151. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  152. {
  153.         struct drm_device *dev = connector->dev;
  154.         struct intel_encoder *encoder = intel_attached_encoder(connector);
  155.         struct drm_crtc *crtc;
  156.         int old_dpms;
  157.  
  158.         /* PCH platforms and VLV only support on/off. */
  159.         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  160.                 mode = DRM_MODE_DPMS_OFF;
  161.  
  162.         if (mode == connector->dpms)
  163.                 return;
  164.  
  165.         old_dpms = connector->dpms;
  166.         connector->dpms = mode;
  167.  
  168.         /* Only need to change hw state when actually enabled */
  169.         crtc = encoder->base.crtc;
  170.         if (!crtc) {
  171.                 encoder->connectors_active = false;
  172.                 return;
  173.         }
  174.  
  175.         /* We need the pipe to run for anything but OFF. */
  176.         if (mode == DRM_MODE_DPMS_OFF)
  177.                 encoder->connectors_active = false;
  178.         else
  179.                 encoder->connectors_active = true;
  180.  
  181.         /* We call connector dpms manually below in case pipe dpms doesn't
  182.          * change due to cloning. */
  183.         if (mode < old_dpms) {
  184.                 /* From off to on, enable the pipe first. */
  185.                 intel_crtc_update_dpms(crtc);
  186.  
  187.                 intel_crt_set_dpms(encoder, mode);
  188.         } else {
  189.                 intel_crt_set_dpms(encoder, mode);
  190.  
  191.                 intel_crtc_update_dpms(crtc);
  192.         }
  193.  
  194.         intel_modeset_check_state(connector->dev);
  195. }
  196.  
  197. static int intel_crt_mode_valid(struct drm_connector *connector,
  198.                                 struct drm_display_mode *mode)
  199. {
  200.         struct drm_device *dev = connector->dev;
  201.  
  202.         int max_clock = 0;
  203.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  204.                 return MODE_NO_DBLESCAN;
  205.  
  206.         if (mode->clock < 25000)
  207.                 return MODE_CLOCK_LOW;
  208.  
  209.         if (IS_GEN2(dev))
  210.                 max_clock = 350000;
  211.         else
  212.                 max_clock = 400000;
  213.         if (mode->clock > max_clock)
  214.                 return MODE_CLOCK_HIGH;
  215.  
  216.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  217.         if (HAS_PCH_LPT(dev) &&
  218.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  219.                 return MODE_CLOCK_HIGH;
  220.  
  221.         return MODE_OK;
  222. }
  223.  
  224. static bool intel_crt_compute_config(struct intel_encoder *encoder,
  225.                                      struct intel_crtc_config *pipe_config)
  226. {
  227.         struct drm_device *dev = encoder->base.dev;
  228.  
  229.         if (HAS_PCH_SPLIT(dev))
  230.                 pipe_config->has_pch_encoder = true;
  231.  
  232.         /* LPT FDI RX only supports 8bpc. */
  233.         if (HAS_PCH_LPT(dev))
  234.                 pipe_config->pipe_bpp = 24;
  235.  
  236.         return true;
  237. }
  238.  
  239. static void intel_crt_mode_set(struct intel_encoder *encoder)
  240. {
  241.  
  242.         struct drm_device *dev = encoder->base.dev;
  243.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  244.         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  245.         struct drm_i915_private *dev_priv = dev->dev_private;
  246.         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  247.         u32 adpa;
  248.  
  249.         if (HAS_PCH_SPLIT(dev))
  250.         adpa = ADPA_HOTPLUG_BITS;
  251.         else
  252.                 adpa = 0;
  253.  
  254.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  255.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  256.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  257.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  258.  
  259.         /* For CPT allow 3 pipe config, for others just use A or B */
  260.         if (HAS_PCH_LPT(dev))
  261.                 ; /* Those bits don't exist here */
  262.         else if (HAS_PCH_CPT(dev))
  263.                 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
  264.         else if (crtc->pipe == 0)
  265.                         adpa |= ADPA_PIPE_A_SELECT;
  266.                 else
  267.                         adpa |= ADPA_PIPE_B_SELECT;
  268.  
  269.         if (!HAS_PCH_SPLIT(dev))
  270.                 I915_WRITE(BCLRPAT(crtc->pipe), 0);
  271.  
  272.         I915_WRITE(crt->adpa_reg, adpa);
  273. }
  274.  
  275. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  276. {
  277.         struct drm_device *dev = connector->dev;
  278.         struct intel_crt *crt = intel_attached_crt(connector);
  279.         struct drm_i915_private *dev_priv = dev->dev_private;
  280.         u32 adpa;
  281.         bool ret;
  282.  
  283.         /* The first time through, trigger an explicit detection cycle */
  284.         if (crt->force_hotplug_required) {
  285.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  286.                 u32 save_adpa;
  287.  
  288.                 crt->force_hotplug_required = 0;
  289.  
  290.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  291.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  292.  
  293.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  294.                 if (turn_off_dac)
  295.                         adpa &= ~ADPA_DAC_ENABLE;
  296.  
  297.                 I915_WRITE(crt->adpa_reg, adpa);
  298.  
  299.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  300.                              1000))
  301.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  302.  
  303.                 if (turn_off_dac) {
  304.                         I915_WRITE(crt->adpa_reg, save_adpa);
  305.                         POSTING_READ(crt->adpa_reg);
  306.                 }
  307.         }
  308.  
  309.         /* Check the status to see if both blue and green are on now */
  310.         adpa = I915_READ(crt->adpa_reg);
  311.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  312.                 ret = true;
  313.         else
  314.                 ret = false;
  315.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  316.  
  317.         return ret;
  318. }
  319.  
  320. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  321. {
  322.         struct drm_device *dev = connector->dev;
  323.         struct intel_crt *crt = intel_attached_crt(connector);
  324.         struct drm_i915_private *dev_priv = dev->dev_private;
  325.         u32 adpa;
  326.         bool ret;
  327.         u32 save_adpa;
  328.  
  329.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  330.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  331.  
  332.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  333.  
  334.         I915_WRITE(crt->adpa_reg, adpa);
  335.  
  336.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  337.                      1000)) {
  338.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  339.                 I915_WRITE(crt->adpa_reg, save_adpa);
  340.         }
  341.  
  342.         /* Check the status to see if both blue and green are on now */
  343.         adpa = I915_READ(crt->adpa_reg);
  344.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  345.                 ret = true;
  346.         else
  347.                 ret = false;
  348.  
  349.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  350.  
  351.         /* FIXME: debug force function and remove */
  352.         ret = true;
  353.  
  354.         return ret;
  355. }
  356.  
  357. /**
  358.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  359.  *
  360.  * Not for i915G/i915GM
  361.  *
  362.  * \return true if CRT is connected.
  363.  * \return false if CRT is disconnected.
  364.  */
  365. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  366. {
  367.         struct drm_device *dev = connector->dev;
  368.         struct drm_i915_private *dev_priv = dev->dev_private;
  369.         u32 hotplug_en, orig, stat;
  370.         bool ret = false;
  371.         int i, tries = 0;
  372.  
  373.         if (HAS_PCH_SPLIT(dev))
  374.                 return intel_ironlake_crt_detect_hotplug(connector);
  375.  
  376.         if (IS_VALLEYVIEW(dev))
  377.                 return valleyview_crt_detect_hotplug(connector);
  378.  
  379.         /*
  380.          * On 4 series desktop, CRT detect sequence need to be done twice
  381.          * to get a reliable result.
  382.          */
  383.  
  384.         if (IS_G4X(dev) && !IS_GM45(dev))
  385.                 tries = 2;
  386.         else
  387.                 tries = 1;
  388.         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  389.         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  390.  
  391.         for (i = 0; i < tries ; i++) {
  392.                 /* turn on the FORCE_DETECT */
  393.                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  394.                 /* wait for FORCE_DETECT to go off */
  395.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  396.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  397.                              1000))
  398.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  399.         }
  400.  
  401.         stat = I915_READ(PORT_HOTPLUG_STAT);
  402.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  403.                 ret = true;
  404.  
  405.         /* clear the interrupt we just generated, if any */
  406.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  407.  
  408.         /* and put the bits back */
  409.         I915_WRITE(PORT_HOTPLUG_EN, orig);
  410.  
  411.         return ret;
  412. }
  413.  
  414. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  415.                                 struct i2c_adapter *i2c)
  416. {
  417.         struct edid *edid;
  418.  
  419.         edid = drm_get_edid(connector, i2c);
  420.  
  421.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  422.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  423.                 intel_gmbus_force_bit(i2c, true);
  424.                 edid = drm_get_edid(connector, i2c);
  425.                 intel_gmbus_force_bit(i2c, false);
  426.         }
  427.  
  428.         return edid;
  429. }
  430.  
  431. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  432. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  433.                                 struct i2c_adapter *adapter)
  434. {
  435.         struct edid *edid;
  436.         int ret;
  437.  
  438.         edid = intel_crt_get_edid(connector, adapter);
  439.         if (!edid)
  440.                 return 0;
  441.  
  442.         ret = intel_connector_update_modes(connector, edid);
  443.         kfree(edid);
  444.  
  445.         return ret;
  446. }
  447.  
  448. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  449. {
  450.         struct intel_crt *crt = intel_attached_crt(connector);
  451.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  452.         struct edid *edid;
  453.         struct i2c_adapter *i2c;
  454.  
  455.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  456.  
  457.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  458.         edid = intel_crt_get_edid(connector, i2c);
  459.  
  460.         if (edid) {
  461.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  462.  
  463.                 /*
  464.                  * This may be a DVI-I connector with a shared DDC
  465.                  * link between analog and digital outputs, so we
  466.                  * have to check the EDID input spec of the attached device.
  467.                  */
  468.                 if (!is_digital) {
  469.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  470.                         return true;
  471.                 }
  472.  
  473.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  474.                 } else {
  475.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  476.                 }
  477.  
  478.         kfree(edid);
  479.  
  480.         return false;
  481. }
  482.  
  483. static enum drm_connector_status
  484. intel_crt_load_detect(struct intel_crt *crt)
  485. {
  486.         struct drm_device *dev = crt->base.base.dev;
  487.         struct drm_i915_private *dev_priv = dev->dev_private;
  488.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  489.         uint32_t save_bclrpat;
  490.         uint32_t save_vtotal;
  491.         uint32_t vtotal, vactive;
  492.         uint32_t vsample;
  493.         uint32_t vblank, vblank_start, vblank_end;
  494.         uint32_t dsl;
  495.         uint32_t bclrpat_reg;
  496.         uint32_t vtotal_reg;
  497.         uint32_t vblank_reg;
  498.         uint32_t vsync_reg;
  499.         uint32_t pipeconf_reg;
  500.         uint32_t pipe_dsl_reg;
  501.         uint8_t st00;
  502.         enum drm_connector_status status;
  503.  
  504.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  505.  
  506.         bclrpat_reg = BCLRPAT(pipe);
  507.         vtotal_reg = VTOTAL(pipe);
  508.         vblank_reg = VBLANK(pipe);
  509.         vsync_reg = VSYNC(pipe);
  510.         pipeconf_reg = PIPECONF(pipe);
  511.         pipe_dsl_reg = PIPEDSL(pipe);
  512.  
  513.         save_bclrpat = I915_READ(bclrpat_reg);
  514.         save_vtotal = I915_READ(vtotal_reg);
  515.         vblank = I915_READ(vblank_reg);
  516.  
  517.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  518.         vactive = (save_vtotal & 0x7ff) + 1;
  519.  
  520.         vblank_start = (vblank & 0xfff) + 1;
  521.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  522.  
  523.         /* Set the border color to purple. */
  524.         I915_WRITE(bclrpat_reg, 0x500050);
  525.  
  526.         if (!IS_GEN2(dev)) {
  527.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  528.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  529.                 POSTING_READ(pipeconf_reg);
  530.                 /* Wait for next Vblank to substitue
  531.                  * border color for Color info */
  532.                 intel_wait_for_vblank(dev, pipe);
  533.                 st00 = I915_READ8(VGA_MSR_WRITE);
  534.                 status = ((st00 & (1 << 4)) != 0) ?
  535.                         connector_status_connected :
  536.                         connector_status_disconnected;
  537.  
  538.                 I915_WRITE(pipeconf_reg, pipeconf);
  539.         } else {
  540.                 bool restore_vblank = false;
  541.                 int count, detect;
  542.  
  543.                 /*
  544.                 * If there isn't any border, add some.
  545.                 * Yes, this will flicker
  546.                 */
  547.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  548.                         uint32_t vsync = I915_READ(vsync_reg);
  549.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  550.  
  551.                         vblank_start = vsync_start;
  552.                         I915_WRITE(vblank_reg,
  553.                                    (vblank_start - 1) |
  554.                                    ((vblank_end - 1) << 16));
  555.                         restore_vblank = true;
  556.                 }
  557.                 /* sample in the vertical border, selecting the larger one */
  558.                 if (vblank_start - vactive >= vtotal - vblank_end)
  559.                         vsample = (vblank_start + vactive) >> 1;
  560.                 else
  561.                         vsample = (vtotal + vblank_end) >> 1;
  562.  
  563.                 /*
  564.                  * Wait for the border to be displayed
  565.                  */
  566.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  567.                         ;
  568.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  569.                         ;
  570.                 /*
  571.                  * Watch ST00 for an entire scanline
  572.                  */
  573.                 detect = 0;
  574.                 count = 0;
  575.                 do {
  576.                         count++;
  577.                         /* Read the ST00 VGA status register */
  578.                         st00 = I915_READ8(VGA_MSR_WRITE);
  579.                         if (st00 & (1 << 4))
  580.                                 detect++;
  581.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  582.  
  583.                 /* restore vblank if necessary */
  584.                 if (restore_vblank)
  585.                         I915_WRITE(vblank_reg, vblank);
  586.                 /*
  587.                  * If more than 3/4 of the scanline detected a monitor,
  588.                  * then it is assumed to be present. This works even on i830,
  589.                  * where there isn't any way to force the border color across
  590.                  * the screen
  591.                  */
  592.                 status = detect * 4 > count * 3 ?
  593.                          connector_status_connected :
  594.                          connector_status_disconnected;
  595.         }
  596.  
  597.         /* Restore previous settings */
  598.         I915_WRITE(bclrpat_reg, save_bclrpat);
  599.  
  600.         return status;
  601. }
  602.  
  603. static enum drm_connector_status
  604. intel_crt_detect(struct drm_connector *connector, bool force)
  605. {
  606.         struct drm_device *dev = connector->dev;
  607.         struct intel_crt *crt = intel_attached_crt(connector);
  608.         enum drm_connector_status status;
  609.         struct intel_load_detect_pipe tmp;
  610.  
  611.         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
  612.                       connector->base.id, drm_get_connector_name(connector),
  613.                       force);
  614.  
  615.         if (I915_HAS_HOTPLUG(dev)) {
  616.                 /* We can not rely on the HPD pin always being correctly wired
  617.                  * up, for example many KVM do not pass it through, and so
  618.                  * only trust an assertion that the monitor is connected.
  619.                  */
  620.                 if (intel_crt_detect_hotplug(connector)) {
  621.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  622.                         return connector_status_connected;
  623.                 } else
  624.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  625.         }
  626.  
  627.         if (intel_crt_detect_ddc(connector))
  628.                 return connector_status_connected;
  629.  
  630.         /* Load detection is broken on HPD capable machines. Whoever wants a
  631.          * broken monitor (without edid) to work behind a broken kvm (that fails
  632.          * to have the right resistors for HP detection) needs to fix this up.
  633.          * For now just bail out. */
  634.         if (I915_HAS_HOTPLUG(dev))
  635.                 return connector_status_disconnected;
  636.  
  637.         if (!force)
  638.                 return connector->status;
  639.  
  640.         /* for pre-945g platforms use load detect */
  641.         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  642.                         if (intel_crt_detect_ddc(connector))
  643.                                 status = connector_status_connected;
  644.                         else
  645.                                 status = intel_crt_load_detect(crt);
  646.                 intel_release_load_detect_pipe(connector, &tmp);
  647.                 } else
  648.                         status = connector_status_unknown;
  649.  
  650.         return status;
  651. }
  652.  
  653. static void intel_crt_destroy(struct drm_connector *connector)
  654. {
  655.         drm_sysfs_connector_remove(connector);
  656.         drm_connector_cleanup(connector);
  657.         kfree(connector);
  658. }
  659.  
  660. static int intel_crt_get_modes(struct drm_connector *connector)
  661. {
  662.         struct drm_device *dev = connector->dev;
  663.         struct drm_i915_private *dev_priv = dev->dev_private;
  664.         int ret;
  665.         struct i2c_adapter *i2c;
  666.  
  667.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
  668.         ret = intel_crt_ddc_get_modes(connector, i2c);
  669.         if (ret || !IS_G4X(dev))
  670.                 return ret;
  671.  
  672.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  673.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  674.         return intel_crt_ddc_get_modes(connector, i2c);
  675. }
  676.  
  677. static int intel_crt_set_property(struct drm_connector *connector,
  678.                                   struct drm_property *property,
  679.                                   uint64_t value)
  680. {
  681.         return 0;
  682. }
  683.  
  684. static void intel_crt_reset(struct drm_connector *connector)
  685. {
  686.         struct drm_device *dev = connector->dev;
  687.         struct drm_i915_private *dev_priv = dev->dev_private;
  688.         struct intel_crt *crt = intel_attached_crt(connector);
  689.  
  690.         if (INTEL_INFO(dev)->gen >= 5) {
  691.                 u32 adpa;
  692.  
  693.                 adpa = I915_READ(crt->adpa_reg);
  694.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  695.                 adpa |= ADPA_HOTPLUG_BITS;
  696.                 I915_WRITE(crt->adpa_reg, adpa);
  697.                 POSTING_READ(crt->adpa_reg);
  698.  
  699.                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  700.                 crt->force_hotplug_required = 1;
  701.         }
  702.  
  703. }
  704.  
  705. /*
  706.  * Routines for controlling stuff on the analog port
  707.  */
  708.  
  709. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  710.         .reset = intel_crt_reset,
  711.         .dpms = intel_crt_dpms,
  712.         .detect = intel_crt_detect,
  713.         .fill_modes = drm_helper_probe_single_connector_modes,
  714.         .destroy = intel_crt_destroy,
  715.         .set_property = intel_crt_set_property,
  716. };
  717.  
  718. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  719.         .mode_valid = intel_crt_mode_valid,
  720.         .get_modes = intel_crt_get_modes,
  721.         .best_encoder = intel_best_encoder,
  722. };
  723.  
  724. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  725.         .destroy = intel_encoder_destroy,
  726. };
  727.  
  728. void intel_crt_init(struct drm_device *dev)
  729. {
  730.         struct drm_connector *connector;
  731.         struct intel_crt *crt;
  732.         struct intel_connector *intel_connector;
  733.         struct drm_i915_private *dev_priv = dev->dev_private;
  734.  
  735.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  736.         if (!crt)
  737.                 return;
  738.  
  739.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  740.         if (!intel_connector) {
  741.                 kfree(crt);
  742.                 return;
  743.         }
  744.  
  745.         connector = &intel_connector->base;
  746.         crt->connector = intel_connector;
  747.         drm_connector_init(dev, &intel_connector->base,
  748.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  749.  
  750.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  751.                          DRM_MODE_ENCODER_DAC);
  752.  
  753.         intel_connector_attach_encoder(intel_connector, &crt->base);
  754.  
  755.         crt->base.type = INTEL_OUTPUT_ANALOG;
  756.         crt->base.cloneable = true;
  757.         if (IS_I830(dev))
  758.                 crt->base.crtc_mask = (1 << 0);
  759.         else
  760.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  761.  
  762.         if (IS_GEN2(dev))
  763.                 connector->interlace_allowed = 0;
  764.         else
  765.         connector->interlace_allowed = 1;
  766.         connector->doublescan_allowed = 0;
  767.  
  768.         if (HAS_PCH_SPLIT(dev))
  769.                 crt->adpa_reg = PCH_ADPA;
  770.         else if (IS_VALLEYVIEW(dev))
  771.                 crt->adpa_reg = VLV_ADPA;
  772.         else
  773.                 crt->adpa_reg = ADPA;
  774.  
  775.         crt->base.compute_config = intel_crt_compute_config;
  776.         crt->base.mode_set = intel_crt_mode_set;
  777.         crt->base.disable = intel_disable_crt;
  778.         crt->base.enable = intel_enable_crt;
  779.         crt->base.get_config = intel_crt_get_config;
  780.         if (I915_HAS_HOTPLUG(dev))
  781.                 crt->base.hpd_pin = HPD_CRT;
  782.         if (HAS_DDI(dev))
  783.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  784.         else
  785.         crt->base.get_hw_state = intel_crt_get_hw_state;
  786.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  787.  
  788.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  789.  
  790.         drm_sysfs_connector_add(connector);
  791.  
  792.         if (!I915_HAS_HOTPLUG(dev))
  793.                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  794.  
  795.         /*
  796.          * Configure the automatic hotplug detection stuff
  797.          */
  798.         crt->force_hotplug_required = 0;
  799.  
  800.         /*
  801.          * TODO: find a proper way to discover whether we need to set the the
  802.          * polarity and link reversal bits or not, instead of relying on the
  803.          * BIOS.
  804.          */
  805.         if (HAS_PCH_LPT(dev)) {
  806.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  807.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  808.  
  809.                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
  810.         }
  811. }
  812.