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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43.                            ADPA_CRT_HOTPLUG_ENABLE)
  44.  
  45. struct intel_crt {
  46.         struct intel_encoder base;
  47.         /* DPMS state is stored in the connector, which we need in the
  48.          * encoder's enable/disable callbacks */
  49.         struct intel_connector *connector;
  50.         bool force_hotplug_required;
  51.         u32 adpa_reg;
  52. };
  53.  
  54. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  55. {
  56.         return container_of(intel_attached_encoder(connector),
  57.                             struct intel_crt, base);
  58. }
  59.  
  60. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  61. {
  62.         return container_of(encoder, struct intel_crt, base);
  63. }
  64.  
  65. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  66.                                    enum pipe *pipe)
  67. {
  68.         struct drm_device *dev = encoder->base.dev;
  69.         struct drm_i915_private *dev_priv = dev->dev_private;
  70.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  71.         u32 tmp;
  72.  
  73.         tmp = I915_READ(crt->adpa_reg);
  74.  
  75.         if (!(tmp & ADPA_DAC_ENABLE))
  76.                 return false;
  77.  
  78.         if (HAS_PCH_CPT(dev))
  79.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  80.         else
  81.                 *pipe = PORT_TO_PIPE(tmp);
  82.  
  83.         return true;
  84. }
  85.  
  86. /* Note: The caller is required to filter out dpms modes not supported by the
  87.  * platform. */
  88. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  89. {
  90.         struct drm_device *dev = encoder->base.dev;
  91.         struct drm_i915_private *dev_priv = dev->dev_private;
  92.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  93.         u32 temp;
  94.  
  95.         temp = I915_READ(crt->adpa_reg);
  96.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  97.         temp &= ~ADPA_DAC_ENABLE;
  98.  
  99.         switch (mode) {
  100.         case DRM_MODE_DPMS_ON:
  101.                 temp |= ADPA_DAC_ENABLE;
  102.                 break;
  103.         case DRM_MODE_DPMS_STANDBY:
  104.                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  105.                 break;
  106.         case DRM_MODE_DPMS_SUSPEND:
  107.                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  108.                 break;
  109.         case DRM_MODE_DPMS_OFF:
  110.                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  111.                 break;
  112.         }
  113.  
  114.         I915_WRITE(crt->adpa_reg, temp);
  115. }
  116.  
  117. static void intel_disable_crt(struct intel_encoder *encoder)
  118. {
  119.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  120. }
  121.  
  122. static void intel_enable_crt(struct intel_encoder *encoder)
  123. {
  124.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  125.  
  126.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  127. }
  128.  
  129.  
  130. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  131. {
  132.         struct drm_device *dev = connector->dev;
  133.         struct intel_encoder *encoder = intel_attached_encoder(connector);
  134.         struct drm_crtc *crtc;
  135.         int old_dpms;
  136.  
  137.         /* PCH platforms and VLV only support on/off. */
  138.         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  139.                 mode = DRM_MODE_DPMS_OFF;
  140.  
  141.         if (mode == connector->dpms)
  142.                 return;
  143.  
  144.         old_dpms = connector->dpms;
  145.         connector->dpms = mode;
  146.  
  147.         /* Only need to change hw state when actually enabled */
  148.         crtc = encoder->base.crtc;
  149.         if (!crtc) {
  150.                 encoder->connectors_active = false;
  151.                 return;
  152.         }
  153.  
  154.         /* We need the pipe to run for anything but OFF. */
  155.         if (mode == DRM_MODE_DPMS_OFF)
  156.                 encoder->connectors_active = false;
  157.         else
  158.                 encoder->connectors_active = true;
  159.  
  160.         if (mode < old_dpms) {
  161.                 /* From off to on, enable the pipe first. */
  162.                 intel_crtc_update_dpms(crtc);
  163.  
  164.                 intel_crt_set_dpms(encoder, mode);
  165.         } else {
  166.                 intel_crt_set_dpms(encoder, mode);
  167.  
  168.                 intel_crtc_update_dpms(crtc);
  169.         }
  170.  
  171.         intel_modeset_check_state(connector->dev);
  172. }
  173.  
  174. static int intel_crt_mode_valid(struct drm_connector *connector,
  175.                                 struct drm_display_mode *mode)
  176. {
  177.         struct drm_device *dev = connector->dev;
  178.  
  179.         int max_clock = 0;
  180.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  181.                 return MODE_NO_DBLESCAN;
  182.  
  183.         if (mode->clock < 25000)
  184.                 return MODE_CLOCK_LOW;
  185.  
  186.         if (IS_GEN2(dev))
  187.                 max_clock = 350000;
  188.         else
  189.                 max_clock = 400000;
  190.         if (mode->clock > max_clock)
  191.                 return MODE_CLOCK_HIGH;
  192.  
  193.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  194.         if (HAS_PCH_LPT(dev) &&
  195.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  196.                 return MODE_CLOCK_HIGH;
  197.  
  198.         return MODE_OK;
  199. }
  200.  
  201. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  202.                                  const struct drm_display_mode *mode,
  203.                                  struct drm_display_mode *adjusted_mode)
  204. {
  205.         return true;
  206. }
  207.  
  208. static void intel_crt_mode_set(struct drm_encoder *encoder,
  209.                                struct drm_display_mode *mode,
  210.                                struct drm_display_mode *adjusted_mode)
  211. {
  212.  
  213.         struct drm_device *dev = encoder->dev;
  214.         struct drm_crtc *crtc = encoder->crtc;
  215.         struct intel_crt *crt =
  216.                 intel_encoder_to_crt(to_intel_encoder(encoder));
  217.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  218.         struct drm_i915_private *dev_priv = dev->dev_private;
  219.         u32 adpa;
  220.  
  221.         if (HAS_PCH_SPLIT(dev))
  222.         adpa = ADPA_HOTPLUG_BITS;
  223.         else
  224.                 adpa = 0;
  225.  
  226.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  227.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  228.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  229.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  230.  
  231.         /* For CPT allow 3 pipe config, for others just use A or B */
  232.         if (HAS_PCH_LPT(dev))
  233.                 ; /* Those bits don't exist here */
  234.         else if (HAS_PCH_CPT(dev))
  235.                 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  236.         else if (intel_crtc->pipe == 0)
  237.                         adpa |= ADPA_PIPE_A_SELECT;
  238.                 else
  239.                         adpa |= ADPA_PIPE_B_SELECT;
  240.  
  241.         if (!HAS_PCH_SPLIT(dev))
  242.                 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  243.  
  244.         I915_WRITE(crt->adpa_reg, adpa);
  245. }
  246.  
  247. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  248. {
  249.         struct drm_device *dev = connector->dev;
  250.         struct intel_crt *crt = intel_attached_crt(connector);
  251.         struct drm_i915_private *dev_priv = dev->dev_private;
  252.         u32 adpa;
  253.         bool ret;
  254.  
  255.         /* The first time through, trigger an explicit detection cycle */
  256.         if (crt->force_hotplug_required) {
  257.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  258.                 u32 save_adpa;
  259.  
  260.                 crt->force_hotplug_required = 0;
  261.  
  262.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  263.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  264.  
  265.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  266.                 if (turn_off_dac)
  267.                         adpa &= ~ADPA_DAC_ENABLE;
  268.  
  269.                 I915_WRITE(crt->adpa_reg, adpa);
  270.  
  271.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  272.                              1000))
  273.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  274.  
  275.                 if (turn_off_dac) {
  276.                         I915_WRITE(crt->adpa_reg, save_adpa);
  277.                         POSTING_READ(crt->adpa_reg);
  278.                 }
  279.         }
  280.  
  281.         /* Check the status to see if both blue and green are on now */
  282.         adpa = I915_READ(crt->adpa_reg);
  283.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  284.                 ret = true;
  285.         else
  286.                 ret = false;
  287.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  288.  
  289.         return ret;
  290. }
  291.  
  292. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  293. {
  294.         struct drm_device *dev = connector->dev;
  295.         struct intel_crt *crt = intel_attached_crt(connector);
  296.         struct drm_i915_private *dev_priv = dev->dev_private;
  297.         u32 adpa;
  298.         bool ret;
  299.         u32 save_adpa;
  300.  
  301.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  302.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  303.  
  304.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  305.  
  306.         I915_WRITE(crt->adpa_reg, adpa);
  307.  
  308.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  309.                      1000)) {
  310.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  311.                 I915_WRITE(crt->adpa_reg, save_adpa);
  312.         }
  313.  
  314.         /* Check the status to see if both blue and green are on now */
  315.         adpa = I915_READ(crt->adpa_reg);
  316.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  317.                 ret = true;
  318.         else
  319.                 ret = false;
  320.  
  321.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  322.  
  323.         /* FIXME: debug force function and remove */
  324.         ret = true;
  325.  
  326.         return ret;
  327. }
  328.  
  329. /**
  330.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  331.  *
  332.  * Not for i915G/i915GM
  333.  *
  334.  * \return true if CRT is connected.
  335.  * \return false if CRT is disconnected.
  336.  */
  337. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  338. {
  339.         struct drm_device *dev = connector->dev;
  340.         struct drm_i915_private *dev_priv = dev->dev_private;
  341.         u32 hotplug_en, orig, stat;
  342.         bool ret = false;
  343.         int i, tries = 0;
  344.  
  345.         if (HAS_PCH_SPLIT(dev))
  346.                 return intel_ironlake_crt_detect_hotplug(connector);
  347.  
  348.         if (IS_VALLEYVIEW(dev))
  349.                 return valleyview_crt_detect_hotplug(connector);
  350.  
  351.         /*
  352.          * On 4 series desktop, CRT detect sequence need to be done twice
  353.          * to get a reliable result.
  354.          */
  355.  
  356.         if (IS_G4X(dev) && !IS_GM45(dev))
  357.                 tries = 2;
  358.         else
  359.                 tries = 1;
  360.         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  361.         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  362.  
  363.         for (i = 0; i < tries ; i++) {
  364.                 /* turn on the FORCE_DETECT */
  365.                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  366.                 /* wait for FORCE_DETECT to go off */
  367.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  368.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  369.                              1000))
  370.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  371.         }
  372.  
  373.         stat = I915_READ(PORT_HOTPLUG_STAT);
  374.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  375.                 ret = true;
  376.  
  377.         /* clear the interrupt we just generated, if any */
  378.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  379.  
  380.         /* and put the bits back */
  381.         I915_WRITE(PORT_HOTPLUG_EN, orig);
  382.  
  383.         return ret;
  384. }
  385.  
  386. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  387.                                 struct i2c_adapter *i2c)
  388. {
  389.         struct edid *edid;
  390.  
  391.         edid = drm_get_edid(connector, i2c);
  392.  
  393.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  394.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  395.                 intel_gmbus_force_bit(i2c, true);
  396.                 edid = drm_get_edid(connector, i2c);
  397.                 intel_gmbus_force_bit(i2c, false);
  398.         }
  399.  
  400.         return edid;
  401. }
  402.  
  403. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  404. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  405.                                 struct i2c_adapter *adapter)
  406. {
  407.         struct edid *edid;
  408.         int ret;
  409.  
  410.         edid = intel_crt_get_edid(connector, adapter);
  411.         if (!edid)
  412.                 return 0;
  413.  
  414.         ret = intel_connector_update_modes(connector, edid);
  415.         kfree(edid);
  416.  
  417.         return ret;
  418. }
  419.  
  420. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  421. {
  422.         struct intel_crt *crt = intel_attached_crt(connector);
  423.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  424.         struct edid *edid;
  425.         struct i2c_adapter *i2c;
  426.  
  427.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  428.  
  429.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  430.         edid = intel_crt_get_edid(connector, i2c);
  431.  
  432.         if (edid) {
  433.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  434.  
  435.                 /*
  436.                  * This may be a DVI-I connector with a shared DDC
  437.                  * link between analog and digital outputs, so we
  438.                  * have to check the EDID input spec of the attached device.
  439.                  */
  440.                 if (!is_digital) {
  441.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  442.                         return true;
  443.                 }
  444.  
  445.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  446.                 } else {
  447.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  448.                 }
  449.  
  450.         kfree(edid);
  451.  
  452.         return false;
  453. }
  454.  
  455. static enum drm_connector_status
  456. intel_crt_load_detect(struct intel_crt *crt)
  457. {
  458.         struct drm_device *dev = crt->base.base.dev;
  459.         struct drm_i915_private *dev_priv = dev->dev_private;
  460.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  461.         uint32_t save_bclrpat;
  462.         uint32_t save_vtotal;
  463.         uint32_t vtotal, vactive;
  464.         uint32_t vsample;
  465.         uint32_t vblank, vblank_start, vblank_end;
  466.         uint32_t dsl;
  467.         uint32_t bclrpat_reg;
  468.         uint32_t vtotal_reg;
  469.         uint32_t vblank_reg;
  470.         uint32_t vsync_reg;
  471.         uint32_t pipeconf_reg;
  472.         uint32_t pipe_dsl_reg;
  473.         uint8_t st00;
  474.         enum drm_connector_status status;
  475.  
  476.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  477.  
  478.         bclrpat_reg = BCLRPAT(pipe);
  479.         vtotal_reg = VTOTAL(pipe);
  480.         vblank_reg = VBLANK(pipe);
  481.         vsync_reg = VSYNC(pipe);
  482.         pipeconf_reg = PIPECONF(pipe);
  483.         pipe_dsl_reg = PIPEDSL(pipe);
  484.  
  485.         save_bclrpat = I915_READ(bclrpat_reg);
  486.         save_vtotal = I915_READ(vtotal_reg);
  487.         vblank = I915_READ(vblank_reg);
  488.  
  489.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  490.         vactive = (save_vtotal & 0x7ff) + 1;
  491.  
  492.         vblank_start = (vblank & 0xfff) + 1;
  493.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  494.  
  495.         /* Set the border color to purple. */
  496.         I915_WRITE(bclrpat_reg, 0x500050);
  497.  
  498.         if (!IS_GEN2(dev)) {
  499.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  500.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  501.                 POSTING_READ(pipeconf_reg);
  502.                 /* Wait for next Vblank to substitue
  503.                  * border color for Color info */
  504.                 intel_wait_for_vblank(dev, pipe);
  505.                 st00 = I915_READ8(VGA_MSR_WRITE);
  506.                 status = ((st00 & (1 << 4)) != 0) ?
  507.                         connector_status_connected :
  508.                         connector_status_disconnected;
  509.  
  510.                 I915_WRITE(pipeconf_reg, pipeconf);
  511.         } else {
  512.                 bool restore_vblank = false;
  513.                 int count, detect;
  514.  
  515.                 /*
  516.                 * If there isn't any border, add some.
  517.                 * Yes, this will flicker
  518.                 */
  519.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  520.                         uint32_t vsync = I915_READ(vsync_reg);
  521.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  522.  
  523.                         vblank_start = vsync_start;
  524.                         I915_WRITE(vblank_reg,
  525.                                    (vblank_start - 1) |
  526.                                    ((vblank_end - 1) << 16));
  527.                         restore_vblank = true;
  528.                 }
  529.                 /* sample in the vertical border, selecting the larger one */
  530.                 if (vblank_start - vactive >= vtotal - vblank_end)
  531.                         vsample = (vblank_start + vactive) >> 1;
  532.                 else
  533.                         vsample = (vtotal + vblank_end) >> 1;
  534.  
  535.                 /*
  536.                  * Wait for the border to be displayed
  537.                  */
  538.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  539.                         ;
  540.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  541.                         ;
  542.                 /*
  543.                  * Watch ST00 for an entire scanline
  544.                  */
  545.                 detect = 0;
  546.                 count = 0;
  547.                 do {
  548.                         count++;
  549.                         /* Read the ST00 VGA status register */
  550.                         st00 = I915_READ8(VGA_MSR_WRITE);
  551.                         if (st00 & (1 << 4))
  552.                                 detect++;
  553.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  554.  
  555.                 /* restore vblank if necessary */
  556.                 if (restore_vblank)
  557.                         I915_WRITE(vblank_reg, vblank);
  558.                 /*
  559.                  * If more than 3/4 of the scanline detected a monitor,
  560.                  * then it is assumed to be present. This works even on i830,
  561.                  * where there isn't any way to force the border color across
  562.                  * the screen
  563.                  */
  564.                 status = detect * 4 > count * 3 ?
  565.                          connector_status_connected :
  566.                          connector_status_disconnected;
  567.         }
  568.  
  569.         /* Restore previous settings */
  570.         I915_WRITE(bclrpat_reg, save_bclrpat);
  571.  
  572.         return status;
  573. }
  574.  
  575. static enum drm_connector_status
  576. intel_crt_detect(struct drm_connector *connector, bool force)
  577. {
  578.         struct drm_device *dev = connector->dev;
  579.         struct intel_crt *crt = intel_attached_crt(connector);
  580.         enum drm_connector_status status;
  581.         struct intel_load_detect_pipe tmp;
  582.  
  583.         if (I915_HAS_HOTPLUG(dev)) {
  584.                 /* We can not rely on the HPD pin always being correctly wired
  585.                  * up, for example many KVM do not pass it through, and so
  586.                  * only trust an assertion that the monitor is connected.
  587.                  */
  588.                 if (intel_crt_detect_hotplug(connector)) {
  589.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  590.                         return connector_status_connected;
  591.                 } else
  592.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  593.         }
  594.  
  595.         if (intel_crt_detect_ddc(connector))
  596.                 return connector_status_connected;
  597.  
  598.         /* Load detection is broken on HPD capable machines. Whoever wants a
  599.          * broken monitor (without edid) to work behind a broken kvm (that fails
  600.          * to have the right resistors for HP detection) needs to fix this up.
  601.          * For now just bail out. */
  602.         if (I915_HAS_HOTPLUG(dev))
  603.                 return connector_status_disconnected;
  604.  
  605.         if (!force)
  606.                 return connector->status;
  607.  
  608.         /* for pre-945g platforms use load detect */
  609.         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  610.                         if (intel_crt_detect_ddc(connector))
  611.                                 status = connector_status_connected;
  612.                         else
  613.                                 status = intel_crt_load_detect(crt);
  614.                 intel_release_load_detect_pipe(connector, &tmp);
  615.                 } else
  616.                         status = connector_status_unknown;
  617.  
  618.         return status;
  619. }
  620.  
  621. static void intel_crt_destroy(struct drm_connector *connector)
  622. {
  623.         drm_sysfs_connector_remove(connector);
  624.         drm_connector_cleanup(connector);
  625.         kfree(connector);
  626. }
  627.  
  628. static int intel_crt_get_modes(struct drm_connector *connector)
  629. {
  630.         struct drm_device *dev = connector->dev;
  631.         struct drm_i915_private *dev_priv = dev->dev_private;
  632.         int ret;
  633.         struct i2c_adapter *i2c;
  634.  
  635.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  636.         ret = intel_crt_ddc_get_modes(connector, i2c);
  637.         if (ret || !IS_G4X(dev))
  638.                 return ret;
  639.  
  640.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  641.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  642.         return intel_crt_ddc_get_modes(connector, i2c);
  643. }
  644.  
  645. static int intel_crt_set_property(struct drm_connector *connector,
  646.                                   struct drm_property *property,
  647.                                   uint64_t value)
  648. {
  649.         return 0;
  650. }
  651.  
  652. static void intel_crt_reset(struct drm_connector *connector)
  653. {
  654.         struct drm_device *dev = connector->dev;
  655.         struct drm_i915_private *dev_priv = dev->dev_private;
  656.         struct intel_crt *crt = intel_attached_crt(connector);
  657.  
  658.         if (HAS_PCH_SPLIT(dev)) {
  659.                 u32 adpa;
  660.  
  661.                 adpa = I915_READ(crt->adpa_reg);
  662.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  663.                 adpa |= ADPA_HOTPLUG_BITS;
  664.                 I915_WRITE(crt->adpa_reg, adpa);
  665.                 POSTING_READ(crt->adpa_reg);
  666.  
  667.                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  668.                 crt->force_hotplug_required = 1;
  669.         }
  670.  
  671. }
  672.  
  673. /*
  674.  * Routines for controlling stuff on the analog port
  675.  */
  676.  
  677. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  678.         .mode_fixup = intel_crt_mode_fixup,
  679.         .mode_set = intel_crt_mode_set,
  680. };
  681.  
  682. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  683.         .reset = intel_crt_reset,
  684.         .dpms = intel_crt_dpms,
  685.         .detect = intel_crt_detect,
  686.         .fill_modes = drm_helper_probe_single_connector_modes,
  687.         .destroy = intel_crt_destroy,
  688.         .set_property = intel_crt_set_property,
  689. };
  690.  
  691. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  692.         .mode_valid = intel_crt_mode_valid,
  693.         .get_modes = intel_crt_get_modes,
  694.         .best_encoder = intel_best_encoder,
  695. };
  696.  
  697. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  698.         .destroy = intel_encoder_destroy,
  699. };
  700.  
  701. void intel_crt_init(struct drm_device *dev)
  702. {
  703.         struct drm_connector *connector;
  704.         struct intel_crt *crt;
  705.         struct intel_connector *intel_connector;
  706.         struct drm_i915_private *dev_priv = dev->dev_private;
  707.  
  708.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  709.         if (!crt)
  710.                 return;
  711.  
  712.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  713.         if (!intel_connector) {
  714.                 kfree(crt);
  715.                 return;
  716.         }
  717.  
  718.         connector = &intel_connector->base;
  719.         crt->connector = intel_connector;
  720.         drm_connector_init(dev, &intel_connector->base,
  721.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  722.  
  723.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  724.                          DRM_MODE_ENCODER_DAC);
  725.  
  726.         intel_connector_attach_encoder(intel_connector, &crt->base);
  727.  
  728.         crt->base.type = INTEL_OUTPUT_ANALOG;
  729.         crt->base.cloneable = true;
  730.         if (IS_I830(dev))
  731.                 crt->base.crtc_mask = (1 << 0);
  732.         else
  733.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  734.  
  735.         if (IS_GEN2(dev))
  736.                 connector->interlace_allowed = 0;
  737.         else
  738.         connector->interlace_allowed = 1;
  739.         connector->doublescan_allowed = 0;
  740.  
  741.         if (HAS_PCH_SPLIT(dev))
  742.                 crt->adpa_reg = PCH_ADPA;
  743.         else if (IS_VALLEYVIEW(dev))
  744.                 crt->adpa_reg = VLV_ADPA;
  745.         else
  746.                 crt->adpa_reg = ADPA;
  747.  
  748.         crt->base.disable = intel_disable_crt;
  749.         crt->base.enable = intel_enable_crt;
  750.         if (HAS_DDI(dev))
  751.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  752.         else
  753.         crt->base.get_hw_state = intel_crt_get_hw_state;
  754.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  755.  
  756.         drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  757.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  758.  
  759.         drm_sysfs_connector_add(connector);
  760.  
  761.         if (I915_HAS_HOTPLUG(dev))
  762.                 connector->polled = DRM_CONNECTOR_POLL_HPD;
  763.         else
  764.                 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  765.  
  766.         /*
  767.          * Configure the automatic hotplug detection stuff
  768.          */
  769.         crt->force_hotplug_required = 0;
  770.  
  771.         dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  772.  
  773.         /*
  774.          * TODO: find a proper way to discover whether we need to set the the
  775.          * polarity and link reversal bits or not, instead of relying on the
  776.          * BIOS.
  777.          */
  778.         if (HAS_PCH_LPT(dev)) {
  779.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  780.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  781.  
  782.                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
  783.         }
  784. }
  785.