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  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43.                            ADPA_CRT_HOTPLUG_ENABLE)
  44.  
  45. struct intel_crt {
  46.         struct intel_encoder base;
  47.         /* DPMS state is stored in the connector, which we need in the
  48.          * encoder's enable/disable callbacks */
  49.         struct intel_connector *connector;
  50.         bool force_hotplug_required;
  51.         u32 adpa_reg;
  52. };
  53.  
  54. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  55. {
  56.         return container_of(intel_attached_encoder(connector),
  57.                             struct intel_crt, base);
  58. }
  59.  
  60. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  61. {
  62.         return container_of(encoder, struct intel_crt, base);
  63. }
  64.  
  65. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  66.                                    enum pipe *pipe)
  67. {
  68.         struct drm_device *dev = encoder->base.dev;
  69.         struct drm_i915_private *dev_priv = dev->dev_private;
  70.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  71.         u32 tmp;
  72.  
  73.         tmp = I915_READ(crt->adpa_reg);
  74.  
  75.         if (!(tmp & ADPA_DAC_ENABLE))
  76.                 return false;
  77.  
  78.         if (HAS_PCH_CPT(dev))
  79.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  80.         else
  81.                 *pipe = PORT_TO_PIPE(tmp);
  82.  
  83.         return true;
  84. }
  85.  
  86. /* Note: The caller is required to filter out dpms modes not supported by the
  87.  * platform. */
  88. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  89. {
  90.         struct drm_device *dev = encoder->base.dev;
  91.         struct drm_i915_private *dev_priv = dev->dev_private;
  92.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  93.         u32 temp;
  94.  
  95.         temp = I915_READ(crt->adpa_reg);
  96.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  97.         temp &= ~ADPA_DAC_ENABLE;
  98.  
  99.         switch (mode) {
  100.         case DRM_MODE_DPMS_ON:
  101.                 temp |= ADPA_DAC_ENABLE;
  102.                 break;
  103.         case DRM_MODE_DPMS_STANDBY:
  104.                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  105.                 break;
  106.         case DRM_MODE_DPMS_SUSPEND:
  107.                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  108.                 break;
  109.         case DRM_MODE_DPMS_OFF:
  110.                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  111.                 break;
  112.         }
  113.  
  114.         I915_WRITE(crt->adpa_reg, temp);
  115. }
  116.  
  117. static void intel_disable_crt(struct intel_encoder *encoder)
  118. {
  119.         intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
  120. }
  121.  
  122. static void intel_enable_crt(struct intel_encoder *encoder)
  123. {
  124.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  125.  
  126.         intel_crt_set_dpms(encoder, crt->connector->base.dpms);
  127. }
  128.  
  129.  
  130. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  131. {
  132.         struct drm_device *dev = connector->dev;
  133.         struct intel_encoder *encoder = intel_attached_encoder(connector);
  134.         struct drm_crtc *crtc;
  135.         int old_dpms;
  136.  
  137.         /* PCH platforms and VLV only support on/off. */
  138.         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  139.                 mode = DRM_MODE_DPMS_OFF;
  140.  
  141.         if (mode == connector->dpms)
  142.                 return;
  143.  
  144.         old_dpms = connector->dpms;
  145.         connector->dpms = mode;
  146.  
  147.         /* Only need to change hw state when actually enabled */
  148.         crtc = encoder->base.crtc;
  149.         if (!crtc) {
  150.                 encoder->connectors_active = false;
  151.                 return;
  152.         }
  153.  
  154.         /* We need the pipe to run for anything but OFF. */
  155.         if (mode == DRM_MODE_DPMS_OFF)
  156.                 encoder->connectors_active = false;
  157.         else
  158.                 encoder->connectors_active = true;
  159.  
  160.         if (mode < old_dpms) {
  161.                 /* From off to on, enable the pipe first. */
  162.                 intel_crtc_update_dpms(crtc);
  163.  
  164.                 intel_crt_set_dpms(encoder, mode);
  165.         } else {
  166.                 intel_crt_set_dpms(encoder, mode);
  167.  
  168.                 intel_crtc_update_dpms(crtc);
  169.         }
  170.  
  171.         intel_modeset_check_state(connector->dev);
  172. }
  173.  
  174. static int intel_crt_mode_valid(struct drm_connector *connector,
  175.                                 struct drm_display_mode *mode)
  176. {
  177.         struct drm_device *dev = connector->dev;
  178.  
  179.         int max_clock = 0;
  180.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  181.                 return MODE_NO_DBLESCAN;
  182.  
  183.         if (mode->clock < 25000)
  184.                 return MODE_CLOCK_LOW;
  185.  
  186.         if (IS_GEN2(dev))
  187.                 max_clock = 350000;
  188.         else
  189.                 max_clock = 400000;
  190.         if (mode->clock > max_clock)
  191.                 return MODE_CLOCK_HIGH;
  192.  
  193.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  194.         if (HAS_PCH_LPT(dev) &&
  195.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  196.                 return MODE_CLOCK_HIGH;
  197.  
  198.         return MODE_OK;
  199. }
  200.  
  201. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  202.                                  const struct drm_display_mode *mode,
  203.                                  struct drm_display_mode *adjusted_mode)
  204. {
  205.         return true;
  206. }
  207.  
  208. static void intel_crt_mode_set(struct drm_encoder *encoder,
  209.                                struct drm_display_mode *mode,
  210.                                struct drm_display_mode *adjusted_mode)
  211. {
  212.  
  213.         struct drm_device *dev = encoder->dev;
  214.         struct drm_crtc *crtc = encoder->crtc;
  215.         struct intel_crt *crt =
  216.                 intel_encoder_to_crt(to_intel_encoder(encoder));
  217.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  218.         struct drm_i915_private *dev_priv = dev->dev_private;
  219.         u32 adpa;
  220.  
  221.         if (HAS_PCH_SPLIT(dev))
  222.         adpa = ADPA_HOTPLUG_BITS;
  223.         else
  224.                 adpa = 0;
  225.  
  226.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  227.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  228.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  229.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  230.  
  231.         /* For CPT allow 3 pipe config, for others just use A or B */
  232.         if (HAS_PCH_LPT(dev))
  233.                 ; /* Those bits don't exist here */
  234.         else if (HAS_PCH_CPT(dev))
  235.                 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  236.         else if (intel_crtc->pipe == 0)
  237.                         adpa |= ADPA_PIPE_A_SELECT;
  238.                 else
  239.                         adpa |= ADPA_PIPE_B_SELECT;
  240.  
  241.         if (!HAS_PCH_SPLIT(dev))
  242.                 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  243.  
  244.         I915_WRITE(crt->adpa_reg, adpa);
  245. }
  246.  
  247. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  248. {
  249.         struct drm_device *dev = connector->dev;
  250.         struct intel_crt *crt = intel_attached_crt(connector);
  251.         struct drm_i915_private *dev_priv = dev->dev_private;
  252.         u32 adpa;
  253.         bool ret;
  254.  
  255.     ENTER();
  256.  
  257.         /* The first time through, trigger an explicit detection cycle */
  258.         if (crt->force_hotplug_required) {
  259.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  260.                 u32 save_adpa;
  261.  
  262.                 crt->force_hotplug_required = 0;
  263.  
  264.                 save_adpa = adpa = I915_READ(crt->adpa_reg);
  265.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  266.  
  267.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  268.                 if (turn_off_dac)
  269.                         adpa &= ~ADPA_DAC_ENABLE;
  270.  
  271.                 I915_WRITE(crt->adpa_reg, adpa);
  272.  
  273.                 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  274.                              1000))
  275.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  276.  
  277.                 if (turn_off_dac) {
  278.                         I915_WRITE(crt->adpa_reg, save_adpa);
  279.                         POSTING_READ(crt->adpa_reg);
  280.                 }
  281.         }
  282.  
  283.         /* Check the status to see if both blue and green are on now */
  284.         adpa = I915_READ(crt->adpa_reg);
  285.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  286.                 ret = true;
  287.         else
  288.                 ret = false;
  289.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  290.  
  291.     LEAVE();
  292.  
  293.         return ret;
  294. }
  295.  
  296. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  297. {
  298.         struct drm_device *dev = connector->dev;
  299.         struct intel_crt *crt = intel_attached_crt(connector);
  300.         struct drm_i915_private *dev_priv = dev->dev_private;
  301.         u32 adpa;
  302.         bool ret;
  303.         u32 save_adpa;
  304.  
  305.     ENTER();
  306.  
  307.         save_adpa = adpa = I915_READ(crt->adpa_reg);
  308.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  309.  
  310.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  311.  
  312.         I915_WRITE(crt->adpa_reg, adpa);
  313.  
  314.         if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  315.                      1000)) {
  316.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  317.                 I915_WRITE(crt->adpa_reg, save_adpa);
  318.         }
  319.  
  320.         /* Check the status to see if both blue and green are on now */
  321.         adpa = I915_READ(crt->adpa_reg);
  322.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  323.                 ret = true;
  324.         else
  325.                 ret = false;
  326.  
  327.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  328.  
  329.         /* FIXME: debug force function and remove */
  330.         ret = true;
  331.  
  332.     LEAVE();
  333.  
  334.         return ret;
  335. }
  336.  
  337. /**
  338.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  339.  *
  340.  * Not for i915G/i915GM
  341.  *
  342.  * \return true if CRT is connected.
  343.  * \return false if CRT is disconnected.
  344.  */
  345. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  346. {
  347.         struct drm_device *dev = connector->dev;
  348.         struct drm_i915_private *dev_priv = dev->dev_private;
  349.         u32 hotplug_en, orig, stat;
  350.         bool ret = false;
  351.         int i, tries = 0;
  352.  
  353.     ENTER();
  354.  
  355.         if (HAS_PCH_SPLIT(dev))
  356.                 return intel_ironlake_crt_detect_hotplug(connector);
  357.  
  358.         if (IS_VALLEYVIEW(dev))
  359.                 return valleyview_crt_detect_hotplug(connector);
  360.  
  361.         /*
  362.          * On 4 series desktop, CRT detect sequence need to be done twice
  363.          * to get a reliable result.
  364.          */
  365.  
  366.         if (IS_G4X(dev) && !IS_GM45(dev))
  367.                 tries = 2;
  368.         else
  369.                 tries = 1;
  370.         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  371.         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  372.  
  373.         for (i = 0; i < tries ; i++) {
  374.                 /* turn on the FORCE_DETECT */
  375.                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  376.                 /* wait for FORCE_DETECT to go off */
  377.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  378.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  379.                              1000))
  380.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  381.         }
  382.  
  383.         stat = I915_READ(PORT_HOTPLUG_STAT);
  384.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  385.                 ret = true;
  386.  
  387.         /* clear the interrupt we just generated, if any */
  388.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  389.  
  390.         /* and put the bits back */
  391.         I915_WRITE(PORT_HOTPLUG_EN, orig);
  392.  
  393.     LEAVE();
  394.  
  395.         return ret;
  396. }
  397.  
  398. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  399.                                 struct i2c_adapter *i2c)
  400. {
  401.         struct edid *edid;
  402.  
  403.     ENTER();
  404.  
  405.         edid = drm_get_edid(connector, i2c);
  406.  
  407.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  408.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  409.                 intel_gmbus_force_bit(i2c, true);
  410.                 edid = drm_get_edid(connector, i2c);
  411.                 intel_gmbus_force_bit(i2c, false);
  412.         }
  413.  
  414.     LEAVE();
  415.  
  416.         return edid;
  417. }
  418.  
  419. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  420. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  421.                                 struct i2c_adapter *adapter)
  422. {
  423.         struct edid *edid;
  424.         int ret;
  425.  
  426.         edid = intel_crt_get_edid(connector, adapter);
  427.         if (!edid)
  428.                 return 0;
  429.  
  430.         ret = intel_connector_update_modes(connector, edid);
  431.         kfree(edid);
  432.  
  433.         return ret;
  434. }
  435.  
  436. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  437. {
  438.         struct intel_crt *crt = intel_attached_crt(connector);
  439.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  440.         struct edid *edid;
  441.         struct i2c_adapter *i2c;
  442.  
  443.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  444.  
  445.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  446.         edid = intel_crt_get_edid(connector, i2c);
  447.  
  448.         if (edid) {
  449.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  450.  
  451.                 /*
  452.                  * This may be a DVI-I connector with a shared DDC
  453.                  * link between analog and digital outputs, so we
  454.                  * have to check the EDID input spec of the attached device.
  455.                  */
  456.                 if (!is_digital) {
  457.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  458.                         return true;
  459.                 }
  460.  
  461.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  462.                 } else {
  463.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  464.                 }
  465.  
  466.         kfree(edid);
  467.  
  468.         return false;
  469. }
  470.  
  471. static enum drm_connector_status
  472. intel_crt_load_detect(struct intel_crt *crt)
  473. {
  474.         struct drm_device *dev = crt->base.base.dev;
  475.         struct drm_i915_private *dev_priv = dev->dev_private;
  476.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  477.         uint32_t save_bclrpat;
  478.         uint32_t save_vtotal;
  479.         uint32_t vtotal, vactive;
  480.         uint32_t vsample;
  481.         uint32_t vblank, vblank_start, vblank_end;
  482.         uint32_t dsl;
  483.         uint32_t bclrpat_reg;
  484.         uint32_t vtotal_reg;
  485.         uint32_t vblank_reg;
  486.         uint32_t vsync_reg;
  487.         uint32_t pipeconf_reg;
  488.         uint32_t pipe_dsl_reg;
  489.         uint8_t st00;
  490.         enum drm_connector_status status;
  491.  
  492.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  493.  
  494.         bclrpat_reg = BCLRPAT(pipe);
  495.         vtotal_reg = VTOTAL(pipe);
  496.         vblank_reg = VBLANK(pipe);
  497.         vsync_reg = VSYNC(pipe);
  498.         pipeconf_reg = PIPECONF(pipe);
  499.         pipe_dsl_reg = PIPEDSL(pipe);
  500.  
  501.         save_bclrpat = I915_READ(bclrpat_reg);
  502.         save_vtotal = I915_READ(vtotal_reg);
  503.         vblank = I915_READ(vblank_reg);
  504.  
  505.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  506.         vactive = (save_vtotal & 0x7ff) + 1;
  507.  
  508.         vblank_start = (vblank & 0xfff) + 1;
  509.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  510.  
  511.         /* Set the border color to purple. */
  512.         I915_WRITE(bclrpat_reg, 0x500050);
  513.  
  514.         if (!IS_GEN2(dev)) {
  515.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  516.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  517.                 POSTING_READ(pipeconf_reg);
  518.                 /* Wait for next Vblank to substitue
  519.                  * border color for Color info */
  520.                 intel_wait_for_vblank(dev, pipe);
  521.                 st00 = I915_READ8(VGA_MSR_WRITE);
  522.                 status = ((st00 & (1 << 4)) != 0) ?
  523.                         connector_status_connected :
  524.                         connector_status_disconnected;
  525.  
  526.                 I915_WRITE(pipeconf_reg, pipeconf);
  527.         } else {
  528.                 bool restore_vblank = false;
  529.                 int count, detect;
  530.  
  531.                 /*
  532.                 * If there isn't any border, add some.
  533.                 * Yes, this will flicker
  534.                 */
  535.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  536.                         uint32_t vsync = I915_READ(vsync_reg);
  537.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  538.  
  539.                         vblank_start = vsync_start;
  540.                         I915_WRITE(vblank_reg,
  541.                                    (vblank_start - 1) |
  542.                                    ((vblank_end - 1) << 16));
  543.                         restore_vblank = true;
  544.                 }
  545.                 /* sample in the vertical border, selecting the larger one */
  546.                 if (vblank_start - vactive >= vtotal - vblank_end)
  547.                         vsample = (vblank_start + vactive) >> 1;
  548.                 else
  549.                         vsample = (vtotal + vblank_end) >> 1;
  550.  
  551.                 /*
  552.                  * Wait for the border to be displayed
  553.                  */
  554.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  555.                         ;
  556.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  557.                         ;
  558.                 /*
  559.                  * Watch ST00 for an entire scanline
  560.                  */
  561.                 detect = 0;
  562.                 count = 0;
  563.                 do {
  564.                         count++;
  565.                         /* Read the ST00 VGA status register */
  566.                         st00 = I915_READ8(VGA_MSR_WRITE);
  567.                         if (st00 & (1 << 4))
  568.                                 detect++;
  569.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  570.  
  571.                 /* restore vblank if necessary */
  572.                 if (restore_vblank)
  573.                         I915_WRITE(vblank_reg, vblank);
  574.                 /*
  575.                  * If more than 3/4 of the scanline detected a monitor,
  576.                  * then it is assumed to be present. This works even on i830,
  577.                  * where there isn't any way to force the border color across
  578.                  * the screen
  579.                  */
  580.                 status = detect * 4 > count * 3 ?
  581.                          connector_status_connected :
  582.                          connector_status_disconnected;
  583.         }
  584.  
  585.         /* Restore previous settings */
  586.         I915_WRITE(bclrpat_reg, save_bclrpat);
  587.  
  588.         return status;
  589. }
  590.  
  591. static enum drm_connector_status
  592. intel_crt_detect(struct drm_connector *connector, bool force)
  593. {
  594.         struct drm_device *dev = connector->dev;
  595.         struct intel_crt *crt = intel_attached_crt(connector);
  596.         enum drm_connector_status status;
  597.         struct intel_load_detect_pipe tmp;
  598.  
  599.         if (I915_HAS_HOTPLUG(dev)) {
  600.                 /* We can not rely on the HPD pin always being correctly wired
  601.                  * up, for example many KVM do not pass it through, and so
  602.                  * only trust an assertion that the monitor is connected.
  603.                  */
  604.                 if (intel_crt_detect_hotplug(connector)) {
  605.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  606.                         return connector_status_connected;
  607.                 } else
  608.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  609.         }
  610.  
  611.         if (intel_crt_detect_ddc(connector))
  612.                 return connector_status_connected;
  613.  
  614.         /* Load detection is broken on HPD capable machines. Whoever wants a
  615.          * broken monitor (without edid) to work behind a broken kvm (that fails
  616.          * to have the right resistors for HP detection) needs to fix this up.
  617.          * For now just bail out. */
  618.         if (I915_HAS_HOTPLUG(dev))
  619.                 return connector_status_disconnected;
  620.  
  621.         if (!force)
  622.                 return connector->status;
  623.  
  624.         /* for pre-945g platforms use load detect */
  625.         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  626.                         if (intel_crt_detect_ddc(connector))
  627.                                 status = connector_status_connected;
  628.                         else
  629.                                 status = intel_crt_load_detect(crt);
  630.                 intel_release_load_detect_pipe(connector, &tmp);
  631.                 } else
  632.                         status = connector_status_unknown;
  633.  
  634.         return status;
  635. }
  636.  
  637. static void intel_crt_destroy(struct drm_connector *connector)
  638. {
  639.         drm_sysfs_connector_remove(connector);
  640.         drm_connector_cleanup(connector);
  641.         kfree(connector);
  642. }
  643.  
  644. static int intel_crt_get_modes(struct drm_connector *connector)
  645. {
  646.         struct drm_device *dev = connector->dev;
  647.         struct drm_i915_private *dev_priv = dev->dev_private;
  648.         int ret;
  649.         struct i2c_adapter *i2c;
  650.  
  651.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  652.         ret = intel_crt_ddc_get_modes(connector, i2c);
  653.         if (ret || !IS_G4X(dev))
  654.                 return ret;
  655.  
  656.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  657.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  658.         return intel_crt_ddc_get_modes(connector, i2c);
  659. }
  660.  
  661. static int intel_crt_set_property(struct drm_connector *connector,
  662.                                   struct drm_property *property,
  663.                                   uint64_t value)
  664. {
  665.         return 0;
  666. }
  667.  
  668. static void intel_crt_reset(struct drm_connector *connector)
  669. {
  670.         struct drm_device *dev = connector->dev;
  671.         struct drm_i915_private *dev_priv = dev->dev_private;
  672.         struct intel_crt *crt = intel_attached_crt(connector);
  673.  
  674.         if (HAS_PCH_SPLIT(dev)) {
  675.                 u32 adpa;
  676.  
  677.                 adpa = I915_READ(crt->adpa_reg);
  678.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  679.                 adpa |= ADPA_HOTPLUG_BITS;
  680.                 I915_WRITE(crt->adpa_reg, adpa);
  681.                 POSTING_READ(crt->adpa_reg);
  682.  
  683.                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  684.                 crt->force_hotplug_required = 1;
  685.         }
  686.  
  687. }
  688.  
  689. /*
  690.  * Routines for controlling stuff on the analog port
  691.  */
  692.  
  693. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  694.         .mode_fixup = intel_crt_mode_fixup,
  695.         .mode_set = intel_crt_mode_set,
  696. };
  697.  
  698. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  699.         .reset = intel_crt_reset,
  700.         .dpms = intel_crt_dpms,
  701.         .detect = intel_crt_detect,
  702.         .fill_modes = drm_helper_probe_single_connector_modes,
  703.         .destroy = intel_crt_destroy,
  704.         .set_property = intel_crt_set_property,
  705. };
  706.  
  707. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  708.         .mode_valid = intel_crt_mode_valid,
  709.         .get_modes = intel_crt_get_modes,
  710.         .best_encoder = intel_best_encoder,
  711. };
  712.  
  713. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  714.         .destroy = intel_encoder_destroy,
  715. };
  716.  
  717. void intel_crt_init(struct drm_device *dev)
  718. {
  719.         struct drm_connector *connector;
  720.         struct intel_crt *crt;
  721.         struct intel_connector *intel_connector;
  722.         struct drm_i915_private *dev_priv = dev->dev_private;
  723.  
  724.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  725.         if (!crt)
  726.                 return;
  727.  
  728.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  729.         if (!intel_connector) {
  730.                 kfree(crt);
  731.                 return;
  732.         }
  733.  
  734.         connector = &intel_connector->base;
  735.         crt->connector = intel_connector;
  736.         drm_connector_init(dev, &intel_connector->base,
  737.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  738.  
  739.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  740.                          DRM_MODE_ENCODER_DAC);
  741.  
  742.         intel_connector_attach_encoder(intel_connector, &crt->base);
  743.  
  744.         crt->base.type = INTEL_OUTPUT_ANALOG;
  745.         crt->base.cloneable = true;
  746.         if (IS_I830(dev))
  747.                 crt->base.crtc_mask = (1 << 0);
  748.         else
  749.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  750.  
  751.         if (IS_GEN2(dev))
  752.                 connector->interlace_allowed = 0;
  753.         else
  754.         connector->interlace_allowed = 1;
  755.         connector->doublescan_allowed = 0;
  756.  
  757.         if (HAS_PCH_SPLIT(dev))
  758.                 crt->adpa_reg = PCH_ADPA;
  759.         else if (IS_VALLEYVIEW(dev))
  760.                 crt->adpa_reg = VLV_ADPA;
  761.         else
  762.                 crt->adpa_reg = ADPA;
  763.  
  764.         crt->base.disable = intel_disable_crt;
  765.         crt->base.enable = intel_enable_crt;
  766.         if (HAS_DDI(dev))
  767.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  768.         else
  769.         crt->base.get_hw_state = intel_crt_get_hw_state;
  770.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  771.  
  772.         drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  773.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  774.  
  775.         drm_sysfs_connector_add(connector);
  776.  
  777.         if (I915_HAS_HOTPLUG(dev))
  778.                 connector->polled = DRM_CONNECTOR_POLL_HPD;
  779.         else
  780.                 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  781.  
  782.         /*
  783.          * Configure the automatic hotplug detection stuff
  784.          */
  785.         crt->force_hotplug_required = 0;
  786.  
  787.         dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  788.  
  789.         /*
  790.          * TODO: find a proper way to discover whether we need to set the the
  791.          * polarity and link reversal bits or not, instead of relying on the
  792.          * BIOS.
  793.          */
  794.         if (HAS_PCH_LPT(dev)) {
  795.                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
  796.                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
  797.  
  798.                 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config;
  799.         }
  800. }
  801.