Subversion Repositories Kolibri OS

Rev

Rev 3120 | Rev 3480 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright © 2006-2007 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21.  * DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *      Eric Anholt <eric@anholt.net>
  25.  */
  26.  
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "intel_drv.h"
  34. #include <drm/i915_drm.h>
  35. #include "i915_drv.h"
  36.  
  37. /* Here's the desired hotplug mode */
  38. #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  39.                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  40.                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  41.                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  42.                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  43.                            ADPA_CRT_HOTPLUG_ENABLE)
  44.  
  45. struct intel_crt {
  46.         struct intel_encoder base;
  47.         bool force_hotplug_required;
  48.         u32 adpa_reg;
  49. };
  50.  
  51. static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
  52. {
  53.         return container_of(intel_attached_encoder(connector),
  54.                             struct intel_crt, base);
  55. }
  56.  
  57. static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  58. {
  59.         return container_of(encoder, struct intel_crt, base);
  60. }
  61.  
  62. static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
  63.                                    enum pipe *pipe)
  64. {
  65.         struct drm_device *dev = encoder->base.dev;
  66.         struct drm_i915_private *dev_priv = dev->dev_private;
  67.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  68.         u32 tmp;
  69.  
  70.         tmp = I915_READ(crt->adpa_reg);
  71.  
  72.         if (!(tmp & ADPA_DAC_ENABLE))
  73.                 return false;
  74.  
  75.         if (HAS_PCH_CPT(dev))
  76.                 *pipe = PORT_TO_PIPE_CPT(tmp);
  77.         else
  78.                 *pipe = PORT_TO_PIPE(tmp);
  79.  
  80.         return true;
  81. }
  82.  
  83. static void intel_disable_crt(struct intel_encoder *encoder)
  84. {
  85.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  86.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  87.         u32 temp;
  88.  
  89.         temp = I915_READ(crt->adpa_reg);
  90.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  91.         temp &= ~ADPA_DAC_ENABLE;
  92.         I915_WRITE(crt->adpa_reg, temp);
  93. }
  94.  
  95. static void intel_enable_crt(struct intel_encoder *encoder)
  96. {
  97.         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  98.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  99.         u32 temp;
  100.  
  101.         temp = I915_READ(crt->adpa_reg);
  102.         temp |= ADPA_DAC_ENABLE;
  103.         I915_WRITE(crt->adpa_reg, temp);
  104. }
  105.  
  106. /* Note: The caller is required to filter out dpms modes not supported by the
  107.  * platform. */
  108. static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
  109. {
  110.         struct drm_device *dev = encoder->base.dev;
  111.         struct drm_i915_private *dev_priv = dev->dev_private;
  112.         struct intel_crt *crt = intel_encoder_to_crt(encoder);
  113.         u32 temp;
  114.  
  115.         temp = I915_READ(crt->adpa_reg);
  116.         temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  117.         temp &= ~ADPA_DAC_ENABLE;
  118.  
  119.         switch (mode) {
  120.         case DRM_MODE_DPMS_ON:
  121.                 temp |= ADPA_DAC_ENABLE;
  122.                 break;
  123.         case DRM_MODE_DPMS_STANDBY:
  124.                 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  125.                 break;
  126.         case DRM_MODE_DPMS_SUSPEND:
  127.                 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  128.                 break;
  129.         case DRM_MODE_DPMS_OFF:
  130.                 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  131.                 break;
  132.         }
  133.  
  134.         I915_WRITE(crt->adpa_reg, temp);
  135. }
  136.  
  137. static void intel_crt_dpms(struct drm_connector *connector, int mode)
  138. {
  139.         struct drm_device *dev = connector->dev;
  140.         struct intel_encoder *encoder = intel_attached_encoder(connector);
  141.         struct drm_crtc *crtc;
  142.         int old_dpms;
  143.  
  144.         /* PCH platforms and VLV only support on/off. */
  145.         if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON)
  146.                 mode = DRM_MODE_DPMS_OFF;
  147.  
  148.         if (mode == connector->dpms)
  149.                 return;
  150.  
  151.         old_dpms = connector->dpms;
  152.         connector->dpms = mode;
  153.  
  154.         /* Only need to change hw state when actually enabled */
  155.         crtc = encoder->base.crtc;
  156.         if (!crtc) {
  157.                 encoder->connectors_active = false;
  158.                 return;
  159.         }
  160.  
  161.         /* We need the pipe to run for anything but OFF. */
  162.         if (mode == DRM_MODE_DPMS_OFF)
  163.                 encoder->connectors_active = false;
  164.         else
  165.                 encoder->connectors_active = true;
  166.  
  167.         if (mode < old_dpms) {
  168.                 /* From off to on, enable the pipe first. */
  169.                 intel_crtc_update_dpms(crtc);
  170.  
  171.                 intel_crt_set_dpms(encoder, mode);
  172.         } else {
  173.                 intel_crt_set_dpms(encoder, mode);
  174.  
  175.                 intel_crtc_update_dpms(crtc);
  176.         }
  177.  
  178.         intel_modeset_check_state(connector->dev);
  179. }
  180.  
  181. static int intel_crt_mode_valid(struct drm_connector *connector,
  182.                                 struct drm_display_mode *mode)
  183. {
  184.         struct drm_device *dev = connector->dev;
  185.  
  186.         int max_clock = 0;
  187.         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  188.                 return MODE_NO_DBLESCAN;
  189.  
  190.         if (mode->clock < 25000)
  191.                 return MODE_CLOCK_LOW;
  192.  
  193.         if (IS_GEN2(dev))
  194.                 max_clock = 350000;
  195.         else
  196.                 max_clock = 400000;
  197.         if (mode->clock > max_clock)
  198.                 return MODE_CLOCK_HIGH;
  199.  
  200.         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
  201.         if (HAS_PCH_LPT(dev) &&
  202.             (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))
  203.                 return MODE_CLOCK_HIGH;
  204.  
  205.         return MODE_OK;
  206. }
  207.  
  208. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  209.                                  const struct drm_display_mode *mode,
  210.                                  struct drm_display_mode *adjusted_mode)
  211. {
  212.         return true;
  213. }
  214.  
  215. static void intel_crt_mode_set(struct drm_encoder *encoder,
  216.                                struct drm_display_mode *mode,
  217.                                struct drm_display_mode *adjusted_mode)
  218. {
  219.  
  220.         struct drm_device *dev = encoder->dev;
  221.         struct drm_crtc *crtc = encoder->crtc;
  222.         struct intel_crt *crt =
  223.                 intel_encoder_to_crt(to_intel_encoder(encoder));
  224.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  225.         struct drm_i915_private *dev_priv = dev->dev_private;
  226.         u32 adpa;
  227.  
  228.         if (HAS_PCH_SPLIT(dev))
  229.         adpa = ADPA_HOTPLUG_BITS;
  230.         else
  231.                 adpa = 0;
  232.  
  233.         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  234.                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  235.         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  236.                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  237.  
  238.         /* For CPT allow 3 pipe config, for others just use A or B */
  239.         if (HAS_PCH_LPT(dev))
  240.                 ; /* Those bits don't exist here */
  241.         else if (HAS_PCH_CPT(dev))
  242.                 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  243.         else if (intel_crtc->pipe == 0)
  244.                         adpa |= ADPA_PIPE_A_SELECT;
  245.                 else
  246.                         adpa |= ADPA_PIPE_B_SELECT;
  247.  
  248.         if (!HAS_PCH_SPLIT(dev))
  249.                 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
  250.  
  251.         I915_WRITE(crt->adpa_reg, adpa);
  252. }
  253.  
  254. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  255. {
  256.         struct drm_device *dev = connector->dev;
  257.         struct intel_crt *crt = intel_attached_crt(connector);
  258.         struct drm_i915_private *dev_priv = dev->dev_private;
  259.         u32 adpa;
  260.         bool ret;
  261.  
  262.         /* The first time through, trigger an explicit detection cycle */
  263.         if (crt->force_hotplug_required) {
  264.                 bool turn_off_dac = HAS_PCH_SPLIT(dev);
  265.                 u32 save_adpa;
  266.  
  267.                 crt->force_hotplug_required = 0;
  268.  
  269.                 save_adpa = adpa = I915_READ(PCH_ADPA);
  270.                 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  271.  
  272.                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  273.                 if (turn_off_dac)
  274.                         adpa &= ~ADPA_DAC_ENABLE;
  275.  
  276.                 I915_WRITE(PCH_ADPA, adpa);
  277.  
  278.                 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  279.                              1000))
  280.                         DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  281.  
  282.                 if (turn_off_dac) {
  283.                         I915_WRITE(PCH_ADPA, save_adpa);
  284.                         POSTING_READ(PCH_ADPA);
  285.                 }
  286.         }
  287.  
  288.         /* Check the status to see if both blue and green are on now */
  289.         adpa = I915_READ(PCH_ADPA);
  290.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  291.                 ret = true;
  292.         else
  293.                 ret = false;
  294.         DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
  295.  
  296.         return ret;
  297. }
  298.  
  299. static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
  300. {
  301.         struct drm_device *dev = connector->dev;
  302.         struct drm_i915_private *dev_priv = dev->dev_private;
  303.         u32 adpa;
  304.         bool ret;
  305.         u32 save_adpa;
  306.  
  307.         save_adpa = adpa = I915_READ(ADPA);
  308.         DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
  309.  
  310.         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
  311.  
  312.         I915_WRITE(ADPA, adpa);
  313.  
  314.         if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  315.                      1000)) {
  316.                 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  317.                 I915_WRITE(ADPA, save_adpa);
  318.         }
  319.  
  320.         /* Check the status to see if both blue and green are on now */
  321.         adpa = I915_READ(ADPA);
  322.         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
  323.                 ret = true;
  324.         else
  325.                 ret = false;
  326.  
  327.         DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
  328.  
  329.         /* FIXME: debug force function and remove */
  330.         ret = true;
  331.  
  332.         return ret;
  333. }
  334.  
  335. /**
  336.  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  337.  *
  338.  * Not for i915G/i915GM
  339.  *
  340.  * \return true if CRT is connected.
  341.  * \return false if CRT is disconnected.
  342.  */
  343. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  344. {
  345.         struct drm_device *dev = connector->dev;
  346.         struct drm_i915_private *dev_priv = dev->dev_private;
  347.         u32 hotplug_en, orig, stat;
  348.         bool ret = false;
  349.         int i, tries = 0;
  350.  
  351.         if (HAS_PCH_SPLIT(dev))
  352.                 return intel_ironlake_crt_detect_hotplug(connector);
  353.  
  354.         if (IS_VALLEYVIEW(dev))
  355.                 return valleyview_crt_detect_hotplug(connector);
  356.  
  357.         /*
  358.          * On 4 series desktop, CRT detect sequence need to be done twice
  359.          * to get a reliable result.
  360.          */
  361.  
  362.         if (IS_G4X(dev) && !IS_GM45(dev))
  363.                 tries = 2;
  364.         else
  365.                 tries = 1;
  366.         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  367.         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  368.  
  369.         for (i = 0; i < tries ; i++) {
  370.                 /* turn on the FORCE_DETECT */
  371.                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  372.                 /* wait for FORCE_DETECT to go off */
  373.                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  374.                               CRT_HOTPLUG_FORCE_DETECT) == 0,
  375.                              1000))
  376.                         DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  377.         }
  378.  
  379.         stat = I915_READ(PORT_HOTPLUG_STAT);
  380.         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  381.                 ret = true;
  382.  
  383.         /* clear the interrupt we just generated, if any */
  384.         I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  385.  
  386.         /* and put the bits back */
  387.         I915_WRITE(PORT_HOTPLUG_EN, orig);
  388.  
  389.         return ret;
  390. }
  391.  
  392. static struct edid *intel_crt_get_edid(struct drm_connector *connector,
  393.                                 struct i2c_adapter *i2c)
  394. {
  395.         struct edid *edid;
  396.  
  397.         edid = drm_get_edid(connector, i2c);
  398.  
  399.         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
  400.                 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
  401.                 intel_gmbus_force_bit(i2c, true);
  402.                 edid = drm_get_edid(connector, i2c);
  403.                 intel_gmbus_force_bit(i2c, false);
  404.         }
  405.  
  406.         return edid;
  407. }
  408.  
  409. /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
  410. static int intel_crt_ddc_get_modes(struct drm_connector *connector,
  411.                                 struct i2c_adapter *adapter)
  412. {
  413.         struct edid *edid;
  414.         int ret;
  415.  
  416.         edid = intel_crt_get_edid(connector, adapter);
  417.         if (!edid)
  418.                 return 0;
  419.  
  420.         ret = intel_connector_update_modes(connector, edid);
  421.         kfree(edid);
  422.  
  423.         return ret;
  424. }
  425.  
  426. static bool intel_crt_detect_ddc(struct drm_connector *connector)
  427. {
  428.         struct intel_crt *crt = intel_attached_crt(connector);
  429.         struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
  430.         struct edid *edid;
  431.         struct i2c_adapter *i2c;
  432.  
  433.         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
  434.  
  435.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  436.         edid = intel_crt_get_edid(connector, i2c);
  437.  
  438.         if (edid) {
  439.                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
  440.  
  441.                 /*
  442.                  * This may be a DVI-I connector with a shared DDC
  443.                  * link between analog and digital outputs, so we
  444.                  * have to check the EDID input spec of the attached device.
  445.                  */
  446.                 if (!is_digital) {
  447.                         DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  448.                         return true;
  449.                 }
  450.  
  451.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
  452.                 } else {
  453.                 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
  454.                 }
  455.  
  456.         kfree(edid);
  457.  
  458.         return false;
  459. }
  460.  
  461. static enum drm_connector_status
  462. intel_crt_load_detect(struct intel_crt *crt)
  463. {
  464.         struct drm_device *dev = crt->base.base.dev;
  465.         struct drm_i915_private *dev_priv = dev->dev_private;
  466.         uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
  467.         uint32_t save_bclrpat;
  468.         uint32_t save_vtotal;
  469.         uint32_t vtotal, vactive;
  470.         uint32_t vsample;
  471.         uint32_t vblank, vblank_start, vblank_end;
  472.         uint32_t dsl;
  473.         uint32_t bclrpat_reg;
  474.         uint32_t vtotal_reg;
  475.         uint32_t vblank_reg;
  476.         uint32_t vsync_reg;
  477.         uint32_t pipeconf_reg;
  478.         uint32_t pipe_dsl_reg;
  479.         uint8_t st00;
  480.         enum drm_connector_status status;
  481.  
  482.         DRM_DEBUG_KMS("starting load-detect on CRT\n");
  483.  
  484.         bclrpat_reg = BCLRPAT(pipe);
  485.         vtotal_reg = VTOTAL(pipe);
  486.         vblank_reg = VBLANK(pipe);
  487.         vsync_reg = VSYNC(pipe);
  488.         pipeconf_reg = PIPECONF(pipe);
  489.         pipe_dsl_reg = PIPEDSL(pipe);
  490.  
  491.         save_bclrpat = I915_READ(bclrpat_reg);
  492.         save_vtotal = I915_READ(vtotal_reg);
  493.         vblank = I915_READ(vblank_reg);
  494.  
  495.         vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  496.         vactive = (save_vtotal & 0x7ff) + 1;
  497.  
  498.         vblank_start = (vblank & 0xfff) + 1;
  499.         vblank_end = ((vblank >> 16) & 0xfff) + 1;
  500.  
  501.         /* Set the border color to purple. */
  502.         I915_WRITE(bclrpat_reg, 0x500050);
  503.  
  504.         if (!IS_GEN2(dev)) {
  505.                 uint32_t pipeconf = I915_READ(pipeconf_reg);
  506.                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  507.                 POSTING_READ(pipeconf_reg);
  508.                 /* Wait for next Vblank to substitue
  509.                  * border color for Color info */
  510.                 intel_wait_for_vblank(dev, pipe);
  511.                 st00 = I915_READ8(VGA_MSR_WRITE);
  512.                 status = ((st00 & (1 << 4)) != 0) ?
  513.                         connector_status_connected :
  514.                         connector_status_disconnected;
  515.  
  516.                 I915_WRITE(pipeconf_reg, pipeconf);
  517.         } else {
  518.                 bool restore_vblank = false;
  519.                 int count, detect;
  520.  
  521.                 /*
  522.                 * If there isn't any border, add some.
  523.                 * Yes, this will flicker
  524.                 */
  525.                 if (vblank_start <= vactive && vblank_end >= vtotal) {
  526.                         uint32_t vsync = I915_READ(vsync_reg);
  527.                         uint32_t vsync_start = (vsync & 0xffff) + 1;
  528.  
  529.                         vblank_start = vsync_start;
  530.                         I915_WRITE(vblank_reg,
  531.                                    (vblank_start - 1) |
  532.                                    ((vblank_end - 1) << 16));
  533.                         restore_vblank = true;
  534.                 }
  535.                 /* sample in the vertical border, selecting the larger one */
  536.                 if (vblank_start - vactive >= vtotal - vblank_end)
  537.                         vsample = (vblank_start + vactive) >> 1;
  538.                 else
  539.                         vsample = (vtotal + vblank_end) >> 1;
  540.  
  541.                 /*
  542.                  * Wait for the border to be displayed
  543.                  */
  544.                 while (I915_READ(pipe_dsl_reg) >= vactive)
  545.                         ;
  546.                 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  547.                         ;
  548.                 /*
  549.                  * Watch ST00 for an entire scanline
  550.                  */
  551.                 detect = 0;
  552.                 count = 0;
  553.                 do {
  554.                         count++;
  555.                         /* Read the ST00 VGA status register */
  556.                         st00 = I915_READ8(VGA_MSR_WRITE);
  557.                         if (st00 & (1 << 4))
  558.                                 detect++;
  559.                 } while ((I915_READ(pipe_dsl_reg) == dsl));
  560.  
  561.                 /* restore vblank if necessary */
  562.                 if (restore_vblank)
  563.                         I915_WRITE(vblank_reg, vblank);
  564.                 /*
  565.                  * If more than 3/4 of the scanline detected a monitor,
  566.                  * then it is assumed to be present. This works even on i830,
  567.                  * where there isn't any way to force the border color across
  568.                  * the screen
  569.                  */
  570.                 status = detect * 4 > count * 3 ?
  571.                          connector_status_connected :
  572.                          connector_status_disconnected;
  573.         }
  574.  
  575.         /* Restore previous settings */
  576.         I915_WRITE(bclrpat_reg, save_bclrpat);
  577.  
  578.         return status;
  579. }
  580.  
  581. static enum drm_connector_status
  582. intel_crt_detect(struct drm_connector *connector, bool force)
  583. {
  584.         struct drm_device *dev = connector->dev;
  585.         struct intel_crt *crt = intel_attached_crt(connector);
  586.         enum drm_connector_status status;
  587.         struct intel_load_detect_pipe tmp;
  588.  
  589.         if (I915_HAS_HOTPLUG(dev)) {
  590.                 /* We can not rely on the HPD pin always being correctly wired
  591.                  * up, for example many KVM do not pass it through, and so
  592.                  * only trust an assertion that the monitor is connected.
  593.                  */
  594.                 if (intel_crt_detect_hotplug(connector)) {
  595.                         DRM_DEBUG_KMS("CRT detected via hotplug\n");
  596.                         return connector_status_connected;
  597.                 } else
  598.                         DRM_DEBUG_KMS("CRT not detected via hotplug\n");
  599.         }
  600.  
  601.         if (intel_crt_detect_ddc(connector))
  602.                 return connector_status_connected;
  603.  
  604.         /* Load detection is broken on HPD capable machines. Whoever wants a
  605.          * broken monitor (without edid) to work behind a broken kvm (that fails
  606.          * to have the right resistors for HP detection) needs to fix this up.
  607.          * For now just bail out. */
  608.         if (I915_HAS_HOTPLUG(dev))
  609.                 return connector_status_disconnected;
  610.  
  611.         if (!force)
  612.                 return connector->status;
  613.  
  614.         /* for pre-945g platforms use load detect */
  615.         if (intel_get_load_detect_pipe(connector, NULL, &tmp)) {
  616.                         if (intel_crt_detect_ddc(connector))
  617.                                 status = connector_status_connected;
  618.                         else
  619.                                 status = intel_crt_load_detect(crt);
  620.                 intel_release_load_detect_pipe(connector, &tmp);
  621.                 } else
  622.                         status = connector_status_unknown;
  623.  
  624.         return status;
  625. }
  626.  
  627. static void intel_crt_destroy(struct drm_connector *connector)
  628. {
  629.         drm_sysfs_connector_remove(connector);
  630.         drm_connector_cleanup(connector);
  631.         kfree(connector);
  632. }
  633.  
  634. static int intel_crt_get_modes(struct drm_connector *connector)
  635. {
  636.         struct drm_device *dev = connector->dev;
  637.         struct drm_i915_private *dev_priv = dev->dev_private;
  638.         int ret;
  639.         struct i2c_adapter *i2c;
  640.  
  641.         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
  642.         ret = intel_crt_ddc_get_modes(connector, i2c);
  643.         if (ret || !IS_G4X(dev))
  644.                 return ret;
  645.  
  646.         /* Try to probe digital port for output in DVI-I -> VGA mode. */
  647.         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  648.         return intel_crt_ddc_get_modes(connector, i2c);
  649. }
  650.  
  651. static int intel_crt_set_property(struct drm_connector *connector,
  652.                                   struct drm_property *property,
  653.                                   uint64_t value)
  654. {
  655.         return 0;
  656. }
  657.  
  658. static void intel_crt_reset(struct drm_connector *connector)
  659. {
  660.         struct drm_device *dev = connector->dev;
  661.         struct drm_i915_private *dev_priv = dev->dev_private;
  662.         struct intel_crt *crt = intel_attached_crt(connector);
  663.  
  664.         if (HAS_PCH_SPLIT(dev)) {
  665.                 u32 adpa;
  666.  
  667.                 adpa = I915_READ(PCH_ADPA);
  668.                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  669.                 adpa |= ADPA_HOTPLUG_BITS;
  670.                 I915_WRITE(PCH_ADPA, adpa);
  671.                 POSTING_READ(PCH_ADPA);
  672.  
  673.                 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
  674.                 crt->force_hotplug_required = 1;
  675.         }
  676.  
  677. }
  678.  
  679. /*
  680.  * Routines for controlling stuff on the analog port
  681.  */
  682.  
  683. static const struct drm_encoder_helper_funcs crt_encoder_funcs = {
  684.         .mode_fixup = intel_crt_mode_fixup,
  685.         .mode_set = intel_crt_mode_set,
  686.         .disable = intel_encoder_noop,
  687. };
  688.  
  689. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  690.         .reset = intel_crt_reset,
  691.         .dpms = intel_crt_dpms,
  692.         .detect = intel_crt_detect,
  693.         .fill_modes = drm_helper_probe_single_connector_modes,
  694.         .destroy = intel_crt_destroy,
  695.         .set_property = intel_crt_set_property,
  696. };
  697.  
  698. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  699.         .mode_valid = intel_crt_mode_valid,
  700.         .get_modes = intel_crt_get_modes,
  701.         .best_encoder = intel_best_encoder,
  702. };
  703.  
  704. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  705.         .destroy = intel_encoder_destroy,
  706. };
  707.  
  708. void intel_crt_init(struct drm_device *dev)
  709. {
  710.         struct drm_connector *connector;
  711.         struct intel_crt *crt;
  712.         struct intel_connector *intel_connector;
  713.         struct drm_i915_private *dev_priv = dev->dev_private;
  714.  
  715.         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
  716.         if (!crt)
  717.                 return;
  718.  
  719.         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  720.         if (!intel_connector) {
  721.                 kfree(crt);
  722.                 return;
  723.         }
  724.  
  725.         connector = &intel_connector->base;
  726.         drm_connector_init(dev, &intel_connector->base,
  727.                            &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  728.  
  729.         drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
  730.                          DRM_MODE_ENCODER_DAC);
  731.  
  732.         intel_connector_attach_encoder(intel_connector, &crt->base);
  733.  
  734.         crt->base.type = INTEL_OUTPUT_ANALOG;
  735.         crt->base.cloneable = true;
  736.         if (IS_I830(dev))
  737.                 crt->base.crtc_mask = (1 << 0);
  738.         else
  739.                 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  740.  
  741.         if (IS_GEN2(dev))
  742.                 connector->interlace_allowed = 0;
  743.         else
  744.         connector->interlace_allowed = 1;
  745.         connector->doublescan_allowed = 0;
  746.  
  747.         if (HAS_PCH_SPLIT(dev))
  748.                 crt->adpa_reg = PCH_ADPA;
  749.         else if (IS_VALLEYVIEW(dev))
  750.                 crt->adpa_reg = VLV_ADPA;
  751.         else
  752.                 crt->adpa_reg = ADPA;
  753.  
  754.         crt->base.disable = intel_disable_crt;
  755.         crt->base.enable = intel_enable_crt;
  756.         if (IS_HASWELL(dev))
  757.                 crt->base.get_hw_state = intel_ddi_get_hw_state;
  758.         else
  759.         crt->base.get_hw_state = intel_crt_get_hw_state;
  760.         intel_connector->get_hw_state = intel_connector_get_hw_state;
  761.  
  762.         drm_encoder_helper_add(&crt->base.base, &crt_encoder_funcs);
  763.         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  764.  
  765.         drm_sysfs_connector_add(connector);
  766.  
  767.         if (I915_HAS_HOTPLUG(dev))
  768.                 connector->polled = DRM_CONNECTOR_POLL_HPD;
  769.         else
  770.                 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  771.  
  772.         /*
  773.          * Configure the automatic hotplug detection stuff
  774.          */
  775.         crt->force_hotplug_required = 0;
  776.  
  777.         dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  778.  
  779.         /*
  780.          * TODO: find a proper way to discover whether we need to set the
  781.          * polarity reversal bit or not, instead of relying on the BIOS.
  782.          */
  783.         if (HAS_PCH_LPT(dev))
  784.                 dev_priv->fdi_rx_polarity_reversed =
  785.                      !!(I915_READ(_FDI_RXA_CTL) & FDI_RX_POLARITY_REVERSED_LPT);
  786. }
  787.