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  1. /*
  2.  * Copyright ะน 2006 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #ifndef _I830_BIOS_H_
  29. #define _I830_BIOS_H_
  30.  
  31. #include "drmP.h"
  32.  
  33. struct vbt_header {
  34.         u8 signature[20];               /**< Always starts with 'VBT$' */
  35.         u16 version;                    /**< decimal */
  36.         u16 header_size;                /**< in bytes */
  37.         u16 vbt_size;                   /**< in bytes */
  38.         u8 vbt_checksum;
  39.         u8 reserved0;
  40.         u32 bdb_offset;                 /**< from beginning of VBT */
  41.         u32 aim_offset[4];              /**< from beginning of VBT */
  42. } __attribute__((packed));
  43.  
  44. struct bdb_header {
  45.         u8 signature[16];               /**< Always 'BIOS_DATA_BLOCK' */
  46.         u16 version;                    /**< decimal */
  47.         u16 header_size;                /**< in bytes */
  48.         u16 bdb_size;                   /**< in bytes */
  49. };
  50.  
  51. /* strictly speaking, this is a "skip" block, but it has interesting info */
  52. struct vbios_data {
  53.         u8 type; /* 0 == desktop, 1 == mobile */
  54.         u8 relstage;
  55.         u8 chipset;
  56.         u8 lvds_present:1;
  57.         u8 tv_present:1;
  58.         u8 rsvd2:6; /* finish byte */
  59.         u8 rsvd3[4];
  60.         u8 signon[155];
  61.         u8 copyright[61];
  62.         u16 code_segment;
  63.         u8 dos_boot_mode;
  64.         u8 bandwidth_percent;
  65.         u8 rsvd4; /* popup memory size */
  66.         u8 resize_pci_bios;
  67.         u8 rsvd5; /* is crt already on ddc2 */
  68. } __attribute__((packed));
  69.  
  70. /*
  71.  * There are several types of BIOS data blocks (BDBs), each block has
  72.  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  73.  * Known types are listed below.
  74.  */
  75. #define BDB_GENERAL_FEATURES      1
  76. #define BDB_GENERAL_DEFINITIONS   2
  77. #define BDB_OLD_TOGGLE_LIST       3
  78. #define BDB_MODE_SUPPORT_LIST     4
  79. #define BDB_GENERIC_MODE_TABLE    5
  80. #define BDB_EXT_MMIO_REGS         6
  81. #define BDB_SWF_IO                7
  82. #define BDB_SWF_MMIO              8
  83. #define BDB_DOT_CLOCK_TABLE       9
  84. #define BDB_MODE_REMOVAL_TABLE   10
  85. #define BDB_CHILD_DEVICE_TABLE   11
  86. #define BDB_DRIVER_FEATURES      12
  87. #define BDB_DRIVER_PERSISTENCE   13
  88. #define BDB_EXT_TABLE_PTRS       14
  89. #define BDB_DOT_CLOCK_OVERRIDE   15
  90. #define BDB_DISPLAY_SELECT       16
  91. /* 17 rsvd */
  92. #define BDB_DRIVER_ROTATION      18
  93. #define BDB_DISPLAY_REMOVE       19
  94. #define BDB_OEM_CUSTOM           20
  95. #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
  96. #define BDB_SDVO_LVDS_OPTIONS    22
  97. #define BDB_SDVO_PANEL_DTDS      23
  98. #define BDB_SDVO_LVDS_PNP_IDS    24
  99. #define BDB_SDVO_LVDS_POWER_SEQ  25
  100. #define BDB_TV_OPTIONS           26
  101. #define BDB_EDP                  27
  102. #define BDB_LVDS_OPTIONS         40
  103. #define BDB_LVDS_LFP_DATA_PTRS   41
  104. #define BDB_LVDS_LFP_DATA        42
  105. #define BDB_LVDS_BACKLIGHT       43
  106. #define BDB_LVDS_POWER           44
  107. #define BDB_SKIP                254 /* VBIOS private block, ignore */
  108.  
  109. struct bdb_general_features {
  110.         /* bits 1 */
  111.         u8 panel_fitting:2;
  112.         u8 flexaim:1;
  113.         u8 msg_enable:1;
  114.         u8 clear_screen:3;
  115.         u8 color_flip:1;
  116.  
  117.         /* bits 2 */
  118.         u8 download_ext_vbt:1;
  119.         u8 enable_ssc:1;
  120.         u8 ssc_freq:1;
  121.         u8 enable_lfp_on_override:1;
  122.         u8 disable_ssc_ddt:1;
  123.         u8 rsvd8:3; /* finish byte */
  124.  
  125.         /* bits 3 */
  126.         u8 disable_smooth_vision:1;
  127.         u8 single_dvi:1;
  128.         u8 rsvd9:6; /* finish byte */
  129.  
  130.         /* bits 4 */
  131.         u8 legacy_monitor_detect;
  132.  
  133.         /* bits 5 */
  134.         u8 int_crt_support:1;
  135.         u8 int_tv_support:1;
  136.         u8 rsvd11:6; /* finish byte */
  137. } __attribute__((packed));
  138.  
  139. /* pre-915 */
  140. #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
  141. #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
  142. #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
  143. #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
  144.  
  145. /* Pre 915 */
  146. #define DEVICE_TYPE_NONE        0x00
  147. #define DEVICE_TYPE_CRT         0x01
  148. #define DEVICE_TYPE_TV          0x09
  149. #define DEVICE_TYPE_EFP         0x12
  150. #define DEVICE_TYPE_LFP         0x22
  151. /* On 915+ */
  152. #define DEVICE_TYPE_CRT_DPMS            0x6001
  153. #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
  154. #define DEVICE_TYPE_TV_COMPOSITE        0x0209
  155. #define DEVICE_TYPE_TV_MACROVISION      0x0289
  156. #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
  157. #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
  158. #define DEVICE_TYPE_TV_SCART            0x0209
  159. #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
  160. #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
  161. #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
  162. #define DEVICE_TYPE_EFP_DVI_I           0x6053
  163. #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
  164. #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
  165. #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
  166. #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
  167. #define DEVICE_TYPE_LFP_PANELLINK       0x5012
  168. #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
  169. #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
  170. #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
  171. #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
  172.  
  173. #define DEVICE_CFG_NONE         0x00
  174. #define DEVICE_CFG_12BIT_DVOB   0x01
  175. #define DEVICE_CFG_12BIT_DVOC   0x02
  176. #define DEVICE_CFG_24BIT_DVOBC  0x09
  177. #define DEVICE_CFG_24BIT_DVOCB  0x0a
  178. #define DEVICE_CFG_DUAL_DVOB    0x11
  179. #define DEVICE_CFG_DUAL_DVOC    0x12
  180. #define DEVICE_CFG_DUAL_DVOBC   0x13
  181. #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
  182. #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
  183.  
  184. #define DEVICE_WIRE_NONE        0x00
  185. #define DEVICE_WIRE_DVOB        0x01
  186. #define DEVICE_WIRE_DVOC        0x02
  187. #define DEVICE_WIRE_DVOBC       0x03
  188. #define DEVICE_WIRE_DVOBB       0x05
  189. #define DEVICE_WIRE_DVOCC       0x06
  190. #define DEVICE_WIRE_DVOB_MASTER 0x0d
  191. #define DEVICE_WIRE_DVOC_MASTER 0x0e
  192.  
  193. #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
  194. #define DEVICE_PORT_DVOB        0x01
  195. #define DEVICE_PORT_DVOC        0x02
  196.  
  197. struct child_device_config {
  198.         u16 handle;
  199.         u16 device_type;
  200.         u8  i2c_speed;
  201.         u8  rsvd[9];
  202.         u16 addin_offset;
  203.         u8  dvo_port; /* See Device_PORT_* above */
  204.         u8  i2c_pin;
  205.         u8  slave_addr;
  206.         u8  ddc_pin;
  207.         u16 edid_ptr;
  208.         u8  dvo_cfg; /* See DEVICE_CFG_* above */
  209.         u8  dvo2_port;
  210.         u8  i2c2_pin;
  211.         u8  slave2_addr;
  212.         u8  ddc2_pin;
  213.         u8  capabilities;
  214.         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
  215.         u8  dvo2_wiring;
  216.         u16 extended_type;
  217.         u8  dvo_function;
  218. } __attribute__((packed));
  219.  
  220. struct bdb_general_definitions {
  221.         /* DDC GPIO */
  222.         u8 crt_ddc_gmbus_pin;
  223.  
  224.         /* DPMS bits */
  225.         u8 dpms_acpi:1;
  226.         u8 skip_boot_crt_detect:1;
  227.         u8 dpms_aim:1;
  228.         u8 rsvd1:5; /* finish byte */
  229.  
  230.         /* boot device bits */
  231.         u8 boot_display[2];
  232.         u8 child_dev_size;
  233.  
  234.         /*
  235.          * Device info:
  236.          * If TV is present, it'll be at devices[0].
  237.          * LVDS will be next, either devices[0] or [1], if present.
  238.          * On some platforms the number of device is 6. But could be as few as
  239.          * 4 if both TV and LVDS are missing.
  240.          * And the device num is related with the size of general definition
  241.          * block. It is obtained by using the following formula:
  242.          * number = (block_size - sizeof(bdb_general_definitions))/
  243.          *              sizeof(child_device_config);
  244.          */
  245.         struct child_device_config devices[0];
  246. } __attribute__((packed));
  247.  
  248. struct bdb_lvds_options {
  249.         u8 panel_type;
  250.         u8 rsvd1;
  251.         /* LVDS capabilities, stored in a dword */
  252.         u8 pfit_mode:2;
  253.         u8 pfit_text_mode_enhanced:1;
  254.         u8 pfit_gfx_mode_enhanced:1;
  255.         u8 pfit_ratio_auto:1;
  256.         u8 pixel_dither:1;
  257.         u8 lvds_edid:1;
  258.         u8 rsvd2:1;
  259.         u8 rsvd4;
  260. } __attribute__((packed));
  261.  
  262. /* LFP pointer table contains entries to the struct below */
  263. struct bdb_lvds_lfp_data_ptr {
  264.         u16 fp_timing_offset; /* offsets are from start of bdb */
  265.         u8 fp_table_size;
  266.         u16 dvo_timing_offset;
  267.         u8 dvo_table_size;
  268.         u16 panel_pnp_id_offset;
  269.         u8 pnp_table_size;
  270. } __attribute__((packed));
  271.  
  272. struct bdb_lvds_lfp_data_ptrs {
  273.         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
  274.         struct bdb_lvds_lfp_data_ptr ptr[16];
  275. } __attribute__((packed));
  276.  
  277. /* LFP data has 3 blocks per entry */
  278. struct lvds_fp_timing {
  279.         u16 x_res;
  280.         u16 y_res;
  281.         u32 lvds_reg;
  282.         u32 lvds_reg_val;
  283.         u32 pp_on_reg;
  284.         u32 pp_on_reg_val;
  285.         u32 pp_off_reg;
  286.         u32 pp_off_reg_val;
  287.         u32 pp_cycle_reg;
  288.         u32 pp_cycle_reg_val;
  289.         u32 pfit_reg;
  290.         u32 pfit_reg_val;
  291.         u16 terminator;
  292. } __attribute__((packed));
  293.  
  294. struct lvds_dvo_timing {
  295.         u16 clock;              /**< In 10khz */
  296.         u8 hactive_lo;
  297.         u8 hblank_lo;
  298.         u8 hblank_hi:4;
  299.         u8 hactive_hi:4;
  300.         u8 vactive_lo;
  301.         u8 vblank_lo;
  302.         u8 vblank_hi:4;
  303.         u8 vactive_hi:4;
  304.         u8 hsync_off_lo;
  305.         u8 hsync_pulse_width;
  306.         u8 vsync_pulse_width:4;
  307.         u8 vsync_off:4;
  308.         u8 rsvd0:6;
  309.         u8 hsync_off_hi:2;
  310.         u8 h_image;
  311.         u8 v_image;
  312.         u8 max_hv;
  313.         u8 h_border;
  314.         u8 v_border;
  315.         u8 rsvd1:3;
  316.         u8 digital:2;
  317.         u8 vsync_positive:1;
  318.         u8 hsync_positive:1;
  319.         u8 rsvd2:1;
  320. } __attribute__((packed));
  321.  
  322. struct lvds_pnp_id {
  323.         u16 mfg_name;
  324.         u16 product_code;
  325.         u32 serial;
  326.         u8 mfg_week;
  327.         u8 mfg_year;
  328. } __attribute__((packed));
  329.  
  330. struct bdb_lvds_lfp_data_entry {
  331.         struct lvds_fp_timing fp_timing;
  332.         struct lvds_dvo_timing dvo_timing;
  333.         struct lvds_pnp_id pnp_id;
  334. } __attribute__((packed));
  335.  
  336. struct bdb_lvds_lfp_data {
  337.         struct bdb_lvds_lfp_data_entry data[16];
  338. } __attribute__((packed));
  339.  
  340. struct aimdb_header {
  341.         char signature[16];
  342.         char oem_device[20];
  343.         u16 aimdb_version;
  344.         u16 aimdb_header_size;
  345.         u16 aimdb_size;
  346. } __attribute__((packed));
  347.  
  348. struct aimdb_block {
  349.         u8 aimdb_id;
  350.         u16 aimdb_size;
  351. } __attribute__((packed));
  352.  
  353. struct vch_panel_data {
  354.         u16 fp_timing_offset;
  355.         u8 fp_timing_size;
  356.         u16 dvo_timing_offset;
  357.         u8 dvo_timing_size;
  358.         u16 text_fitting_offset;
  359.         u8 text_fitting_size;
  360.         u16 graphics_fitting_offset;
  361.         u8 graphics_fitting_size;
  362. } __attribute__((packed));
  363.  
  364. struct vch_bdb_22 {
  365.         struct aimdb_block aimdb_block;
  366.         struct vch_panel_data panels[16];
  367. } __attribute__((packed));
  368.  
  369. struct bdb_sdvo_lvds_options {
  370.         u8 panel_backlight;
  371.         u8 h40_set_panel_type;
  372.         u8 panel_type;
  373.         u8 ssc_clk_freq;
  374.         u16 als_low_trip;
  375.         u16 als_high_trip;
  376.         u8 sclalarcoeff_tab_row_num;
  377.         u8 sclalarcoeff_tab_row_size;
  378.         u8 coefficient[8];
  379.         u8 panel_misc_bits_1;
  380.         u8 panel_misc_bits_2;
  381.         u8 panel_misc_bits_3;
  382.         u8 panel_misc_bits_4;
  383. } __attribute__((packed));
  384.  
  385.  
  386. #define BDB_DRIVER_FEATURE_NO_LVDS              0
  387. #define BDB_DRIVER_FEATURE_INT_LVDS             1
  388. #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
  389. #define BDB_DRIVER_FEATURE_EDP                  3
  390.  
  391. struct bdb_driver_features {
  392.         u8 boot_dev_algorithm:1;
  393.         u8 block_display_switch:1;
  394.         u8 allow_display_switch:1;
  395.         u8 hotplug_dvo:1;
  396.         u8 dual_view_zoom:1;
  397.         u8 int15h_hook:1;
  398.         u8 sprite_in_clone:1;
  399.         u8 primary_lfp_id:1;
  400.  
  401.         u16 boot_mode_x;
  402.         u16 boot_mode_y;
  403.         u8 boot_mode_bpp;
  404.         u8 boot_mode_refresh;
  405.  
  406.         u16 enable_lfp_primary:1;
  407.         u16 selective_mode_pruning:1;
  408.         u16 dual_frequency:1;
  409.         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
  410.         u16 nt_clone_support:1;
  411.         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
  412.         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
  413.         u16 cui_aspect_scaling:1;
  414.         u16 preserve_aspect_ratio:1;
  415.         u16 sdvo_device_power_down:1;
  416.         u16 crt_hotplug:1;
  417.         u16 lvds_config:2;
  418.         u16 tv_hotplug:1;
  419.         u16 hdmi_config:2;
  420.  
  421.         u8 static_display:1;
  422.         u8 reserved2:7;
  423.         u16 legacy_crt_max_x;
  424.         u16 legacy_crt_max_y;
  425.         u8 legacy_crt_max_refresh;
  426.  
  427.         u8 hdmi_termination;
  428.         u8 custom_vbt_version;
  429. } __attribute__((packed));
  430.  
  431. #define EDP_18BPP       0
  432. #define EDP_24BPP       1
  433. #define EDP_30BPP       2
  434. #define EDP_RATE_1_62   0
  435. #define EDP_RATE_2_7    1
  436. #define EDP_LANE_1      0
  437. #define EDP_LANE_2      1
  438. #define EDP_LANE_4      3
  439. #define EDP_PREEMPHASIS_NONE    0
  440. #define EDP_PREEMPHASIS_3_5dB   1
  441. #define EDP_PREEMPHASIS_6dB     2
  442. #define EDP_PREEMPHASIS_9_5dB   3
  443. #define EDP_VSWING_0_4V         0
  444. #define EDP_VSWING_0_6V         1
  445. #define EDP_VSWING_0_8V         2
  446. #define EDP_VSWING_1_2V         3
  447.  
  448. struct edp_power_seq {
  449.         u16 t3;
  450.         u16 t7;
  451.         u16 t9;
  452.         u16 t10;
  453.         u16 t12;
  454. } __attribute__ ((packed));
  455.  
  456. struct edp_link_params {
  457.         u8 rate:4;
  458.         u8 lanes:4;
  459.         u8 preemphasis:4;
  460.         u8 vswing:4;
  461. } __attribute__ ((packed));
  462.  
  463. struct bdb_edp {
  464.         struct edp_power_seq power_seqs[16];
  465.         u32 color_depth;
  466.         u32 sdrrs_msa_timing_delay;
  467.         struct edp_link_params link_params[16];
  468. } __attribute__ ((packed));
  469.  
  470. void intel_setup_bios(struct drm_device *dev);
  471. bool intel_parse_bios(struct drm_device *dev);
  472.  
  473. /*
  474.  * Driver<->VBIOS interaction occurs through scratch bits in
  475.  * GR18 & SWF*.
  476.  */
  477.  
  478. /* GR18 bits are set on display switch and hotkey events */
  479. #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
  480. #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
  481. #define   GR18_HK_NONE          (0x0<<3)
  482. #define   GR18_HK_LFP_STRETCH   (0x1<<3)
  483. #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
  484. #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
  485. #define   GR18_HK_POPUP_DISABLED (0x6<<3)
  486. #define   GR18_HK_POPUP_ENABLED (0x7<<3)
  487. #define   GR18_HK_PFIT          (0x8<<3)
  488. #define   GR18_HK_APM_CHANGE    (0xa<<3)
  489. #define   GR18_HK_MULTIPLE      (0xc<<3)
  490. #define GR18_USER_INT_EN        (1<<2)
  491. #define GR18_A0000_FLUSH_EN     (1<<1)
  492. #define GR18_SMM_EN             (1<<0)
  493.  
  494. /* Set by driver, cleared by VBIOS */
  495. #define SWF00_YRES_SHIFT        16
  496. #define SWF00_XRES_SHIFT        0
  497. #define SWF00_RES_MASK          0xffff
  498.  
  499. /* Set by VBIOS at boot time and driver at runtime */
  500. #define SWF01_TV2_FORMAT_SHIFT  8
  501. #define SWF01_TV1_FORMAT_SHIFT  0
  502. #define SWF01_TV_FORMAT_MASK    0xffff
  503.  
  504. #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
  505. #define SWF10_GTT_OVERRIDE_EN   (1<<28)
  506. #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
  507. #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
  508. #define   SWF10_OLD_TOGGLE      0x0
  509. #define   SWF10_TOGGLE_LIST_1   0x1
  510. #define   SWF10_TOGGLE_LIST_2   0x2
  511. #define   SWF10_TOGGLE_LIST_3   0x3
  512. #define   SWF10_TOGGLE_LIST_4   0x4
  513. #define SWF10_PANNING_EN        (1<<23)
  514. #define SWF10_DRIVER_LOADED     (1<<22)
  515. #define SWF10_EXTENDED_DESKTOP  (1<<21)
  516. #define SWF10_EXCLUSIVE_MODE    (1<<20)
  517. #define SWF10_OVERLAY_EN        (1<<19)
  518. #define SWF10_PLANEB_HOLDOFF    (1<<18)
  519. #define SWF10_PLANEA_HOLDOFF    (1<<17)
  520. #define SWF10_VGA_HOLDOFF       (1<<16)
  521. #define SWF10_ACTIVE_DISP_MASK  0xffff
  522. #define   SWF10_PIPEB_LFP2      (1<<15)
  523. #define   SWF10_PIPEB_EFP2      (1<<14)
  524. #define   SWF10_PIPEB_TV2       (1<<13)
  525. #define   SWF10_PIPEB_CRT2      (1<<12)
  526. #define   SWF10_PIPEB_LFP       (1<<11)
  527. #define   SWF10_PIPEB_EFP       (1<<10)
  528. #define   SWF10_PIPEB_TV        (1<<9)
  529. #define   SWF10_PIPEB_CRT       (1<<8)
  530. #define   SWF10_PIPEA_LFP2      (1<<7)
  531. #define   SWF10_PIPEA_EFP2      (1<<6)
  532. #define   SWF10_PIPEA_TV2       (1<<5)
  533. #define   SWF10_PIPEA_CRT2      (1<<4)
  534. #define   SWF10_PIPEA_LFP       (1<<3)
  535. #define   SWF10_PIPEA_EFP       (1<<2)
  536. #define   SWF10_PIPEA_TV        (1<<1)
  537. #define   SWF10_PIPEA_CRT       (1<<0)
  538.  
  539. #define SWF11_MEMORY_SIZE_SHIFT 16
  540. #define SWF11_SV_TEST_EN        (1<<15)
  541. #define SWF11_IS_AGP            (1<<14)
  542. #define SWF11_DISPLAY_HOLDOFF   (1<<13)
  543. #define SWF11_DPMS_REDUCED      (1<<12)
  544. #define SWF11_IS_VBE_MODE       (1<<11)
  545. #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
  546. #define SWF11_DPMS_MASK         0x07
  547. #define   SWF11_DPMS_OFF        (1<<2)
  548. #define   SWF11_DPMS_SUSPEND    (1<<1)
  549. #define   SWF11_DPMS_STANDBY    (1<<0)
  550. #define   SWF11_DPMS_ON         0
  551.  
  552. #define SWF14_GFX_PFIT_EN       (1<<31)
  553. #define SWF14_TEXT_PFIT_EN      (1<<30)
  554. #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
  555. #define SWF14_POPUP_EN          (1<<28)
  556. #define SWF14_DISPLAY_HOLDOFF   (1<<27)
  557. #define SWF14_DISP_DETECT_EN    (1<<26)
  558. #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
  559. #define SWF14_DRIVER_STATUS     (1<<24)
  560. #define SWF14_OS_TYPE_WIN9X     (1<<23)
  561. #define SWF14_OS_TYPE_WINNT     (1<<22)
  562. /* 21:19 rsvd */
  563. #define SWF14_PM_TYPE_MASK      0x00070000
  564. #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
  565. #define   SWF14_PM_ACPI         (0x3 << 16)
  566. #define   SWF14_PM_APM_12       (0x2 << 16)
  567. #define   SWF14_PM_APM_11       (0x1 << 16)
  568. #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
  569.           /* if GR18 indicates a display switch */
  570. #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
  571. #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
  572. #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
  573. #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
  574. #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
  575. #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
  576. #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
  577. #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
  578. #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
  579. #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
  580. #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
  581. #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
  582. #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
  583. #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
  584. #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
  585. #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
  586.           /* if GR18 indicates a panel fitting request */
  587. #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
  588.           /* if GR18 indicates an APM change request */
  589. #define   SWF14_APM_HIBERNATE   0x4
  590. #define   SWF14_APM_SUSPEND     0x3
  591. #define   SWF14_APM_STANDBY     0x1
  592. #define   SWF14_APM_RESTORE     0x0
  593.  
  594. /* Add the device class for LFP, TV, HDMI */
  595. #define  DEVICE_TYPE_INT_LFP    0x1022
  596. #define  DEVICE_TYPE_INT_TV     0x1009
  597. #define  DEVICE_TYPE_HDMI       0x60D2
  598. #define  DEVICE_TYPE_DP         0x68C6
  599. #define  DEVICE_TYPE_eDP        0x78C6
  600.  
  601. /* define the DVO port for HDMI output type */
  602. #define         DVO_B           1
  603. #define         DVO_C           2
  604. #define         DVO_D           3
  605.  
  606. /* define the PORT for DP output type */
  607. #define         PORT_IDPB       7
  608. #define         PORT_IDPC       8
  609. #define         PORT_IDPD       9
  610.  
  611. #endif /* _I830_BIOS_H_ */
  612.