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  1. /*
  2.  * Copyright © 2006 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #ifndef _I830_BIOS_H_
  29. #define _I830_BIOS_H_
  30.  
  31. #include "drmP.h"
  32.  
  33. struct vbt_header {
  34.         u8 signature[20];               /**< Always starts with 'VBT$' */
  35.         u16 version;                    /**< decimal */
  36.         u16 header_size;                /**< in bytes */
  37.         u16 vbt_size;                   /**< in bytes */
  38.         u8 vbt_checksum;
  39.         u8 reserved0;
  40.         u32 bdb_offset;                 /**< from beginning of VBT */
  41.         u32 aim_offset[4];              /**< from beginning of VBT */
  42. } __attribute__((packed));
  43.  
  44. struct bdb_header {
  45.         u8 signature[16];               /**< Always 'BIOS_DATA_BLOCK' */
  46.         u16 version;                    /**< decimal */
  47.         u16 header_size;                /**< in bytes */
  48.         u16 bdb_size;                   /**< in bytes */
  49. };
  50.  
  51. /* strictly speaking, this is a "skip" block, but it has interesting info */
  52. struct vbios_data {
  53.         u8 type; /* 0 == desktop, 1 == mobile */
  54.         u8 relstage;
  55.         u8 chipset;
  56.         u8 lvds_present:1;
  57.         u8 tv_present:1;
  58.         u8 rsvd2:6; /* finish byte */
  59.         u8 rsvd3[4];
  60.         u8 signon[155];
  61.         u8 copyright[61];
  62.         u16 code_segment;
  63.         u8 dos_boot_mode;
  64.         u8 bandwidth_percent;
  65.         u8 rsvd4; /* popup memory size */
  66.         u8 resize_pci_bios;
  67.         u8 rsvd5; /* is crt already on ddc2 */
  68. } __attribute__((packed));
  69.  
  70. /*
  71.  * There are several types of BIOS data blocks (BDBs), each block has
  72.  * an ID and size in the first 3 bytes (ID in first, size in next 2).
  73.  * Known types are listed below.
  74.  */
  75. #define BDB_GENERAL_FEATURES      1
  76. #define BDB_GENERAL_DEFINITIONS   2
  77. #define BDB_OLD_TOGGLE_LIST       3
  78. #define BDB_MODE_SUPPORT_LIST     4
  79. #define BDB_GENERIC_MODE_TABLE    5
  80. #define BDB_EXT_MMIO_REGS         6
  81. #define BDB_SWF_IO                7
  82. #define BDB_SWF_MMIO              8
  83. #define BDB_DOT_CLOCK_TABLE       9
  84. #define BDB_MODE_REMOVAL_TABLE   10
  85. #define BDB_CHILD_DEVICE_TABLE   11
  86. #define BDB_DRIVER_FEATURES      12
  87. #define BDB_DRIVER_PERSISTENCE   13
  88. #define BDB_EXT_TABLE_PTRS       14
  89. #define BDB_DOT_CLOCK_OVERRIDE   15
  90. #define BDB_DISPLAY_SELECT       16
  91. /* 17 rsvd */
  92. #define BDB_DRIVER_ROTATION      18
  93. #define BDB_DISPLAY_REMOVE       19
  94. #define BDB_OEM_CUSTOM           20
  95. #define BDB_EFP_LIST             21 /* workarounds for VGA hsync/vsync */
  96. #define BDB_SDVO_LVDS_OPTIONS    22
  97. #define BDB_SDVO_PANEL_DTDS      23
  98. #define BDB_SDVO_LVDS_PNP_IDS    24
  99. #define BDB_SDVO_LVDS_POWER_SEQ  25
  100. #define BDB_TV_OPTIONS           26
  101. #define BDB_EDP                  27
  102. #define BDB_LVDS_OPTIONS         40
  103. #define BDB_LVDS_LFP_DATA_PTRS   41
  104. #define BDB_LVDS_LFP_DATA        42
  105. #define BDB_LVDS_BACKLIGHT       43
  106. #define BDB_LVDS_POWER           44
  107. #define BDB_SKIP                254 /* VBIOS private block, ignore */
  108.  
  109. struct bdb_general_features {
  110.         /* bits 1 */
  111.         u8 panel_fitting:2;
  112.         u8 flexaim:1;
  113.         u8 msg_enable:1;
  114.         u8 clear_screen:3;
  115.         u8 color_flip:1;
  116.  
  117.         /* bits 2 */
  118.         u8 download_ext_vbt:1;
  119.         u8 enable_ssc:1;
  120.         u8 ssc_freq:1;
  121.         u8 enable_lfp_on_override:1;
  122.         u8 disable_ssc_ddt:1;
  123.         u8 rsvd7:1;
  124.         u8 display_clock_mode:1;
  125.         u8 rsvd8:1; /* finish byte */
  126.  
  127.         /* bits 3 */
  128.         u8 disable_smooth_vision:1;
  129.         u8 single_dvi:1;
  130.         u8 rsvd9:6; /* finish byte */
  131.  
  132.         /* bits 4 */
  133.         u8 legacy_monitor_detect;
  134.  
  135.         /* bits 5 */
  136.         u8 int_crt_support:1;
  137.         u8 int_tv_support:1;
  138.         u8 int_efp_support:1;
  139.         u8 dp_ssc_enb:1;        /* PCH attached eDP supports SSC */
  140.         u8 dp_ssc_freq:1;       /* SSC freq for PCH attached eDP */
  141.         u8 rsvd11:3; /* finish byte */
  142. } __attribute__((packed));
  143.  
  144. /* pre-915 */
  145. #define GPIO_PIN_DVI_LVDS       0x03 /* "DVI/LVDS DDC GPIO pins" */
  146. #define GPIO_PIN_ADD_I2C        0x05 /* "ADDCARD I2C GPIO pins" */
  147. #define GPIO_PIN_ADD_DDC        0x04 /* "ADDCARD DDC GPIO pins" */
  148. #define GPIO_PIN_ADD_DDC_I2C    0x06 /* "ADDCARD DDC/I2C GPIO pins" */
  149.  
  150. /* Pre 915 */
  151. #define DEVICE_TYPE_NONE        0x00
  152. #define DEVICE_TYPE_CRT         0x01
  153. #define DEVICE_TYPE_TV          0x09
  154. #define DEVICE_TYPE_EFP         0x12
  155. #define DEVICE_TYPE_LFP         0x22
  156. /* On 915+ */
  157. #define DEVICE_TYPE_CRT_DPMS            0x6001
  158. #define DEVICE_TYPE_CRT_DPMS_HOTPLUG    0x4001
  159. #define DEVICE_TYPE_TV_COMPOSITE        0x0209
  160. #define DEVICE_TYPE_TV_MACROVISION      0x0289
  161. #define DEVICE_TYPE_TV_RF_COMPOSITE     0x020c
  162. #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
  163. #define DEVICE_TYPE_TV_SCART            0x0209
  164. #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
  165. #define DEVICE_TYPE_EFP_HOTPLUG_PWR     0x6012
  166. #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
  167. #define DEVICE_TYPE_EFP_DVI_I           0x6053
  168. #define DEVICE_TYPE_EFP_DVI_D_DUAL      0x6152
  169. #define DEVICE_TYPE_EFP_DVI_D_HDCP      0x60d2
  170. #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
  171. #define DEVICE_TYPE_OPENLDI_DUALPIX     0x6162
  172. #define DEVICE_TYPE_LFP_PANELLINK       0x5012
  173. #define DEVICE_TYPE_LFP_CMOS_PWR        0x5042
  174. #define DEVICE_TYPE_LFP_LVDS_PWR        0x5062
  175. #define DEVICE_TYPE_LFP_LVDS_DUAL       0x5162
  176. #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP  0x51e2
  177.  
  178. #define DEVICE_CFG_NONE         0x00
  179. #define DEVICE_CFG_12BIT_DVOB   0x01
  180. #define DEVICE_CFG_12BIT_DVOC   0x02
  181. #define DEVICE_CFG_24BIT_DVOBC  0x09
  182. #define DEVICE_CFG_24BIT_DVOCB  0x0a
  183. #define DEVICE_CFG_DUAL_DVOB    0x11
  184. #define DEVICE_CFG_DUAL_DVOC    0x12
  185. #define DEVICE_CFG_DUAL_DVOBC   0x13
  186. #define DEVICE_CFG_DUAL_LINK_DVOBC      0x19
  187. #define DEVICE_CFG_DUAL_LINK_DVOCB      0x1a
  188.  
  189. #define DEVICE_WIRE_NONE        0x00
  190. #define DEVICE_WIRE_DVOB        0x01
  191. #define DEVICE_WIRE_DVOC        0x02
  192. #define DEVICE_WIRE_DVOBC       0x03
  193. #define DEVICE_WIRE_DVOBB       0x05
  194. #define DEVICE_WIRE_DVOCC       0x06
  195. #define DEVICE_WIRE_DVOB_MASTER 0x0d
  196. #define DEVICE_WIRE_DVOC_MASTER 0x0e
  197.  
  198. #define DEVICE_PORT_DVOA        0x00 /* none on 845+ */
  199. #define DEVICE_PORT_DVOB        0x01
  200. #define DEVICE_PORT_DVOC        0x02
  201.  
  202. struct child_device_config {
  203.         u16 handle;
  204.         u16 device_type;
  205.         u8  device_id[10]; /* ascii string */
  206.         u16 addin_offset;
  207.         u8  dvo_port; /* See Device_PORT_* above */
  208.         u8  i2c_pin;
  209.         u8  slave_addr;
  210.         u8  ddc_pin;
  211.         u16 edid_ptr;
  212.         u8  dvo_cfg; /* See DEVICE_CFG_* above */
  213.         u8  dvo2_port;
  214.         u8  i2c2_pin;
  215.         u8  slave2_addr;
  216.         u8  ddc2_pin;
  217.         u8  capabilities;
  218.         u8  dvo_wiring;/* See DEVICE_WIRE_* above */
  219.         u8  dvo2_wiring;
  220.         u16 extended_type;
  221.         u8  dvo_function;
  222. } __attribute__((packed));
  223.  
  224. struct bdb_general_definitions {
  225.         /* DDC GPIO */
  226.         u8 crt_ddc_gmbus_pin;
  227.  
  228.         /* DPMS bits */
  229.         u8 dpms_acpi:1;
  230.         u8 skip_boot_crt_detect:1;
  231.         u8 dpms_aim:1;
  232.         u8 rsvd1:5; /* finish byte */
  233.  
  234.         /* boot device bits */
  235.         u8 boot_display[2];
  236.         u8 child_dev_size;
  237.  
  238.         /*
  239.          * Device info:
  240.          * If TV is present, it'll be at devices[0].
  241.          * LVDS will be next, either devices[0] or [1], if present.
  242.          * On some platforms the number of device is 6. But could be as few as
  243.          * 4 if both TV and LVDS are missing.
  244.          * And the device num is related with the size of general definition
  245.          * block. It is obtained by using the following formula:
  246.          * number = (block_size - sizeof(bdb_general_definitions))/
  247.          *           sizeof(child_device_config);
  248.          */
  249.         struct child_device_config devices[0];
  250. } __attribute__((packed));
  251.  
  252. struct bdb_lvds_options {
  253.         u8 panel_type;
  254.         u8 rsvd1;
  255.         /* LVDS capabilities, stored in a dword */
  256.         u8 pfit_mode:2;
  257.         u8 pfit_text_mode_enhanced:1;
  258.         u8 pfit_gfx_mode_enhanced:1;
  259.         u8 pfit_ratio_auto:1;
  260.         u8 pixel_dither:1;
  261.         u8 lvds_edid:1;
  262.         u8 rsvd2:1;
  263.         u8 rsvd4;
  264. } __attribute__((packed));
  265.  
  266. /* LFP pointer table contains entries to the struct below */
  267. struct bdb_lvds_lfp_data_ptr {
  268.         u16 fp_timing_offset; /* offsets are from start of bdb */
  269.         u8 fp_table_size;
  270.         u16 dvo_timing_offset;
  271.         u8 dvo_table_size;
  272.         u16 panel_pnp_id_offset;
  273.         u8 pnp_table_size;
  274. } __attribute__((packed));
  275.  
  276. struct bdb_lvds_lfp_data_ptrs {
  277.         u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
  278.         struct bdb_lvds_lfp_data_ptr ptr[16];
  279. } __attribute__((packed));
  280.  
  281. /* LFP data has 3 blocks per entry */
  282. struct lvds_fp_timing {
  283.         u16 x_res;
  284.         u16 y_res;
  285.         u32 lvds_reg;
  286.         u32 lvds_reg_val;
  287.         u32 pp_on_reg;
  288.         u32 pp_on_reg_val;
  289.         u32 pp_off_reg;
  290.         u32 pp_off_reg_val;
  291.         u32 pp_cycle_reg;
  292.         u32 pp_cycle_reg_val;
  293.         u32 pfit_reg;
  294.         u32 pfit_reg_val;
  295.         u16 terminator;
  296. } __attribute__((packed));
  297.  
  298. struct lvds_dvo_timing {
  299.         u16 clock;              /**< In 10khz */
  300.         u8 hactive_lo;
  301.         u8 hblank_lo;
  302.         u8 hblank_hi:4;
  303.         u8 hactive_hi:4;
  304.         u8 vactive_lo;
  305.         u8 vblank_lo;
  306.         u8 vblank_hi:4;
  307.         u8 vactive_hi:4;
  308.         u8 hsync_off_lo;
  309.         u8 hsync_pulse_width;
  310.         u8 vsync_pulse_width:4;
  311.         u8 vsync_off:4;
  312.         u8 rsvd0:6;
  313.         u8 hsync_off_hi:2;
  314.         u8 h_image;
  315.         u8 v_image;
  316.         u8 max_hv;
  317.         u8 h_border;
  318.         u8 v_border;
  319.         u8 rsvd1:3;
  320.         u8 digital:2;
  321.         u8 vsync_positive:1;
  322.         u8 hsync_positive:1;
  323.         u8 rsvd2:1;
  324. } __attribute__((packed));
  325.  
  326. struct lvds_pnp_id {
  327.         u16 mfg_name;
  328.         u16 product_code;
  329.         u32 serial;
  330.         u8 mfg_week;
  331.         u8 mfg_year;
  332. } __attribute__((packed));
  333.  
  334. struct bdb_lvds_lfp_data_entry {
  335.         struct lvds_fp_timing fp_timing;
  336.         struct lvds_dvo_timing dvo_timing;
  337.         struct lvds_pnp_id pnp_id;
  338. } __attribute__((packed));
  339.  
  340. struct bdb_lvds_lfp_data {
  341.         struct bdb_lvds_lfp_data_entry data[16];
  342. } __attribute__((packed));
  343.  
  344. struct aimdb_header {
  345.         char signature[16];
  346.         char oem_device[20];
  347.         u16 aimdb_version;
  348.         u16 aimdb_header_size;
  349.         u16 aimdb_size;
  350. } __attribute__((packed));
  351.  
  352. struct aimdb_block {
  353.         u8 aimdb_id;
  354.         u16 aimdb_size;
  355. } __attribute__((packed));
  356.  
  357. struct vch_panel_data {
  358.         u16 fp_timing_offset;
  359.         u8 fp_timing_size;
  360.         u16 dvo_timing_offset;
  361.         u8 dvo_timing_size;
  362.         u16 text_fitting_offset;
  363.         u8 text_fitting_size;
  364.         u16 graphics_fitting_offset;
  365.         u8 graphics_fitting_size;
  366. } __attribute__((packed));
  367.  
  368. struct vch_bdb_22 {
  369.         struct aimdb_block aimdb_block;
  370.         struct vch_panel_data panels[16];
  371. } __attribute__((packed));
  372.  
  373. struct bdb_sdvo_lvds_options {
  374.         u8 panel_backlight;
  375.         u8 h40_set_panel_type;
  376.         u8 panel_type;
  377.         u8 ssc_clk_freq;
  378.         u16 als_low_trip;
  379.         u16 als_high_trip;
  380.         u8 sclalarcoeff_tab_row_num;
  381.         u8 sclalarcoeff_tab_row_size;
  382.         u8 coefficient[8];
  383.         u8 panel_misc_bits_1;
  384.         u8 panel_misc_bits_2;
  385.         u8 panel_misc_bits_3;
  386.         u8 panel_misc_bits_4;
  387. } __attribute__((packed));
  388.  
  389.  
  390. #define BDB_DRIVER_FEATURE_NO_LVDS              0
  391. #define BDB_DRIVER_FEATURE_INT_LVDS             1
  392. #define BDB_DRIVER_FEATURE_SDVO_LVDS            2
  393. #define BDB_DRIVER_FEATURE_EDP                  3
  394.  
  395. struct bdb_driver_features {
  396.         u8 boot_dev_algorithm:1;
  397.         u8 block_display_switch:1;
  398.         u8 allow_display_switch:1;
  399.         u8 hotplug_dvo:1;
  400.         u8 dual_view_zoom:1;
  401.         u8 int15h_hook:1;
  402.         u8 sprite_in_clone:1;
  403.         u8 primary_lfp_id:1;
  404.  
  405.         u16 boot_mode_x;
  406.         u16 boot_mode_y;
  407.         u8 boot_mode_bpp;
  408.         u8 boot_mode_refresh;
  409.  
  410.         u16 enable_lfp_primary:1;
  411.         u16 selective_mode_pruning:1;
  412.         u16 dual_frequency:1;
  413.         u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
  414.         u16 nt_clone_support:1;
  415.         u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
  416.         u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
  417.         u16 cui_aspect_scaling:1;
  418.         u16 preserve_aspect_ratio:1;
  419.         u16 sdvo_device_power_down:1;
  420.         u16 crt_hotplug:1;
  421.         u16 lvds_config:2;
  422.         u16 tv_hotplug:1;
  423.         u16 hdmi_config:2;
  424.  
  425.         u8 static_display:1;
  426.         u8 reserved2:7;
  427.         u16 legacy_crt_max_x;
  428.         u16 legacy_crt_max_y;
  429.         u8 legacy_crt_max_refresh;
  430.  
  431.         u8 hdmi_termination;
  432.         u8 custom_vbt_version;
  433. } __attribute__((packed));
  434.  
  435. #define EDP_18BPP       0
  436. #define EDP_24BPP       1
  437. #define EDP_30BPP       2
  438. #define EDP_RATE_1_62   0
  439. #define EDP_RATE_2_7    1
  440. #define EDP_LANE_1      0
  441. #define EDP_LANE_2      1
  442. #define EDP_LANE_4      3
  443. #define EDP_PREEMPHASIS_NONE    0
  444. #define EDP_PREEMPHASIS_3_5dB   1
  445. #define EDP_PREEMPHASIS_6dB     2
  446. #define EDP_PREEMPHASIS_9_5dB   3
  447. #define EDP_VSWING_0_4V         0
  448. #define EDP_VSWING_0_6V         1
  449. #define EDP_VSWING_0_8V         2
  450. #define EDP_VSWING_1_2V         3
  451.  
  452. struct edp_power_seq {
  453.         u16 t1_t3;
  454.         u16 t8;
  455.         u16 t9;
  456.         u16 t10;
  457.         u16 t11_t12;
  458. } __attribute__ ((packed));
  459.  
  460. struct edp_link_params {
  461.         u8 rate:4;
  462.         u8 lanes:4;
  463.         u8 preemphasis:4;
  464.         u8 vswing:4;
  465. } __attribute__ ((packed));
  466.  
  467. struct bdb_edp {
  468.         struct edp_power_seq power_seqs[16];
  469.         u32 color_depth;
  470.         struct edp_link_params link_params[16];
  471.         u32 sdrrs_msa_timing_delay;
  472.  
  473.         /* ith bit indicates enabled/disabled for (i+1)th panel */
  474.         u16 edp_s3d_feature;
  475.         u16 edp_t3_optimization;
  476. } __attribute__ ((packed));
  477.  
  478. void intel_setup_bios(struct drm_device *dev);
  479. bool intel_parse_bios(struct drm_device *dev);
  480.  
  481. /*
  482.  * Driver<->VBIOS interaction occurs through scratch bits in
  483.  * GR18 & SWF*.
  484.  */
  485.  
  486. /* GR18 bits are set on display switch and hotkey events */
  487. #define GR18_DRIVER_SWITCH_EN   (1<<7) /* 0: VBIOS control, 1: driver control */
  488. #define GR18_HOTKEY_MASK        0x78 /* See also SWF4 15:0 */
  489. #define   GR18_HK_NONE          (0x0<<3)
  490. #define   GR18_HK_LFP_STRETCH   (0x1<<3)
  491. #define   GR18_HK_TOGGLE_DISP   (0x2<<3)
  492. #define   GR18_HK_DISP_SWITCH   (0x4<<3) /* see SWF14 15:0 for what to enable */
  493. #define   GR18_HK_POPUP_DISABLED (0x6<<3)
  494. #define   GR18_HK_POPUP_ENABLED (0x7<<3)
  495. #define   GR18_HK_PFIT          (0x8<<3)
  496. #define   GR18_HK_APM_CHANGE    (0xa<<3)
  497. #define   GR18_HK_MULTIPLE      (0xc<<3)
  498. #define GR18_USER_INT_EN        (1<<2)
  499. #define GR18_A0000_FLUSH_EN     (1<<1)
  500. #define GR18_SMM_EN             (1<<0)
  501.  
  502. /* Set by driver, cleared by VBIOS */
  503. #define SWF00_YRES_SHIFT        16
  504. #define SWF00_XRES_SHIFT        0
  505. #define SWF00_RES_MASK          0xffff
  506.  
  507. /* Set by VBIOS at boot time and driver at runtime */
  508. #define SWF01_TV2_FORMAT_SHIFT  8
  509. #define SWF01_TV1_FORMAT_SHIFT  0
  510. #define SWF01_TV_FORMAT_MASK    0xffff
  511.  
  512. #define SWF10_VBIOS_BLC_I2C_EN  (1<<29)
  513. #define SWF10_GTT_OVERRIDE_EN   (1<<28)
  514. #define SWF10_LFP_DPMS_OVR      (1<<27) /* override DPMS on display switch */
  515. #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
  516. #define   SWF10_OLD_TOGGLE      0x0
  517. #define   SWF10_TOGGLE_LIST_1   0x1
  518. #define   SWF10_TOGGLE_LIST_2   0x2
  519. #define   SWF10_TOGGLE_LIST_3   0x3
  520. #define   SWF10_TOGGLE_LIST_4   0x4
  521. #define SWF10_PANNING_EN        (1<<23)
  522. #define SWF10_DRIVER_LOADED     (1<<22)
  523. #define SWF10_EXTENDED_DESKTOP  (1<<21)
  524. #define SWF10_EXCLUSIVE_MODE    (1<<20)
  525. #define SWF10_OVERLAY_EN        (1<<19)
  526. #define SWF10_PLANEB_HOLDOFF    (1<<18)
  527. #define SWF10_PLANEA_HOLDOFF    (1<<17)
  528. #define SWF10_VGA_HOLDOFF       (1<<16)
  529. #define SWF10_ACTIVE_DISP_MASK  0xffff
  530. #define   SWF10_PIPEB_LFP2      (1<<15)
  531. #define   SWF10_PIPEB_EFP2      (1<<14)
  532. #define   SWF10_PIPEB_TV2       (1<<13)
  533. #define   SWF10_PIPEB_CRT2      (1<<12)
  534. #define   SWF10_PIPEB_LFP       (1<<11)
  535. #define   SWF10_PIPEB_EFP       (1<<10)
  536. #define   SWF10_PIPEB_TV        (1<<9)
  537. #define   SWF10_PIPEB_CRT       (1<<8)
  538. #define   SWF10_PIPEA_LFP2      (1<<7)
  539. #define   SWF10_PIPEA_EFP2      (1<<6)
  540. #define   SWF10_PIPEA_TV2       (1<<5)
  541. #define   SWF10_PIPEA_CRT2      (1<<4)
  542. #define   SWF10_PIPEA_LFP       (1<<3)
  543. #define   SWF10_PIPEA_EFP       (1<<2)
  544. #define   SWF10_PIPEA_TV        (1<<1)
  545. #define   SWF10_PIPEA_CRT       (1<<0)
  546.  
  547. #define SWF11_MEMORY_SIZE_SHIFT 16
  548. #define SWF11_SV_TEST_EN        (1<<15)
  549. #define SWF11_IS_AGP            (1<<14)
  550. #define SWF11_DISPLAY_HOLDOFF   (1<<13)
  551. #define SWF11_DPMS_REDUCED      (1<<12)
  552. #define SWF11_IS_VBE_MODE       (1<<11)
  553. #define SWF11_PIPEB_ACCESS      (1<<10) /* 0 here means pipe a */
  554. #define SWF11_DPMS_MASK         0x07
  555. #define   SWF11_DPMS_OFF        (1<<2)
  556. #define   SWF11_DPMS_SUSPEND    (1<<1)
  557. #define   SWF11_DPMS_STANDBY    (1<<0)
  558. #define   SWF11_DPMS_ON         0
  559.  
  560. #define SWF14_GFX_PFIT_EN       (1<<31)
  561. #define SWF14_TEXT_PFIT_EN      (1<<30)
  562. #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
  563. #define SWF14_POPUP_EN          (1<<28)
  564. #define SWF14_DISPLAY_HOLDOFF   (1<<27)
  565. #define SWF14_DISP_DETECT_EN    (1<<26)
  566. #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
  567. #define SWF14_DRIVER_STATUS     (1<<24)
  568. #define SWF14_OS_TYPE_WIN9X     (1<<23)
  569. #define SWF14_OS_TYPE_WINNT     (1<<22)
  570. /* 21:19 rsvd */
  571. #define SWF14_PM_TYPE_MASK      0x00070000
  572. #define   SWF14_PM_ACPI_VIDEO   (0x4 << 16)
  573. #define   SWF14_PM_ACPI         (0x3 << 16)
  574. #define   SWF14_PM_APM_12       (0x2 << 16)
  575. #define   SWF14_PM_APM_11       (0x1 << 16)
  576. #define SWF14_HK_REQUEST_MASK   0x0000ffff /* see GR18 6:3 for event type */
  577.           /* if GR18 indicates a display switch */
  578. #define   SWF14_DS_PIPEB_LFP2_EN (1<<15)
  579. #define   SWF14_DS_PIPEB_EFP2_EN (1<<14)
  580. #define   SWF14_DS_PIPEB_TV2_EN  (1<<13)
  581. #define   SWF14_DS_PIPEB_CRT2_EN (1<<12)
  582. #define   SWF14_DS_PIPEB_LFP_EN  (1<<11)
  583. #define   SWF14_DS_PIPEB_EFP_EN  (1<<10)
  584. #define   SWF14_DS_PIPEB_TV_EN   (1<<9)
  585. #define   SWF14_DS_PIPEB_CRT_EN  (1<<8)
  586. #define   SWF14_DS_PIPEA_LFP2_EN (1<<7)
  587. #define   SWF14_DS_PIPEA_EFP2_EN (1<<6)
  588. #define   SWF14_DS_PIPEA_TV2_EN  (1<<5)
  589. #define   SWF14_DS_PIPEA_CRT2_EN (1<<4)
  590. #define   SWF14_DS_PIPEA_LFP_EN  (1<<3)
  591. #define   SWF14_DS_PIPEA_EFP_EN  (1<<2)
  592. #define   SWF14_DS_PIPEA_TV_EN   (1<<1)
  593. #define   SWF14_DS_PIPEA_CRT_EN  (1<<0)
  594.           /* if GR18 indicates a panel fitting request */
  595. #define   SWF14_PFIT_EN         (1<<0) /* 0 means disable */
  596.           /* if GR18 indicates an APM change request */
  597. #define   SWF14_APM_HIBERNATE   0x4
  598. #define   SWF14_APM_SUSPEND     0x3
  599. #define   SWF14_APM_STANDBY     0x1
  600. #define   SWF14_APM_RESTORE     0x0
  601.  
  602. /* Add the device class for LFP, TV, HDMI */
  603. #define  DEVICE_TYPE_INT_LFP    0x1022
  604. #define  DEVICE_TYPE_INT_TV     0x1009
  605. #define  DEVICE_TYPE_HDMI       0x60D2
  606. #define  DEVICE_TYPE_DP         0x68C6
  607. #define  DEVICE_TYPE_eDP        0x78C6
  608.  
  609. /* define the DVO port for HDMI output type */
  610. #define         DVO_B           1
  611. #define         DVO_C           2
  612. #define         DVO_D           3
  613.  
  614. /* define the PORT for DP output type */
  615. #define         PORT_IDPB       7
  616. #define         PORT_IDPC       8
  617. #define         PORT_IDPD       9
  618.  
  619. #endif /* _I830_BIOS_H_ */
  620.