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  1. /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  2.  * All Rights Reserved.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  */
  24.  
  25. #ifndef _I915_REG_H_
  26. #define _I915_REG_H_
  27.  
  28. #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
  29. #define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
  30.  
  31. #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
  32. #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
  33.                                (pipe) == PIPE_B ? (b) : (c))
  34.  
  35. #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
  36. #define _MASKED_BIT_DISABLE(a) ((a) << 16)
  37.  
  38. /* PCI config space */
  39.  
  40. #define HPLLCC  0xc0 /* 855 only */
  41. #define   GC_CLOCK_CONTROL_MASK         (0xf << 0)
  42. #define   GC_CLOCK_133_200              (0 << 0)
  43. #define   GC_CLOCK_100_200              (1 << 0)
  44. #define   GC_CLOCK_100_133              (2 << 0)
  45. #define   GC_CLOCK_166_250              (3 << 0)
  46. #define GCFGC2  0xda
  47. #define GCFGC   0xf0 /* 915+ only */
  48. #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
  49. #define   GC_DISPLAY_CLOCK_190_200_MHZ  (0 << 4)
  50. #define   GC_DISPLAY_CLOCK_333_MHZ      (4 << 4)
  51. #define   GC_DISPLAY_CLOCK_267_MHZ_PNV  (0 << 4)
  52. #define   GC_DISPLAY_CLOCK_333_MHZ_PNV  (1 << 4)
  53. #define   GC_DISPLAY_CLOCK_444_MHZ_PNV  (2 << 4)
  54. #define   GC_DISPLAY_CLOCK_200_MHZ_PNV  (5 << 4)
  55. #define   GC_DISPLAY_CLOCK_133_MHZ_PNV  (6 << 4)
  56. #define   GC_DISPLAY_CLOCK_167_MHZ_PNV  (7 << 4)
  57. #define   GC_DISPLAY_CLOCK_MASK         (7 << 4)
  58. #define   GM45_GC_RENDER_CLOCK_MASK     (0xf << 0)
  59. #define   GM45_GC_RENDER_CLOCK_266_MHZ  (8 << 0)
  60. #define   GM45_GC_RENDER_CLOCK_320_MHZ  (9 << 0)
  61. #define   GM45_GC_RENDER_CLOCK_400_MHZ  (0xb << 0)
  62. #define   GM45_GC_RENDER_CLOCK_533_MHZ  (0xc << 0)
  63. #define   I965_GC_RENDER_CLOCK_MASK     (0xf << 0)
  64. #define   I965_GC_RENDER_CLOCK_267_MHZ  (2 << 0)
  65. #define   I965_GC_RENDER_CLOCK_333_MHZ  (3 << 0)
  66. #define   I965_GC_RENDER_CLOCK_444_MHZ  (4 << 0)
  67. #define   I965_GC_RENDER_CLOCK_533_MHZ  (5 << 0)
  68. #define   I945_GC_RENDER_CLOCK_MASK     (7 << 0)
  69. #define   I945_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
  70. #define   I945_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
  71. #define   I945_GC_RENDER_CLOCK_250_MHZ  (3 << 0)
  72. #define   I945_GC_RENDER_CLOCK_400_MHZ  (5 << 0)
  73. #define   I915_GC_RENDER_CLOCK_MASK     (7 << 0)
  74. #define   I915_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
  75. #define   I915_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
  76. #define   I915_GC_RENDER_CLOCK_333_MHZ  (4 << 0)
  77. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
  78.  
  79.  
  80. /* Graphics reset regs */
  81. #define I965_GDRST 0xc0 /* PCI config register */
  82. #define  GRDOM_FULL     (0<<2)
  83. #define  GRDOM_RENDER   (1<<2)
  84. #define  GRDOM_MEDIA    (3<<2)
  85. #define  GRDOM_MASK     (3<<2)
  86. #define  GRDOM_RESET_ENABLE (1<<0)
  87.  
  88. #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
  89. #define  ILK_GRDOM_FULL         (0<<1)
  90. #define  ILK_GRDOM_RENDER       (1<<1)
  91. #define  ILK_GRDOM_MEDIA        (3<<1)
  92. #define  ILK_GRDOM_MASK         (3<<1)
  93. #define  ILK_GRDOM_RESET_ENABLE (1<<0)
  94.  
  95. #define GEN6_MBCUNIT_SNPCR      0x900c /* for LLC config */
  96. #define   GEN6_MBC_SNPCR_SHIFT  21
  97. #define   GEN6_MBC_SNPCR_MASK   (3<<21)
  98. #define   GEN6_MBC_SNPCR_MAX    (0<<21)
  99. #define   GEN6_MBC_SNPCR_MED    (1<<21)
  100. #define   GEN6_MBC_SNPCR_LOW    (2<<21)
  101. #define   GEN6_MBC_SNPCR_MIN    (3<<21) /* only 1/16th of the cache is shared */
  102.  
  103. #define VLV_G3DCTL              0x9024
  104. #define VLV_GSCKGCTL            0x9028
  105.  
  106. #define GEN6_MBCTL              0x0907c
  107. #define   GEN6_MBCTL_ENABLE_BOOT_FETCH  (1 << 4)
  108. #define   GEN6_MBCTL_CTX_FETCH_NEEDED   (1 << 3)
  109. #define   GEN6_MBCTL_BME_UPDATE_ENABLE  (1 << 2)
  110. #define   GEN6_MBCTL_MAE_UPDATE_ENABLE  (1 << 1)
  111. #define   GEN6_MBCTL_BOOT_FETCH_MECH    (1 << 0)
  112.  
  113. #define GEN6_GDRST      0x941c
  114. #define  GEN6_GRDOM_FULL                (1 << 0)
  115. #define  GEN6_GRDOM_RENDER              (1 << 1)
  116. #define  GEN6_GRDOM_MEDIA               (1 << 2)
  117. #define  GEN6_GRDOM_BLT                 (1 << 3)
  118.  
  119. #define RING_PP_DIR_BASE(ring)          ((ring)->mmio_base+0x228)
  120. #define RING_PP_DIR_BASE_READ(ring)     ((ring)->mmio_base+0x518)
  121. #define RING_PP_DIR_DCLV(ring)          ((ring)->mmio_base+0x220)
  122. #define   PP_DIR_DCLV_2G                0xffffffff
  123.  
  124. #define GEN8_RING_PDP_UDW(ring, n)      ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
  125. #define GEN8_RING_PDP_LDW(ring, n)      ((ring)->mmio_base+0x270 + (n) * 8)
  126.  
  127. #define GAM_ECOCHK                      0x4090
  128. #define   ECOCHK_SNB_BIT                (1<<10)
  129. #define   HSW_ECOCHK_ARB_PRIO_SOL       (1<<6)
  130. #define   ECOCHK_PPGTT_CACHE64B         (0x3<<3)
  131. #define   ECOCHK_PPGTT_CACHE4B          (0x0<<3)
  132. #define   ECOCHK_PPGTT_GFDT_IVB         (0x1<<4)
  133. #define   ECOCHK_PPGTT_LLC_IVB          (0x1<<3)
  134. #define   ECOCHK_PPGTT_UC_HSW           (0x1<<3)
  135. #define   ECOCHK_PPGTT_WT_HSW           (0x2<<3)
  136. #define   ECOCHK_PPGTT_WB_HSW           (0x3<<3)
  137.  
  138. #define GAC_ECO_BITS                    0x14090
  139. #define   ECOBITS_SNB_BIT               (1<<13)
  140. #define   ECOBITS_PPGTT_CACHE64B        (3<<8)
  141. #define   ECOBITS_PPGTT_CACHE4B         (0<<8)
  142.  
  143. #define GAB_CTL                         0x24000
  144. #define   GAB_CTL_CONT_AFTER_PAGEFAULT  (1<<8)
  145.  
  146. /* VGA stuff */
  147.  
  148. #define VGA_ST01_MDA 0x3ba
  149. #define VGA_ST01_CGA 0x3da
  150.  
  151. #define VGA_MSR_WRITE 0x3c2
  152. #define VGA_MSR_READ 0x3cc
  153. #define   VGA_MSR_MEM_EN (1<<1)
  154. #define   VGA_MSR_CGA_MODE (1<<0)
  155.  
  156. #define VGA_SR_INDEX 0x3c4
  157. #define SR01                    1
  158. #define VGA_SR_DATA 0x3c5
  159.  
  160. #define VGA_AR_INDEX 0x3c0
  161. #define   VGA_AR_VID_EN (1<<5)
  162. #define VGA_AR_DATA_WRITE 0x3c0
  163. #define VGA_AR_DATA_READ 0x3c1
  164.  
  165. #define VGA_GR_INDEX 0x3ce
  166. #define VGA_GR_DATA 0x3cf
  167. /* GR05 */
  168. #define   VGA_GR_MEM_READ_MODE_SHIFT 3
  169. #define     VGA_GR_MEM_READ_MODE_PLANE 1
  170. /* GR06 */
  171. #define   VGA_GR_MEM_MODE_MASK 0xc
  172. #define   VGA_GR_MEM_MODE_SHIFT 2
  173. #define   VGA_GR_MEM_A0000_AFFFF 0
  174. #define   VGA_GR_MEM_A0000_BFFFF 1
  175. #define   VGA_GR_MEM_B0000_B7FFF 2
  176. #define   VGA_GR_MEM_B0000_BFFFF 3
  177.  
  178. #define VGA_DACMASK 0x3c6
  179. #define VGA_DACRX 0x3c7
  180. #define VGA_DACWX 0x3c8
  181. #define VGA_DACDATA 0x3c9
  182.  
  183. #define VGA_CR_INDEX_MDA 0x3b4
  184. #define VGA_CR_DATA_MDA 0x3b5
  185. #define VGA_CR_INDEX_CGA 0x3d4
  186. #define VGA_CR_DATA_CGA 0x3d5
  187.  
  188. /*
  189.  * Instruction field definitions used by the command parser
  190.  */
  191. #define INSTR_CLIENT_SHIFT      29
  192. #define INSTR_CLIENT_MASK       0xE0000000
  193. #define   INSTR_MI_CLIENT       0x0
  194. #define   INSTR_BC_CLIENT       0x2
  195. #define   INSTR_RC_CLIENT       0x3
  196. #define INSTR_SUBCLIENT_SHIFT   27
  197. #define INSTR_SUBCLIENT_MASK    0x18000000
  198. #define   INSTR_MEDIA_SUBCLIENT 0x2
  199.  
  200. /*
  201.  * Memory interface instructions used by the kernel
  202.  */
  203. #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
  204. /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
  205. #define  MI_GLOBAL_GTT    (1<<22)
  206.  
  207. #define MI_NOOP                 MI_INSTR(0, 0)
  208. #define MI_USER_INTERRUPT       MI_INSTR(0x02, 0)
  209. #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
  210. #define   MI_WAIT_FOR_OVERLAY_FLIP      (1<<16)
  211. #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
  212. #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
  213. #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  214. #define MI_FLUSH                MI_INSTR(0x04, 0)
  215. #define   MI_READ_FLUSH         (1 << 0)
  216. #define   MI_EXE_FLUSH          (1 << 1)
  217. #define   MI_NO_WRITE_FLUSH     (1 << 2)
  218. #define   MI_SCENE_COUNT        (1 << 3) /* just increment scene count */
  219. #define   MI_END_SCENE          (1 << 4) /* flush binner and incr scene count */
  220. #define   MI_INVALIDATE_ISP     (1 << 5) /* invalidate indirect state pointers */
  221. #define MI_REPORT_HEAD          MI_INSTR(0x07, 0)
  222. #define MI_ARB_ON_OFF           MI_INSTR(0x08, 0)
  223. #define   MI_ARB_ENABLE                 (1<<0)
  224. #define   MI_ARB_DISABLE                (0<<0)
  225. #define MI_BATCH_BUFFER_END     MI_INSTR(0x0a, 0)
  226. #define MI_SUSPEND_FLUSH        MI_INSTR(0x0b, 0)
  227. #define   MI_SUSPEND_FLUSH_EN   (1<<0)
  228. #define MI_OVERLAY_FLIP         MI_INSTR(0x11, 0)
  229. #define   MI_OVERLAY_CONTINUE   (0x0<<21)
  230. #define   MI_OVERLAY_ON         (0x1<<21)
  231. #define   MI_OVERLAY_OFF        (0x2<<21)
  232. #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
  233. #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
  234. #define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
  235. #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
  236. /* IVB has funny definitions for which plane to flip. */
  237. #define   MI_DISPLAY_FLIP_IVB_PLANE_A  (0 << 19)
  238. #define   MI_DISPLAY_FLIP_IVB_PLANE_B  (1 << 19)
  239. #define   MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
  240. #define   MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
  241. #define   MI_DISPLAY_FLIP_IVB_PLANE_C  (4 << 19)
  242. #define   MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
  243. #define MI_SEMAPHORE_MBOX       MI_INSTR(0x16, 1) /* gen6, gen7 */
  244. #define   MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
  245. #define   MI_SEMAPHORE_UPDATE       (1<<21)
  246. #define   MI_SEMAPHORE_COMPARE      (1<<20)
  247. #define   MI_SEMAPHORE_REGISTER     (1<<18)
  248. #define   MI_SEMAPHORE_SYNC_VR      (0<<16) /* RCS  wait for VCS  (RVSYNC) */
  249. #define   MI_SEMAPHORE_SYNC_VER     (1<<16) /* RCS  wait for VECS (RVESYNC) */
  250. #define   MI_SEMAPHORE_SYNC_BR      (2<<16) /* RCS  wait for BCS  (RBSYNC) */
  251. #define   MI_SEMAPHORE_SYNC_BV      (0<<16) /* VCS  wait for BCS  (VBSYNC) */
  252. #define   MI_SEMAPHORE_SYNC_VEV     (1<<16) /* VCS  wait for VECS (VVESYNC) */
  253. #define   MI_SEMAPHORE_SYNC_RV      (2<<16) /* VCS  wait for RCS  (VRSYNC) */
  254. #define   MI_SEMAPHORE_SYNC_RB      (0<<16) /* BCS  wait for RCS  (BRSYNC) */
  255. #define   MI_SEMAPHORE_SYNC_VEB     (1<<16) /* BCS  wait for VECS (BVESYNC) */
  256. #define   MI_SEMAPHORE_SYNC_VB      (2<<16) /* BCS  wait for VCS  (BVSYNC) */
  257. #define   MI_SEMAPHORE_SYNC_BVE     (0<<16) /* VECS wait for BCS  (VEBSYNC) */
  258. #define   MI_SEMAPHORE_SYNC_VVE     (1<<16) /* VECS wait for VCS  (VEVSYNC) */
  259. #define   MI_SEMAPHORE_SYNC_RVE     (2<<16) /* VECS wait for RCS  (VERSYNC) */
  260. #define   MI_SEMAPHORE_SYNC_INVALID  (3<<16)
  261. #define   MI_SEMAPHORE_SYNC_MASK    (3<<16)
  262. #define MI_SET_CONTEXT          MI_INSTR(0x18, 0)
  263. #define   MI_MM_SPACE_GTT               (1<<8)
  264. #define   MI_MM_SPACE_PHYSICAL          (0<<8)
  265. #define   MI_SAVE_EXT_STATE_EN          (1<<3)
  266. #define   MI_RESTORE_EXT_STATE_EN       (1<<2)
  267. #define   MI_FORCE_RESTORE              (1<<1)
  268. #define   MI_RESTORE_INHIBIT            (1<<0)
  269. #define MI_SEMAPHORE_SIGNAL     MI_INSTR(0x1b, 0) /* GEN8+ */
  270. #define   MI_SEMAPHORE_TARGET(engine)   ((engine)<<15)
  271. #define MI_SEMAPHORE_WAIT       MI_INSTR(0x1c, 2) /* GEN8+ */
  272. #define   MI_SEMAPHORE_POLL             (1<<15)
  273. #define   MI_SEMAPHORE_SAD_GTE_SDD      (1<<12)
  274. #define MI_STORE_DWORD_IMM      MI_INSTR(0x20, 1)
  275. #define   MI_MEM_VIRTUAL        (1 << 22) /* 965+ only */
  276. #define MI_STORE_DWORD_INDEX    MI_INSTR(0x21, 1)
  277. #define   MI_STORE_DWORD_INDEX_SHIFT 2
  278. /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
  279.  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
  280.  *   simply ignores the register load under certain conditions.
  281.  * - One can actually load arbitrary many arbitrary registers: Simply issue x
  282.  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
  283.  */
  284. #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
  285. #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1)
  286. #define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1)
  287. #define   MI_SRM_LRM_GLOBAL_GTT         (1<<22)
  288. #define MI_FLUSH_DW             MI_INSTR(0x26, 1) /* for GEN6 */
  289. #define   MI_FLUSH_DW_STORE_INDEX       (1<<21)
  290. #define   MI_INVALIDATE_TLB     (1<<18)
  291. #define   MI_FLUSH_DW_OP_STOREDW        (1<<14)
  292. #define   MI_FLUSH_DW_OP_MASK           (3<<14)
  293. #define   MI_FLUSH_DW_NOTIFY            (1<<8)
  294. #define   MI_INVALIDATE_BSD     (1<<7)
  295. #define   MI_FLUSH_DW_USE_GTT           (1<<2)
  296. #define   MI_FLUSH_DW_USE_PPGTT         (0<<2)
  297. #define MI_BATCH_BUFFER         MI_INSTR(0x30, 1)
  298. #define   MI_BATCH_NON_SECURE   (1)
  299. /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
  300. #define   MI_BATCH_NON_SECURE_I965 (1<<8)
  301. #define   MI_BATCH_PPGTT_HSW            (1<<8)
  302. #define   MI_BATCH_NON_SECURE_HSW       (1<<13)
  303. #define MI_BATCH_BUFFER_START   MI_INSTR(0x31, 0)
  304. #define   MI_BATCH_GTT              (2<<6) /* aliased with (1<<7) on gen4 */
  305. #define MI_BATCH_BUFFER_START_GEN8      MI_INSTR(0x31, 1)
  306.  
  307.  
  308. #define MI_PREDICATE_RESULT_2   (0x2214)
  309. #define  LOWER_SLICE_ENABLED    (1<<0)
  310. #define  LOWER_SLICE_DISABLED   (0<<0)
  311.  
  312. /*
  313.  * 3D instructions used by the kernel
  314.  */
  315. #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
  316.  
  317. #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
  318. #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  319. #define   SC_UPDATE_SCISSOR       (0x1<<1)
  320. #define   SC_ENABLE_MASK          (0x1<<0)
  321. #define   SC_ENABLE               (0x1<<0)
  322. #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
  323. #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  324. #define   SCI_YMIN_MASK      (0xffff<<16)
  325. #define   SCI_XMIN_MASK      (0xffff<<0)
  326. #define   SCI_YMAX_MASK      (0xffff<<16)
  327. #define   SCI_XMAX_MASK      (0xffff<<0)
  328. #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  329. #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
  330. #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  331. #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  332. #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
  333. #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  334. #define GFX_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
  335. #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  336. #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
  337. #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
  338. #define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
  339. #define XY_MONO_SRC_COPY_IMM_BLT        ((2<<29)|(0x71<<22)|5)
  340. #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
  341. #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
  342. #define   BLT_DEPTH_8                   (0<<24)
  343. #define   BLT_DEPTH_16_565              (1<<24)
  344. #define   BLT_DEPTH_16_1555             (2<<24)
  345. #define   BLT_DEPTH_32                  (3<<24)
  346. #define   BLT_ROP_GXCOPY                (0xcc<<16)
  347. #define XY_SRC_COPY_BLT_SRC_TILED       (1<<15) /* 965+ only */
  348. #define XY_SRC_COPY_BLT_DST_TILED       (1<<11) /* 965+ only */
  349. #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
  350. #define   ASYNC_FLIP                (1<<22)
  351. #define   DISPLAY_PLANE_A           (0<<20)
  352. #define   DISPLAY_PLANE_B           (1<<20)
  353. #define GFX_OP_PIPE_CONTROL(len)        ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
  354. #define   PIPE_CONTROL_GLOBAL_GTT_IVB                   (1<<24) /* gen7+ */
  355. #define   PIPE_CONTROL_MMIO_WRITE                       (1<<23)
  356. #define   PIPE_CONTROL_STORE_DATA_INDEX                 (1<<21)
  357. #define   PIPE_CONTROL_CS_STALL                         (1<<20)
  358. #define   PIPE_CONTROL_TLB_INVALIDATE                   (1<<18)
  359. #define   PIPE_CONTROL_QW_WRITE (1<<14)
  360. #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
  361. #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
  362. #define   PIPE_CONTROL_WRITE_FLUSH                      (1<<12)
  363. #define   PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH        (1<<12) /* gen6+ */
  364. #define   PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE     (1<<11) /* MBZ on Ironlake */
  365. #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE         (1<<10) /* GM45+ only */
  366. #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE           (1<<9)
  367. #define   PIPE_CONTROL_NOTIFY   (1<<8)
  368. #define   PIPE_CONTROL_FLUSH_ENABLE                     (1<<7) /* gen7+ */
  369. #define   PIPE_CONTROL_VF_CACHE_INVALIDATE              (1<<4)
  370. #define   PIPE_CONTROL_CONST_CACHE_INVALIDATE           (1<<3)
  371. #define   PIPE_CONTROL_STATE_CACHE_INVALIDATE           (1<<2)
  372. #define   PIPE_CONTROL_STALL_AT_SCOREBOARD              (1<<1)
  373. #define   PIPE_CONTROL_DEPTH_CACHE_FLUSH                (1<<0)
  374. #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
  375.  
  376. /*
  377.  * Commands used only by the command parser
  378.  */
  379. #define MI_SET_PREDICATE        MI_INSTR(0x01, 0)
  380. #define MI_ARB_CHECK            MI_INSTR(0x05, 0)
  381. #define MI_RS_CONTROL           MI_INSTR(0x06, 0)
  382. #define MI_URB_ATOMIC_ALLOC     MI_INSTR(0x09, 0)
  383. #define MI_PREDICATE            MI_INSTR(0x0C, 0)
  384. #define MI_RS_CONTEXT           MI_INSTR(0x0F, 0)
  385. #define MI_TOPOLOGY_FILTER      MI_INSTR(0x0D, 0)
  386. #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
  387. #define MI_URB_CLEAR            MI_INSTR(0x19, 0)
  388. #define MI_UPDATE_GTT           MI_INSTR(0x23, 0)
  389. #define MI_CLFLUSH              MI_INSTR(0x27, 0)
  390. #define MI_REPORT_PERF_COUNT    MI_INSTR(0x28, 0)
  391. #define   MI_REPORT_PERF_COUNT_GGTT (1<<0)
  392. #define MI_LOAD_REGISTER_MEM    MI_INSTR(0x29, 0)
  393. #define MI_LOAD_REGISTER_REG    MI_INSTR(0x2A, 0)
  394. #define MI_RS_STORE_DATA_IMM    MI_INSTR(0x2B, 0)
  395. #define MI_LOAD_URB_MEM         MI_INSTR(0x2C, 0)
  396. #define MI_STORE_URB_MEM        MI_INSTR(0x2D, 0)
  397. #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
  398.  
  399. #define PIPELINE_SELECT                ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
  400. #define GFX_OP_3DSTATE_VF_STATISTICS   ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
  401. #define MEDIA_VFE_STATE                ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
  402. #define  MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
  403. #define GPGPU_OBJECT                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
  404. #define GPGPU_WALKER                   ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
  405. #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
  406.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
  407. #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
  408.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
  409. #define GFX_OP_3DSTATE_SO_DECL_LIST \
  410.         ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
  411.  
  412. #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
  413.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
  414. #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
  415.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
  416. #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
  417.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
  418. #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
  419.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
  420. #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
  421.         ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
  422.  
  423. #define MFX_WAIT  ((0x3<<29)|(0x1<<27)|(0x0<<16))
  424.  
  425. #define COLOR_BLT     ((0x2<<29)|(0x40<<22))
  426. #define SRC_COPY_BLT  ((0x2<<29)|(0x43<<22))
  427.  
  428. /*
  429.  * Registers used only by the command parser
  430.  */
  431. #define BCS_SWCTRL 0x22200
  432.  
  433. #define HS_INVOCATION_COUNT 0x2300
  434. #define DS_INVOCATION_COUNT 0x2308
  435. #define IA_VERTICES_COUNT   0x2310
  436. #define IA_PRIMITIVES_COUNT 0x2318
  437. #define VS_INVOCATION_COUNT 0x2320
  438. #define GS_INVOCATION_COUNT 0x2328
  439. #define GS_PRIMITIVES_COUNT 0x2330
  440. #define CL_INVOCATION_COUNT 0x2338
  441. #define CL_PRIMITIVES_COUNT 0x2340
  442. #define PS_INVOCATION_COUNT 0x2348
  443. #define PS_DEPTH_COUNT      0x2350
  444.  
  445. /* There are the 4 64-bit counter registers, one for each stream output */
  446. #define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
  447.  
  448. #define GEN7_SO_PRIM_STORAGE_NEEDED(n)  (0x5240 + (n) * 8)
  449.  
  450. #define GEN7_3DPRIM_END_OFFSET          0x2420
  451. #define GEN7_3DPRIM_START_VERTEX        0x2430
  452. #define GEN7_3DPRIM_VERTEX_COUNT        0x2434
  453. #define GEN7_3DPRIM_INSTANCE_COUNT      0x2438
  454. #define GEN7_3DPRIM_START_INSTANCE      0x243C
  455. #define GEN7_3DPRIM_BASE_VERTEX         0x2440
  456.  
  457. #define OACONTROL 0x2360
  458.  
  459. #define _GEN7_PIPEA_DE_LOAD_SL  0x70068
  460. #define _GEN7_PIPEB_DE_LOAD_SL  0x71068
  461. #define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \
  462.                                          _GEN7_PIPEA_DE_LOAD_SL, \
  463.                                          _GEN7_PIPEB_DE_LOAD_SL)
  464.  
  465. /*
  466.  * Reset registers
  467.  */
  468. #define DEBUG_RESET_I830                0x6070
  469. #define  DEBUG_RESET_FULL               (1<<7)
  470. #define  DEBUG_RESET_RENDER             (1<<8)
  471. #define  DEBUG_RESET_DISPLAY            (1<<9)
  472.  
  473. /*
  474.  * IOSF sideband
  475.  */
  476. #define VLV_IOSF_DOORBELL_REQ                   (VLV_DISPLAY_BASE + 0x2100)
  477. #define   IOSF_DEVFN_SHIFT                      24
  478. #define   IOSF_OPCODE_SHIFT                     16
  479. #define   IOSF_PORT_SHIFT                       8
  480. #define   IOSF_BYTE_ENABLES_SHIFT               4
  481. #define   IOSF_BAR_SHIFT                        1
  482. #define   IOSF_SB_BUSY                          (1<<0)
  483. #define   IOSF_PORT_BUNIT                       0x3
  484. #define   IOSF_PORT_PUNIT                       0x4
  485. #define   IOSF_PORT_NC                          0x11
  486. #define   IOSF_PORT_DPIO                        0x12
  487. #define   IOSF_PORT_DPIO_2                      0x1a
  488. #define   IOSF_PORT_GPIO_NC                     0x13
  489. #define   IOSF_PORT_CCK                         0x14
  490. #define   IOSF_PORT_CCU                         0xA9
  491. #define   IOSF_PORT_GPS_CORE                    0x48
  492. #define   IOSF_PORT_FLISDSI                     0x1B
  493. #define VLV_IOSF_DATA                           (VLV_DISPLAY_BASE + 0x2104)
  494. #define VLV_IOSF_ADDR                           (VLV_DISPLAY_BASE + 0x2108)
  495.  
  496. /* See configdb bunit SB addr map */
  497. #define BUNIT_REG_BISOC                         0x11
  498.  
  499. #define PUNIT_REG_DSPFREQ                       0x36
  500. #define   DSPFREQSTAT_SHIFT                     30
  501. #define   DSPFREQSTAT_MASK                      (0x3 << DSPFREQSTAT_SHIFT)
  502. #define   DSPFREQGUAR_SHIFT                     14
  503. #define   DSPFREQGUAR_MASK                      (0x3 << DSPFREQGUAR_SHIFT)
  504.  
  505. /* See the PUNIT HAS v0.8 for the below bits */
  506. enum punit_power_well {
  507.         PUNIT_POWER_WELL_RENDER                 = 0,
  508.         PUNIT_POWER_WELL_MEDIA                  = 1,
  509.         PUNIT_POWER_WELL_DISP2D                 = 3,
  510.         PUNIT_POWER_WELL_DPIO_CMN_BC            = 5,
  511.         PUNIT_POWER_WELL_DPIO_TX_B_LANES_01     = 6,
  512.         PUNIT_POWER_WELL_DPIO_TX_B_LANES_23     = 7,
  513.         PUNIT_POWER_WELL_DPIO_TX_C_LANES_01     = 8,
  514.         PUNIT_POWER_WELL_DPIO_TX_C_LANES_23     = 9,
  515.         PUNIT_POWER_WELL_DPIO_RX0               = 10,
  516.         PUNIT_POWER_WELL_DPIO_RX1               = 11,
  517.  
  518.         PUNIT_POWER_WELL_NUM,
  519. };
  520.  
  521. #define PUNIT_REG_PWRGT_CTRL                    0x60
  522. #define PUNIT_REG_PWRGT_STATUS                  0x61
  523. #define   PUNIT_PWRGT_MASK(power_well)          (3 << ((power_well) * 2))
  524. #define   PUNIT_PWRGT_PWR_ON(power_well)        (0 << ((power_well) * 2))
  525. #define   PUNIT_PWRGT_CLK_GATE(power_well)      (1 << ((power_well) * 2))
  526. #define   PUNIT_PWRGT_RESET(power_well)         (2 << ((power_well) * 2))
  527. #define   PUNIT_PWRGT_PWR_GATE(power_well)      (3 << ((power_well) * 2))
  528.  
  529. #define PUNIT_REG_GPU_LFM                       0xd3
  530. #define PUNIT_REG_GPU_FREQ_REQ                  0xd4
  531. #define PUNIT_REG_GPU_FREQ_STS                  0xd8
  532. #define   GENFREQSTATUS                         (1<<0)
  533. #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ          0xdc
  534. #define PUNIT_REG_CZ_TIMESTAMP                  0xce
  535.  
  536. #define PUNIT_FUSE_BUS2                         0xf6 /* bits 47:40 */
  537. #define PUNIT_FUSE_BUS1                         0xf5 /* bits 55:48 */
  538.  
  539. #define PUNIT_GPU_STATUS_REG                    0xdb
  540. #define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
  541. #define PUNIT_GPU_STATUS_MAX_FREQ_MASK          0xff
  542. #define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT     8
  543. #define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK      0xff
  544.  
  545. #define PUNIT_GPU_DUTYCYCLE_REG         0xdf
  546. #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT      8
  547. #define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK       0xff
  548.  
  549. #define IOSF_NC_FB_GFX_FREQ_FUSE                0x1c
  550. #define   FB_GFX_MAX_FREQ_FUSE_SHIFT            3
  551. #define   FB_GFX_MAX_FREQ_FUSE_MASK             0x000007f8
  552. #define   FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT    11
  553. #define   FB_GFX_FGUARANTEED_FREQ_FUSE_MASK     0x0007f800
  554. #define IOSF_NC_FB_GFX_FMAX_FUSE_HI             0x34
  555. #define   FB_FMAX_VMIN_FREQ_HI_MASK             0x00000007
  556. #define IOSF_NC_FB_GFX_FMAX_FUSE_LO             0x30
  557. #define   FB_FMAX_VMIN_FREQ_LO_SHIFT            27
  558. #define   FB_FMAX_VMIN_FREQ_LO_MASK             0xf8000000
  559.  
  560. #define VLV_CZ_CLOCK_TO_MILLI_SEC               100000
  561. #define VLV_RP_UP_EI_THRESHOLD                  90
  562. #define VLV_RP_DOWN_EI_THRESHOLD                70
  563. #define VLV_INT_COUNT_FOR_DOWN_EI               5
  564.  
  565. /* vlv2 north clock has */
  566. #define CCK_FUSE_REG                            0x8
  567. #define  CCK_FUSE_HPLL_FREQ_MASK                0x3
  568. #define CCK_REG_DSI_PLL_FUSE                    0x44
  569. #define CCK_REG_DSI_PLL_CONTROL                 0x48
  570. #define  DSI_PLL_VCO_EN                         (1 << 31)
  571. #define  DSI_PLL_LDO_GATE                       (1 << 30)
  572. #define  DSI_PLL_P1_POST_DIV_SHIFT              17
  573. #define  DSI_PLL_P1_POST_DIV_MASK               (0x1ff << 17)
  574. #define  DSI_PLL_P2_MUX_DSI0_DIV2               (1 << 13)
  575. #define  DSI_PLL_P3_MUX_DSI1_DIV2               (1 << 12)
  576. #define  DSI_PLL_MUX_MASK                       (3 << 9)
  577. #define  DSI_PLL_MUX_DSI0_DSIPLL                (0 << 10)
  578. #define  DSI_PLL_MUX_DSI0_CCK                   (1 << 10)
  579. #define  DSI_PLL_MUX_DSI1_DSIPLL                (0 << 9)
  580. #define  DSI_PLL_MUX_DSI1_CCK                   (1 << 9)
  581. #define  DSI_PLL_CLK_GATE_MASK                  (0xf << 5)
  582. #define  DSI_PLL_CLK_GATE_DSI0_DSIPLL           (1 << 8)
  583. #define  DSI_PLL_CLK_GATE_DSI1_DSIPLL           (1 << 7)
  584. #define  DSI_PLL_CLK_GATE_DSI0_CCK              (1 << 6)
  585. #define  DSI_PLL_CLK_GATE_DSI1_CCK              (1 << 5)
  586. #define  DSI_PLL_LOCK                           (1 << 0)
  587. #define CCK_REG_DSI_PLL_DIVIDER                 0x4c
  588. #define  DSI_PLL_LFSR                           (1 << 31)
  589. #define  DSI_PLL_FRACTION_EN                    (1 << 30)
  590. #define  DSI_PLL_FRAC_COUNTER_SHIFT             27
  591. #define  DSI_PLL_FRAC_COUNTER_MASK              (7 << 27)
  592. #define  DSI_PLL_USYNC_CNT_SHIFT                18
  593. #define  DSI_PLL_USYNC_CNT_MASK                 (0x1ff << 18)
  594. #define  DSI_PLL_N1_DIV_SHIFT                   16
  595. #define  DSI_PLL_N1_DIV_MASK                    (3 << 16)
  596. #define  DSI_PLL_M1_DIV_SHIFT                   0
  597. #define  DSI_PLL_M1_DIV_MASK                    (0x1ff << 0)
  598. #define CCK_DISPLAY_CLOCK_CONTROL               0x6b
  599. #define  DISPLAY_TRUNK_FORCE_ON                 (1 << 17)
  600. #define  DISPLAY_TRUNK_FORCE_OFF                (1 << 16)
  601. #define  DISPLAY_FREQUENCY_STATUS               (0x1f << 8)
  602. #define  DISPLAY_FREQUENCY_STATUS_SHIFT         8
  603. #define  DISPLAY_FREQUENCY_VALUES               (0x1f << 0)
  604.  
  605. /**
  606.  * DOC: DPIO
  607.  *
  608.  * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI
  609.  * ports. DPIO is the name given to such a display PHY. These PHYs
  610.  * don't follow the standard programming model using direct MMIO
  611.  * registers, and instead their registers must be accessed trough IOSF
  612.  * sideband. VLV has one such PHY for driving ports B and C, and CHV
  613.  * adds another PHY for driving port D. Each PHY responds to specific
  614.  * IOSF-SB port.
  615.  *
  616.  * Each display PHY is made up of one or two channels. Each channel
  617.  * houses a common lane part which contains the PLL and other common
  618.  * logic. CH0 common lane also contains the IOSF-SB logic for the
  619.  * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
  620.  * must be running when any DPIO registers are accessed.
  621.  *
  622.  * In addition to having their own registers, the PHYs are also
  623.  * controlled through some dedicated signals from the display
  624.  * controller. These include PLL reference clock enable, PLL enable,
  625.  * and CRI clock selection, for example.
  626.  *
  627.  * Eeach channel also has two splines (also called data lanes), and
  628.  * each spline is made up of one Physical Access Coding Sub-Layer
  629.  * (PCS) block and two TX lanes. So each channel has two PCS blocks
  630.  * and four TX lanes. The TX lanes are used as DP lanes or TMDS
  631.  * data/clock pairs depending on the output type.
  632.  *
  633.  * Additionally the PHY also contains an AUX lane with AUX blocks
  634.  * for each channel. This is used for DP AUX communication, but
  635.  * this fact isn't really relevant for the driver since AUX is
  636.  * controlled from the display controller side. No DPIO registers
  637.  * need to be accessed during AUX communication,
  638.  *
  639.  * Generally the common lane corresponds to the pipe and
  640.  * the spline (PCS/TX) correponds to the port.
  641.  *
  642.  * For dual channel PHY (VLV/CHV):
  643.  *
  644.  *  pipe A == CMN/PLL/REF CH0
  645.  *
  646.  *  pipe B == CMN/PLL/REF CH1
  647.  *
  648.  *  port B == PCS/TX CH0
  649.  *
  650.  *  port C == PCS/TX CH1
  651.  *
  652.  * This is especially important when we cross the streams
  653.  * ie. drive port B with pipe B, or port C with pipe A.
  654.  *
  655.  * For single channel PHY (CHV):
  656.  *
  657.  *  pipe C == CMN/PLL/REF CH0
  658.  *
  659.  *  port D == PCS/TX CH0
  660.  *
  661.  * Note: digital port B is DDI0, digital port C is DDI1,
  662.  * digital port D is DDI2
  663.  */
  664. /*
  665.  * Dual channel PHY (VLV/CHV)
  666.  * ---------------------------------
  667.  * |      CH0      |      CH1      |
  668.  * |  CMN/PLL/REF  |  CMN/PLL/REF  |
  669.  * |---------------|---------------| Display PHY
  670.  * | PCS01 | PCS23 | PCS01 | PCS23 |
  671.  * |-------|-------|-------|-------|
  672.  * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
  673.  * ---------------------------------
  674.  * |     DDI0      |     DDI1      | DP/HDMI ports
  675.  * ---------------------------------
  676.  *
  677.  * Single channel PHY (CHV)
  678.  * -----------------
  679.  * |      CH0      |
  680.  * |  CMN/PLL/REF  |
  681.  * |---------------| Display PHY
  682.  * | PCS01 | PCS23 |
  683.  * |-------|-------|
  684.  * |TX0|TX1|TX2|TX3|
  685.  * -----------------
  686.  * |     DDI2      | DP/HDMI port
  687.  * -----------------
  688.  */
  689. #define DPIO_DEVFN                      0
  690.  
  691. #define DPIO_CTL                        (VLV_DISPLAY_BASE + 0x2110)
  692. #define  DPIO_MODSEL1                   (1<<3) /* if ref clk b == 27 */
  693. #define  DPIO_MODSEL0                   (1<<2) /* if ref clk a == 27 */
  694. #define  DPIO_SFR_BYPASS                (1<<1)
  695. #define  DPIO_CMNRST                    (1<<0)
  696.  
  697. #define DPIO_PHY(pipe)                  ((pipe) >> 1)
  698. #define DPIO_PHY_IOSF_PORT(phy)         (dev_priv->dpio_phy_iosf_port[phy])
  699.  
  700. /*
  701.  * Per pipe/PLL DPIO regs
  702.  */
  703. #define _VLV_PLL_DW3_CH0                0x800c
  704. #define   DPIO_POST_DIV_SHIFT           (28) /* 3 bits */
  705. #define   DPIO_POST_DIV_DAC             0
  706. #define   DPIO_POST_DIV_HDMIDP          1 /* DAC 225-400M rate */
  707. #define   DPIO_POST_DIV_LVDS1           2
  708. #define   DPIO_POST_DIV_LVDS2           3
  709. #define   DPIO_K_SHIFT                  (24) /* 4 bits */
  710. #define   DPIO_P1_SHIFT                 (21) /* 3 bits */
  711. #define   DPIO_P2_SHIFT                 (16) /* 5 bits */
  712. #define   DPIO_N_SHIFT                  (12) /* 4 bits */
  713. #define   DPIO_ENABLE_CALIBRATION       (1<<11)
  714. #define   DPIO_M1DIV_SHIFT              (8) /* 3 bits */
  715. #define   DPIO_M2DIV_MASK               0xff
  716. #define _VLV_PLL_DW3_CH1                0x802c
  717. #define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
  718.  
  719. #define _VLV_PLL_DW5_CH0                0x8014
  720. #define   DPIO_REFSEL_OVERRIDE          27
  721. #define   DPIO_PLL_MODESEL_SHIFT        24 /* 3 bits */
  722. #define   DPIO_BIAS_CURRENT_CTL_SHIFT   21 /* 3 bits, always 0x7 */
  723. #define   DPIO_PLL_REFCLK_SEL_SHIFT     16 /* 2 bits */
  724. #define   DPIO_PLL_REFCLK_SEL_MASK      3
  725. #define   DPIO_DRIVER_CTL_SHIFT         12 /* always set to 0x8 */
  726. #define   DPIO_CLK_BIAS_CTL_SHIFT       8 /* always set to 0x5 */
  727. #define _VLV_PLL_DW5_CH1                0x8034
  728. #define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
  729.  
  730. #define _VLV_PLL_DW7_CH0                0x801c
  731. #define _VLV_PLL_DW7_CH1                0x803c
  732. #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
  733.  
  734. #define _VLV_PLL_DW8_CH0                0x8040
  735. #define _VLV_PLL_DW8_CH1                0x8060
  736. #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
  737.  
  738. #define VLV_PLL_DW9_BCAST               0xc044
  739. #define _VLV_PLL_DW9_CH0                0x8044
  740. #define _VLV_PLL_DW9_CH1                0x8064
  741. #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
  742.  
  743. #define _VLV_PLL_DW10_CH0               0x8048
  744. #define _VLV_PLL_DW10_CH1               0x8068
  745. #define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
  746.  
  747. #define _VLV_PLL_DW11_CH0               0x804c
  748. #define _VLV_PLL_DW11_CH1               0x806c
  749. #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
  750.  
  751. /* Spec for ref block start counts at DW10 */
  752. #define VLV_REF_DW13                    0x80ac
  753.  
  754. #define VLV_CMN_DW0                     0x8100
  755.  
  756. /*
  757.  * Per DDI channel DPIO regs
  758.  */
  759.  
  760. #define _VLV_PCS_DW0_CH0                0x8200
  761. #define _VLV_PCS_DW0_CH1                0x8400
  762. #define   DPIO_PCS_TX_LANE2_RESET       (1<<16)
  763. #define   DPIO_PCS_TX_LANE1_RESET       (1<<7)
  764. #define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
  765.  
  766. #define _VLV_PCS01_DW0_CH0              0x200
  767. #define _VLV_PCS23_DW0_CH0              0x400
  768. #define _VLV_PCS01_DW0_CH1              0x2600
  769. #define _VLV_PCS23_DW0_CH1              0x2800
  770. #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
  771. #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
  772.  
  773. #define _VLV_PCS_DW1_CH0                0x8204
  774. #define _VLV_PCS_DW1_CH1                0x8404
  775. #define   CHV_PCS_REQ_SOFTRESET_EN      (1<<23)
  776. #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
  777. #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
  778. #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT  (6)
  779. #define   DPIO_PCS_CLK_SOFT_RESET       (1<<5)
  780. #define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
  781.  
  782. #define _VLV_PCS01_DW1_CH0              0x204
  783. #define _VLV_PCS23_DW1_CH0              0x404
  784. #define _VLV_PCS01_DW1_CH1              0x2604
  785. #define _VLV_PCS23_DW1_CH1              0x2804
  786. #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
  787. #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
  788.  
  789. #define _VLV_PCS_DW8_CH0                0x8220
  790. #define _VLV_PCS_DW8_CH1                0x8420
  791. #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE        (1 << 20)
  792. #define   CHV_PCS_USEDCLKCHANNEL                (1 << 21)
  793. #define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
  794.  
  795. #define _VLV_PCS01_DW8_CH0              0x0220
  796. #define _VLV_PCS23_DW8_CH0              0x0420
  797. #define _VLV_PCS01_DW8_CH1              0x2620
  798. #define _VLV_PCS23_DW8_CH1              0x2820
  799. #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
  800. #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
  801.  
  802. #define _VLV_PCS_DW9_CH0                0x8224
  803. #define _VLV_PCS_DW9_CH1                0x8424
  804. #define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
  805.  
  806. #define _CHV_PCS_DW10_CH0               0x8228
  807. #define _CHV_PCS_DW10_CH1               0x8428
  808. #define   DPIO_PCS_SWING_CALC_TX0_TX2   (1<<30)
  809. #define   DPIO_PCS_SWING_CALC_TX1_TX3   (1<<31)
  810. #define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
  811.  
  812. #define _VLV_PCS01_DW10_CH0             0x0228
  813. #define _VLV_PCS23_DW10_CH0             0x0428
  814. #define _VLV_PCS01_DW10_CH1             0x2628
  815. #define _VLV_PCS23_DW10_CH1             0x2828
  816. #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
  817. #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
  818.  
  819. #define _VLV_PCS_DW11_CH0               0x822c
  820. #define _VLV_PCS_DW11_CH1               0x842c
  821. #define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
  822.  
  823. #define _VLV_PCS_DW12_CH0               0x8230
  824. #define _VLV_PCS_DW12_CH1               0x8430
  825. #define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
  826.  
  827. #define _VLV_PCS_DW14_CH0               0x8238
  828. #define _VLV_PCS_DW14_CH1               0x8438
  829. #define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
  830.  
  831. #define _VLV_PCS_DW23_CH0               0x825c
  832. #define _VLV_PCS_DW23_CH1               0x845c
  833. #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
  834.  
  835. #define _VLV_TX_DW2_CH0                 0x8288
  836. #define _VLV_TX_DW2_CH1                 0x8488
  837. #define   DPIO_SWING_MARGIN_SHIFT       16
  838. #define   DPIO_SWING_MARGIN_MASK        (0xff << DPIO_SWING_MARGIN_SHIFT)
  839. #define   DPIO_UNIQ_TRANS_SCALE_SHIFT   8
  840. #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
  841.  
  842. #define _VLV_TX_DW3_CH0                 0x828c
  843. #define _VLV_TX_DW3_CH1                 0x848c
  844. /* The following bit for CHV phy */
  845. #define   DPIO_TX_UNIQ_TRANS_SCALE_EN   (1<<27)
  846. #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
  847.  
  848. #define _VLV_TX_DW4_CH0                 0x8290
  849. #define _VLV_TX_DW4_CH1                 0x8490
  850. #define   DPIO_SWING_DEEMPH9P5_SHIFT    24
  851. #define   DPIO_SWING_DEEMPH9P5_MASK     (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
  852. #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
  853.  
  854. #define _VLV_TX3_DW4_CH0                0x690
  855. #define _VLV_TX3_DW4_CH1                0x2a90
  856. #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
  857.  
  858. #define _VLV_TX_DW5_CH0                 0x8294
  859. #define _VLV_TX_DW5_CH1                 0x8494
  860. #define   DPIO_TX_OCALINIT_EN           (1<<31)
  861. #define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
  862.  
  863. #define _VLV_TX_DW11_CH0                0x82ac
  864. #define _VLV_TX_DW11_CH1                0x84ac
  865. #define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
  866.  
  867. #define _VLV_TX_DW14_CH0                0x82b8
  868. #define _VLV_TX_DW14_CH1                0x84b8
  869. #define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
  870.  
  871. /* CHV dpPhy registers */
  872. #define _CHV_PLL_DW0_CH0                0x8000
  873. #define _CHV_PLL_DW0_CH1                0x8180
  874. #define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
  875.  
  876. #define _CHV_PLL_DW1_CH0                0x8004
  877. #define _CHV_PLL_DW1_CH1                0x8184
  878. #define   DPIO_CHV_N_DIV_SHIFT          8
  879. #define   DPIO_CHV_M1_DIV_BY_2          (0 << 0)
  880. #define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
  881.  
  882. #define _CHV_PLL_DW2_CH0                0x8008
  883. #define _CHV_PLL_DW2_CH1                0x8188
  884. #define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
  885.  
  886. #define _CHV_PLL_DW3_CH0                0x800c
  887. #define _CHV_PLL_DW3_CH1                0x818c
  888. #define  DPIO_CHV_FRAC_DIV_EN           (1 << 16)
  889. #define  DPIO_CHV_FIRST_MOD             (0 << 8)
  890. #define  DPIO_CHV_SECOND_MOD            (1 << 8)
  891. #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT    0
  892. #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
  893.  
  894. #define _CHV_PLL_DW6_CH0                0x8018
  895. #define _CHV_PLL_DW6_CH1                0x8198
  896. #define   DPIO_CHV_GAIN_CTRL_SHIFT      16
  897. #define   DPIO_CHV_INT_COEFF_SHIFT      8
  898. #define   DPIO_CHV_PROP_COEFF_SHIFT     0
  899. #define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
  900.  
  901. #define _CHV_CMN_DW5_CH0               0x8114
  902. #define   CHV_BUFRIGHTENA1_DISABLE      (0 << 20)
  903. #define   CHV_BUFRIGHTENA1_NORMAL       (1 << 20)
  904. #define   CHV_BUFRIGHTENA1_FORCE        (3 << 20)
  905. #define   CHV_BUFRIGHTENA1_MASK         (3 << 20)
  906. #define   CHV_BUFLEFTENA1_DISABLE       (0 << 22)
  907. #define   CHV_BUFLEFTENA1_NORMAL        (1 << 22)
  908. #define   CHV_BUFLEFTENA1_FORCE         (3 << 22)
  909. #define   CHV_BUFLEFTENA1_MASK          (3 << 22)
  910.  
  911. #define _CHV_CMN_DW13_CH0               0x8134
  912. #define _CHV_CMN_DW0_CH1                0x8080
  913. #define   DPIO_CHV_S1_DIV_SHIFT         21
  914. #define   DPIO_CHV_P1_DIV_SHIFT         13 /* 3 bits */
  915. #define   DPIO_CHV_P2_DIV_SHIFT         8  /* 5 bits */
  916. #define   DPIO_CHV_K_DIV_SHIFT          4
  917. #define   DPIO_PLL_FREQLOCK             (1 << 1)
  918. #define   DPIO_PLL_LOCK                 (1 << 0)
  919. #define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
  920.  
  921. #define _CHV_CMN_DW14_CH0               0x8138
  922. #define _CHV_CMN_DW1_CH1                0x8084
  923. #define   DPIO_AFC_RECAL                (1 << 14)
  924. #define   DPIO_DCLKP_EN                 (1 << 13)
  925. #define   CHV_BUFLEFTENA2_DISABLE       (0 << 17) /* CL2 DW1 only */
  926. #define   CHV_BUFLEFTENA2_NORMAL        (1 << 17) /* CL2 DW1 only */
  927. #define   CHV_BUFLEFTENA2_FORCE         (3 << 17) /* CL2 DW1 only */
  928. #define   CHV_BUFLEFTENA2_MASK          (3 << 17) /* CL2 DW1 only */
  929. #define   CHV_BUFRIGHTENA2_DISABLE      (0 << 19) /* CL2 DW1 only */
  930. #define   CHV_BUFRIGHTENA2_NORMAL       (1 << 19) /* CL2 DW1 only */
  931. #define   CHV_BUFRIGHTENA2_FORCE        (3 << 19) /* CL2 DW1 only */
  932. #define   CHV_BUFRIGHTENA2_MASK         (3 << 19) /* CL2 DW1 only */
  933. #define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
  934.  
  935. #define _CHV_CMN_DW19_CH0               0x814c
  936. #define _CHV_CMN_DW6_CH1                0x8098
  937. #define   CHV_CMN_USEDCLKCHANNEL        (1 << 13)
  938. #define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
  939.  
  940. #define CHV_CMN_DW30                    0x8178
  941. #define   DPIO_LRC_BYPASS               (1 << 3)
  942.  
  943. #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
  944.                                         (lane) * 0x200 + (offset))
  945.  
  946. #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
  947. #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
  948. #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
  949. #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
  950. #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
  951. #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
  952. #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
  953. #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
  954. #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
  955. #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
  956. #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
  957. #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
  958. #define   DPIO_FRC_LATENCY_SHFIT        8
  959. #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
  960. #define   DPIO_UPAR_SHIFT               30
  961. /*
  962.  * Fence registers
  963.  */
  964. #define FENCE_REG_830_0                 0x2000
  965. #define FENCE_REG_945_8                 0x3000
  966. #define   I830_FENCE_START_MASK         0x07f80000
  967. #define   I830_FENCE_TILING_Y_SHIFT     12
  968. #define   I830_FENCE_SIZE_BITS(size)    ((ffs((size) >> 19) - 1) << 8)
  969. #define   I830_FENCE_PITCH_SHIFT        4
  970. #define   I830_FENCE_REG_VALID          (1<<0)
  971. #define   I915_FENCE_MAX_PITCH_VAL      4
  972. #define   I830_FENCE_MAX_PITCH_VAL      6
  973. #define   I830_FENCE_MAX_SIZE_VAL       (1<<8)
  974.  
  975. #define   I915_FENCE_START_MASK         0x0ff00000
  976. #define   I915_FENCE_SIZE_BITS(size)    ((ffs((size) >> 20) - 1) << 8)
  977.  
  978. #define FENCE_REG_965_0                 0x03000
  979. #define   I965_FENCE_PITCH_SHIFT        2
  980. #define   I965_FENCE_TILING_Y_SHIFT     1
  981. #define   I965_FENCE_REG_VALID          (1<<0)
  982. #define   I965_FENCE_MAX_PITCH_VAL      0x0400
  983.  
  984. #define FENCE_REG_SANDYBRIDGE_0         0x100000
  985. #define   SANDYBRIDGE_FENCE_PITCH_SHIFT 32
  986. #define   GEN7_FENCE_MAX_PITCH_VAL      0x0800
  987.  
  988.  
  989. /* control register for cpu gtt access */
  990. #define TILECTL                         0x101000
  991. #define   TILECTL_SWZCTL                        (1 << 0)
  992. #define   TILECTL_TLB_PREFETCH_DIS      (1 << 2)
  993. #define   TILECTL_BACKSNOOP_DIS         (1 << 3)
  994.  
  995. /*
  996.  * Instruction and interrupt control regs
  997.  */
  998. #define PGTBL_CTL       0x02020
  999. #define   PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
  1000. #define   PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
  1001. #define PGTBL_ER        0x02024
  1002. #define RENDER_RING_BASE        0x02000
  1003. #define BSD_RING_BASE           0x04000
  1004. #define GEN6_BSD_RING_BASE      0x12000
  1005. #define GEN8_BSD2_RING_BASE     0x1c000
  1006. #define VEBOX_RING_BASE         0x1a000
  1007. #define BLT_RING_BASE           0x22000
  1008. #define RING_TAIL(base)         ((base)+0x30)
  1009. #define RING_HEAD(base)         ((base)+0x34)
  1010. #define RING_START(base)        ((base)+0x38)
  1011. #define RING_CTL(base)          ((base)+0x3c)
  1012. #define RING_SYNC_0(base)       ((base)+0x40)
  1013. #define RING_SYNC_1(base)       ((base)+0x44)
  1014. #define RING_SYNC_2(base)       ((base)+0x48)
  1015. #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
  1016. #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
  1017. #define GEN6_RVESYNC    (RING_SYNC_2(RENDER_RING_BASE))
  1018. #define GEN6_VBSYNC     (RING_SYNC_0(GEN6_BSD_RING_BASE))
  1019. #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
  1020. #define GEN6_VVESYNC    (RING_SYNC_2(GEN6_BSD_RING_BASE))
  1021. #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
  1022. #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
  1023. #define GEN6_BVESYNC    (RING_SYNC_2(BLT_RING_BASE))
  1024. #define GEN6_VEBSYNC    (RING_SYNC_0(VEBOX_RING_BASE))
  1025. #define GEN6_VERSYNC    (RING_SYNC_1(VEBOX_RING_BASE))
  1026. #define GEN6_VEVSYNC    (RING_SYNC_2(VEBOX_RING_BASE))
  1027. #define GEN6_NOSYNC 0
  1028. #define RING_MAX_IDLE(base)     ((base)+0x54)
  1029. #define RING_HWS_PGA(base)      ((base)+0x80)
  1030. #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
  1031.  
  1032. #define GEN7_WR_WATERMARK       0x4028
  1033. #define GEN7_GFX_PRIO_CTRL      0x402C
  1034. #define ARB_MODE                0x4030
  1035. #define   ARB_MODE_SWIZZLE_SNB  (1<<4)
  1036. #define   ARB_MODE_SWIZZLE_IVB  (1<<5)
  1037. #define GEN7_GFX_PEND_TLB0      0x4034
  1038. #define GEN7_GFX_PEND_TLB1      0x4038
  1039. /* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
  1040. #define GEN7_LRA_LIMITS_BASE    0x403C
  1041. #define GEN7_LRA_LIMITS_REG_NUM 13
  1042. #define GEN7_MEDIA_MAX_REQ_COUNT        0x4070
  1043. #define GEN7_GFX_MAX_REQ_COUNT          0x4074
  1044.  
  1045. #define GAMTARBMODE             0x04a08
  1046. #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
  1047. #define   ARB_MODE_SWIZZLE_BDW  (1<<1)
  1048. #define RENDER_HWS_PGA_GEN7     (0x04080)
  1049. #define RING_FAULT_REG(ring)    (0x4094 + 0x100*(ring)->id)
  1050. #define   RING_FAULT_GTTSEL_MASK (1<<11)
  1051. #define   RING_FAULT_SRCID(x)   ((x >> 3) & 0xff)
  1052. #define   RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
  1053. #define   RING_FAULT_VALID      (1<<0)
  1054. #define DONE_REG                0x40b0
  1055. #define GEN8_PRIVATE_PAT        0x40e0
  1056. #define BSD_HWS_PGA_GEN7        (0x04180)
  1057. #define BLT_HWS_PGA_GEN7        (0x04280)
  1058. #define VEBOX_HWS_PGA_GEN7      (0x04380)
  1059. #define RING_ACTHD(base)        ((base)+0x74)
  1060. #define RING_ACTHD_UDW(base)    ((base)+0x5c)
  1061. #define RING_NOPID(base)        ((base)+0x94)
  1062. #define RING_IMR(base)          ((base)+0xa8)
  1063. #define RING_TIMESTAMP(base)    ((base)+0x358)
  1064. #define   TAIL_ADDR             0x001FFFF8
  1065. #define   HEAD_WRAP_COUNT       0xFFE00000
  1066. #define   HEAD_WRAP_ONE         0x00200000
  1067. #define   HEAD_ADDR             0x001FFFFC
  1068. #define   RING_NR_PAGES         0x001FF000
  1069. #define   RING_REPORT_MASK      0x00000006
  1070. #define   RING_REPORT_64K       0x00000002
  1071. #define   RING_REPORT_128K      0x00000004
  1072. #define   RING_NO_REPORT        0x00000000
  1073. #define   RING_VALID_MASK       0x00000001
  1074. #define   RING_VALID            0x00000001
  1075. #define   RING_INVALID          0x00000000
  1076. #define   RING_WAIT_I8XX        (1<<0) /* gen2, PRBx_HEAD */
  1077. #define   RING_WAIT             (1<<11) /* gen3+, PRBx_CTL */
  1078. #define   RING_WAIT_SEMAPHORE   (1<<10) /* gen6+ */
  1079.  
  1080. #define GEN7_TLB_RD_ADDR        0x4700
  1081.  
  1082. #if 0
  1083. #define PRB0_TAIL       0x02030
  1084. #define PRB0_HEAD       0x02034
  1085. #define PRB0_START      0x02038
  1086. #define PRB0_CTL        0x0203c
  1087. #define PRB1_TAIL       0x02040 /* 915+ only */
  1088. #define PRB1_HEAD       0x02044 /* 915+ only */
  1089. #define PRB1_START      0x02048 /* 915+ only */
  1090. #define PRB1_CTL        0x0204c /* 915+ only */
  1091. #endif
  1092. #define IPEIR_I965      0x02064
  1093. #define IPEHR_I965      0x02068
  1094. #define INSTDONE_I965   0x0206c
  1095. #define GEN7_INSTDONE_1         0x0206c
  1096. #define GEN7_SC_INSTDONE        0x07100
  1097. #define GEN7_SAMPLER_INSTDONE   0x0e160
  1098. #define GEN7_ROW_INSTDONE       0x0e164
  1099. #define I915_NUM_INSTDONE_REG   4
  1100. #define RING_IPEIR(base)        ((base)+0x64)
  1101. #define RING_IPEHR(base)        ((base)+0x68)
  1102. #define RING_INSTDONE(base)     ((base)+0x6c)
  1103. #define RING_INSTPS(base)       ((base)+0x70)
  1104. #define RING_DMA_FADD(base)     ((base)+0x78)
  1105. #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */
  1106. #define RING_INSTPM(base)       ((base)+0xc0)
  1107. #define RING_MI_MODE(base)      ((base)+0x9c)
  1108. #define INSTPS          0x02070 /* 965+ only */
  1109. #define INSTDONE1       0x0207c /* 965+ only */
  1110. #define ACTHD_I965      0x02074
  1111. #define HWS_PGA         0x02080
  1112. #define HWS_ADDRESS_MASK        0xfffff000
  1113. #define HWS_START_ADDRESS_SHIFT 4
  1114. #define PWRCTXA         0x2088 /* 965GM+ only */
  1115. #define   PWRCTX_EN     (1<<0)
  1116. #define IPEIR           0x02088
  1117. #define IPEHR           0x0208c
  1118. #define INSTDONE        0x02090
  1119. #define NOPID           0x02094
  1120. #define HWSTAM          0x02098
  1121. #define DMA_FADD_I8XX   0x020d0
  1122. #define RING_BBSTATE(base)      ((base)+0x110)
  1123. #define RING_BBADDR(base)       ((base)+0x140)
  1124. #define RING_BBADDR_UDW(base)   ((base)+0x168) /* gen8+ */
  1125.  
  1126. #define ERROR_GEN6      0x040a0
  1127. #define GEN7_ERR_INT    0x44040
  1128. #define   ERR_INT_POISON                (1<<31)
  1129. #define   ERR_INT_MMIO_UNCLAIMED (1<<13)
  1130. #define   ERR_INT_PIPE_CRC_DONE_C       (1<<8)
  1131. #define   ERR_INT_FIFO_UNDERRUN_C       (1<<6)
  1132. #define   ERR_INT_PIPE_CRC_DONE_B       (1<<5)
  1133. #define   ERR_INT_FIFO_UNDERRUN_B       (1<<3)
  1134. #define   ERR_INT_PIPE_CRC_DONE_A       (1<<2)
  1135. #define   ERR_INT_PIPE_CRC_DONE(pipe)   (1<<(2 + pipe*3))
  1136. #define   ERR_INT_FIFO_UNDERRUN_A       (1<<0)
  1137. #define   ERR_INT_FIFO_UNDERRUN(pipe)   (1<<(pipe*3))
  1138.  
  1139. #define FPGA_DBG                0x42300
  1140. #define   FPGA_DBG_RM_NOCLAIM   (1<<31)
  1141.  
  1142. #define DERRMR          0x44050
  1143. /* Note that HBLANK events are reserved on bdw+ */
  1144. #define   DERRMR_PIPEA_SCANLINE         (1<<0)
  1145. #define   DERRMR_PIPEA_PRI_FLIP_DONE    (1<<1)
  1146. #define   DERRMR_PIPEA_SPR_FLIP_DONE    (1<<2)
  1147. #define   DERRMR_PIPEA_VBLANK           (1<<3)
  1148. #define   DERRMR_PIPEA_HBLANK           (1<<5)
  1149. #define   DERRMR_PIPEB_SCANLINE         (1<<8)
  1150. #define   DERRMR_PIPEB_PRI_FLIP_DONE    (1<<9)
  1151. #define   DERRMR_PIPEB_SPR_FLIP_DONE    (1<<10)
  1152. #define   DERRMR_PIPEB_VBLANK           (1<<11)
  1153. #define   DERRMR_PIPEB_HBLANK           (1<<13)
  1154. /* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
  1155. #define   DERRMR_PIPEC_SCANLINE         (1<<14)
  1156. #define   DERRMR_PIPEC_PRI_FLIP_DONE    (1<<15)
  1157. #define   DERRMR_PIPEC_SPR_FLIP_DONE    (1<<20)
  1158. #define   DERRMR_PIPEC_VBLANK           (1<<21)
  1159. #define   DERRMR_PIPEC_HBLANK           (1<<22)
  1160.  
  1161.  
  1162. /* GM45+ chicken bits -- debug workaround bits that may be required
  1163.  * for various sorts of correct behavior.  The top 16 bits of each are
  1164.  * the enables for writing to the corresponding low bit.
  1165.  */
  1166. #define _3D_CHICKEN     0x02084
  1167. #define  _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB      (1 << 10)
  1168. #define _3D_CHICKEN2    0x0208c
  1169. /* Disables pipelining of read flushes past the SF-WIZ interface.
  1170.  * Required on all Ironlake steppings according to the B-Spec, but the
  1171.  * particular danger of not doing so is not specified.
  1172.  */
  1173. # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
  1174. #define _3D_CHICKEN3    0x02090
  1175. #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL             (1 << 10)
  1176. #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL          (1 << 5)
  1177. #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)       ((x)<<1) /* gen8+ */
  1178. #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH   (1 << 1) /* gen6 */
  1179.  
  1180. #define MI_MODE         0x0209c
  1181. # define VS_TIMER_DISPATCH                              (1 << 6)
  1182. # define MI_FLUSH_ENABLE                                (1 << 12)
  1183. # define ASYNC_FLIP_PERF_DISABLE                        (1 << 14)
  1184. # define MODE_IDLE                                      (1 << 9)
  1185. # define STOP_RING                                      (1 << 8)
  1186.  
  1187. #define GEN6_GT_MODE    0x20d0
  1188. #define GEN7_GT_MODE    0x7008
  1189. #define   GEN6_WIZ_HASHING(hi, lo)                      (((hi) << 9) | ((lo) << 7))
  1190. #define   GEN6_WIZ_HASHING_8x8                          GEN6_WIZ_HASHING(0, 0)
  1191. #define   GEN6_WIZ_HASHING_8x4                          GEN6_WIZ_HASHING(0, 1)
  1192. #define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
  1193. #define   GEN6_WIZ_HASHING_MASK                         (GEN6_WIZ_HASHING(1, 1) << 16)
  1194. #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
  1195.  
  1196. #define GFX_MODE        0x02520
  1197. #define GFX_MODE_GEN7   0x0229c
  1198. #define RING_MODE_GEN7(ring)    ((ring)->mmio_base+0x29c)
  1199. #define   GFX_RUN_LIST_ENABLE           (1<<15)
  1200. #define   GFX_TLB_INVALIDATE_EXPLICIT   (1<<13)
  1201. #define   GFX_SURFACE_FAULT_ENABLE      (1<<12)
  1202. #define   GFX_REPLAY_MODE               (1<<11)
  1203. #define   GFX_PSMI_GRANULARITY          (1<<10)
  1204. #define   GFX_PPGTT_ENABLE              (1<<9)
  1205.  
  1206. #define VLV_DISPLAY_BASE 0x180000
  1207. #define VLV_MIPI_BASE VLV_DISPLAY_BASE
  1208.  
  1209. #define VLV_GU_CTL0     (VLV_DISPLAY_BASE + 0x2030)
  1210. #define VLV_GU_CTL1     (VLV_DISPLAY_BASE + 0x2034)
  1211. #define SCPD0           0x0209c /* 915+ only */
  1212. #define IER             0x020a0
  1213. #define IIR             0x020a4
  1214. #define IMR             0x020a8
  1215. #define ISR             0x020ac
  1216. #define VLV_GUNIT_CLOCK_GATE    (VLV_DISPLAY_BASE + 0x2060)
  1217. #define   GINT_DIS              (1<<22)
  1218. #define   GCFG_DIS              (1<<8)
  1219. #define VLV_GUNIT_CLOCK_GATE2   (VLV_DISPLAY_BASE + 0x2064)
  1220. #define VLV_IIR_RW      (VLV_DISPLAY_BASE + 0x2084)
  1221. #define VLV_IER         (VLV_DISPLAY_BASE + 0x20a0)
  1222. #define VLV_IIR         (VLV_DISPLAY_BASE + 0x20a4)
  1223. #define VLV_IMR         (VLV_DISPLAY_BASE + 0x20a8)
  1224. #define VLV_ISR         (VLV_DISPLAY_BASE + 0x20ac)
  1225. #define VLV_PCBR        (VLV_DISPLAY_BASE + 0x2120)
  1226. #define VLV_PCBR_ADDR_SHIFT     12
  1227.  
  1228. #define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
  1229. #define EIR             0x020b0
  1230. #define EMR             0x020b4
  1231. #define ESR             0x020b8
  1232. #define   GM45_ERROR_PAGE_TABLE                         (1<<5)
  1233. #define   GM45_ERROR_MEM_PRIV                           (1<<4)
  1234. #define   I915_ERROR_PAGE_TABLE                         (1<<4)
  1235. #define   GM45_ERROR_CP_PRIV                            (1<<3)
  1236. #define   I915_ERROR_MEMORY_REFRESH                     (1<<1)
  1237. #define   I915_ERROR_INSTRUCTION                        (1<<0)
  1238. #define INSTPM          0x020c0
  1239. #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
  1240. #define   INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
  1241.                                         will not assert AGPBUSY# and will only
  1242.                                         be delivered when out of C3. */
  1243. #define   INSTPM_FORCE_ORDERING                         (1<<7) /* GEN6+ */
  1244. #define   INSTPM_TLB_INVALIDATE (1<<9)
  1245. #define   INSTPM_SYNC_FLUSH     (1<<5)
  1246. #define ACTHD           0x020c8
  1247. #define FW_BLC          0x020d8
  1248. #define FW_BLC2         0x020dc
  1249. #define FW_BLC_SELF     0x020e0 /* 915+ only */
  1250. #define   FW_BLC_SELF_EN_MASK      (1<<31)
  1251. #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
  1252. #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
  1253. #define MM_BURST_LENGTH     0x00700000
  1254. #define MM_FIFO_WATERMARK   0x0001F000
  1255. #define LM_BURST_LENGTH     0x00000700
  1256. #define LM_FIFO_WATERMARK   0x0000001F
  1257. #define MI_ARB_STATE    0x020e4 /* 915+ only */
  1258.  
  1259. /* Make render/texture TLB fetches lower priorty than associated data
  1260.  *   fetches. This is not turned on by default
  1261.  */
  1262. #define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
  1263.  
  1264. /* Isoch request wait on GTT enable (Display A/B/C streams).
  1265.  * Make isoch requests stall on the TLB update. May cause
  1266.  * display underruns (test mode only)
  1267.  */
  1268. #define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
  1269.  
  1270. /* Block grant count for isoch requests when block count is
  1271.  * set to a finite value.
  1272.  */
  1273. #define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
  1274. #define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
  1275. #define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
  1276. #define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
  1277. #define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
  1278.  
  1279. /* Enable render writes to complete in C2/C3/C4 power states.
  1280.  * If this isn't enabled, render writes are prevented in low
  1281.  * power states. That seems bad to me.
  1282.  */
  1283. #define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
  1284.  
  1285. /* This acknowledges an async flip immediately instead
  1286.  * of waiting for 2TLB fetches.
  1287.  */
  1288. #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
  1289.  
  1290. /* Enables non-sequential data reads through arbiter
  1291.  */
  1292. #define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
  1293.  
  1294. /* Disable FSB snooping of cacheable write cycles from binner/render
  1295.  * command stream
  1296.  */
  1297. #define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
  1298.  
  1299. /* Arbiter time slice for non-isoch streams */
  1300. #define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
  1301. #define   MI_ARB_TIME_SLICE_1                   (0 << 5)
  1302. #define   MI_ARB_TIME_SLICE_2                   (1 << 5)
  1303. #define   MI_ARB_TIME_SLICE_4                   (2 << 5)
  1304. #define   MI_ARB_TIME_SLICE_6                   (3 << 5)
  1305. #define   MI_ARB_TIME_SLICE_8                   (4 << 5)
  1306. #define   MI_ARB_TIME_SLICE_10                  (5 << 5)
  1307. #define   MI_ARB_TIME_SLICE_14                  (6 << 5)
  1308. #define   MI_ARB_TIME_SLICE_16                  (7 << 5)
  1309.  
  1310. /* Low priority grace period page size */
  1311. #define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
  1312. #define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
  1313.  
  1314. /* Disable display A/B trickle feed */
  1315. #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
  1316.  
  1317. /* Set display plane priority */
  1318. #define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
  1319. #define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
  1320.  
  1321. #define MI_STATE        0x020e4 /* gen2 only */
  1322. #define   MI_AGPBUSY_INT_EN                     (1 << 1) /* 85x only */
  1323. #define   MI_AGPBUSY_830_MODE                   (1 << 0) /* 85x only */
  1324.  
  1325. #define CACHE_MODE_0    0x02120 /* 915+ only */
  1326. #define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
  1327. #define   CM0_IZ_OPT_DISABLE      (1<<6)
  1328. #define   CM0_ZR_OPT_DISABLE      (1<<5)
  1329. #define   CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
  1330. #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
  1331. #define   CM0_COLOR_EVICT_DISABLE (1<<3)
  1332. #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
  1333. #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
  1334. #define GFX_FLSH_CNTL   0x02170 /* 915+ only */
  1335. #define GFX_FLSH_CNTL_GEN6      0x101008
  1336. #define   GFX_FLSH_CNTL_EN      (1<<0)
  1337. #define ECOSKPD         0x021d0
  1338. #define   ECO_GATING_CX_ONLY    (1<<3)
  1339. #define   ECO_FLIP_DONE         (1<<0)
  1340.  
  1341. #define CACHE_MODE_0_GEN7       0x7000 /* IVB+ */
  1342. #define RC_OP_FLUSH_ENABLE (1<<0)
  1343. #define   HIZ_RAW_STALL_OPT_DISABLE (1<<2)
  1344. #define CACHE_MODE_1            0x7004 /* IVB+ */
  1345. #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
  1346. #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1<<6)
  1347.  
  1348. #define GEN6_BLITTER_ECOSKPD    0x221d0
  1349. #define   GEN6_BLITTER_LOCK_SHIFT                       16
  1350. #define   GEN6_BLITTER_FBC_NOTIFY                       (1<<3)
  1351.  
  1352. #define GEN6_RC_SLEEP_PSMI_CONTROL      0x2050
  1353. #define   GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
  1354. #define   GEN8_FF_DOP_CLOCK_GATE_DISABLE        (1<<10)
  1355.  
  1356. #define GEN6_BSD_SLEEP_PSMI_CONTROL     0x12050
  1357. #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
  1358. #define   GEN6_BSD_SLEEP_FLUSH_DISABLE  (1 << 2)
  1359. #define   GEN6_BSD_SLEEP_INDICATOR      (1 << 3)
  1360. #define   GEN6_BSD_GO_INDICATOR         (1 << 4)
  1361.  
  1362. /* On modern GEN architectures interrupt control consists of two sets
  1363.  * of registers. The first set pertains to the ring generating the
  1364.  * interrupt. The second control is for the functional block generating the
  1365.  * interrupt. These are PM, GT, DE, etc.
  1366.  *
  1367.  * Luckily *knocks on wood* all the ring interrupt bits match up with the
  1368.  * GT interrupt bits, so we don't need to duplicate the defines.
  1369.  *
  1370.  * These defines should cover us well from SNB->HSW with minor exceptions
  1371.  * it can also work on ILK.
  1372.  */
  1373. #define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT         (1 << 26)
  1374. #define GT_BLT_CS_ERROR_INTERRUPT               (1 << 25)
  1375. #define GT_BLT_USER_INTERRUPT                   (1 << 22)
  1376. #define GT_BSD_CS_ERROR_INTERRUPT               (1 << 15)
  1377. #define GT_BSD_USER_INTERRUPT                   (1 << 12)
  1378. #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1  (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
  1379. #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT     (1 <<  5) /* !snb */
  1380. #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT      (1 <<  4)
  1381. #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT     (1 <<  3)
  1382. #define GT_RENDER_SYNC_STATUS_INTERRUPT         (1 <<  2)
  1383. #define GT_RENDER_DEBUG_INTERRUPT               (1 <<  1)
  1384. #define GT_RENDER_USER_INTERRUPT                (1 <<  0)
  1385.  
  1386. #define PM_VEBOX_CS_ERROR_INTERRUPT             (1 << 12) /* hsw+ */
  1387. #define PM_VEBOX_USER_INTERRUPT                 (1 << 10) /* hsw+ */
  1388.  
  1389. #define GT_PARITY_ERROR(dev) \
  1390.         (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
  1391.          (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
  1392.  
  1393. /* These are all the "old" interrupts */
  1394. #define ILK_BSD_USER_INTERRUPT                          (1<<5)
  1395.  
  1396. #define I915_PM_INTERRUPT                               (1<<31)
  1397. #define I915_ISP_INTERRUPT                              (1<<22)
  1398. #define I915_LPE_PIPE_B_INTERRUPT                       (1<<21)
  1399. #define I915_LPE_PIPE_A_INTERRUPT                       (1<<20)
  1400. #define I915_MIPIB_INTERRUPT                            (1<<19)
  1401. #define I915_MIPIA_INTERRUPT                            (1<<18)
  1402. #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT              (1<<18)
  1403. #define I915_DISPLAY_PORT_INTERRUPT                     (1<<17)
  1404. #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT            (1<<16)
  1405. #define I915_MASTER_ERROR_INTERRUPT                     (1<<15)
  1406. #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT      (1<<15)
  1407. #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT            (1<<14)
  1408. #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT        (1<<14) /* p-state */
  1409. #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT            (1<<13)
  1410. #define I915_HWB_OOM_INTERRUPT                          (1<<13)
  1411. #define I915_LPE_PIPE_C_INTERRUPT                       (1<<12)
  1412. #define I915_SYNC_STATUS_INTERRUPT                      (1<<12)
  1413. #define I915_MISC_INTERRUPT                             (1<<11)
  1414. #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT     (1<<11)
  1415. #define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT            (1<<10)
  1416. #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT     (1<<10)
  1417. #define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT             (1<<9)
  1418. #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT       (1<<9)
  1419. #define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT              (1<<8)
  1420. #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT     (1<<8)
  1421. #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT            (1<<7)
  1422. #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT             (1<<6)
  1423. #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT            (1<<5)
  1424. #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT             (1<<4)
  1425. #define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT              (1<<3)
  1426. #define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT              (1<<2)
  1427. #define I915_DEBUG_INTERRUPT                            (1<<2)
  1428. #define I915_WINVALID_INTERRUPT                         (1<<1)
  1429. #define I915_USER_INTERRUPT                             (1<<1)
  1430. #define I915_ASLE_INTERRUPT                             (1<<0)
  1431. #define I915_BSD_USER_INTERRUPT                         (1<<25)
  1432.  
  1433. #define GEN6_BSD_RNCID                  0x12198
  1434.  
  1435. #define GEN7_FF_THREAD_MODE             0x20a0
  1436. #define   GEN7_FF_SCHED_MASK            0x0077070
  1437. #define   GEN8_FF_DS_REF_CNT_FFME       (1 << 19)
  1438. #define   GEN7_FF_TS_SCHED_HS1          (0x5<<16)
  1439. #define   GEN7_FF_TS_SCHED_HS0          (0x3<<16)
  1440. #define   GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
  1441. #define   GEN7_FF_TS_SCHED_HW           (0x0<<16) /* Default */
  1442. #define   GEN7_FF_VS_REF_CNT_FFME       (1 << 15)
  1443. #define   GEN7_FF_VS_SCHED_HS1          (0x5<<12)
  1444. #define   GEN7_FF_VS_SCHED_HS0          (0x3<<12)
  1445. #define   GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
  1446. #define   GEN7_FF_VS_SCHED_HW           (0x0<<12)
  1447. #define   GEN7_FF_DS_SCHED_HS1          (0x5<<4)
  1448. #define   GEN7_FF_DS_SCHED_HS0          (0x3<<4)
  1449. #define   GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4)  /* Default */
  1450. #define   GEN7_FF_DS_SCHED_HW           (0x0<<4)
  1451.  
  1452. /*
  1453.  * Framebuffer compression (915+ only)
  1454.  */
  1455.  
  1456. #define FBC_CFB_BASE            0x03200 /* 4k page aligned */
  1457. #define FBC_LL_BASE             0x03204 /* 4k page aligned */
  1458. #define FBC_CONTROL             0x03208
  1459. #define   FBC_CTL_EN            (1<<31)
  1460. #define   FBC_CTL_PERIODIC      (1<<30)
  1461. #define   FBC_CTL_INTERVAL_SHIFT (16)
  1462. #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
  1463. #define   FBC_CTL_C3_IDLE       (1<<13)
  1464. #define   FBC_CTL_STRIDE_SHIFT  (5)
  1465. #define   FBC_CTL_FENCENO_SHIFT (0)
  1466. #define FBC_COMMAND             0x0320c
  1467. #define   FBC_CMD_COMPRESS      (1<<0)
  1468. #define FBC_STATUS              0x03210
  1469. #define   FBC_STAT_COMPRESSING  (1<<31)
  1470. #define   FBC_STAT_COMPRESSED   (1<<30)
  1471. #define   FBC_STAT_MODIFIED     (1<<29)
  1472. #define   FBC_STAT_CURRENT_LINE_SHIFT   (0)
  1473. #define FBC_CONTROL2            0x03214
  1474. #define   FBC_CTL_FENCE_DBL     (0<<4)
  1475. #define   FBC_CTL_IDLE_IMM      (0<<2)
  1476. #define   FBC_CTL_IDLE_FULL     (1<<2)
  1477. #define   FBC_CTL_IDLE_LINE     (2<<2)
  1478. #define   FBC_CTL_IDLE_DEBUG    (3<<2)
  1479. #define   FBC_CTL_CPU_FENCE     (1<<1)
  1480. #define   FBC_CTL_PLANE(plane)  ((plane)<<0)
  1481. #define FBC_FENCE_OFF           0x03218 /* BSpec typo has 321Bh */
  1482. #define FBC_TAG                 0x03300
  1483.  
  1484. #define FBC_LL_SIZE             (1536)
  1485.  
  1486. /* Framebuffer compression for GM45+ */
  1487. #define DPFC_CB_BASE            0x3200
  1488. #define DPFC_CONTROL            0x3208
  1489. #define   DPFC_CTL_EN           (1<<31)
  1490. #define   DPFC_CTL_PLANE(plane) ((plane)<<30)
  1491. #define   IVB_DPFC_CTL_PLANE(plane)     ((plane)<<29)
  1492. #define   DPFC_CTL_FENCE_EN     (1<<29)
  1493. #define   IVB_DPFC_CTL_FENCE_EN (1<<28)
  1494. #define   DPFC_CTL_PERSISTENT_MODE      (1<<25)
  1495. #define   DPFC_SR_EN            (1<<10)
  1496. #define   DPFC_CTL_LIMIT_1X     (0<<6)
  1497. #define   DPFC_CTL_LIMIT_2X     (1<<6)
  1498. #define   DPFC_CTL_LIMIT_4X     (2<<6)
  1499. #define DPFC_RECOMP_CTL         0x320c
  1500. #define   DPFC_RECOMP_STALL_EN  (1<<27)
  1501. #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
  1502. #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
  1503. #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
  1504. #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
  1505. #define DPFC_STATUS             0x3210
  1506. #define   DPFC_INVAL_SEG_SHIFT  (16)
  1507. #define   DPFC_INVAL_SEG_MASK   (0x07ff0000)
  1508. #define   DPFC_COMP_SEG_SHIFT   (0)
  1509. #define   DPFC_COMP_SEG_MASK    (0x000003ff)
  1510. #define DPFC_STATUS2            0x3214
  1511. #define DPFC_FENCE_YOFF         0x3218
  1512. #define DPFC_CHICKEN            0x3224
  1513. #define   DPFC_HT_MODIFY        (1<<31)
  1514.  
  1515. /* Framebuffer compression for Ironlake */
  1516. #define ILK_DPFC_CB_BASE        0x43200
  1517. #define ILK_DPFC_CONTROL        0x43208
  1518. /* The bit 28-8 is reserved */
  1519. #define   DPFC_RESERVED         (0x1FFFFF00)
  1520. #define ILK_DPFC_RECOMP_CTL     0x4320c
  1521. #define ILK_DPFC_STATUS         0x43210
  1522. #define ILK_DPFC_FENCE_YOFF     0x43218
  1523. #define ILK_DPFC_CHICKEN        0x43224
  1524. #define ILK_FBC_RT_BASE         0x2128
  1525. #define   ILK_FBC_RT_VALID      (1<<0)
  1526. #define   SNB_FBC_FRONT_BUFFER  (1<<1)
  1527.  
  1528. #define ILK_DISPLAY_CHICKEN1    0x42000
  1529. #define   ILK_FBCQ_DIS          (1<<22)
  1530. #define   ILK_PABSTRETCH_DIS    (1<<21)
  1531.  
  1532.  
  1533. /*
  1534.  * Framebuffer compression for Sandybridge
  1535.  *
  1536.  * The following two registers are of type GTTMMADR
  1537.  */
  1538. #define SNB_DPFC_CTL_SA         0x100100
  1539. #define   SNB_CPU_FENCE_ENABLE  (1<<29)
  1540. #define DPFC_CPU_FENCE_OFFSET   0x100104
  1541.  
  1542. /* Framebuffer compression for Ivybridge */
  1543. #define IVB_FBC_RT_BASE                 0x7020
  1544.  
  1545. #define IPS_CTL         0x43408
  1546. #define   IPS_ENABLE    (1 << 31)
  1547.  
  1548. #define MSG_FBC_REND_STATE      0x50380
  1549. #define   FBC_REND_NUKE         (1<<2)
  1550. #define   FBC_REND_CACHE_CLEAN  (1<<1)
  1551.  
  1552. /*
  1553.  * GPIO regs
  1554.  */
  1555. #define GPIOA                   0x5010
  1556. #define GPIOB                   0x5014
  1557. #define GPIOC                   0x5018
  1558. #define GPIOD                   0x501c
  1559. #define GPIOE                   0x5020
  1560. #define GPIOF                   0x5024
  1561. #define GPIOG                   0x5028
  1562. #define GPIOH                   0x502c
  1563. # define GPIO_CLOCK_DIR_MASK            (1 << 0)
  1564. # define GPIO_CLOCK_DIR_IN              (0 << 1)
  1565. # define GPIO_CLOCK_DIR_OUT             (1 << 1)
  1566. # define GPIO_CLOCK_VAL_MASK            (1 << 2)
  1567. # define GPIO_CLOCK_VAL_OUT             (1 << 3)
  1568. # define GPIO_CLOCK_VAL_IN              (1 << 4)
  1569. # define GPIO_CLOCK_PULLUP_DISABLE      (1 << 5)
  1570. # define GPIO_DATA_DIR_MASK             (1 << 8)
  1571. # define GPIO_DATA_DIR_IN               (0 << 9)
  1572. # define GPIO_DATA_DIR_OUT              (1 << 9)
  1573. # define GPIO_DATA_VAL_MASK             (1 << 10)
  1574. # define GPIO_DATA_VAL_OUT              (1 << 11)
  1575. # define GPIO_DATA_VAL_IN               (1 << 12)
  1576. # define GPIO_DATA_PULLUP_DISABLE       (1 << 13)
  1577.  
  1578. #define GMBUS0                  0x5100 /* clock/port select */
  1579. #define   GMBUS_RATE_100KHZ     (0<<8)
  1580. #define   GMBUS_RATE_50KHZ      (1<<8)
  1581. #define   GMBUS_RATE_400KHZ     (2<<8) /* reserved on Pineview */
  1582. #define   GMBUS_RATE_1MHZ       (3<<8) /* reserved on Pineview */
  1583. #define   GMBUS_HOLD_EXT        (1<<7) /* 300ns hold time, rsvd on Pineview */
  1584. #define   GMBUS_PORT_DISABLED   0
  1585. #define   GMBUS_PORT_SSC        1
  1586. #define   GMBUS_PORT_VGADDC     2
  1587. #define   GMBUS_PORT_PANEL      3
  1588. #define   GMBUS_PORT_DPD_CHV    3 /* HDMID_CHV */
  1589. #define   GMBUS_PORT_DPC        4 /* HDMIC */
  1590. #define   GMBUS_PORT_DPB        5 /* SDVO, HDMIB */
  1591. #define   GMBUS_PORT_DPD        6 /* HDMID */
  1592. #define   GMBUS_PORT_RESERVED   7 /* 7 reserved */
  1593. #define   GMBUS_NUM_PORTS       (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
  1594. #define GMBUS1                  0x5104 /* command/status */
  1595. #define   GMBUS_SW_CLR_INT      (1<<31)
  1596. #define   GMBUS_SW_RDY          (1<<30)
  1597. #define   GMBUS_ENT             (1<<29) /* enable timeout */
  1598. #define   GMBUS_CYCLE_NONE      (0<<25)
  1599. #define   GMBUS_CYCLE_WAIT      (1<<25)
  1600. #define   GMBUS_CYCLE_INDEX     (2<<25)
  1601. #define   GMBUS_CYCLE_STOP      (4<<25)
  1602. #define   GMBUS_BYTE_COUNT_SHIFT 16
  1603. #define   GMBUS_SLAVE_INDEX_SHIFT 8
  1604. #define   GMBUS_SLAVE_ADDR_SHIFT 1
  1605. #define   GMBUS_SLAVE_READ      (1<<0)
  1606. #define   GMBUS_SLAVE_WRITE     (0<<0)
  1607. #define GMBUS2                  0x5108 /* status */
  1608. #define   GMBUS_INUSE           (1<<15)
  1609. #define   GMBUS_HW_WAIT_PHASE   (1<<14)
  1610. #define   GMBUS_STALL_TIMEOUT   (1<<13)
  1611. #define   GMBUS_INT             (1<<12)
  1612. #define   GMBUS_HW_RDY          (1<<11)
  1613. #define   GMBUS_SATOER          (1<<10)
  1614. #define   GMBUS_ACTIVE          (1<<9)
  1615. #define GMBUS3                  0x510c /* data buffer bytes 3-0 */
  1616. #define GMBUS4                  0x5110 /* interrupt mask (Pineview+) */
  1617. #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
  1618. #define   GMBUS_NAK_EN          (1<<3)
  1619. #define   GMBUS_IDLE_EN         (1<<2)
  1620. #define   GMBUS_HW_WAIT_EN      (1<<1)
  1621. #define   GMBUS_HW_RDY_EN       (1<<0)
  1622. #define GMBUS5                  0x5120 /* byte index */
  1623. #define   GMBUS_2BYTE_INDEX_EN  (1<<31)
  1624.  
  1625. /*
  1626.  * Clock control & power management
  1627.  */
  1628. #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
  1629. #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
  1630. #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
  1631. #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
  1632.  
  1633. #define VGA0    0x6000
  1634. #define VGA1    0x6004
  1635. #define VGA_PD  0x6010
  1636. #define   VGA0_PD_P2_DIV_4      (1 << 7)
  1637. #define   VGA0_PD_P1_DIV_2      (1 << 5)
  1638. #define   VGA0_PD_P1_SHIFT      0
  1639. #define   VGA0_PD_P1_MASK       (0x1f << 0)
  1640. #define   VGA1_PD_P2_DIV_4      (1 << 15)
  1641. #define   VGA1_PD_P1_DIV_2      (1 << 13)
  1642. #define   VGA1_PD_P1_SHIFT      8
  1643. #define   VGA1_PD_P1_MASK       (0x1f << 8)
  1644. #define   DPLL_VCO_ENABLE               (1 << 31)
  1645. #define   DPLL_SDVO_HIGH_SPEED          (1 << 30)
  1646. #define   DPLL_DVO_2X_MODE              (1 << 30)
  1647. #define   DPLL_EXT_BUFFER_ENABLE_VLV    (1 << 30)
  1648. #define   DPLL_SYNCLOCK_ENABLE          (1 << 29)
  1649. #define   DPLL_REFA_CLK_ENABLE_VLV      (1 << 29)
  1650. #define   DPLL_VGA_MODE_DIS             (1 << 28)
  1651. #define   DPLLB_MODE_DAC_SERIAL         (1 << 26) /* i915 */
  1652. #define   DPLLB_MODE_LVDS               (2 << 26) /* i915 */
  1653. #define   DPLL_MODE_MASK                (3 << 26)
  1654. #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
  1655. #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
  1656. #define   DPLLB_LVDS_P2_CLOCK_DIV_14    (0 << 24) /* i915 */
  1657. #define   DPLLB_LVDS_P2_CLOCK_DIV_7     (1 << 24) /* i915 */
  1658. #define   DPLL_P2_CLOCK_DIV_MASK        0x03000000 /* i915 */
  1659. #define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
  1660. #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
  1661. #define   DPLL_LOCK_VLV                 (1<<15)
  1662. #define   DPLL_INTEGRATED_CRI_CLK_VLV   (1<<14)
  1663. #define   DPLL_INTEGRATED_CLOCK_VLV     (1<<13)
  1664. #define   DPLL_SSC_REF_CLOCK_CHV        (1<<13)
  1665. #define   DPLL_PORTC_READY_MASK         (0xf << 4)
  1666. #define   DPLL_PORTB_READY_MASK         (0xf)
  1667.  
  1668. #define   DPLL_FPA01_P1_POST_DIV_MASK_I830      0x001f0000
  1669.  
  1670. /* Additional CHV pll/phy registers */
  1671. #define DPIO_PHY_STATUS                 (VLV_DISPLAY_BASE + 0x6240)
  1672. #define   DPLL_PORTD_READY_MASK         (0xf)
  1673. #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
  1674. #define   PHY_COM_LANE_RESET_DEASSERT(phy, val) \
  1675.                                 ((phy == DPIO_PHY0) ? (val | 1) : (val | 2))
  1676. #define   PHY_COM_LANE_RESET_ASSERT(phy, val) \
  1677.                                 ((phy == DPIO_PHY0) ? (val & ~1) : (val & ~2))
  1678. #define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104)
  1679. #define   PHY_POWERGOOD(phy)    ((phy == DPIO_PHY0) ? (1<<31) : (1<<30))
  1680.  
  1681. /*
  1682.  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  1683.  * this field (only one bit may be set).
  1684.  */
  1685. #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
  1686. #define   DPLL_FPA01_P1_POST_DIV_SHIFT  16
  1687. #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
  1688. /* i830, required in DVO non-gang */
  1689. #define   PLL_P2_DIVIDE_BY_4            (1 << 23)
  1690. #define   PLL_P1_DIVIDE_BY_TWO          (1 << 21) /* i830 */
  1691. #define   PLL_REF_INPUT_DREFCLK         (0 << 13)
  1692. #define   PLL_REF_INPUT_TVCLKINA        (1 << 13) /* i830 */
  1693. #define   PLL_REF_INPUT_TVCLKINBC       (2 << 13) /* SDVO TVCLKIN */
  1694. #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
  1695. #define   PLL_REF_INPUT_MASK            (3 << 13)
  1696. #define   PLL_LOAD_PULSE_PHASE_SHIFT            9
  1697. /* Ironlake */
  1698. # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
  1699. # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
  1700. # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)        (((x)-1) << 9)
  1701. # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
  1702. # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
  1703.  
  1704. /*
  1705.  * Parallel to Serial Load Pulse phase selection.
  1706.  * Selects the phase for the 10X DPLL clock for the PCIe
  1707.  * digital display port. The range is 4 to 13; 10 or more
  1708.  * is just a flip delay. The default is 6
  1709.  */
  1710. #define   PLL_LOAD_PULSE_PHASE_MASK             (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
  1711. #define   DISPLAY_RATE_SELECT_FPA1              (1 << 8)
  1712. /*
  1713.  * SDVO multiplier for 945G/GM. Not used on 965.
  1714.  */
  1715. #define   SDVO_MULTIPLIER_MASK                  0x000000ff
  1716. #define   SDVO_MULTIPLIER_SHIFT_HIRES           4
  1717. #define   SDVO_MULTIPLIER_SHIFT_VGA             0
  1718.  
  1719. #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
  1720. #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
  1721. #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
  1722. #define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
  1723.  
  1724. /*
  1725.  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  1726.  *
  1727.  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
  1728.  */
  1729. #define   DPLL_MD_UDI_DIVIDER_MASK              0x3f000000
  1730. #define   DPLL_MD_UDI_DIVIDER_SHIFT             24
  1731. /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
  1732. #define   DPLL_MD_VGA_UDI_DIVIDER_MASK          0x003f0000
  1733. #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT         16
  1734. /*
  1735.  * SDVO/UDI pixel multiplier.
  1736.  *
  1737.  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
  1738.  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
  1739.  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
  1740.  * dummy bytes in the datastream at an increased clock rate, with both sides of
  1741.  * the link knowing how many bytes are fill.
  1742.  *
  1743.  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
  1744.  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
  1745.  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
  1746.  * through an SDVO command.
  1747.  *
  1748.  * This register field has values of multiplication factor minus 1, with
  1749.  * a maximum multiplier of 5 for SDVO.
  1750.  */
  1751. #define   DPLL_MD_UDI_MULTIPLIER_MASK           0x00003f00
  1752. #define   DPLL_MD_UDI_MULTIPLIER_SHIFT          8
  1753. /*
  1754.  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
  1755.  * This best be set to the default value (3) or the CRT won't work. No,
  1756.  * I don't entirely understand what this does...
  1757.  */
  1758. #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK       0x0000003f
  1759. #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT      0
  1760.  
  1761. #define _FPA0   0x06040
  1762. #define _FPA1   0x06044
  1763. #define _FPB0   0x06048
  1764. #define _FPB1   0x0604c
  1765. #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
  1766. #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
  1767. #define   FP_N_DIV_MASK         0x003f0000
  1768. #define   FP_N_PINEVIEW_DIV_MASK        0x00ff0000
  1769. #define   FP_N_DIV_SHIFT                16
  1770. #define   FP_M1_DIV_MASK        0x00003f00
  1771. #define   FP_M1_DIV_SHIFT                8
  1772. #define   FP_M2_DIV_MASK        0x0000003f
  1773. #define   FP_M2_PINEVIEW_DIV_MASK       0x000000ff
  1774. #define   FP_M2_DIV_SHIFT                0
  1775. #define DPLL_TEST       0x606c
  1776. #define   DPLLB_TEST_SDVO_DIV_1         (0 << 22)
  1777. #define   DPLLB_TEST_SDVO_DIV_2         (1 << 22)
  1778. #define   DPLLB_TEST_SDVO_DIV_4         (2 << 22)
  1779. #define   DPLLB_TEST_SDVO_DIV_MASK      (3 << 22)
  1780. #define   DPLLB_TEST_N_BYPASS           (1 << 19)
  1781. #define   DPLLB_TEST_M_BYPASS           (1 << 18)
  1782. #define   DPLLB_INPUT_BUFFER_ENABLE     (1 << 16)
  1783. #define   DPLLA_TEST_N_BYPASS           (1 << 3)
  1784. #define   DPLLA_TEST_M_BYPASS           (1 << 2)
  1785. #define   DPLLA_INPUT_BUFFER_ENABLE     (1 << 0)
  1786. #define D_STATE         0x6104
  1787. #define  DSTATE_GFX_RESET_I830                  (1<<6)
  1788. #define  DSTATE_PLL_D3_OFF                      (1<<3)
  1789. #define  DSTATE_GFX_CLOCK_GATING                (1<<1)
  1790. #define  DSTATE_DOT_CLOCK_GATING                (1<<0)
  1791. #define DSPCLK_GATE_D   (dev_priv->info.display_mmio_offset + 0x6200)
  1792. # define DPUNIT_B_CLOCK_GATE_DISABLE            (1 << 30) /* 965 */
  1793. # define VSUNIT_CLOCK_GATE_DISABLE              (1 << 29) /* 965 */
  1794. # define VRHUNIT_CLOCK_GATE_DISABLE             (1 << 28) /* 965 */
  1795. # define VRDUNIT_CLOCK_GATE_DISABLE             (1 << 27) /* 965 */
  1796. # define AUDUNIT_CLOCK_GATE_DISABLE             (1 << 26) /* 965 */
  1797. # define DPUNIT_A_CLOCK_GATE_DISABLE            (1 << 25) /* 965 */
  1798. # define DPCUNIT_CLOCK_GATE_DISABLE             (1 << 24) /* 965 */
  1799. # define TVRUNIT_CLOCK_GATE_DISABLE             (1 << 23) /* 915-945 */
  1800. # define TVCUNIT_CLOCK_GATE_DISABLE             (1 << 22) /* 915-945 */
  1801. # define TVFUNIT_CLOCK_GATE_DISABLE             (1 << 21) /* 915-945 */
  1802. # define TVEUNIT_CLOCK_GATE_DISABLE             (1 << 20) /* 915-945 */
  1803. # define DVSUNIT_CLOCK_GATE_DISABLE             (1 << 19) /* 915-945 */
  1804. # define DSSUNIT_CLOCK_GATE_DISABLE             (1 << 18) /* 915-945 */
  1805. # define DDBUNIT_CLOCK_GATE_DISABLE             (1 << 17) /* 915-945 */
  1806. # define DPRUNIT_CLOCK_GATE_DISABLE             (1 << 16) /* 915-945 */
  1807. # define DPFUNIT_CLOCK_GATE_DISABLE             (1 << 15) /* 915-945 */
  1808. # define DPBMUNIT_CLOCK_GATE_DISABLE            (1 << 14) /* 915-945 */
  1809. # define DPLSUNIT_CLOCK_GATE_DISABLE            (1 << 13) /* 915-945 */
  1810. # define DPLUNIT_CLOCK_GATE_DISABLE             (1 << 12) /* 915-945 */
  1811. # define DPOUNIT_CLOCK_GATE_DISABLE             (1 << 11)
  1812. # define DPBUNIT_CLOCK_GATE_DISABLE             (1 << 10)
  1813. # define DCUNIT_CLOCK_GATE_DISABLE              (1 << 9)
  1814. # define DPUNIT_CLOCK_GATE_DISABLE              (1 << 8)
  1815. # define VRUNIT_CLOCK_GATE_DISABLE              (1 << 7) /* 915+: reserved */
  1816. # define OVHUNIT_CLOCK_GATE_DISABLE             (1 << 6) /* 830-865 */
  1817. # define DPIOUNIT_CLOCK_GATE_DISABLE            (1 << 6) /* 915-945 */
  1818. # define OVFUNIT_CLOCK_GATE_DISABLE             (1 << 5)
  1819. # define OVBUNIT_CLOCK_GATE_DISABLE             (1 << 4)
  1820. /*
  1821.  * This bit must be set on the 830 to prevent hangs when turning off the
  1822.  * overlay scaler.
  1823.  */
  1824. # define OVRUNIT_CLOCK_GATE_DISABLE             (1 << 3)
  1825. # define OVCUNIT_CLOCK_GATE_DISABLE             (1 << 2)
  1826. # define OVUUNIT_CLOCK_GATE_DISABLE             (1 << 1)
  1827. # define ZVUNIT_CLOCK_GATE_DISABLE              (1 << 0) /* 830 */
  1828. # define OVLUNIT_CLOCK_GATE_DISABLE             (1 << 0) /* 845,865 */
  1829.  
  1830. #define RENCLK_GATE_D1          0x6204
  1831. # define BLITTER_CLOCK_GATE_DISABLE             (1 << 13) /* 945GM only */
  1832. # define MPEG_CLOCK_GATE_DISABLE                (1 << 12) /* 945GM only */
  1833. # define PC_FE_CLOCK_GATE_DISABLE               (1 << 11)
  1834. # define PC_BE_CLOCK_GATE_DISABLE               (1 << 10)
  1835. # define WINDOWER_CLOCK_GATE_DISABLE            (1 << 9)
  1836. # define INTERPOLATOR_CLOCK_GATE_DISABLE        (1 << 8)
  1837. # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE    (1 << 7)
  1838. # define MOTION_COMP_CLOCK_GATE_DISABLE         (1 << 6)
  1839. # define MAG_CLOCK_GATE_DISABLE                 (1 << 5)
  1840. /* This bit must be unset on 855,865 */
  1841. # define MECI_CLOCK_GATE_DISABLE                (1 << 4)
  1842. # define DCMP_CLOCK_GATE_DISABLE                (1 << 3)
  1843. # define MEC_CLOCK_GATE_DISABLE                 (1 << 2)
  1844. # define MECO_CLOCK_GATE_DISABLE                (1 << 1)
  1845. /* This bit must be set on 855,865. */
  1846. # define SV_CLOCK_GATE_DISABLE                  (1 << 0)
  1847. # define I915_MPEG_CLOCK_GATE_DISABLE           (1 << 16)
  1848. # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE      (1 << 15)
  1849. # define I915_MOTION_COMP_CLOCK_GATE_DISABLE    (1 << 14)
  1850. # define I915_BD_BF_CLOCK_GATE_DISABLE          (1 << 13)
  1851. # define I915_SF_SE_CLOCK_GATE_DISABLE          (1 << 12)
  1852. # define I915_WM_CLOCK_GATE_DISABLE             (1 << 11)
  1853. # define I915_IZ_CLOCK_GATE_DISABLE             (1 << 10)
  1854. # define I915_PI_CLOCK_GATE_DISABLE             (1 << 9)
  1855. # define I915_DI_CLOCK_GATE_DISABLE             (1 << 8)
  1856. # define I915_SH_SV_CLOCK_GATE_DISABLE          (1 << 7)
  1857. # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE    (1 << 6)
  1858. # define I915_SC_CLOCK_GATE_DISABLE             (1 << 5)
  1859. # define I915_FL_CLOCK_GATE_DISABLE             (1 << 4)
  1860. # define I915_DM_CLOCK_GATE_DISABLE             (1 << 3)
  1861. # define I915_PS_CLOCK_GATE_DISABLE             (1 << 2)
  1862. # define I915_CC_CLOCK_GATE_DISABLE             (1 << 1)
  1863. # define I915_BY_CLOCK_GATE_DISABLE             (1 << 0)
  1864.  
  1865. # define I965_RCZ_CLOCK_GATE_DISABLE            (1 << 30)
  1866. /* This bit must always be set on 965G/965GM */
  1867. # define I965_RCC_CLOCK_GATE_DISABLE            (1 << 29)
  1868. # define I965_RCPB_CLOCK_GATE_DISABLE           (1 << 28)
  1869. # define I965_DAP_CLOCK_GATE_DISABLE            (1 << 27)
  1870. # define I965_ROC_CLOCK_GATE_DISABLE            (1 << 26)
  1871. # define I965_GW_CLOCK_GATE_DISABLE             (1 << 25)
  1872. # define I965_TD_CLOCK_GATE_DISABLE             (1 << 24)
  1873. /* This bit must always be set on 965G */
  1874. # define I965_ISC_CLOCK_GATE_DISABLE            (1 << 23)
  1875. # define I965_IC_CLOCK_GATE_DISABLE             (1 << 22)
  1876. # define I965_EU_CLOCK_GATE_DISABLE             (1 << 21)
  1877. # define I965_IF_CLOCK_GATE_DISABLE             (1 << 20)
  1878. # define I965_TC_CLOCK_GATE_DISABLE             (1 << 19)
  1879. # define I965_SO_CLOCK_GATE_DISABLE             (1 << 17)
  1880. # define I965_FBC_CLOCK_GATE_DISABLE            (1 << 16)
  1881. # define I965_MARI_CLOCK_GATE_DISABLE           (1 << 15)
  1882. # define I965_MASF_CLOCK_GATE_DISABLE           (1 << 14)
  1883. # define I965_MAWB_CLOCK_GATE_DISABLE           (1 << 13)
  1884. # define I965_EM_CLOCK_GATE_DISABLE             (1 << 12)
  1885. # define I965_UC_CLOCK_GATE_DISABLE             (1 << 11)
  1886. # define I965_SI_CLOCK_GATE_DISABLE             (1 << 6)
  1887. # define I965_MT_CLOCK_GATE_DISABLE             (1 << 5)
  1888. # define I965_PL_CLOCK_GATE_DISABLE             (1 << 4)
  1889. # define I965_DG_CLOCK_GATE_DISABLE             (1 << 3)
  1890. # define I965_QC_CLOCK_GATE_DISABLE             (1 << 2)
  1891. # define I965_FT_CLOCK_GATE_DISABLE             (1 << 1)
  1892. # define I965_DM_CLOCK_GATE_DISABLE             (1 << 0)
  1893.  
  1894. #define RENCLK_GATE_D2          0x6208
  1895. #define VF_UNIT_CLOCK_GATE_DISABLE              (1 << 9)
  1896. #define GS_UNIT_CLOCK_GATE_DISABLE              (1 << 7)
  1897. #define CL_UNIT_CLOCK_GATE_DISABLE              (1 << 6)
  1898.  
  1899. #define VDECCLK_GATE_D          0x620C          /* g4x only */
  1900. #define  VCP_UNIT_CLOCK_GATE_DISABLE            (1 << 4)
  1901.  
  1902. #define RAMCLK_GATE_D           0x6210          /* CRL only */
  1903. #define DEUC                    0x6214          /* CRL only */
  1904.  
  1905. #define FW_BLC_SELF_VLV         (VLV_DISPLAY_BASE + 0x6500)
  1906. #define  FW_CSPWRDWNEN          (1<<15)
  1907.  
  1908. #define MI_ARB_VLV              (VLV_DISPLAY_BASE + 0x6504)
  1909.  
  1910. #define CZCLK_CDCLK_FREQ_RATIO  (VLV_DISPLAY_BASE + 0x6508)
  1911. #define   CDCLK_FREQ_SHIFT      4
  1912. #define   CDCLK_FREQ_MASK       (0x1f << CDCLK_FREQ_SHIFT)
  1913. #define   CZCLK_FREQ_MASK       0xf
  1914. #define GMBUSFREQ_VLV           (VLV_DISPLAY_BASE + 0x6510)
  1915.  
  1916. /*
  1917.  * Palette regs
  1918.  */
  1919. #define PALETTE_A_OFFSET 0xa000
  1920. #define PALETTE_B_OFFSET 0xa800
  1921. #define CHV_PALETTE_C_OFFSET 0xc000
  1922. #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
  1923.                        dev_priv->info.display_mmio_offset)
  1924.  
  1925. /* MCH MMIO space */
  1926.  
  1927. /*
  1928.  * MCHBAR mirror.
  1929.  *
  1930.  * This mirrors the MCHBAR MMIO space whose location is determined by
  1931.  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
  1932.  * every way.  It is not accessible from the CP register read instructions.
  1933.  *
  1934.  * Starting from Haswell, you can't write registers using the MCHBAR mirror,
  1935.  * just read.
  1936.  */
  1937. #define MCHBAR_MIRROR_BASE      0x10000
  1938.  
  1939. #define MCHBAR_MIRROR_BASE_SNB  0x140000
  1940.  
  1941. /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
  1942. #define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
  1943.  
  1944. /* 915-945 and GM965 MCH register controlling DRAM channel access */
  1945. #define DCC                     0x10200
  1946. #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
  1947. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
  1948. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
  1949. #define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
  1950. #define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
  1951. #define DCC_CHANNEL_XOR_BIT_17                          (1 << 9)
  1952.  
  1953. /* Pineview MCH register contains DDR3 setting */
  1954. #define CSHRDDR3CTL            0x101a8
  1955. #define CSHRDDR3CTL_DDR3       (1 << 2)
  1956.  
  1957. /* 965 MCH register controlling DRAM channel configuration */
  1958. #define C0DRB3                  0x10206
  1959. #define C1DRB3                  0x10606
  1960.  
  1961. /* snb MCH registers for reading the DRAM channel configuration */
  1962. #define MAD_DIMM_C0                     (MCHBAR_MIRROR_BASE_SNB + 0x5004)
  1963. #define MAD_DIMM_C1                     (MCHBAR_MIRROR_BASE_SNB + 0x5008)
  1964. #define MAD_DIMM_C2                     (MCHBAR_MIRROR_BASE_SNB + 0x500C)
  1965. #define   MAD_DIMM_ECC_MASK             (0x3 << 24)
  1966. #define   MAD_DIMM_ECC_OFF              (0x0 << 24)
  1967. #define   MAD_DIMM_ECC_IO_ON_LOGIC_OFF  (0x1 << 24)
  1968. #define   MAD_DIMM_ECC_IO_OFF_LOGIC_ON  (0x2 << 24)
  1969. #define   MAD_DIMM_ECC_ON               (0x3 << 24)
  1970. #define   MAD_DIMM_ENH_INTERLEAVE       (0x1 << 22)
  1971. #define   MAD_DIMM_RANK_INTERLEAVE      (0x1 << 21)
  1972. #define   MAD_DIMM_B_WIDTH_X16          (0x1 << 20) /* X8 chips if unset */
  1973. #define   MAD_DIMM_A_WIDTH_X16          (0x1 << 19) /* X8 chips if unset */
  1974. #define   MAD_DIMM_B_DUAL_RANK          (0x1 << 18)
  1975. #define   MAD_DIMM_A_DUAL_RANK          (0x1 << 17)
  1976. #define   MAD_DIMM_A_SELECT             (0x1 << 16)
  1977. /* DIMM sizes are in multiples of 256mb. */
  1978. #define   MAD_DIMM_B_SIZE_SHIFT         8
  1979. #define   MAD_DIMM_B_SIZE_MASK          (0xff << MAD_DIMM_B_SIZE_SHIFT)
  1980. #define   MAD_DIMM_A_SIZE_SHIFT         0
  1981. #define   MAD_DIMM_A_SIZE_MASK          (0xff << MAD_DIMM_A_SIZE_SHIFT)
  1982.  
  1983. /* snb MCH registers for priority tuning */
  1984. #define MCH_SSKPD                       (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
  1985. #define   MCH_SSKPD_WM0_MASK            0x3f
  1986. #define   MCH_SSKPD_WM0_VAL             0xc
  1987.  
  1988. #define MCH_SECP_NRG_STTS               (MCHBAR_MIRROR_BASE_SNB + 0x592c)
  1989.  
  1990. /* Clocking configuration register */
  1991. #define CLKCFG                  0x10c00
  1992. #define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
  1993. #define CLKCFG_FSB_533                                  (1 << 0)        /* hrawclk 133 */
  1994. #define CLKCFG_FSB_667                                  (3 << 0)        /* hrawclk 166 */
  1995. #define CLKCFG_FSB_800                                  (2 << 0)        /* hrawclk 200 */
  1996. #define CLKCFG_FSB_1067                                 (6 << 0)        /* hrawclk 266 */
  1997. #define CLKCFG_FSB_1333                                 (7 << 0)        /* hrawclk 333 */
  1998. /* Note, below two are guess */
  1999. #define CLKCFG_FSB_1600                                 (4 << 0)        /* hrawclk 400 */
  2000. #define CLKCFG_FSB_1600_ALT                             (0 << 0)        /* hrawclk 400 */
  2001. #define CLKCFG_FSB_MASK                                 (7 << 0)
  2002. #define CLKCFG_MEM_533                                  (1 << 4)
  2003. #define CLKCFG_MEM_667                                  (2 << 4)
  2004. #define CLKCFG_MEM_800                                  (3 << 4)
  2005. #define CLKCFG_MEM_MASK                                 (7 << 4)
  2006.  
  2007. #define TSC1                    0x11001
  2008. #define   TSE                   (1<<0)
  2009. #define TR1                     0x11006
  2010. #define TSFS                    0x11020
  2011. #define   TSFS_SLOPE_MASK       0x0000ff00
  2012. #define   TSFS_SLOPE_SHIFT      8
  2013. #define   TSFS_INTR_MASK        0x000000ff
  2014.  
  2015. #define CRSTANDVID              0x11100
  2016. #define PXVFREQ_BASE            0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
  2017. #define   PXVFREQ_PX_MASK       0x7f000000
  2018. #define   PXVFREQ_PX_SHIFT      24
  2019. #define VIDFREQ_BASE            0x11110
  2020. #define VIDFREQ1                0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
  2021. #define VIDFREQ2                0x11114
  2022. #define VIDFREQ3                0x11118
  2023. #define VIDFREQ4                0x1111c
  2024. #define   VIDFREQ_P0_MASK       0x1f000000
  2025. #define   VIDFREQ_P0_SHIFT      24
  2026. #define   VIDFREQ_P0_CSCLK_MASK 0x00f00000
  2027. #define   VIDFREQ_P0_CSCLK_SHIFT 20
  2028. #define   VIDFREQ_P0_CRCLK_MASK 0x000f0000
  2029. #define   VIDFREQ_P0_CRCLK_SHIFT 16
  2030. #define   VIDFREQ_P1_MASK       0x00001f00
  2031. #define   VIDFREQ_P1_SHIFT      8
  2032. #define   VIDFREQ_P1_CSCLK_MASK 0x000000f0
  2033. #define   VIDFREQ_P1_CSCLK_SHIFT 4
  2034. #define   VIDFREQ_P1_CRCLK_MASK 0x0000000f
  2035. #define INTTOEXT_BASE_ILK       0x11300
  2036. #define INTTOEXT_BASE           0x11120 /* INTTOEXT1-8 (0x1113c) */
  2037. #define   INTTOEXT_MAP3_SHIFT   24
  2038. #define   INTTOEXT_MAP3_MASK    (0x1f << INTTOEXT_MAP3_SHIFT)
  2039. #define   INTTOEXT_MAP2_SHIFT   16
  2040. #define   INTTOEXT_MAP2_MASK    (0x1f << INTTOEXT_MAP2_SHIFT)
  2041. #define   INTTOEXT_MAP1_SHIFT   8
  2042. #define   INTTOEXT_MAP1_MASK    (0x1f << INTTOEXT_MAP1_SHIFT)
  2043. #define   INTTOEXT_MAP0_SHIFT   0
  2044. #define   INTTOEXT_MAP0_MASK    (0x1f << INTTOEXT_MAP0_SHIFT)
  2045. #define MEMSWCTL                0x11170 /* Ironlake only */
  2046. #define   MEMCTL_CMD_MASK       0xe000
  2047. #define   MEMCTL_CMD_SHIFT      13
  2048. #define   MEMCTL_CMD_RCLK_OFF   0
  2049. #define   MEMCTL_CMD_RCLK_ON    1
  2050. #define   MEMCTL_CMD_CHFREQ     2
  2051. #define   MEMCTL_CMD_CHVID      3
  2052. #define   MEMCTL_CMD_VMMOFF     4
  2053. #define   MEMCTL_CMD_VMMON      5
  2054. #define   MEMCTL_CMD_STS        (1<<12) /* write 1 triggers command, clears
  2055.                                            when command complete */
  2056. #define   MEMCTL_FREQ_MASK      0x0f00 /* jitter, from 0-15 */
  2057. #define   MEMCTL_FREQ_SHIFT     8
  2058. #define   MEMCTL_SFCAVM         (1<<7)
  2059. #define   MEMCTL_TGT_VID_MASK   0x007f
  2060. #define MEMIHYST                0x1117c
  2061. #define MEMINTREN               0x11180 /* 16 bits */
  2062. #define   MEMINT_RSEXIT_EN      (1<<8)
  2063. #define   MEMINT_CX_SUPR_EN     (1<<7)
  2064. #define   MEMINT_CONT_BUSY_EN   (1<<6)
  2065. #define   MEMINT_AVG_BUSY_EN    (1<<5)
  2066. #define   MEMINT_EVAL_CHG_EN    (1<<4)
  2067. #define   MEMINT_MON_IDLE_EN    (1<<3)
  2068. #define   MEMINT_UP_EVAL_EN     (1<<2)
  2069. #define   MEMINT_DOWN_EVAL_EN   (1<<1)
  2070. #define   MEMINT_SW_CMD_EN      (1<<0)
  2071. #define MEMINTRSTR              0x11182 /* 16 bits */
  2072. #define   MEM_RSEXIT_MASK       0xc000
  2073. #define   MEM_RSEXIT_SHIFT      14
  2074. #define   MEM_CONT_BUSY_MASK    0x3000
  2075. #define   MEM_CONT_BUSY_SHIFT   12
  2076. #define   MEM_AVG_BUSY_MASK     0x0c00
  2077. #define   MEM_AVG_BUSY_SHIFT    10
  2078. #define   MEM_EVAL_CHG_MASK     0x0300
  2079. #define   MEM_EVAL_BUSY_SHIFT   8
  2080. #define   MEM_MON_IDLE_MASK     0x00c0
  2081. #define   MEM_MON_IDLE_SHIFT    6
  2082. #define   MEM_UP_EVAL_MASK      0x0030
  2083. #define   MEM_UP_EVAL_SHIFT     4
  2084. #define   MEM_DOWN_EVAL_MASK    0x000c
  2085. #define   MEM_DOWN_EVAL_SHIFT   2
  2086. #define   MEM_SW_CMD_MASK       0x0003
  2087. #define   MEM_INT_STEER_GFX     0
  2088. #define   MEM_INT_STEER_CMR     1
  2089. #define   MEM_INT_STEER_SMI     2
  2090. #define   MEM_INT_STEER_SCI     3
  2091. #define MEMINTRSTS              0x11184
  2092. #define   MEMINT_RSEXIT         (1<<7)
  2093. #define   MEMINT_CONT_BUSY      (1<<6)
  2094. #define   MEMINT_AVG_BUSY       (1<<5)
  2095. #define   MEMINT_EVAL_CHG       (1<<4)
  2096. #define   MEMINT_MON_IDLE       (1<<3)
  2097. #define   MEMINT_UP_EVAL        (1<<2)
  2098. #define   MEMINT_DOWN_EVAL      (1<<1)
  2099. #define   MEMINT_SW_CMD         (1<<0)
  2100. #define MEMMODECTL              0x11190
  2101. #define   MEMMODE_BOOST_EN      (1<<31)
  2102. #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
  2103. #define   MEMMODE_BOOST_FREQ_SHIFT 24
  2104. #define   MEMMODE_IDLE_MODE_MASK 0x00030000
  2105. #define   MEMMODE_IDLE_MODE_SHIFT 16
  2106. #define   MEMMODE_IDLE_MODE_EVAL 0
  2107. #define   MEMMODE_IDLE_MODE_CONT 1
  2108. #define   MEMMODE_HWIDLE_EN     (1<<15)
  2109. #define   MEMMODE_SWMODE_EN     (1<<14)
  2110. #define   MEMMODE_RCLK_GATE     (1<<13)
  2111. #define   MEMMODE_HW_UPDATE     (1<<12)
  2112. #define   MEMMODE_FSTART_MASK   0x00000f00 /* starting jitter, 0-15 */
  2113. #define   MEMMODE_FSTART_SHIFT  8
  2114. #define   MEMMODE_FMAX_MASK     0x000000f0 /* max jitter, 0-15 */
  2115. #define   MEMMODE_FMAX_SHIFT    4
  2116. #define   MEMMODE_FMIN_MASK     0x0000000f /* min jitter, 0-15 */
  2117. #define RCBMAXAVG               0x1119c
  2118. #define MEMSWCTL2               0x1119e /* Cantiga only */
  2119. #define   SWMEMCMD_RENDER_OFF   (0 << 13)
  2120. #define   SWMEMCMD_RENDER_ON    (1 << 13)
  2121. #define   SWMEMCMD_SWFREQ       (2 << 13)
  2122. #define   SWMEMCMD_TARVID       (3 << 13)
  2123. #define   SWMEMCMD_VRM_OFF      (4 << 13)
  2124. #define   SWMEMCMD_VRM_ON       (5 << 13)
  2125. #define   CMDSTS                (1<<12)
  2126. #define   SFCAVM                (1<<11)
  2127. #define   SWFREQ_MASK           0x0380 /* P0-7 */
  2128. #define   SWFREQ_SHIFT          7
  2129. #define   TARVID_MASK           0x001f
  2130. #define MEMSTAT_CTG             0x111a0
  2131. #define RCBMINAVG               0x111a0
  2132. #define RCUPEI                  0x111b0
  2133. #define RCDNEI                  0x111b4
  2134. #define RSTDBYCTL               0x111b8
  2135. #define   RS1EN                 (1<<31)
  2136. #define   RS2EN                 (1<<30)
  2137. #define   RS3EN                 (1<<29)
  2138. #define   D3RS3EN               (1<<28) /* Display D3 imlies RS3 */
  2139. #define   SWPROMORSX            (1<<27) /* RSx promotion timers ignored */
  2140. #define   RCWAKERW              (1<<26) /* Resetwarn from PCH causes wakeup */
  2141. #define   DPRSLPVREN            (1<<25) /* Fast voltage ramp enable */
  2142. #define   GFXTGHYST             (1<<24) /* Hysteresis to allow trunk gating */
  2143. #define   RCX_SW_EXIT           (1<<23) /* Leave RSx and prevent re-entry */
  2144. #define   RSX_STATUS_MASK       (7<<20)
  2145. #define   RSX_STATUS_ON         (0<<20)
  2146. #define   RSX_STATUS_RC1        (1<<20)
  2147. #define   RSX_STATUS_RC1E       (2<<20)
  2148. #define   RSX_STATUS_RS1        (3<<20)
  2149. #define   RSX_STATUS_RS2        (4<<20) /* aka rc6 */
  2150. #define   RSX_STATUS_RSVD       (5<<20) /* deep rc6 unsupported on ilk */
  2151. #define   RSX_STATUS_RS3        (6<<20) /* rs3 unsupported on ilk */
  2152. #define   RSX_STATUS_RSVD2      (7<<20)
  2153. #define   UWRCRSXE              (1<<19) /* wake counter limit prevents rsx */
  2154. #define   RSCRP                 (1<<18) /* rs requests control on rs1/2 reqs */
  2155. #define   JRSC                  (1<<17) /* rsx coupled to cpu c-state */
  2156. #define   RS2INC0               (1<<16) /* allow rs2 in cpu c0 */
  2157. #define   RS1CONTSAV_MASK       (3<<14)
  2158. #define   RS1CONTSAV_NO_RS1     (0<<14) /* rs1 doesn't save/restore context */
  2159. #define   RS1CONTSAV_RSVD       (1<<14)
  2160. #define   RS1CONTSAV_SAVE_RS1   (2<<14) /* rs1 saves context */
  2161. #define   RS1CONTSAV_FULL_RS1   (3<<14) /* rs1 saves and restores context */
  2162. #define   NORMSLEXLAT_MASK      (3<<12)
  2163. #define   SLOW_RS123            (0<<12)
  2164. #define   SLOW_RS23             (1<<12)
  2165. #define   SLOW_RS3              (2<<12)
  2166. #define   NORMAL_RS123          (3<<12)
  2167. #define   RCMODE_TIMEOUT        (1<<11) /* 0 is eval interval method */
  2168. #define   IMPROMOEN             (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
  2169. #define   RCENTSYNC             (1<<9) /* rs coupled to cpu c-state (3/6/7) */
  2170. #define   STATELOCK             (1<<7) /* locked to rs_cstate if 0 */
  2171. #define   RS_CSTATE_MASK        (3<<4)
  2172. #define   RS_CSTATE_C367_RS1    (0<<4)
  2173. #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
  2174. #define   RS_CSTATE_RSVD        (2<<4)
  2175. #define   RS_CSTATE_C367_RS2    (3<<4)
  2176. #define   REDSAVES              (1<<3) /* no context save if was idle during rs0 */
  2177. #define   REDRESTORES           (1<<2) /* no restore if was idle during rs0 */
  2178. #define VIDCTL                  0x111c0
  2179. #define VIDSTS                  0x111c8
  2180. #define VIDSTART                0x111cc /* 8 bits */
  2181. #define MEMSTAT_ILK                     0x111f8
  2182. #define   MEMSTAT_VID_MASK      0x7f00
  2183. #define   MEMSTAT_VID_SHIFT     8
  2184. #define   MEMSTAT_PSTATE_MASK   0x00f8
  2185. #define   MEMSTAT_PSTATE_SHIFT  3
  2186. #define   MEMSTAT_MON_ACTV      (1<<2)
  2187. #define   MEMSTAT_SRC_CTL_MASK  0x0003
  2188. #define   MEMSTAT_SRC_CTL_CORE  0
  2189. #define   MEMSTAT_SRC_CTL_TRB   1
  2190. #define   MEMSTAT_SRC_CTL_THM   2
  2191. #define   MEMSTAT_SRC_CTL_STDBY 3
  2192. #define RCPREVBSYTUPAVG         0x113b8
  2193. #define RCPREVBSYTDNAVG         0x113bc
  2194. #define PMMISC                  0x11214
  2195. #define   MCPPCE_EN             (1<<0) /* enable PM_MSG from PCH->MPC */
  2196. #define SDEW                    0x1124c
  2197. #define CSIEW0                  0x11250
  2198. #define CSIEW1                  0x11254
  2199. #define CSIEW2                  0x11258
  2200. #define PEW                     0x1125c
  2201. #define DEW                     0x11270
  2202. #define MCHAFE                  0x112c0
  2203. #define CSIEC                   0x112e0
  2204. #define DMIEC                   0x112e4
  2205. #define DDREC                   0x112e8
  2206. #define PEG0EC                  0x112ec
  2207. #define PEG1EC                  0x112f0
  2208. #define GFXEC                   0x112f4
  2209. #define RPPREVBSYTUPAVG         0x113b8
  2210. #define RPPREVBSYTDNAVG         0x113bc
  2211. #define ECR                     0x11600
  2212. #define   ECR_GPFE              (1<<31)
  2213. #define   ECR_IMONE             (1<<30)
  2214. #define   ECR_CAP_MASK          0x0000001f /* Event range, 0-31 */
  2215. #define OGW0                    0x11608
  2216. #define OGW1                    0x1160c
  2217. #define EG0                     0x11610
  2218. #define EG1                     0x11614
  2219. #define EG2                     0x11618
  2220. #define EG3                     0x1161c
  2221. #define EG4                     0x11620
  2222. #define EG5                     0x11624
  2223. #define EG6                     0x11628
  2224. #define EG7                     0x1162c
  2225. #define PXW                     0x11664
  2226. #define PXWL                    0x11680
  2227. #define LCFUSE02                0x116c0
  2228. #define   LCFUSE_HIV_MASK       0x000000ff
  2229. #define CSIPLL0                 0x12c10
  2230. #define DDRMPLL1                0X12c20
  2231. #define PEG_BAND_GAP_DATA       0x14d68
  2232.  
  2233. #define GEN6_GT_THREAD_STATUS_REG 0x13805c
  2234. #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
  2235. #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
  2236.  
  2237. #define GEN6_GT_PERF_STATUS     (MCHBAR_MIRROR_BASE_SNB + 0x5948)
  2238. #define GEN6_RP_STATE_LIMITS    (MCHBAR_MIRROR_BASE_SNB + 0x5994)
  2239. #define GEN6_RP_STATE_CAP       (MCHBAR_MIRROR_BASE_SNB + 0x5998)
  2240.  
  2241. /*
  2242.  * Logical Context regs
  2243.  */
  2244. #define CCID                    0x2180
  2245. #define   CCID_EN               (1<<0)
  2246. /*
  2247.  * Notes on SNB/IVB/VLV context size:
  2248.  * - Power context is saved elsewhere (LLC or stolen)
  2249.  * - Ring/execlist context is saved on SNB, not on IVB
  2250.  * - Extended context size already includes render context size
  2251.  * - We always need to follow the extended context size.
  2252.  *   SNB BSpec has comments indicating that we should use the
  2253.  *   render context size instead if execlists are disabled, but
  2254.  *   based on empirical testing that's just nonsense.
  2255.  * - Pipelined/VF state is saved on SNB/IVB respectively
  2256.  * - GT1 size just indicates how much of render context
  2257.  *   doesn't need saving on GT1
  2258.  */
  2259. #define CXT_SIZE                0x21a0
  2260. #define GEN6_CXT_POWER_SIZE(cxt_reg)    ((cxt_reg >> 24) & 0x3f)
  2261. #define GEN6_CXT_RING_SIZE(cxt_reg)     ((cxt_reg >> 18) & 0x3f)
  2262. #define GEN6_CXT_RENDER_SIZE(cxt_reg)   ((cxt_reg >> 12) & 0x3f)
  2263. #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
  2264. #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
  2265. #define GEN6_CXT_TOTAL_SIZE(cxt_reg)    (GEN6_CXT_RING_SIZE(cxt_reg) + \
  2266.                                         GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
  2267.                                         GEN6_CXT_PIPELINE_SIZE(cxt_reg))
  2268. #define GEN7_CXT_SIZE           0x21a8
  2269. #define GEN7_CXT_POWER_SIZE(ctx_reg)    ((ctx_reg >> 25) & 0x7f)
  2270. #define GEN7_CXT_RING_SIZE(ctx_reg)     ((ctx_reg >> 22) & 0x7)
  2271. #define GEN7_CXT_RENDER_SIZE(ctx_reg)   ((ctx_reg >> 16) & 0x3f)
  2272. #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
  2273. #define GEN7_CXT_GT1_SIZE(ctx_reg)      ((ctx_reg >> 6) & 0x7)
  2274. #define GEN7_CXT_VFSTATE_SIZE(ctx_reg)  ((ctx_reg >> 0) & 0x3f)
  2275. #define GEN7_CXT_TOTAL_SIZE(ctx_reg)    (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
  2276.                                          GEN7_CXT_VFSTATE_SIZE(ctx_reg))
  2277. /* Haswell does have the CXT_SIZE register however it does not appear to be
  2278.  * valid. Now, docs explain in dwords what is in the context object. The full
  2279.  * size is 70720 bytes, however, the power context and execlist context will
  2280.  * never be saved (power context is stored elsewhere, and execlists don't work
  2281.  * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
  2282.  */
  2283. #define HSW_CXT_TOTAL_SIZE              (17 * PAGE_SIZE)
  2284. /* Same as Haswell, but 72064 bytes now. */
  2285. #define GEN8_CXT_TOTAL_SIZE             (18 * PAGE_SIZE)
  2286.  
  2287. #define CHV_CLK_CTL1                    0x101100
  2288. #define VLV_CLK_CTL2                    0x101104
  2289. #define   CLK_CTL2_CZCOUNT_30NS_SHIFT   28
  2290.  
  2291. /*
  2292.  * Overlay regs
  2293.  */
  2294.  
  2295. #define OVADD                   0x30000
  2296. #define DOVSTA                  0x30008
  2297. #define OC_BUF                  (0x3<<20)
  2298. #define OGAMC5                  0x30010
  2299. #define OGAMC4                  0x30014
  2300. #define OGAMC3                  0x30018
  2301. #define OGAMC2                  0x3001c
  2302. #define OGAMC1                  0x30020
  2303. #define OGAMC0                  0x30024
  2304.  
  2305. /*
  2306.  * Display engine regs
  2307.  */
  2308.  
  2309. /* Pipe A CRC regs */
  2310. #define _PIPE_CRC_CTL_A                 0x60050
  2311. #define   PIPE_CRC_ENABLE               (1 << 31)
  2312. /* ivb+ source selection */
  2313. #define   PIPE_CRC_SOURCE_PRIMARY_IVB   (0 << 29)
  2314. #define   PIPE_CRC_SOURCE_SPRITE_IVB    (1 << 29)
  2315. #define   PIPE_CRC_SOURCE_PF_IVB        (2 << 29)
  2316. /* ilk+ source selection */
  2317. #define   PIPE_CRC_SOURCE_PRIMARY_ILK   (0 << 28)
  2318. #define   PIPE_CRC_SOURCE_SPRITE_ILK    (1 << 28)
  2319. #define   PIPE_CRC_SOURCE_PIPE_ILK      (2 << 28)
  2320. /* embedded DP port on the north display block, reserved on ivb */
  2321. #define   PIPE_CRC_SOURCE_PORT_A_ILK    (4 << 28)
  2322. #define   PIPE_CRC_SOURCE_FDI_ILK       (5 << 28) /* reserved on ivb */
  2323. /* vlv source selection */
  2324. #define   PIPE_CRC_SOURCE_PIPE_VLV      (0 << 27)
  2325. #define   PIPE_CRC_SOURCE_HDMIB_VLV     (1 << 27)
  2326. #define   PIPE_CRC_SOURCE_HDMIC_VLV     (2 << 27)
  2327. /* with DP port the pipe source is invalid */
  2328. #define   PIPE_CRC_SOURCE_DP_D_VLV      (3 << 27)
  2329. #define   PIPE_CRC_SOURCE_DP_B_VLV      (6 << 27)
  2330. #define   PIPE_CRC_SOURCE_DP_C_VLV      (7 << 27)
  2331. /* gen3+ source selection */
  2332. #define   PIPE_CRC_SOURCE_PIPE_I9XX     (0 << 28)
  2333. #define   PIPE_CRC_SOURCE_SDVOB_I9XX    (1 << 28)
  2334. #define   PIPE_CRC_SOURCE_SDVOC_I9XX    (2 << 28)
  2335. /* with DP/TV port the pipe source is invalid */
  2336. #define   PIPE_CRC_SOURCE_DP_D_G4X      (3 << 28)
  2337. #define   PIPE_CRC_SOURCE_TV_PRE        (4 << 28)
  2338. #define   PIPE_CRC_SOURCE_TV_POST       (5 << 28)
  2339. #define   PIPE_CRC_SOURCE_DP_B_G4X      (6 << 28)
  2340. #define   PIPE_CRC_SOURCE_DP_C_G4X      (7 << 28)
  2341. /* gen2 doesn't have source selection bits */
  2342. #define   PIPE_CRC_INCLUDE_BORDER_I8XX  (1 << 30)
  2343.  
  2344. #define _PIPE_CRC_RES_1_A_IVB           0x60064
  2345. #define _PIPE_CRC_RES_2_A_IVB           0x60068
  2346. #define _PIPE_CRC_RES_3_A_IVB           0x6006c
  2347. #define _PIPE_CRC_RES_4_A_IVB           0x60070
  2348. #define _PIPE_CRC_RES_5_A_IVB           0x60074
  2349.  
  2350. #define _PIPE_CRC_RES_RED_A             0x60060
  2351. #define _PIPE_CRC_RES_GREEN_A           0x60064
  2352. #define _PIPE_CRC_RES_BLUE_A            0x60068
  2353. #define _PIPE_CRC_RES_RES1_A_I915       0x6006c
  2354. #define _PIPE_CRC_RES_RES2_A_G4X        0x60080
  2355.  
  2356. /* Pipe B CRC regs */
  2357. #define _PIPE_CRC_RES_1_B_IVB           0x61064
  2358. #define _PIPE_CRC_RES_2_B_IVB           0x61068
  2359. #define _PIPE_CRC_RES_3_B_IVB           0x6106c
  2360. #define _PIPE_CRC_RES_4_B_IVB           0x61070
  2361. #define _PIPE_CRC_RES_5_B_IVB           0x61074
  2362.  
  2363. #define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
  2364. #define PIPE_CRC_RES_1_IVB(pipe)        \
  2365.         _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
  2366. #define PIPE_CRC_RES_2_IVB(pipe)        \
  2367.         _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
  2368. #define PIPE_CRC_RES_3_IVB(pipe)        \
  2369.         _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
  2370. #define PIPE_CRC_RES_4_IVB(pipe)        \
  2371.         _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
  2372. #define PIPE_CRC_RES_5_IVB(pipe)        \
  2373.         _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
  2374.  
  2375. #define PIPE_CRC_RES_RED(pipe) \
  2376.         _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
  2377. #define PIPE_CRC_RES_GREEN(pipe) \
  2378.         _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
  2379. #define PIPE_CRC_RES_BLUE(pipe) \
  2380.         _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
  2381. #define PIPE_CRC_RES_RES1_I915(pipe) \
  2382.         _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
  2383. #define PIPE_CRC_RES_RES2_G4X(pipe) \
  2384.         _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
  2385.  
  2386. /* Pipe A timing regs */
  2387. #define _HTOTAL_A       0x60000
  2388. #define _HBLANK_A       0x60004
  2389. #define _HSYNC_A        0x60008
  2390. #define _VTOTAL_A       0x6000c
  2391. #define _VBLANK_A       0x60010
  2392. #define _VSYNC_A        0x60014
  2393. #define _PIPEASRC       0x6001c
  2394. #define _BCLRPAT_A      0x60020
  2395. #define _VSYNCSHIFT_A   0x60028
  2396.  
  2397. /* Pipe B timing regs */
  2398. #define _HTOTAL_B       0x61000
  2399. #define _HBLANK_B       0x61004
  2400. #define _HSYNC_B        0x61008
  2401. #define _VTOTAL_B       0x6100c
  2402. #define _VBLANK_B       0x61010
  2403. #define _VSYNC_B        0x61014
  2404. #define _PIPEBSRC       0x6101c
  2405. #define _BCLRPAT_B      0x61020
  2406. #define _VSYNCSHIFT_B   0x61028
  2407.  
  2408. #define TRANSCODER_A_OFFSET 0x60000
  2409. #define TRANSCODER_B_OFFSET 0x61000
  2410. #define TRANSCODER_C_OFFSET 0x62000
  2411. #define CHV_TRANSCODER_C_OFFSET 0x63000
  2412. #define TRANSCODER_EDP_OFFSET 0x6f000
  2413.  
  2414. #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
  2415.         dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
  2416.         dev_priv->info.display_mmio_offset)
  2417.  
  2418. #define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
  2419. #define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
  2420. #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
  2421. #define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
  2422. #define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
  2423. #define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
  2424. #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
  2425. #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
  2426. #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
  2427.  
  2428. /* HSW+ eDP PSR registers */
  2429. #define EDP_PSR_BASE(dev)                       (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
  2430. #define EDP_PSR_CTL(dev)                        (EDP_PSR_BASE(dev) + 0)
  2431. #define   EDP_PSR_ENABLE                        (1<<31)
  2432. #define   BDW_PSR_SINGLE_FRAME                  (1<<30)
  2433. #define   EDP_PSR_LINK_DISABLE                  (0<<27)
  2434. #define   EDP_PSR_LINK_STANDBY                  (1<<27)
  2435. #define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK      (3<<25)
  2436. #define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   (0<<25)
  2437. #define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES   (1<<25)
  2438. #define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES   (2<<25)
  2439. #define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES   (3<<25)
  2440. #define   EDP_PSR_MAX_SLEEP_TIME_SHIFT          20
  2441. #define   EDP_PSR_SKIP_AUX_EXIT                 (1<<12)
  2442. #define   EDP_PSR_TP1_TP2_SEL                   (0<<11)
  2443. #define   EDP_PSR_TP1_TP3_SEL                   (1<<11)
  2444. #define   EDP_PSR_TP2_TP3_TIME_500us            (0<<8)
  2445. #define   EDP_PSR_TP2_TP3_TIME_100us            (1<<8)
  2446. #define   EDP_PSR_TP2_TP3_TIME_2500us           (2<<8)
  2447. #define   EDP_PSR_TP2_TP3_TIME_0us              (3<<8)
  2448. #define   EDP_PSR_TP1_TIME_500us                (0<<4)
  2449. #define   EDP_PSR_TP1_TIME_100us                (1<<4)
  2450. #define   EDP_PSR_TP1_TIME_2500us               (2<<4)
  2451. #define   EDP_PSR_TP1_TIME_0us                  (3<<4)
  2452. #define   EDP_PSR_IDLE_FRAME_SHIFT              0
  2453.  
  2454. #define EDP_PSR_AUX_CTL(dev)                    (EDP_PSR_BASE(dev) + 0x10)
  2455. #define EDP_PSR_AUX_DATA1(dev)                  (EDP_PSR_BASE(dev) + 0x14)
  2456. #define   EDP_PSR_DPCD_COMMAND          0x80060000
  2457. #define EDP_PSR_AUX_DATA2(dev)                  (EDP_PSR_BASE(dev) + 0x18)
  2458. #define   EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
  2459. #define EDP_PSR_AUX_DATA3(dev)                  (EDP_PSR_BASE(dev) + 0x1c)
  2460. #define EDP_PSR_AUX_DATA4(dev)                  (EDP_PSR_BASE(dev) + 0x20)
  2461. #define EDP_PSR_AUX_DATA5(dev)                  (EDP_PSR_BASE(dev) + 0x24)
  2462.  
  2463. #define EDP_PSR_STATUS_CTL(dev)                 (EDP_PSR_BASE(dev) + 0x40)
  2464. #define   EDP_PSR_STATUS_STATE_MASK             (7<<29)
  2465. #define   EDP_PSR_STATUS_STATE_IDLE             (0<<29)
  2466. #define   EDP_PSR_STATUS_STATE_SRDONACK         (1<<29)
  2467. #define   EDP_PSR_STATUS_STATE_SRDENT           (2<<29)
  2468. #define   EDP_PSR_STATUS_STATE_BUFOFF           (3<<29)
  2469. #define   EDP_PSR_STATUS_STATE_BUFON            (4<<29)
  2470. #define   EDP_PSR_STATUS_STATE_AUXACK           (5<<29)
  2471. #define   EDP_PSR_STATUS_STATE_SRDOFFACK        (6<<29)
  2472. #define   EDP_PSR_STATUS_LINK_MASK              (3<<26)
  2473. #define   EDP_PSR_STATUS_LINK_FULL_OFF          (0<<26)
  2474. #define   EDP_PSR_STATUS_LINK_FULL_ON           (1<<26)
  2475. #define   EDP_PSR_STATUS_LINK_STANDBY           (2<<26)
  2476. #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT  20
  2477. #define   EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK   0x1f
  2478. #define   EDP_PSR_STATUS_COUNT_SHIFT            16
  2479. #define   EDP_PSR_STATUS_COUNT_MASK             0xf
  2480. #define   EDP_PSR_STATUS_AUX_ERROR              (1<<15)
  2481. #define   EDP_PSR_STATUS_AUX_SENDING            (1<<12)
  2482. #define   EDP_PSR_STATUS_SENDING_IDLE           (1<<9)
  2483. #define   EDP_PSR_STATUS_SENDING_TP2_TP3        (1<<8)
  2484. #define   EDP_PSR_STATUS_SENDING_TP1            (1<<4)
  2485. #define   EDP_PSR_STATUS_IDLE_MASK              0xf
  2486.  
  2487. #define EDP_PSR_PERF_CNT(dev)           (EDP_PSR_BASE(dev) + 0x44)
  2488. #define   EDP_PSR_PERF_CNT_MASK         0xffffff
  2489.  
  2490. #define EDP_PSR_DEBUG_CTL(dev)          (EDP_PSR_BASE(dev) + 0x60)
  2491. #define   EDP_PSR_DEBUG_MASK_LPSP       (1<<27)
  2492. #define   EDP_PSR_DEBUG_MASK_MEMUP      (1<<26)
  2493. #define   EDP_PSR_DEBUG_MASK_HPD        (1<<25)
  2494.  
  2495. /* VGA port control */
  2496. #define ADPA                    0x61100
  2497. #define PCH_ADPA                0xe1100
  2498. #define VLV_ADPA                (VLV_DISPLAY_BASE + ADPA)
  2499.  
  2500. #define   ADPA_DAC_ENABLE       (1<<31)
  2501. #define   ADPA_DAC_DISABLE      0
  2502. #define   ADPA_PIPE_SELECT_MASK (1<<30)
  2503. #define   ADPA_PIPE_A_SELECT    0
  2504. #define   ADPA_PIPE_B_SELECT    (1<<30)
  2505. #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
  2506. /* CPT uses bits 29:30 for pch transcoder select */
  2507. #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
  2508. #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
  2509. #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
  2510. #define   ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
  2511. #define   ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
  2512. #define   ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
  2513. #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
  2514. #define   ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
  2515. #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
  2516. #define   ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
  2517. #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
  2518. #define   ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
  2519. #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
  2520. #define   ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
  2521. #define   ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
  2522. #define   ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
  2523. #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
  2524. #define   ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
  2525. #define   ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
  2526. #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
  2527. #define   ADPA_SETS_HVPOLARITY  0
  2528. #define   ADPA_VSYNC_CNTL_DISABLE (1<<10)
  2529. #define   ADPA_VSYNC_CNTL_ENABLE 0
  2530. #define   ADPA_HSYNC_CNTL_DISABLE (1<<11)
  2531. #define   ADPA_HSYNC_CNTL_ENABLE 0
  2532. #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
  2533. #define   ADPA_VSYNC_ACTIVE_LOW 0
  2534. #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
  2535. #define   ADPA_HSYNC_ACTIVE_LOW 0
  2536. #define   ADPA_DPMS_MASK        (~(3<<10))
  2537. #define   ADPA_DPMS_ON          (0<<10)
  2538. #define   ADPA_DPMS_SUSPEND     (1<<10)
  2539. #define   ADPA_DPMS_STANDBY     (2<<10)
  2540. #define   ADPA_DPMS_OFF         (3<<10)
  2541.  
  2542.  
  2543. /* Hotplug control (945+ only) */
  2544. #define PORT_HOTPLUG_EN         (dev_priv->info.display_mmio_offset + 0x61110)
  2545. #define   PORTB_HOTPLUG_INT_EN                  (1 << 29)
  2546. #define   PORTC_HOTPLUG_INT_EN                  (1 << 28)
  2547. #define   PORTD_HOTPLUG_INT_EN                  (1 << 27)
  2548. #define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
  2549. #define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
  2550. #define   TV_HOTPLUG_INT_EN                     (1 << 18)
  2551. #define   CRT_HOTPLUG_INT_EN                    (1 << 9)
  2552. #define HOTPLUG_INT_EN_MASK                     (PORTB_HOTPLUG_INT_EN | \
  2553.                                                  PORTC_HOTPLUG_INT_EN | \
  2554.                                                  PORTD_HOTPLUG_INT_EN | \
  2555.                                                  SDVOC_HOTPLUG_INT_EN | \
  2556.                                                  SDVOB_HOTPLUG_INT_EN | \
  2557.                                                  CRT_HOTPLUG_INT_EN)
  2558. #define   CRT_HOTPLUG_FORCE_DETECT              (1 << 3)
  2559. #define CRT_HOTPLUG_ACTIVATION_PERIOD_32        (0 << 8)
  2560. /* must use period 64 on GM45 according to docs */
  2561. #define CRT_HOTPLUG_ACTIVATION_PERIOD_64        (1 << 8)
  2562. #define CRT_HOTPLUG_DAC_ON_TIME_2M              (0 << 7)
  2563. #define CRT_HOTPLUG_DAC_ON_TIME_4M              (1 << 7)
  2564. #define CRT_HOTPLUG_VOLTAGE_COMPARE_40          (0 << 5)
  2565. #define CRT_HOTPLUG_VOLTAGE_COMPARE_50          (1 << 5)
  2566. #define CRT_HOTPLUG_VOLTAGE_COMPARE_60          (2 << 5)
  2567. #define CRT_HOTPLUG_VOLTAGE_COMPARE_70          (3 << 5)
  2568. #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK        (3 << 5)
  2569. #define CRT_HOTPLUG_DETECT_DELAY_1G             (0 << 4)
  2570. #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
  2571. #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
  2572. #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
  2573.  
  2574. #define PORT_HOTPLUG_STAT       (dev_priv->info.display_mmio_offset + 0x61114)
  2575. /*
  2576.  * HDMI/DP bits are gen4+
  2577.  *
  2578.  * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
  2579.  * Please check the detailed lore in the commit message for for experimental
  2580.  * evidence.
  2581.  */
  2582. #define   PORTD_HOTPLUG_LIVE_STATUS_G4X         (1 << 29)
  2583. #define   PORTC_HOTPLUG_LIVE_STATUS_G4X         (1 << 28)
  2584. #define   PORTB_HOTPLUG_LIVE_STATUS_G4X         (1 << 27)
  2585. /* VLV DP/HDMI bits again match Bspec */
  2586. #define   PORTD_HOTPLUG_LIVE_STATUS_VLV         (1 << 27)
  2587. #define   PORTC_HOTPLUG_LIVE_STATUS_VLV         (1 << 28)
  2588. #define   PORTB_HOTPLUG_LIVE_STATUS_VLV         (1 << 29)
  2589. #define   PORTD_HOTPLUG_INT_STATUS              (3 << 21)
  2590. #define   PORTD_HOTPLUG_INT_LONG_PULSE          (2 << 21)
  2591. #define   PORTD_HOTPLUG_INT_SHORT_PULSE         (1 << 21)
  2592. #define   PORTC_HOTPLUG_INT_STATUS              (3 << 19)
  2593. #define   PORTC_HOTPLUG_INT_LONG_PULSE          (2 << 19)
  2594. #define   PORTC_HOTPLUG_INT_SHORT_PULSE         (1 << 19)
  2595. #define   PORTB_HOTPLUG_INT_STATUS              (3 << 17)
  2596. #define   PORTB_HOTPLUG_INT_LONG_PULSE          (2 << 17)
  2597. #define   PORTB_HOTPLUG_INT_SHORT_PLUSE         (1 << 17)
  2598. /* CRT/TV common between gen3+ */
  2599. #define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
  2600. #define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
  2601. #define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
  2602. #define   CRT_HOTPLUG_MONITOR_COLOR             (3 << 8)
  2603. #define   CRT_HOTPLUG_MONITOR_MONO              (2 << 8)
  2604. #define   CRT_HOTPLUG_MONITOR_NONE              (0 << 8)
  2605. #define   DP_AUX_CHANNEL_D_INT_STATUS_G4X       (1 << 6)
  2606. #define   DP_AUX_CHANNEL_C_INT_STATUS_G4X       (1 << 5)
  2607. #define   DP_AUX_CHANNEL_B_INT_STATUS_G4X       (1 << 4)
  2608. #define   DP_AUX_CHANNEL_MASK_INT_STATUS_G4X    (7 << 4)
  2609.  
  2610. /* SDVO is different across gen3/4 */
  2611. #define   SDVOC_HOTPLUG_INT_STATUS_G4X          (1 << 3)
  2612. #define   SDVOB_HOTPLUG_INT_STATUS_G4X          (1 << 2)
  2613. /*
  2614.  * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
  2615.  * since reality corrobates that they're the same as on gen3. But keep these
  2616.  * bits here (and the comment!) to help any other lost wanderers back onto the
  2617.  * right tracks.
  2618.  */
  2619. #define   SDVOC_HOTPLUG_INT_STATUS_I965         (3 << 4)
  2620. #define   SDVOB_HOTPLUG_INT_STATUS_I965         (3 << 2)
  2621. #define   SDVOC_HOTPLUG_INT_STATUS_I915         (1 << 7)
  2622. #define   SDVOB_HOTPLUG_INT_STATUS_I915         (1 << 6)
  2623. #define   HOTPLUG_INT_STATUS_G4X                (CRT_HOTPLUG_INT_STATUS | \
  2624.                                                  SDVOB_HOTPLUG_INT_STATUS_G4X | \
  2625.                                                  SDVOC_HOTPLUG_INT_STATUS_G4X | \
  2626.                                                  PORTB_HOTPLUG_INT_STATUS | \
  2627.                                                  PORTC_HOTPLUG_INT_STATUS | \
  2628.                                                  PORTD_HOTPLUG_INT_STATUS)
  2629.  
  2630. #define HOTPLUG_INT_STATUS_I915                 (CRT_HOTPLUG_INT_STATUS | \
  2631.                                                  SDVOB_HOTPLUG_INT_STATUS_I915 | \
  2632.                                                  SDVOC_HOTPLUG_INT_STATUS_I915 | \
  2633.                                                  PORTB_HOTPLUG_INT_STATUS | \
  2634.                                                  PORTC_HOTPLUG_INT_STATUS | \
  2635.                                                  PORTD_HOTPLUG_INT_STATUS)
  2636.  
  2637. /* SDVO and HDMI port control.
  2638.  * The same register may be used for SDVO or HDMI */
  2639. #define GEN3_SDVOB      0x61140
  2640. #define GEN3_SDVOC      0x61160
  2641. #define GEN4_HDMIB      GEN3_SDVOB
  2642. #define GEN4_HDMIC      GEN3_SDVOC
  2643. #define CHV_HDMID       0x6116C
  2644. #define PCH_SDVOB       0xe1140
  2645. #define PCH_HDMIB       PCH_SDVOB
  2646. #define PCH_HDMIC       0xe1150
  2647. #define PCH_HDMID       0xe1160
  2648.  
  2649. #define PORT_DFT_I9XX                           0x61150
  2650. #define   DC_BALANCE_RESET                      (1 << 25)
  2651. #define PORT_DFT2_G4X           (dev_priv->info.display_mmio_offset + 0x61154)
  2652. #define   DC_BALANCE_RESET_VLV                  (1 << 31)
  2653. #define   PIPE_SCRAMBLE_RESET_MASK              (0x3 << 0)
  2654. #define   PIPE_B_SCRAMBLE_RESET                 (1 << 1)
  2655. #define   PIPE_A_SCRAMBLE_RESET                 (1 << 0)
  2656.  
  2657. /* Gen 3 SDVO bits: */
  2658. #define   SDVO_ENABLE           (1 << 31)
  2659. #define   SDVO_PIPE_SEL(pipe)                   ((pipe) << 30)
  2660. #define   SDVO_PIPE_SEL_MASK                    (1 << 30)
  2661. #define   SDVO_PIPE_B_SELECT    (1 << 30)
  2662. #define   SDVO_STALL_SELECT     (1 << 29)
  2663. #define   SDVO_INTERRUPT_ENABLE (1 << 26)
  2664. /*
  2665.  * 915G/GM SDVO pixel multiplier.
  2666.  * Programmed value is multiplier - 1, up to 5x.
  2667.  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
  2668.  */
  2669. #define   SDVO_PORT_MULTIPLY_MASK       (7 << 23)
  2670. #define   SDVO_PORT_MULTIPLY_SHIFT              23
  2671. #define   SDVO_PHASE_SELECT_MASK        (15 << 19)
  2672. #define   SDVO_PHASE_SELECT_DEFAULT     (6 << 19)
  2673. #define   SDVO_CLOCK_OUTPUT_INVERT      (1 << 18)
  2674. #define   SDVOC_GANG_MODE                       (1 << 16) /* Port C only */
  2675. #define   SDVO_BORDER_ENABLE                    (1 << 7) /* SDVO only */
  2676. #define   SDVOB_PCIE_CONCURRENCY                (1 << 3) /* Port B only */
  2677. #define   SDVO_DETECTED                         (1 << 2)
  2678. /* Bits to be preserved when writing */
  2679. #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
  2680.                                SDVO_INTERRUPT_ENABLE)
  2681. #define   SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
  2682.  
  2683. /* Gen 4 SDVO/HDMI bits: */
  2684. #define   SDVO_COLOR_FORMAT_8bpc                (0 << 26)
  2685. #define   SDVO_COLOR_FORMAT_MASK                (7 << 26)
  2686. #define   SDVO_ENCODING_SDVO                    (0 << 10)
  2687. #define   SDVO_ENCODING_HDMI                    (2 << 10)
  2688. #define   HDMI_MODE_SELECT_HDMI                 (1 << 9) /* HDMI only */
  2689. #define   HDMI_MODE_SELECT_DVI                  (0 << 9) /* HDMI only */
  2690. #define   HDMI_COLOR_RANGE_16_235               (1 << 8) /* HDMI only */
  2691. #define   SDVO_AUDIO_ENABLE             (1 << 6)
  2692. /* VSYNC/HSYNC bits new with 965, default is to be set */
  2693. #define   SDVO_VSYNC_ACTIVE_HIGH        (1 << 4)
  2694. #define   SDVO_HSYNC_ACTIVE_HIGH        (1 << 3)
  2695.  
  2696. /* Gen 5 (IBX) SDVO/HDMI bits: */
  2697. #define   HDMI_COLOR_FORMAT_12bpc               (3 << 26) /* HDMI only */
  2698. #define   SDVOB_HOTPLUG_ENABLE                  (1 << 23) /* SDVO only */
  2699.  
  2700. /* Gen 6 (CPT) SDVO/HDMI bits: */
  2701. #define   SDVO_PIPE_SEL_CPT(pipe)               ((pipe) << 29)
  2702. #define   SDVO_PIPE_SEL_MASK_CPT                (3 << 29)
  2703.  
  2704. /* CHV SDVO/HDMI bits: */
  2705. #define   SDVO_PIPE_SEL_CHV(pipe)               ((pipe) << 24)
  2706. #define   SDVO_PIPE_SEL_MASK_CHV                (3 << 24)
  2707.  
  2708.  
  2709. /* DVO port control */
  2710. #define DVOA                    0x61120
  2711. #define DVOB                    0x61140
  2712. #define DVOC                    0x61160
  2713. #define   DVO_ENABLE                    (1 << 31)
  2714. #define   DVO_PIPE_B_SELECT             (1 << 30)
  2715. #define   DVO_PIPE_STALL_UNUSED         (0 << 28)
  2716. #define   DVO_PIPE_STALL                (1 << 28)
  2717. #define   DVO_PIPE_STALL_TV             (2 << 28)
  2718. #define   DVO_PIPE_STALL_MASK           (3 << 28)
  2719. #define   DVO_USE_VGA_SYNC              (1 << 15)
  2720. #define   DVO_DATA_ORDER_I740           (0 << 14)
  2721. #define   DVO_DATA_ORDER_FP             (1 << 14)
  2722. #define   DVO_VSYNC_DISABLE             (1 << 11)
  2723. #define   DVO_HSYNC_DISABLE             (1 << 10)
  2724. #define   DVO_VSYNC_TRISTATE            (1 << 9)
  2725. #define   DVO_HSYNC_TRISTATE            (1 << 8)
  2726. #define   DVO_BORDER_ENABLE             (1 << 7)
  2727. #define   DVO_DATA_ORDER_GBRG           (1 << 6)
  2728. #define   DVO_DATA_ORDER_RGGB           (0 << 6)
  2729. #define   DVO_DATA_ORDER_GBRG_ERRATA    (0 << 6)
  2730. #define   DVO_DATA_ORDER_RGGB_ERRATA    (1 << 6)
  2731. #define   DVO_VSYNC_ACTIVE_HIGH         (1 << 4)
  2732. #define   DVO_HSYNC_ACTIVE_HIGH         (1 << 3)
  2733. #define   DVO_BLANK_ACTIVE_HIGH         (1 << 2)
  2734. #define   DVO_OUTPUT_CSTATE_PIXELS      (1 << 1)        /* SDG only */
  2735. #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)        /* SDG only */
  2736. #define   DVO_PRESERVE_MASK             (0x7<<24)
  2737. #define DVOA_SRCDIM             0x61124
  2738. #define DVOB_SRCDIM             0x61144
  2739. #define DVOC_SRCDIM             0x61164
  2740. #define   DVO_SRCDIM_HORIZONTAL_SHIFT   12
  2741. #define   DVO_SRCDIM_VERTICAL_SHIFT     0
  2742.  
  2743. /* LVDS port control */
  2744. #define LVDS                    0x61180
  2745. /*
  2746.  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
  2747.  * the DPLL semantics change when the LVDS is assigned to that pipe.
  2748.  */
  2749. #define   LVDS_PORT_EN                  (1 << 31)
  2750. /* Selects pipe B for LVDS data.  Must be set on pre-965. */
  2751. #define   LVDS_PIPEB_SELECT             (1 << 30)
  2752. #define   LVDS_PIPE_MASK                (1 << 30)
  2753. #define   LVDS_PIPE(pipe)               ((pipe) << 30)
  2754. /* LVDS dithering flag on 965/g4x platform */
  2755. #define   LVDS_ENABLE_DITHER            (1 << 25)
  2756. /* LVDS sync polarity flags. Set to invert (i.e. negative) */
  2757. #define   LVDS_VSYNC_POLARITY           (1 << 21)
  2758. #define   LVDS_HSYNC_POLARITY           (1 << 20)
  2759.  
  2760. /* Enable border for unscaled (or aspect-scaled) display */
  2761. #define   LVDS_BORDER_ENABLE            (1 << 15)
  2762. /*
  2763.  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
  2764.  * pixel.
  2765.  */
  2766. #define   LVDS_A0A2_CLKA_POWER_MASK     (3 << 8)
  2767. #define   LVDS_A0A2_CLKA_POWER_DOWN     (0 << 8)
  2768. #define   LVDS_A0A2_CLKA_POWER_UP       (3 << 8)
  2769. /*
  2770.  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
  2771.  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
  2772.  * on.
  2773.  */
  2774. #define   LVDS_A3_POWER_MASK            (3 << 6)
  2775. #define   LVDS_A3_POWER_DOWN            (0 << 6)
  2776. #define   LVDS_A3_POWER_UP              (3 << 6)
  2777. /*
  2778.  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
  2779.  * is set.
  2780.  */
  2781. #define   LVDS_CLKB_POWER_MASK          (3 << 4)
  2782. #define   LVDS_CLKB_POWER_DOWN          (0 << 4)
  2783. #define   LVDS_CLKB_POWER_UP            (3 << 4)
  2784. /*
  2785.  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
  2786.  * setting for whether we are in dual-channel mode.  The B3 pair will
  2787.  * additionally only be powered up when LVDS_A3_POWER_UP is set.
  2788.  */
  2789. #define   LVDS_B0B3_POWER_MASK          (3 << 2)
  2790. #define   LVDS_B0B3_POWER_DOWN          (0 << 2)
  2791. #define   LVDS_B0B3_POWER_UP            (3 << 2)
  2792.  
  2793. /* Video Data Island Packet control */
  2794. #define VIDEO_DIP_DATA          0x61178
  2795. /* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
  2796.  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  2797.  * of the infoframe structure specified by CEA-861. */
  2798. #define   VIDEO_DIP_DATA_SIZE   32
  2799. #define   VIDEO_DIP_VSC_DATA_SIZE       36
  2800. #define VIDEO_DIP_CTL           0x61170
  2801. /* Pre HSW: */
  2802. #define   VIDEO_DIP_ENABLE              (1 << 31)
  2803. #define   VIDEO_DIP_PORT(port)          ((port) << 29)
  2804. #define   VIDEO_DIP_PORT_MASK           (3 << 29)
  2805. #define   VIDEO_DIP_ENABLE_GCP          (1 << 25)
  2806. #define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
  2807. #define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
  2808. #define   VIDEO_DIP_ENABLE_GAMUT        (4 << 21)
  2809. #define   VIDEO_DIP_ENABLE_SPD          (8 << 21)
  2810. #define   VIDEO_DIP_SELECT_AVI          (0 << 19)
  2811. #define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
  2812. #define   VIDEO_DIP_SELECT_SPD          (3 << 19)
  2813. #define   VIDEO_DIP_SELECT_MASK         (3 << 19)
  2814. #define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
  2815. #define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
  2816. #define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
  2817. #define   VIDEO_DIP_FREQ_MASK           (3 << 16)
  2818. /* HSW and later: */
  2819. #define   VIDEO_DIP_ENABLE_VSC_HSW      (1 << 20)
  2820. #define   VIDEO_DIP_ENABLE_GCP_HSW      (1 << 16)
  2821. #define   VIDEO_DIP_ENABLE_AVI_HSW      (1 << 12)
  2822. #define   VIDEO_DIP_ENABLE_VS_HSW       (1 << 8)
  2823. #define   VIDEO_DIP_ENABLE_GMP_HSW      (1 << 4)
  2824. #define   VIDEO_DIP_ENABLE_SPD_HSW      (1 << 0)
  2825.  
  2826. /* Panel power sequencing */
  2827. #define PP_STATUS       0x61200
  2828. #define   PP_ON         (1 << 31)
  2829. /*
  2830.  * Indicates that all dependencies of the panel are on:
  2831.  *
  2832.  * - PLL enabled
  2833.  * - pipe enabled
  2834.  * - LVDS/DVOB/DVOC on
  2835.  */
  2836. #define   PP_READY              (1 << 30)
  2837. #define   PP_SEQUENCE_NONE      (0 << 28)
  2838. #define   PP_SEQUENCE_POWER_UP  (1 << 28)
  2839. #define   PP_SEQUENCE_POWER_DOWN (2 << 28)
  2840. #define   PP_SEQUENCE_MASK      (3 << 28)
  2841. #define   PP_SEQUENCE_SHIFT     28
  2842. #define   PP_CYCLE_DELAY_ACTIVE (1 << 27)
  2843. #define   PP_SEQUENCE_STATE_MASK 0x0000000f
  2844. #define   PP_SEQUENCE_STATE_OFF_IDLE    (0x0 << 0)
  2845. #define   PP_SEQUENCE_STATE_OFF_S0_1    (0x1 << 0)
  2846. #define   PP_SEQUENCE_STATE_OFF_S0_2    (0x2 << 0)
  2847. #define   PP_SEQUENCE_STATE_OFF_S0_3    (0x3 << 0)
  2848. #define   PP_SEQUENCE_STATE_ON_IDLE     (0x8 << 0)
  2849. #define   PP_SEQUENCE_STATE_ON_S1_0     (0x9 << 0)
  2850. #define   PP_SEQUENCE_STATE_ON_S1_2     (0xa << 0)
  2851. #define   PP_SEQUENCE_STATE_ON_S1_3     (0xb << 0)
  2852. #define   PP_SEQUENCE_STATE_RESET       (0xf << 0)
  2853. #define PP_CONTROL      0x61204
  2854. #define   POWER_TARGET_ON       (1 << 0)
  2855. #define PP_ON_DELAYS    0x61208
  2856. #define PP_OFF_DELAYS   0x6120c
  2857. #define PP_DIVISOR      0x61210
  2858.  
  2859. /* Panel fitting */
  2860. #define PFIT_CONTROL    (dev_priv->info.display_mmio_offset + 0x61230)
  2861. #define   PFIT_ENABLE           (1 << 31)
  2862. #define   PFIT_PIPE_MASK        (3 << 29)
  2863. #define   PFIT_PIPE_SHIFT       29
  2864. #define   VERT_INTERP_DISABLE   (0 << 10)
  2865. #define   VERT_INTERP_BILINEAR  (1 << 10)
  2866. #define   VERT_INTERP_MASK      (3 << 10)
  2867. #define   VERT_AUTO_SCALE       (1 << 9)
  2868. #define   HORIZ_INTERP_DISABLE  (0 << 6)
  2869. #define   HORIZ_INTERP_BILINEAR (1 << 6)
  2870. #define   HORIZ_INTERP_MASK     (3 << 6)
  2871. #define   HORIZ_AUTO_SCALE      (1 << 5)
  2872. #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
  2873. #define   PFIT_FILTER_FUZZY     (0 << 24)
  2874. #define   PFIT_SCALING_AUTO     (0 << 26)
  2875. #define   PFIT_SCALING_PROGRAMMED (1 << 26)
  2876. #define   PFIT_SCALING_PILLAR   (2 << 26)
  2877. #define   PFIT_SCALING_LETTER   (3 << 26)
  2878. #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
  2879. /* Pre-965 */
  2880. #define         PFIT_VERT_SCALE_SHIFT           20
  2881. #define         PFIT_VERT_SCALE_MASK            0xfff00000
  2882. #define         PFIT_HORIZ_SCALE_SHIFT          4
  2883. #define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
  2884. /* 965+ */
  2885. #define         PFIT_VERT_SCALE_SHIFT_965       16
  2886. #define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
  2887. #define         PFIT_HORIZ_SCALE_SHIFT_965      0
  2888. #define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff
  2889.  
  2890. #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
  2891.  
  2892. #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
  2893. #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
  2894. #define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
  2895.                                      _VLV_BLC_PWM_CTL2_B)
  2896.  
  2897. #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
  2898. #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
  2899. #define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
  2900.                                     _VLV_BLC_PWM_CTL_B)
  2901.  
  2902. #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
  2903. #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
  2904. #define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
  2905.                                      _VLV_BLC_HIST_CTL_B)
  2906.  
  2907. /* Backlight control */
  2908. #define BLC_PWM_CTL2    (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
  2909. #define   BLM_PWM_ENABLE                (1 << 31)
  2910. #define   BLM_COMBINATION_MODE          (1 << 30) /* gen4 only */
  2911. #define   BLM_PIPE_SELECT               (1 << 29)
  2912. #define   BLM_PIPE_SELECT_IVB           (3 << 29)
  2913. #define   BLM_PIPE_A                    (0 << 29)
  2914. #define   BLM_PIPE_B                    (1 << 29)
  2915. #define   BLM_PIPE_C                    (2 << 29) /* ivb + */
  2916. #define   BLM_TRANSCODER_A              BLM_PIPE_A /* hsw */
  2917. #define   BLM_TRANSCODER_B              BLM_PIPE_B
  2918. #define   BLM_TRANSCODER_C              BLM_PIPE_C
  2919. #define   BLM_TRANSCODER_EDP            (3 << 29)
  2920. #define   BLM_PIPE(pipe)                ((pipe) << 29)
  2921. #define   BLM_POLARITY_I965             (1 << 28) /* gen4 only */
  2922. #define   BLM_PHASE_IN_INTERUPT_STATUS  (1 << 26)
  2923. #define   BLM_PHASE_IN_ENABLE           (1 << 25)
  2924. #define   BLM_PHASE_IN_INTERUPT_ENABL   (1 << 24)
  2925. #define   BLM_PHASE_IN_TIME_BASE_SHIFT  (16)
  2926. #define   BLM_PHASE_IN_TIME_BASE_MASK   (0xff << 16)
  2927. #define   BLM_PHASE_IN_COUNT_SHIFT      (8)
  2928. #define   BLM_PHASE_IN_COUNT_MASK       (0xff << 8)
  2929. #define   BLM_PHASE_IN_INCR_SHIFT       (0)
  2930. #define   BLM_PHASE_IN_INCR_MASK        (0xff << 0)
  2931. #define BLC_PWM_CTL     (dev_priv->info.display_mmio_offset + 0x61254)
  2932. /*
  2933.  * This is the most significant 15 bits of the number of backlight cycles in a
  2934.  * complete cycle of the modulated backlight control.
  2935.  *
  2936.  * The actual value is this field multiplied by two.
  2937.  */
  2938. #define   BACKLIGHT_MODULATION_FREQ_SHIFT       (17)
  2939. #define   BACKLIGHT_MODULATION_FREQ_MASK                (0x7fff << 17)
  2940. #define   BLM_LEGACY_MODE                       (1 << 16) /* gen2 only */
  2941. /*
  2942.  * This is the number of cycles out of the backlight modulation cycle for which
  2943.  * the backlight is on.
  2944.  *
  2945.  * This field must be no greater than the number of cycles in the complete
  2946.  * backlight modulation cycle.
  2947.  */
  2948. #define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
  2949. #define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
  2950. #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV         (0xfffe)
  2951. #define   BLM_POLARITY_PNV                      (1 << 0) /* pnv only */
  2952.  
  2953. #define BLC_HIST_CTL    (dev_priv->info.display_mmio_offset + 0x61260)
  2954.  
  2955. /* New registers for PCH-split platforms. Safe where new bits show up, the
  2956.  * register layout machtes with gen4 BLC_PWM_CTL[12]. */
  2957. #define BLC_PWM_CPU_CTL2        0x48250
  2958. #define BLC_PWM_CPU_CTL         0x48254
  2959.  
  2960. #define HSW_BLC_PWM2_CTL        0x48350
  2961.  
  2962. /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
  2963.  * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
  2964. #define BLC_PWM_PCH_CTL1        0xc8250
  2965. #define   BLM_PCH_PWM_ENABLE                    (1 << 31)
  2966. #define   BLM_PCH_OVERRIDE_ENABLE               (1 << 30)
  2967. #define   BLM_PCH_POLARITY                      (1 << 29)
  2968. #define BLC_PWM_PCH_CTL2        0xc8254
  2969.  
  2970. #define UTIL_PIN_CTL            0x48400
  2971. #define   UTIL_PIN_ENABLE       (1 << 31)
  2972.  
  2973. #define PCH_GTC_CTL             0xe7000
  2974. #define   PCH_GTC_ENABLE        (1 << 31)
  2975.  
  2976. /* TV port control */
  2977. #define TV_CTL                  0x68000
  2978. /* Enables the TV encoder */
  2979. # define TV_ENC_ENABLE                  (1 << 31)
  2980. /* Sources the TV encoder input from pipe B instead of A. */
  2981. # define TV_ENC_PIPEB_SELECT            (1 << 30)
  2982. /* Outputs composite video (DAC A only) */
  2983. # define TV_ENC_OUTPUT_COMPOSITE        (0 << 28)
  2984. /* Outputs SVideo video (DAC B/C) */
  2985. # define TV_ENC_OUTPUT_SVIDEO           (1 << 28)
  2986. /* Outputs Component video (DAC A/B/C) */
  2987. # define TV_ENC_OUTPUT_COMPONENT        (2 << 28)
  2988. /* Outputs Composite and SVideo (DAC A/B/C) */
  2989. # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
  2990. # define TV_TRILEVEL_SYNC               (1 << 21)
  2991. /* Enables slow sync generation (945GM only) */
  2992. # define TV_SLOW_SYNC                   (1 << 20)
  2993. /* Selects 4x oversampling for 480i and 576p */
  2994. # define TV_OVERSAMPLE_4X               (0 << 18)
  2995. /* Selects 2x oversampling for 720p and 1080i */
  2996. # define TV_OVERSAMPLE_2X               (1 << 18)
  2997. /* Selects no oversampling for 1080p */
  2998. # define TV_OVERSAMPLE_NONE             (2 << 18)
  2999. /* Selects 8x oversampling */
  3000. # define TV_OVERSAMPLE_8X               (3 << 18)
  3001. /* Selects progressive mode rather than interlaced */
  3002. # define TV_PROGRESSIVE                 (1 << 17)
  3003. /* Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
  3004. # define TV_PAL_BURST                   (1 << 16)
  3005. /* Field for setting delay of Y compared to C */
  3006. # define TV_YC_SKEW_MASK                (7 << 12)
  3007. /* Enables a fix for 480p/576p standard definition modes on the 915GM only */
  3008. # define TV_ENC_SDP_FIX                 (1 << 11)
  3009. /*
  3010.  * Enables a fix for the 915GM only.
  3011.  *
  3012.  * Not sure what it does.
  3013.  */
  3014. # define TV_ENC_C0_FIX                  (1 << 10)
  3015. /* Bits that must be preserved by software */
  3016. # define TV_CTL_SAVE                    ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
  3017. # define TV_FUSE_STATE_MASK             (3 << 4)
  3018. /* Read-only state that reports all features enabled */
  3019. # define TV_FUSE_STATE_ENABLED          (0 << 4)
  3020. /* Read-only state that reports that Macrovision is disabled in hardware*/
  3021. # define TV_FUSE_STATE_NO_MACROVISION   (1 << 4)
  3022. /* Read-only state that reports that TV-out is disabled in hardware. */
  3023. # define TV_FUSE_STATE_DISABLED         (2 << 4)
  3024. /* Normal operation */
  3025. # define TV_TEST_MODE_NORMAL            (0 << 0)
  3026. /* Encoder test pattern 1 - combo pattern */
  3027. # define TV_TEST_MODE_PATTERN_1         (1 << 0)
  3028. /* Encoder test pattern 2 - full screen vertical 75% color bars */
  3029. # define TV_TEST_MODE_PATTERN_2         (2 << 0)
  3030. /* Encoder test pattern 3 - full screen horizontal 75% color bars */
  3031. # define TV_TEST_MODE_PATTERN_3         (3 << 0)
  3032. /* Encoder test pattern 4 - random noise */
  3033. # define TV_TEST_MODE_PATTERN_4         (4 << 0)
  3034. /* Encoder test pattern 5 - linear color ramps */
  3035. # define TV_TEST_MODE_PATTERN_5         (5 << 0)
  3036. /*
  3037.  * This test mode forces the DACs to 50% of full output.
  3038.  *
  3039.  * This is used for load detection in combination with TVDAC_SENSE_MASK
  3040.  */
  3041. # define TV_TEST_MODE_MONITOR_DETECT    (7 << 0)
  3042. # define TV_TEST_MODE_MASK              (7 << 0)
  3043.  
  3044. #define TV_DAC                  0x68004
  3045. # define TV_DAC_SAVE            0x00ffff00
  3046. /*
  3047.  * Reports that DAC state change logic has reported change (RO).
  3048.  *
  3049.  * This gets cleared when TV_DAC_STATE_EN is cleared
  3050. */
  3051. # define TVDAC_STATE_CHG                (1 << 31)
  3052. # define TVDAC_SENSE_MASK               (7 << 28)
  3053. /* Reports that DAC A voltage is above the detect threshold */
  3054. # define TVDAC_A_SENSE                  (1 << 30)
  3055. /* Reports that DAC B voltage is above the detect threshold */
  3056. # define TVDAC_B_SENSE                  (1 << 29)
  3057. /* Reports that DAC C voltage is above the detect threshold */
  3058. # define TVDAC_C_SENSE                  (1 << 28)
  3059. /*
  3060.  * Enables DAC state detection logic, for load-based TV detection.
  3061.  *
  3062.  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
  3063.  * to off, for load detection to work.
  3064.  */
  3065. # define TVDAC_STATE_CHG_EN             (1 << 27)
  3066. /* Sets the DAC A sense value to high */
  3067. # define TVDAC_A_SENSE_CTL              (1 << 26)
  3068. /* Sets the DAC B sense value to high */
  3069. # define TVDAC_B_SENSE_CTL              (1 << 25)
  3070. /* Sets the DAC C sense value to high */
  3071. # define TVDAC_C_SENSE_CTL              (1 << 24)
  3072. /* Overrides the ENC_ENABLE and DAC voltage levels */
  3073. # define DAC_CTL_OVERRIDE               (1 << 7)
  3074. /* Sets the slew rate.  Must be preserved in software */
  3075. # define ENC_TVDAC_SLEW_FAST            (1 << 6)
  3076. # define DAC_A_1_3_V                    (0 << 4)
  3077. # define DAC_A_1_1_V                    (1 << 4)
  3078. # define DAC_A_0_7_V                    (2 << 4)
  3079. # define DAC_A_MASK                     (3 << 4)
  3080. # define DAC_B_1_3_V                    (0 << 2)
  3081. # define DAC_B_1_1_V                    (1 << 2)
  3082. # define DAC_B_0_7_V                    (2 << 2)
  3083. # define DAC_B_MASK                     (3 << 2)
  3084. # define DAC_C_1_3_V                    (0 << 0)
  3085. # define DAC_C_1_1_V                    (1 << 0)
  3086. # define DAC_C_0_7_V                    (2 << 0)
  3087. # define DAC_C_MASK                     (3 << 0)
  3088.  
  3089. /*
  3090.  * CSC coefficients are stored in a floating point format with 9 bits of
  3091.  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
  3092.  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
  3093.  * -1 (0x3) being the only legal negative value.
  3094.  */
  3095. #define TV_CSC_Y                0x68010
  3096. # define TV_RY_MASK                     0x07ff0000
  3097. # define TV_RY_SHIFT                    16
  3098. # define TV_GY_MASK                     0x00000fff
  3099. # define TV_GY_SHIFT                    0
  3100.  
  3101. #define TV_CSC_Y2               0x68014
  3102. # define TV_BY_MASK                     0x07ff0000
  3103. # define TV_BY_SHIFT                    16
  3104. /*
  3105.  * Y attenuation for component video.
  3106.  *
  3107.  * Stored in 1.9 fixed point.
  3108.  */
  3109. # define TV_AY_MASK                     0x000003ff
  3110. # define TV_AY_SHIFT                    0
  3111.  
  3112. #define TV_CSC_U                0x68018
  3113. # define TV_RU_MASK                     0x07ff0000
  3114. # define TV_RU_SHIFT                    16
  3115. # define TV_GU_MASK                     0x000007ff
  3116. # define TV_GU_SHIFT                    0
  3117.  
  3118. #define TV_CSC_U2               0x6801c
  3119. # define TV_BU_MASK                     0x07ff0000
  3120. # define TV_BU_SHIFT                    16
  3121. /*
  3122.  * U attenuation for component video.
  3123.  *
  3124.  * Stored in 1.9 fixed point.
  3125.  */
  3126. # define TV_AU_MASK                     0x000003ff
  3127. # define TV_AU_SHIFT                    0
  3128.  
  3129. #define TV_CSC_V                0x68020
  3130. # define TV_RV_MASK                     0x0fff0000
  3131. # define TV_RV_SHIFT                    16
  3132. # define TV_GV_MASK                     0x000007ff
  3133. # define TV_GV_SHIFT                    0
  3134.  
  3135. #define TV_CSC_V2               0x68024
  3136. # define TV_BV_MASK                     0x07ff0000
  3137. # define TV_BV_SHIFT                    16
  3138. /*
  3139.  * V attenuation for component video.
  3140.  *
  3141.  * Stored in 1.9 fixed point.
  3142.  */
  3143. # define TV_AV_MASK                     0x000007ff
  3144. # define TV_AV_SHIFT                    0
  3145.  
  3146. #define TV_CLR_KNOBS            0x68028
  3147. /* 2s-complement brightness adjustment */
  3148. # define TV_BRIGHTNESS_MASK             0xff000000
  3149. # define TV_BRIGHTNESS_SHIFT            24
  3150. /* Contrast adjustment, as a 2.6 unsigned floating point number */
  3151. # define TV_CONTRAST_MASK               0x00ff0000
  3152. # define TV_CONTRAST_SHIFT              16
  3153. /* Saturation adjustment, as a 2.6 unsigned floating point number */
  3154. # define TV_SATURATION_MASK             0x0000ff00
  3155. # define TV_SATURATION_SHIFT            8
  3156. /* Hue adjustment, as an integer phase angle in degrees */
  3157. # define TV_HUE_MASK                    0x000000ff
  3158. # define TV_HUE_SHIFT                   0
  3159.  
  3160. #define TV_CLR_LEVEL            0x6802c
  3161. /* Controls the DAC level for black */
  3162. # define TV_BLACK_LEVEL_MASK            0x01ff0000
  3163. # define TV_BLACK_LEVEL_SHIFT           16
  3164. /* Controls the DAC level for blanking */
  3165. # define TV_BLANK_LEVEL_MASK            0x000001ff
  3166. # define TV_BLANK_LEVEL_SHIFT           0
  3167.  
  3168. #define TV_H_CTL_1              0x68030
  3169. /* Number of pixels in the hsync. */
  3170. # define TV_HSYNC_END_MASK              0x1fff0000
  3171. # define TV_HSYNC_END_SHIFT             16
  3172. /* Total number of pixels minus one in the line (display and blanking). */
  3173. # define TV_HTOTAL_MASK                 0x00001fff
  3174. # define TV_HTOTAL_SHIFT                0
  3175.  
  3176. #define TV_H_CTL_2              0x68034
  3177. /* Enables the colorburst (needed for non-component color) */
  3178. # define TV_BURST_ENA                   (1 << 31)
  3179. /* Offset of the colorburst from the start of hsync, in pixels minus one. */
  3180. # define TV_HBURST_START_SHIFT          16
  3181. # define TV_HBURST_START_MASK           0x1fff0000
  3182. /* Length of the colorburst */
  3183. # define TV_HBURST_LEN_SHIFT            0
  3184. # define TV_HBURST_LEN_MASK             0x0001fff
  3185.  
  3186. #define TV_H_CTL_3              0x68038
  3187. /* End of hblank, measured in pixels minus one from start of hsync */
  3188. # define TV_HBLANK_END_SHIFT            16
  3189. # define TV_HBLANK_END_MASK             0x1fff0000
  3190. /* Start of hblank, measured in pixels minus one from start of hsync */
  3191. # define TV_HBLANK_START_SHIFT          0
  3192. # define TV_HBLANK_START_MASK           0x0001fff
  3193.  
  3194. #define TV_V_CTL_1              0x6803c
  3195. /* XXX */
  3196. # define TV_NBR_END_SHIFT               16
  3197. # define TV_NBR_END_MASK                0x07ff0000
  3198. /* XXX */
  3199. # define TV_VI_END_F1_SHIFT             8
  3200. # define TV_VI_END_F1_MASK              0x00003f00
  3201. /* XXX */
  3202. # define TV_VI_END_F2_SHIFT             0
  3203. # define TV_VI_END_F2_MASK              0x0000003f
  3204.  
  3205. #define TV_V_CTL_2              0x68040
  3206. /* Length of vsync, in half lines */
  3207. # define TV_VSYNC_LEN_MASK              0x07ff0000
  3208. # define TV_VSYNC_LEN_SHIFT             16
  3209. /* Offset of the start of vsync in field 1, measured in one less than the
  3210.  * number of half lines.
  3211.  */
  3212. # define TV_VSYNC_START_F1_MASK         0x00007f00
  3213. # define TV_VSYNC_START_F1_SHIFT        8
  3214. /*
  3215.  * Offset of the start of vsync in field 2, measured in one less than the
  3216.  * number of half lines.
  3217.  */
  3218. # define TV_VSYNC_START_F2_MASK         0x0000007f
  3219. # define TV_VSYNC_START_F2_SHIFT        0
  3220.  
  3221. #define TV_V_CTL_3              0x68044
  3222. /* Enables generation of the equalization signal */
  3223. # define TV_EQUAL_ENA                   (1 << 31)
  3224. /* Length of vsync, in half lines */
  3225. # define TV_VEQ_LEN_MASK                0x007f0000
  3226. # define TV_VEQ_LEN_SHIFT               16
  3227. /* Offset of the start of equalization in field 1, measured in one less than
  3228.  * the number of half lines.
  3229.  */
  3230. # define TV_VEQ_START_F1_MASK           0x0007f00
  3231. # define TV_VEQ_START_F1_SHIFT          8
  3232. /*
  3233.  * Offset of the start of equalization in field 2, measured in one less than
  3234.  * the number of half lines.
  3235.  */
  3236. # define TV_VEQ_START_F2_MASK           0x000007f
  3237. # define TV_VEQ_START_F2_SHIFT          0
  3238.  
  3239. #define TV_V_CTL_4              0x68048
  3240. /*
  3241.  * Offset to start of vertical colorburst, measured in one less than the
  3242.  * number of lines from vertical start.
  3243.  */
  3244. # define TV_VBURST_START_F1_MASK        0x003f0000
  3245. # define TV_VBURST_START_F1_SHIFT       16
  3246. /*
  3247.  * Offset to the end of vertical colorburst, measured in one less than the
  3248.  * number of lines from the start of NBR.
  3249.  */
  3250. # define TV_VBURST_END_F1_MASK          0x000000ff
  3251. # define TV_VBURST_END_F1_SHIFT         0
  3252.  
  3253. #define TV_V_CTL_5              0x6804c
  3254. /*
  3255.  * Offset to start of vertical colorburst, measured in one less than the
  3256.  * number of lines from vertical start.
  3257.  */
  3258. # define TV_VBURST_START_F2_MASK        0x003f0000
  3259. # define TV_VBURST_START_F2_SHIFT       16
  3260. /*
  3261.  * Offset to the end of vertical colorburst, measured in one less than the
  3262.  * number of lines from the start of NBR.
  3263.  */
  3264. # define TV_VBURST_END_F2_MASK          0x000000ff
  3265. # define TV_VBURST_END_F2_SHIFT         0
  3266.  
  3267. #define TV_V_CTL_6              0x68050
  3268. /*
  3269.  * Offset to start of vertical colorburst, measured in one less than the
  3270.  * number of lines from vertical start.
  3271.  */
  3272. # define TV_VBURST_START_F3_MASK        0x003f0000
  3273. # define TV_VBURST_START_F3_SHIFT       16
  3274. /*
  3275.  * Offset to the end of vertical colorburst, measured in one less than the
  3276.  * number of lines from the start of NBR.
  3277.  */
  3278. # define TV_VBURST_END_F3_MASK          0x000000ff
  3279. # define TV_VBURST_END_F3_SHIFT         0
  3280.  
  3281. #define TV_V_CTL_7              0x68054
  3282. /*
  3283.  * Offset to start of vertical colorburst, measured in one less than the
  3284.  * number of lines from vertical start.
  3285.  */
  3286. # define TV_VBURST_START_F4_MASK        0x003f0000
  3287. # define TV_VBURST_START_F4_SHIFT       16
  3288. /*
  3289.  * Offset to the end of vertical colorburst, measured in one less than the
  3290.  * number of lines from the start of NBR.
  3291.  */
  3292. # define TV_VBURST_END_F4_MASK          0x000000ff
  3293. # define TV_VBURST_END_F4_SHIFT         0
  3294.  
  3295. #define TV_SC_CTL_1             0x68060
  3296. /* Turns on the first subcarrier phase generation DDA */
  3297. # define TV_SC_DDA1_EN                  (1 << 31)
  3298. /* Turns on the first subcarrier phase generation DDA */
  3299. # define TV_SC_DDA2_EN                  (1 << 30)
  3300. /* Turns on the first subcarrier phase generation DDA */
  3301. # define TV_SC_DDA3_EN                  (1 << 29)
  3302. /* Sets the subcarrier DDA to reset frequency every other field */
  3303. # define TV_SC_RESET_EVERY_2            (0 << 24)
  3304. /* Sets the subcarrier DDA to reset frequency every fourth field */
  3305. # define TV_SC_RESET_EVERY_4            (1 << 24)
  3306. /* Sets the subcarrier DDA to reset frequency every eighth field */
  3307. # define TV_SC_RESET_EVERY_8            (2 << 24)
  3308. /* Sets the subcarrier DDA to never reset the frequency */
  3309. # define TV_SC_RESET_NEVER              (3 << 24)
  3310. /* Sets the peak amplitude of the colorburst.*/
  3311. # define TV_BURST_LEVEL_MASK            0x00ff0000
  3312. # define TV_BURST_LEVEL_SHIFT           16
  3313. /* Sets the increment of the first subcarrier phase generation DDA */
  3314. # define TV_SCDDA1_INC_MASK             0x00000fff
  3315. # define TV_SCDDA1_INC_SHIFT            0
  3316.  
  3317. #define TV_SC_CTL_2             0x68064
  3318. /* Sets the rollover for the second subcarrier phase generation DDA */
  3319. # define TV_SCDDA2_SIZE_MASK            0x7fff0000
  3320. # define TV_SCDDA2_SIZE_SHIFT           16
  3321. /* Sets the increent of the second subcarrier phase generation DDA */
  3322. # define TV_SCDDA2_INC_MASK             0x00007fff
  3323. # define TV_SCDDA2_INC_SHIFT            0
  3324.  
  3325. #define TV_SC_CTL_3             0x68068
  3326. /* Sets the rollover for the third subcarrier phase generation DDA */
  3327. # define TV_SCDDA3_SIZE_MASK            0x7fff0000
  3328. # define TV_SCDDA3_SIZE_SHIFT           16
  3329. /* Sets the increent of the third subcarrier phase generation DDA */
  3330. # define TV_SCDDA3_INC_MASK             0x00007fff
  3331. # define TV_SCDDA3_INC_SHIFT            0
  3332.  
  3333. #define TV_WIN_POS              0x68070
  3334. /* X coordinate of the display from the start of horizontal active */
  3335. # define TV_XPOS_MASK                   0x1fff0000
  3336. # define TV_XPOS_SHIFT                  16
  3337. /* Y coordinate of the display from the start of vertical active (NBR) */
  3338. # define TV_YPOS_MASK                   0x00000fff
  3339. # define TV_YPOS_SHIFT                  0
  3340.  
  3341. #define TV_WIN_SIZE             0x68074
  3342. /* Horizontal size of the display window, measured in pixels*/
  3343. # define TV_XSIZE_MASK                  0x1fff0000
  3344. # define TV_XSIZE_SHIFT                 16
  3345. /*
  3346.  * Vertical size of the display window, measured in pixels.
  3347.  *
  3348.  * Must be even for interlaced modes.
  3349.  */
  3350. # define TV_YSIZE_MASK                  0x00000fff
  3351. # define TV_YSIZE_SHIFT                 0
  3352.  
  3353. #define TV_FILTER_CTL_1         0x68080
  3354. /*
  3355.  * Enables automatic scaling calculation.
  3356.  *
  3357.  * If set, the rest of the registers are ignored, and the calculated values can
  3358.  * be read back from the register.
  3359.  */
  3360. # define TV_AUTO_SCALE                  (1 << 31)
  3361. /*
  3362.  * Disables the vertical filter.
  3363.  *
  3364.  * This is required on modes more than 1024 pixels wide */
  3365. # define TV_V_FILTER_BYPASS             (1 << 29)
  3366. /* Enables adaptive vertical filtering */
  3367. # define TV_VADAPT                      (1 << 28)
  3368. # define TV_VADAPT_MODE_MASK            (3 << 26)
  3369. /* Selects the least adaptive vertical filtering mode */
  3370. # define TV_VADAPT_MODE_LEAST           (0 << 26)
  3371. /* Selects the moderately adaptive vertical filtering mode */
  3372. # define TV_VADAPT_MODE_MODERATE        (1 << 26)
  3373. /* Selects the most adaptive vertical filtering mode */
  3374. # define TV_VADAPT_MODE_MOST            (3 << 26)
  3375. /*
  3376.  * Sets the horizontal scaling factor.
  3377.  *
  3378.  * This should be the fractional part of the horizontal scaling factor divided
  3379.  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
  3380.  *
  3381.  * (src width - 1) / ((oversample * dest width) - 1)
  3382.  */
  3383. # define TV_HSCALE_FRAC_MASK            0x00003fff
  3384. # define TV_HSCALE_FRAC_SHIFT           0
  3385.  
  3386. #define TV_FILTER_CTL_2         0x68084
  3387. /*
  3388.  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  3389.  *
  3390.  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
  3391.  */
  3392. # define TV_VSCALE_INT_MASK             0x00038000
  3393. # define TV_VSCALE_INT_SHIFT            15
  3394. /*
  3395.  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  3396.  *
  3397.  * \sa TV_VSCALE_INT_MASK
  3398.  */
  3399. # define TV_VSCALE_FRAC_MASK            0x00007fff
  3400. # define TV_VSCALE_FRAC_SHIFT           0
  3401.  
  3402. #define TV_FILTER_CTL_3         0x68088
  3403. /*
  3404.  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  3405.  *
  3406.  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
  3407.  *
  3408.  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  3409.  */
  3410. # define TV_VSCALE_IP_INT_MASK          0x00038000
  3411. # define TV_VSCALE_IP_INT_SHIFT         15
  3412. /*
  3413.  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  3414.  *
  3415.  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  3416.  *
  3417.  * \sa TV_VSCALE_IP_INT_MASK
  3418.  */
  3419. # define TV_VSCALE_IP_FRAC_MASK         0x00007fff
  3420. # define TV_VSCALE_IP_FRAC_SHIFT                0
  3421.  
  3422. #define TV_CC_CONTROL           0x68090
  3423. # define TV_CC_ENABLE                   (1 << 31)
  3424. /*
  3425.  * Specifies which field to send the CC data in.
  3426.  *
  3427.  * CC data is usually sent in field 0.
  3428.  */
  3429. # define TV_CC_FID_MASK                 (1 << 27)
  3430. # define TV_CC_FID_SHIFT                27
  3431. /* Sets the horizontal position of the CC data.  Usually 135. */
  3432. # define TV_CC_HOFF_MASK                0x03ff0000
  3433. # define TV_CC_HOFF_SHIFT               16
  3434. /* Sets the vertical position of the CC data.  Usually 21 */
  3435. # define TV_CC_LINE_MASK                0x0000003f
  3436. # define TV_CC_LINE_SHIFT               0
  3437.  
  3438. #define TV_CC_DATA              0x68094
  3439. # define TV_CC_RDY                      (1 << 31)
  3440. /* Second word of CC data to be transmitted. */
  3441. # define TV_CC_DATA_2_MASK              0x007f0000
  3442. # define TV_CC_DATA_2_SHIFT             16
  3443. /* First word of CC data to be transmitted. */
  3444. # define TV_CC_DATA_1_MASK              0x0000007f
  3445. # define TV_CC_DATA_1_SHIFT             0
  3446.  
  3447. #define TV_H_LUMA_0             0x68100
  3448. #define TV_H_LUMA_59            0x681ec
  3449. #define TV_H_CHROMA_0           0x68200
  3450. #define TV_H_CHROMA_59          0x682ec
  3451. #define TV_V_LUMA_0             0x68300
  3452. #define TV_V_LUMA_42            0x683a8
  3453. #define TV_V_CHROMA_0           0x68400
  3454. #define TV_V_CHROMA_42          0x684a8
  3455.  
  3456. /* Display Port */
  3457. #define DP_A                            0x64000 /* eDP */
  3458. #define DP_B                            0x64100
  3459. #define DP_C                            0x64200
  3460. #define DP_D                            0x64300
  3461.  
  3462. #define   DP_PORT_EN                    (1 << 31)
  3463. #define   DP_PIPEB_SELECT               (1 << 30)
  3464. #define   DP_PIPE_MASK                  (1 << 30)
  3465. #define   DP_PIPE_SELECT_CHV(pipe)      ((pipe) << 16)
  3466. #define   DP_PIPE_MASK_CHV              (3 << 16)
  3467.  
  3468. /* Link training mode - select a suitable mode for each stage */
  3469. #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
  3470. #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
  3471. #define   DP_LINK_TRAIN_PAT_IDLE        (2 << 28)
  3472. #define   DP_LINK_TRAIN_OFF             (3 << 28)
  3473. #define   DP_LINK_TRAIN_MASK            (3 << 28)
  3474. #define   DP_LINK_TRAIN_SHIFT           28
  3475.  
  3476. /* CPT Link training mode */
  3477. #define   DP_LINK_TRAIN_PAT_1_CPT       (0 << 8)
  3478. #define   DP_LINK_TRAIN_PAT_2_CPT       (1 << 8)
  3479. #define   DP_LINK_TRAIN_PAT_IDLE_CPT    (2 << 8)
  3480. #define   DP_LINK_TRAIN_OFF_CPT         (3 << 8)
  3481. #define   DP_LINK_TRAIN_MASK_CPT        (7 << 8)
  3482. #define   DP_LINK_TRAIN_SHIFT_CPT       8
  3483.  
  3484. /* Signal voltages. These are mostly controlled by the other end */
  3485. #define   DP_VOLTAGE_0_4                (0 << 25)
  3486. #define   DP_VOLTAGE_0_6                (1 << 25)
  3487. #define   DP_VOLTAGE_0_8                (2 << 25)
  3488. #define   DP_VOLTAGE_1_2                (3 << 25)
  3489. #define   DP_VOLTAGE_MASK               (7 << 25)
  3490. #define   DP_VOLTAGE_SHIFT              25
  3491.  
  3492. /* Signal pre-emphasis levels, like voltages, the other end tells us what
  3493.  * they want
  3494.  */
  3495. #define   DP_PRE_EMPHASIS_0             (0 << 22)
  3496. #define   DP_PRE_EMPHASIS_3_5           (1 << 22)
  3497. #define   DP_PRE_EMPHASIS_6             (2 << 22)
  3498. #define   DP_PRE_EMPHASIS_9_5           (3 << 22)
  3499. #define   DP_PRE_EMPHASIS_MASK          (7 << 22)
  3500. #define   DP_PRE_EMPHASIS_SHIFT         22
  3501.  
  3502. /* How many wires to use. I guess 3 was too hard */
  3503. #define   DP_PORT_WIDTH(width)          (((width) - 1) << 19)
  3504. #define   DP_PORT_WIDTH_MASK            (7 << 19)
  3505.  
  3506. /* Mystic DPCD version 1.1 special mode */
  3507. #define   DP_ENHANCED_FRAMING           (1 << 18)
  3508.  
  3509. /* eDP */
  3510. #define   DP_PLL_FREQ_270MHZ            (0 << 16)
  3511. #define   DP_PLL_FREQ_160MHZ            (1 << 16)
  3512. #define   DP_PLL_FREQ_MASK              (3 << 16)
  3513.  
  3514. /* locked once port is enabled */
  3515. #define   DP_PORT_REVERSAL              (1 << 15)
  3516.  
  3517. /* eDP */
  3518. #define   DP_PLL_ENABLE                 (1 << 14)
  3519.  
  3520. /* sends the clock on lane 15 of the PEG for debug */
  3521. #define   DP_CLOCK_OUTPUT_ENABLE        (1 << 13)
  3522.  
  3523. #define   DP_SCRAMBLING_DISABLE         (1 << 12)
  3524. #define   DP_SCRAMBLING_DISABLE_IRONLAKE        (1 << 7)
  3525.  
  3526. /* limit RGB values to avoid confusing TVs */
  3527. #define   DP_COLOR_RANGE_16_235         (1 << 8)
  3528.  
  3529. /* Turn on the audio link */
  3530. #define   DP_AUDIO_OUTPUT_ENABLE        (1 << 6)
  3531.  
  3532. /* vs and hs sync polarity */
  3533. #define   DP_SYNC_VS_HIGH               (1 << 4)
  3534. #define   DP_SYNC_HS_HIGH               (1 << 3)
  3535.  
  3536. /* A fantasy */
  3537. #define   DP_DETECTED                   (1 << 2)
  3538.  
  3539. /* The aux channel provides a way to talk to the
  3540.  * signal sink for DDC etc. Max packet size supported
  3541.  * is 20 bytes in each direction, hence the 5 fixed
  3542.  * data registers
  3543.  */
  3544. #define DPA_AUX_CH_CTL                  0x64010
  3545. #define DPA_AUX_CH_DATA1                0x64014
  3546. #define DPA_AUX_CH_DATA2                0x64018
  3547. #define DPA_AUX_CH_DATA3                0x6401c
  3548. #define DPA_AUX_CH_DATA4                0x64020
  3549. #define DPA_AUX_CH_DATA5                0x64024
  3550.  
  3551. #define DPB_AUX_CH_CTL                  0x64110
  3552. #define DPB_AUX_CH_DATA1                0x64114
  3553. #define DPB_AUX_CH_DATA2                0x64118
  3554. #define DPB_AUX_CH_DATA3                0x6411c
  3555. #define DPB_AUX_CH_DATA4                0x64120
  3556. #define DPB_AUX_CH_DATA5                0x64124
  3557.  
  3558. #define DPC_AUX_CH_CTL                  0x64210
  3559. #define DPC_AUX_CH_DATA1                0x64214
  3560. #define DPC_AUX_CH_DATA2                0x64218
  3561. #define DPC_AUX_CH_DATA3                0x6421c
  3562. #define DPC_AUX_CH_DATA4                0x64220
  3563. #define DPC_AUX_CH_DATA5                0x64224
  3564.  
  3565. #define DPD_AUX_CH_CTL                  0x64310
  3566. #define DPD_AUX_CH_DATA1                0x64314
  3567. #define DPD_AUX_CH_DATA2                0x64318
  3568. #define DPD_AUX_CH_DATA3                0x6431c
  3569. #define DPD_AUX_CH_DATA4                0x64320
  3570. #define DPD_AUX_CH_DATA5                0x64324
  3571.  
  3572. #define   DP_AUX_CH_CTL_SEND_BUSY           (1 << 31)
  3573. #define   DP_AUX_CH_CTL_DONE                (1 << 30)
  3574. #define   DP_AUX_CH_CTL_INTERRUPT           (1 << 29)
  3575. #define   DP_AUX_CH_CTL_TIME_OUT_ERROR      (1 << 28)
  3576. #define   DP_AUX_CH_CTL_TIME_OUT_400us      (0 << 26)
  3577. #define   DP_AUX_CH_CTL_TIME_OUT_600us      (1 << 26)
  3578. #define   DP_AUX_CH_CTL_TIME_OUT_800us      (2 << 26)
  3579. #define   DP_AUX_CH_CTL_TIME_OUT_1600us     (3 << 26)
  3580. #define   DP_AUX_CH_CTL_TIME_OUT_MASK       (3 << 26)
  3581. #define   DP_AUX_CH_CTL_RECEIVE_ERROR       (1 << 25)
  3582. #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
  3583. #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
  3584. #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
  3585. #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
  3586. #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT     (1 << 15)
  3587. #define   DP_AUX_CH_CTL_MANCHESTER_TEST     (1 << 14)
  3588. #define   DP_AUX_CH_CTL_SYNC_TEST           (1 << 13)
  3589. #define   DP_AUX_CH_CTL_DEGLITCH_TEST       (1 << 12)
  3590. #define   DP_AUX_CH_CTL_PRECHARGE_TEST      (1 << 11)
  3591. #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
  3592. #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
  3593.  
  3594. /*
  3595.  * Computing GMCH M and N values for the Display Port link
  3596.  *
  3597.  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
  3598.  *
  3599.  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
  3600.  *
  3601.  * The GMCH value is used internally
  3602.  *
  3603.  * bytes_per_pixel is the number of bytes coming out of the plane,
  3604.  * which is after the LUTs, so we want the bytes for our color format.
  3605.  * For our current usage, this is always 3, one byte for R, G and B.
  3606.  */
  3607. #define _PIPEA_DATA_M_G4X       0x70050
  3608. #define _PIPEB_DATA_M_G4X       0x71050
  3609.  
  3610. /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
  3611. #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
  3612. #define  TU_SIZE_SHIFT          25
  3613. #define  TU_SIZE_MASK           (0x3f << 25)
  3614.  
  3615. #define  DATA_LINK_M_N_MASK     (0xffffff)
  3616. #define  DATA_LINK_N_MAX        (0x800000)
  3617.  
  3618. #define _PIPEA_DATA_N_G4X       0x70054
  3619. #define _PIPEB_DATA_N_G4X       0x71054
  3620. #define   PIPE_GMCH_DATA_N_MASK                 (0xffffff)
  3621.  
  3622. /*
  3623.  * Computing Link M and N values for the Display Port link
  3624.  *
  3625.  * Link M / N = pixel_clock / ls_clk
  3626.  *
  3627.  * (the DP spec calls pixel_clock the 'strm_clk')
  3628.  *
  3629.  * The Link value is transmitted in the Main Stream
  3630.  * Attributes and VB-ID.
  3631.  */
  3632.  
  3633. #define _PIPEA_LINK_M_G4X       0x70060
  3634. #define _PIPEB_LINK_M_G4X       0x71060
  3635. #define   PIPEA_DP_LINK_M_MASK                  (0xffffff)
  3636.  
  3637. #define _PIPEA_LINK_N_G4X       0x70064
  3638. #define _PIPEB_LINK_N_G4X       0x71064
  3639. #define   PIPEA_DP_LINK_N_MASK                  (0xffffff)
  3640.  
  3641. #define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
  3642. #define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
  3643. #define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
  3644. #define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
  3645.  
  3646. /* Display & cursor control */
  3647.  
  3648. /* Pipe A */
  3649. #define _PIPEADSL               0x70000
  3650. #define   DSL_LINEMASK_GEN2     0x00000fff
  3651. #define   DSL_LINEMASK_GEN3     0x00001fff
  3652. #define _PIPEACONF              0x70008
  3653. #define   PIPECONF_ENABLE       (1<<31)
  3654. #define   PIPECONF_DISABLE      0
  3655. #define   PIPECONF_DOUBLE_WIDE  (1<<30)
  3656. #define   I965_PIPECONF_ACTIVE  (1<<30)
  3657. #define   PIPECONF_DSI_PLL_LOCKED       (1<<29) /* vlv & pipe A only */
  3658. #define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)
  3659. #define   PIPECONF_SINGLE_WIDE  0
  3660. #define   PIPECONF_PIPE_UNLOCKED 0
  3661. #define   PIPECONF_PIPE_LOCKED  (1<<25)
  3662. #define   PIPECONF_PALETTE      0
  3663. #define   PIPECONF_GAMMA                (1<<24)
  3664. #define   PIPECONF_FORCE_BORDER (1<<25)
  3665. #define   PIPECONF_INTERLACE_MASK       (7 << 21)
  3666. #define   PIPECONF_INTERLACE_MASK_HSW   (3 << 21)
  3667. /* Note that pre-gen3 does not support interlaced display directly. Panel
  3668.  * fitting must be disabled on pre-ilk for interlaced. */
  3669. #define   PIPECONF_PROGRESSIVE  (0 << 21)
  3670. #define   PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
  3671. #define   PIPECONF_INTERLACE_W_SYNC_SHIFT       (5 << 21) /* gen4 only */
  3672. #define   PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
  3673. #define   PIPECONF_INTERLACE_FIELD_0_ONLY       (7 << 21) /* gen3 only */
  3674. /* Ironlake and later have a complete new set of values for interlaced. PFIT
  3675.  * means panel fitter required, PF means progressive fetch, DBL means power
  3676.  * saving pixel doubling. */
  3677. #define   PIPECONF_PFIT_PF_INTERLACED_ILK       (1 << 21)
  3678. #define   PIPECONF_INTERLACED_ILK               (3 << 21)
  3679. #define   PIPECONF_INTERLACED_DBL_ILK           (4 << 21) /* ilk/snb only */
  3680. #define   PIPECONF_PFIT_PF_INTERLACED_DBL_ILK   (5 << 21) /* ilk/snb only */
  3681. #define   PIPECONF_INTERLACE_MODE_MASK          (7 << 21)
  3682. #define   PIPECONF_EDP_RR_MODE_SWITCH           (1 << 20)
  3683. #define   PIPECONF_CXSR_DOWNCLOCK       (1<<16)
  3684. #define   PIPECONF_COLOR_RANGE_SELECT   (1 << 13)
  3685. #define   PIPECONF_BPC_MASK     (0x7 << 5)
  3686. #define   PIPECONF_8BPC         (0<<5)
  3687. #define   PIPECONF_10BPC        (1<<5)
  3688. #define   PIPECONF_6BPC         (2<<5)
  3689. #define   PIPECONF_12BPC        (3<<5)
  3690. #define   PIPECONF_DITHER_EN    (1<<4)
  3691. #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
  3692. #define   PIPECONF_DITHER_TYPE_SP (0<<2)
  3693. #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
  3694. #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
  3695. #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
  3696. #define _PIPEASTAT              0x70024
  3697. #define   PIPE_FIFO_UNDERRUN_STATUS             (1UL<<31)
  3698. #define   SPRITE1_FLIP_DONE_INT_EN_VLV          (1UL<<30)
  3699. #define   PIPE_CRC_ERROR_ENABLE                 (1UL<<29)
  3700. #define   PIPE_CRC_DONE_ENABLE                  (1UL<<28)
  3701. #define   PERF_COUNTER2_INTERRUPT_EN            (1UL<<27)
  3702. #define   PIPE_GMBUS_EVENT_ENABLE               (1UL<<27)
  3703. #define   PLANE_FLIP_DONE_INT_EN_VLV            (1UL<<26)
  3704. #define   PIPE_HOTPLUG_INTERRUPT_ENABLE         (1UL<<26)
  3705. #define   PIPE_VSYNC_INTERRUPT_ENABLE           (1UL<<25)
  3706. #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE      (1UL<<24)
  3707. #define   PIPE_DPST_EVENT_ENABLE                (1UL<<23)
  3708. #define   SPRITE0_FLIP_DONE_INT_EN_VLV          (1UL<<22)
  3709. #define   PIPE_LEGACY_BLC_EVENT_ENABLE          (1UL<<22)
  3710. #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE       (1UL<<21)
  3711. #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE      (1UL<<20)
  3712. #define   PIPE_B_PSR_INTERRUPT_ENABLE_VLV       (1UL<<19)
  3713. #define   PERF_COUNTER_INTERRUPT_EN             (1UL<<19)
  3714. #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE      (1UL<<18) /* pre-965 */
  3715. #define   PIPE_START_VBLANK_INTERRUPT_ENABLE    (1UL<<18) /* 965 or later */
  3716. #define   PIPE_FRAMESTART_INTERRUPT_ENABLE      (1UL<<17)
  3717. #define   PIPE_VBLANK_INTERRUPT_ENABLE          (1UL<<17)
  3718. #define   PIPEA_HBLANK_INT_EN_VLV               (1UL<<16)
  3719. #define   PIPE_OVERLAY_UPDATED_ENABLE           (1UL<<16)
  3720. #define   SPRITE1_FLIP_DONE_INT_STATUS_VLV      (1UL<<15)
  3721. #define   SPRITE0_FLIP_DONE_INT_STATUS_VLV      (1UL<<14)
  3722. #define   PIPE_CRC_ERROR_INTERRUPT_STATUS       (1UL<<13)
  3723. #define   PIPE_CRC_DONE_INTERRUPT_STATUS        (1UL<<12)
  3724. #define   PERF_COUNTER2_INTERRUPT_STATUS        (1UL<<11)
  3725. #define   PIPE_GMBUS_INTERRUPT_STATUS           (1UL<<11)
  3726. #define   PLANE_FLIP_DONE_INT_STATUS_VLV        (1UL<<10)
  3727. #define   PIPE_HOTPLUG_INTERRUPT_STATUS         (1UL<<10)
  3728. #define   PIPE_VSYNC_INTERRUPT_STATUS           (1UL<<9)
  3729. #define   PIPE_DISPLAY_LINE_COMPARE_STATUS      (1UL<<8)
  3730. #define   PIPE_DPST_EVENT_STATUS                (1UL<<7)
  3731. #define   PIPE_LEGACY_BLC_EVENT_STATUS          (1UL<<6)
  3732. #define   PIPE_A_PSR_STATUS_VLV                 (1UL<<6)
  3733. #define   PIPE_LEGACY_BLC_EVENT_STATUS          (1UL<<6)
  3734. #define   PIPE_ODD_FIELD_INTERRUPT_STATUS       (1UL<<5)
  3735. #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS      (1UL<<4)
  3736. #define   PIPE_B_PSR_STATUS_VLV                 (1UL<<3)
  3737. #define   PERF_COUNTER_INTERRUPT_STATUS         (1UL<<3)
  3738. #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS      (1UL<<2) /* pre-965 */
  3739. #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL<<2) /* 965 or later */
  3740. #define   PIPE_FRAMESTART_INTERRUPT_STATUS      (1UL<<1)
  3741. #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL<<1)
  3742. #define   PIPE_HBLANK_INT_STATUS                (1UL<<0)
  3743. #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL<<0)
  3744.  
  3745. #define PIPESTAT_INT_ENABLE_MASK                0x7fff0000
  3746. #define PIPESTAT_INT_STATUS_MASK                0x0000ffff
  3747.  
  3748. #define PIPE_A_OFFSET   0x70000
  3749. #define PIPE_B_OFFSET   0x71000
  3750. #define PIPE_C_OFFSET   0x72000
  3751. #define CHV_PIPE_C_OFFSET       0x74000
  3752. /*
  3753.  * There's actually no pipe EDP. Some pipe registers have
  3754.  * simply shifted from the pipe to the transcoder, while
  3755.  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
  3756.  * to access such registers in transcoder EDP.
  3757.  */
  3758. #define PIPE_EDP_OFFSET 0x7f000
  3759.  
  3760. #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
  3761.         dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
  3762.         dev_priv->info.display_mmio_offset)
  3763.  
  3764. #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
  3765. #define PIPEDSL(pipe)  _PIPE2(pipe, _PIPEADSL)
  3766. #define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
  3767. #define PIPEFRAMEPIXEL(pipe)  _PIPE2(pipe, _PIPEAFRAMEPIXEL)
  3768. #define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
  3769.  
  3770. #define _PIPE_MISC_A                    0x70030
  3771. #define _PIPE_MISC_B                    0x71030
  3772. #define   PIPEMISC_DITHER_BPC_MASK      (7<<5)
  3773. #define   PIPEMISC_DITHER_8_BPC         (0<<5)
  3774. #define   PIPEMISC_DITHER_10_BPC        (1<<5)
  3775. #define   PIPEMISC_DITHER_6_BPC         (2<<5)
  3776. #define   PIPEMISC_DITHER_12_BPC        (3<<5)
  3777. #define   PIPEMISC_DITHER_ENABLE        (1<<4)
  3778. #define   PIPEMISC_DITHER_TYPE_MASK     (3<<2)
  3779. #define   PIPEMISC_DITHER_TYPE_SP       (0<<2)
  3780. #define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
  3781.  
  3782. #define VLV_DPFLIPSTAT                          (VLV_DISPLAY_BASE + 0x70028)
  3783. #define   PIPEB_LINE_COMPARE_INT_EN             (1<<29)
  3784. #define   PIPEB_HLINE_INT_EN                    (1<<28)
  3785. #define   PIPEB_VBLANK_INT_EN                   (1<<27)
  3786. #define   SPRITED_FLIP_DONE_INT_EN              (1<<26)
  3787. #define   SPRITEC_FLIP_DONE_INT_EN              (1<<25)
  3788. #define   PLANEB_FLIP_DONE_INT_EN               (1<<24)
  3789. #define   PIPE_PSR_INT_EN                       (1<<22)
  3790. #define   PIPEA_LINE_COMPARE_INT_EN             (1<<21)
  3791. #define   PIPEA_HLINE_INT_EN                    (1<<20)
  3792. #define   PIPEA_VBLANK_INT_EN                   (1<<19)
  3793. #define   SPRITEB_FLIP_DONE_INT_EN              (1<<18)
  3794. #define   SPRITEA_FLIP_DONE_INT_EN              (1<<17)
  3795. #define   PLANEA_FLIPDONE_INT_EN                (1<<16)
  3796. #define   PIPEC_LINE_COMPARE_INT_EN             (1<<13)
  3797. #define   PIPEC_HLINE_INT_EN                    (1<<12)
  3798. #define   PIPEC_VBLANK_INT_EN                   (1<<11)
  3799. #define   SPRITEF_FLIPDONE_INT_EN               (1<<10)
  3800. #define   SPRITEE_FLIPDONE_INT_EN               (1<<9)
  3801. #define   PLANEC_FLIPDONE_INT_EN                (1<<8)
  3802.  
  3803. #define DPINVGTT                                (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
  3804. #define   SPRITEF_INVALID_GTT_INT_EN            (1<<27)
  3805. #define   SPRITEE_INVALID_GTT_INT_EN            (1<<26)
  3806. #define   PLANEC_INVALID_GTT_INT_EN             (1<<25)
  3807. #define   CURSORC_INVALID_GTT_INT_EN            (1<<24)
  3808. #define   CURSORB_INVALID_GTT_INT_EN            (1<<23)
  3809. #define   CURSORA_INVALID_GTT_INT_EN            (1<<22)
  3810. #define   SPRITED_INVALID_GTT_INT_EN            (1<<21)
  3811. #define   SPRITEC_INVALID_GTT_INT_EN            (1<<20)
  3812. #define   PLANEB_INVALID_GTT_INT_EN             (1<<19)
  3813. #define   SPRITEB_INVALID_GTT_INT_EN            (1<<18)
  3814. #define   SPRITEA_INVALID_GTT_INT_EN            (1<<17)
  3815. #define   PLANEA_INVALID_GTT_INT_EN             (1<<16)
  3816. #define   DPINVGTT_EN_MASK                      0xff0000
  3817. #define   DPINVGTT_EN_MASK_CHV                  0xfff0000
  3818. #define   SPRITEF_INVALID_GTT_STATUS            (1<<11)
  3819. #define   SPRITEE_INVALID_GTT_STATUS            (1<<10)
  3820. #define   PLANEC_INVALID_GTT_STATUS             (1<<9)
  3821. #define   CURSORC_INVALID_GTT_STATUS            (1<<8)
  3822. #define   CURSORB_INVALID_GTT_STATUS            (1<<7)
  3823. #define   CURSORA_INVALID_GTT_STATUS            (1<<6)
  3824. #define   SPRITED_INVALID_GTT_STATUS            (1<<5)
  3825. #define   SPRITEC_INVALID_GTT_STATUS            (1<<4)
  3826. #define   PLANEB_INVALID_GTT_STATUS             (1<<3)
  3827. #define   SPRITEB_INVALID_GTT_STATUS            (1<<2)
  3828. #define   SPRITEA_INVALID_GTT_STATUS            (1<<1)
  3829. #define   PLANEA_INVALID_GTT_STATUS             (1<<0)
  3830. #define   DPINVGTT_STATUS_MASK                  0xff
  3831. #define   DPINVGTT_STATUS_MASK_CHV              0xfff
  3832.  
  3833. #define DSPARB                  0x70030
  3834. #define   DSPARB_CSTART_MASK    (0x7f << 7)
  3835. #define   DSPARB_CSTART_SHIFT   7
  3836. #define   DSPARB_BSTART_MASK    (0x7f)
  3837. #define   DSPARB_BSTART_SHIFT   0
  3838. #define   DSPARB_BEND_SHIFT     9 /* on 855 */
  3839. #define   DSPARB_AEND_SHIFT     0
  3840.  
  3841. #define DSPFW1                  (dev_priv->info.display_mmio_offset + 0x70034)
  3842. #define   DSPFW_SR_SHIFT        23
  3843. #define   DSPFW_SR_MASK         (0x1ff<<23)
  3844. #define   DSPFW_CURSORB_SHIFT   16
  3845. #define   DSPFW_CURSORB_MASK    (0x3f<<16)
  3846. #define   DSPFW_PLANEB_SHIFT    8
  3847. #define   DSPFW_PLANEB_MASK     (0x7f<<8)
  3848. #define   DSPFW_PLANEA_MASK     (0x7f)
  3849. #define DSPFW2                  (dev_priv->info.display_mmio_offset + 0x70038)
  3850. #define   DSPFW_CURSORA_MASK    0x00003f00
  3851. #define   DSPFW_CURSORA_SHIFT   8
  3852. #define   DSPFW_PLANEC_MASK     (0x7f)
  3853. #define DSPFW3                  (dev_priv->info.display_mmio_offset + 0x7003c)
  3854. #define   DSPFW_HPLL_SR_EN      (1<<31)
  3855. #define   DSPFW_CURSOR_SR_SHIFT 24
  3856. #define   PINEVIEW_SELF_REFRESH_EN      (1<<30)
  3857. #define   DSPFW_CURSOR_SR_MASK          (0x3f<<24)
  3858. #define   DSPFW_HPLL_CURSOR_SHIFT       16
  3859. #define   DSPFW_HPLL_CURSOR_MASK        (0x3f<<16)
  3860. #define   DSPFW_HPLL_SR_MASK            (0x1ff)
  3861. #define DSPFW4                  (dev_priv->info.display_mmio_offset + 0x70070)
  3862. #define DSPFW7                  (dev_priv->info.display_mmio_offset + 0x7007c)
  3863.  
  3864. /* drain latency register values*/
  3865. #define DRAIN_LATENCY_PRECISION_32      32
  3866. #define DRAIN_LATENCY_PRECISION_64      64
  3867. #define VLV_DDL1                        (VLV_DISPLAY_BASE + 0x70050)
  3868. #define DDL_CURSORA_PRECISION_64        (1<<31)
  3869. #define DDL_CURSORA_PRECISION_32        (0<<31)
  3870. #define DDL_CURSORA_SHIFT               24
  3871. #define DDL_SPRITEB_PRECISION_64        (1<<23)
  3872. #define DDL_SPRITEB_PRECISION_32        (0<<23)
  3873. #define DDL_SPRITEB_SHIFT               16
  3874. #define DDL_SPRITEA_PRECISION_64        (1<<15)
  3875. #define DDL_SPRITEA_PRECISION_32        (0<<15)
  3876. #define DDL_SPRITEA_SHIFT               8
  3877. #define DDL_PLANEA_PRECISION_64         (1<<7)
  3878. #define DDL_PLANEA_PRECISION_32         (0<<7)
  3879. #define DDL_PLANEA_SHIFT                0
  3880.  
  3881. #define VLV_DDL2                        (VLV_DISPLAY_BASE + 0x70054)
  3882. #define DDL_CURSORB_PRECISION_64        (1<<31)
  3883. #define DDL_CURSORB_PRECISION_32        (0<<31)
  3884. #define DDL_CURSORB_SHIFT               24
  3885. #define DDL_SPRITED_PRECISION_64        (1<<23)
  3886. #define DDL_SPRITED_PRECISION_32        (0<<23)
  3887. #define DDL_SPRITED_SHIFT               16
  3888. #define DDL_SPRITEC_PRECISION_64        (1<<15)
  3889. #define DDL_SPRITEC_PRECISION_32        (0<<15)
  3890. #define DDL_SPRITEC_SHIFT               8
  3891. #define DDL_PLANEB_PRECISION_64         (1<<7)
  3892. #define DDL_PLANEB_PRECISION_32         (0<<7)
  3893. #define DDL_PLANEB_SHIFT                0
  3894.  
  3895. #define VLV_DDL3                        (VLV_DISPLAY_BASE + 0x70058)
  3896. #define DDL_CURSORC_PRECISION_64        (1<<31)
  3897. #define DDL_CURSORC_PRECISION_32        (0<<31)
  3898. #define DDL_CURSORC_SHIFT               24
  3899. #define DDL_SPRITEF_PRECISION_64        (1<<23)
  3900. #define DDL_SPRITEF_PRECISION_32        (0<<23)
  3901. #define DDL_SPRITEF_SHIFT               16
  3902. #define DDL_SPRITEE_PRECISION_64        (1<<15)
  3903. #define DDL_SPRITEE_PRECISION_32        (0<<15)
  3904. #define DDL_SPRITEE_SHIFT               8
  3905. #define DDL_PLANEC_PRECISION_64         (1<<7)
  3906. #define DDL_PLANEC_PRECISION_32         (0<<7)
  3907. #define DDL_PLANEC_SHIFT                0
  3908.  
  3909. /* FIFO watermark sizes etc */
  3910. #define G4X_FIFO_LINE_SIZE      64
  3911. #define I915_FIFO_LINE_SIZE     64
  3912. #define I830_FIFO_LINE_SIZE     32
  3913.  
  3914. #define VALLEYVIEW_FIFO_SIZE    255
  3915. #define G4X_FIFO_SIZE           127
  3916. #define I965_FIFO_SIZE          512
  3917. #define I945_FIFO_SIZE          127
  3918. #define I915_FIFO_SIZE          95
  3919. #define I855GM_FIFO_SIZE        127 /* In cachelines */
  3920. #define I830_FIFO_SIZE          95
  3921.  
  3922. #define VALLEYVIEW_MAX_WM       0xff
  3923. #define G4X_MAX_WM              0x3f
  3924. #define I915_MAX_WM             0x3f
  3925.  
  3926. #define PINEVIEW_DISPLAY_FIFO   512 /* in 64byte unit */
  3927. #define PINEVIEW_FIFO_LINE_SIZE 64
  3928. #define PINEVIEW_MAX_WM         0x1ff
  3929. #define PINEVIEW_DFT_WM         0x3f
  3930. #define PINEVIEW_DFT_HPLLOFF_WM 0
  3931. #define PINEVIEW_GUARD_WM               10
  3932. #define PINEVIEW_CURSOR_FIFO            64
  3933. #define PINEVIEW_CURSOR_MAX_WM  0x3f
  3934. #define PINEVIEW_CURSOR_DFT_WM  0
  3935. #define PINEVIEW_CURSOR_GUARD_WM        5
  3936.  
  3937. #define VALLEYVIEW_CURSOR_MAX_WM 64
  3938. #define I965_CURSOR_FIFO        64
  3939. #define I965_CURSOR_MAX_WM      32
  3940. #define I965_CURSOR_DFT_WM      8
  3941.  
  3942. /* define the Watermark register on Ironlake */
  3943. #define WM0_PIPEA_ILK           0x45100
  3944. #define  WM0_PIPE_PLANE_MASK    (0xffff<<16)
  3945. #define  WM0_PIPE_PLANE_SHIFT   16
  3946. #define  WM0_PIPE_SPRITE_MASK   (0xff<<8)
  3947. #define  WM0_PIPE_SPRITE_SHIFT  8
  3948. #define  WM0_PIPE_CURSOR_MASK   (0xff)
  3949.  
  3950. #define WM0_PIPEB_ILK           0x45104
  3951. #define WM0_PIPEC_IVB           0x45200
  3952. #define WM1_LP_ILK              0x45108
  3953. #define  WM1_LP_SR_EN           (1<<31)
  3954. #define  WM1_LP_LATENCY_SHIFT   24
  3955. #define  WM1_LP_LATENCY_MASK    (0x7f<<24)
  3956. #define  WM1_LP_FBC_MASK        (0xf<<20)
  3957. #define  WM1_LP_FBC_SHIFT       20
  3958. #define  WM1_LP_FBC_SHIFT_BDW   19
  3959. #define  WM1_LP_SR_MASK         (0x7ff<<8)
  3960. #define  WM1_LP_SR_SHIFT        8
  3961. #define  WM1_LP_CURSOR_MASK     (0xff)
  3962. #define WM2_LP_ILK              0x4510c
  3963. #define  WM2_LP_EN              (1<<31)
  3964. #define WM3_LP_ILK              0x45110
  3965. #define  WM3_LP_EN              (1<<31)
  3966. #define WM1S_LP_ILK             0x45120
  3967. #define WM2S_LP_IVB             0x45124
  3968. #define WM3S_LP_IVB             0x45128
  3969. #define  WM1S_LP_EN             (1<<31)
  3970.  
  3971. #define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
  3972.         (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
  3973.          ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
  3974.  
  3975. /* Memory latency timer register */
  3976. #define MLTR_ILK                0x11222
  3977. #define  MLTR_WM1_SHIFT         0
  3978. #define  MLTR_WM2_SHIFT         8
  3979. /* the unit of memory self-refresh latency time is 0.5us */
  3980. #define  ILK_SRLT_MASK          0x3f
  3981.  
  3982.  
  3983. /* the address where we get all kinds of latency value */
  3984. #define SSKPD                   0x5d10
  3985. #define SSKPD_WM_MASK           0x3f
  3986. #define SSKPD_WM0_SHIFT         0
  3987. #define SSKPD_WM1_SHIFT         8
  3988. #define SSKPD_WM2_SHIFT         16
  3989. #define SSKPD_WM3_SHIFT         24
  3990.  
  3991. /*
  3992.  * The two pipe frame counter registers are not synchronized, so
  3993.  * reading a stable value is somewhat tricky. The following code
  3994.  * should work:
  3995.  *
  3996.  *  do {
  3997.  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  3998.  *             PIPE_FRAME_HIGH_SHIFT;
  3999.  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
  4000.  *             PIPE_FRAME_LOW_SHIFT);
  4001.  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  4002.  *             PIPE_FRAME_HIGH_SHIFT);
  4003.  *  } while (high1 != high2);
  4004.  *  frame = (high1 << 8) | low1;
  4005.  */
  4006. #define _PIPEAFRAMEHIGH          0x70040
  4007. #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
  4008. #define   PIPE_FRAME_HIGH_SHIFT   0
  4009. #define _PIPEAFRAMEPIXEL         0x70044
  4010. #define   PIPE_FRAME_LOW_MASK     0xff000000
  4011. #define   PIPE_FRAME_LOW_SHIFT    24
  4012. #define   PIPE_PIXEL_MASK         0x00ffffff
  4013. #define   PIPE_PIXEL_SHIFT        0
  4014. /* GM45+ just has to be different */
  4015. #define _PIPEA_FRMCOUNT_GM45    0x70040
  4016. #define _PIPEA_FLIPCOUNT_GM45   0x70044
  4017. #define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45)
  4018. #define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45)
  4019.  
  4020. /* Cursor A & B regs */
  4021. #define _CURACNTR               0x70080
  4022. /* Old style CUR*CNTR flags (desktop 8xx) */
  4023. #define   CURSOR_ENABLE         0x80000000
  4024. #define   CURSOR_GAMMA_ENABLE   0x40000000
  4025. #define   CURSOR_STRIDE_MASK    0x30000000
  4026. #define   CURSOR_PIPE_CSC_ENABLE (1<<24)
  4027. #define   CURSOR_FORMAT_SHIFT   24
  4028. #define   CURSOR_FORMAT_MASK    (0x07 << CURSOR_FORMAT_SHIFT)
  4029. #define   CURSOR_FORMAT_2C      (0x00 << CURSOR_FORMAT_SHIFT)
  4030. #define   CURSOR_FORMAT_3C      (0x01 << CURSOR_FORMAT_SHIFT)
  4031. #define   CURSOR_FORMAT_4C      (0x02 << CURSOR_FORMAT_SHIFT)
  4032. #define   CURSOR_FORMAT_ARGB    (0x04 << CURSOR_FORMAT_SHIFT)
  4033. #define   CURSOR_FORMAT_XRGB    (0x05 << CURSOR_FORMAT_SHIFT)
  4034. /* New style CUR*CNTR flags */
  4035. #define   CURSOR_MODE           0x27
  4036. #define   CURSOR_MODE_DISABLE   0x00
  4037. #define   CURSOR_MODE_128_32B_AX 0x02
  4038. #define   CURSOR_MODE_256_32B_AX 0x03
  4039. #define   CURSOR_MODE_64_32B_AX 0x07
  4040. #define   CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
  4041. #define   CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
  4042. #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
  4043. #define   MCURSOR_PIPE_SELECT   (1 << 28)
  4044. #define   MCURSOR_PIPE_A        0x00
  4045. #define   MCURSOR_PIPE_B        (1 << 28)
  4046. #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
  4047. #define   CURSOR_TRICKLE_FEED_DISABLE   (1 << 14)
  4048. #define _CURABASE               0x70084
  4049. #define _CURAPOS                0x70088
  4050. #define   CURSOR_POS_MASK       0x007FF
  4051. #define   CURSOR_POS_SIGN       0x8000
  4052. #define   CURSOR_X_SHIFT        0
  4053. #define   CURSOR_Y_SHIFT        16
  4054. #define CURSIZE                 0x700a0
  4055. #define _CURBCNTR               0x700c0
  4056. #define _CURBBASE               0x700c4
  4057. #define _CURBPOS                0x700c8
  4058.  
  4059. #define _CURBCNTR_IVB           0x71080
  4060. #define _CURBBASE_IVB           0x71084
  4061. #define _CURBPOS_IVB            0x71088
  4062.  
  4063. #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
  4064.         dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
  4065.         dev_priv->info.display_mmio_offset)
  4066.  
  4067. #define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
  4068. #define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
  4069. #define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
  4070.  
  4071. #define CURSOR_A_OFFSET 0x70080
  4072. #define CURSOR_B_OFFSET 0x700c0
  4073. #define CHV_CURSOR_C_OFFSET 0x700e0
  4074. #define IVB_CURSOR_B_OFFSET 0x71080
  4075. #define IVB_CURSOR_C_OFFSET 0x72080
  4076.  
  4077. /* Display A control */
  4078. #define _DSPACNTR                               0x70180
  4079. #define   DISPLAY_PLANE_ENABLE                  (1<<31)
  4080. #define   DISPLAY_PLANE_DISABLE                 0
  4081. #define   DISPPLANE_GAMMA_ENABLE                (1<<30)
  4082. #define   DISPPLANE_GAMMA_DISABLE               0
  4083. #define   DISPPLANE_PIXFORMAT_MASK              (0xf<<26)
  4084. #define   DISPPLANE_YUV422                      (0x0<<26)
  4085. #define   DISPPLANE_8BPP                        (0x2<<26)
  4086. #define   DISPPLANE_BGRA555                     (0x3<<26)
  4087. #define   DISPPLANE_BGRX555                     (0x4<<26)
  4088. #define   DISPPLANE_BGRX565                     (0x5<<26)
  4089. #define   DISPPLANE_BGRX888                     (0x6<<26)
  4090. #define   DISPPLANE_BGRA888                     (0x7<<26)
  4091. #define   DISPPLANE_RGBX101010                  (0x8<<26)
  4092. #define   DISPPLANE_RGBA101010                  (0x9<<26)
  4093. #define   DISPPLANE_BGRX101010                  (0xa<<26)
  4094. #define   DISPPLANE_RGBX161616                  (0xc<<26)
  4095. #define   DISPPLANE_RGBX888                     (0xe<<26)
  4096. #define   DISPPLANE_RGBA888                     (0xf<<26)
  4097. #define   DISPPLANE_STEREO_ENABLE               (1<<25)
  4098. #define   DISPPLANE_STEREO_DISABLE              0
  4099. #define   DISPPLANE_PIPE_CSC_ENABLE             (1<<24)
  4100. #define   DISPPLANE_SEL_PIPE_SHIFT              24
  4101. #define   DISPPLANE_SEL_PIPE_MASK               (3<<DISPPLANE_SEL_PIPE_SHIFT)
  4102. #define   DISPPLANE_SEL_PIPE_A                  0
  4103. #define   DISPPLANE_SEL_PIPE_B                  (1<<DISPPLANE_SEL_PIPE_SHIFT)
  4104. #define   DISPPLANE_SRC_KEY_ENABLE              (1<<22)
  4105. #define   DISPPLANE_SRC_KEY_DISABLE             0
  4106. #define   DISPPLANE_LINE_DOUBLE                 (1<<20)
  4107. #define   DISPPLANE_NO_LINE_DOUBLE              0
  4108. #define   DISPPLANE_STEREO_POLARITY_FIRST       0
  4109. #define   DISPPLANE_STEREO_POLARITY_SECOND      (1<<18)
  4110. #define   DISPPLANE_TRICKLE_FEED_DISABLE        (1<<14) /* Ironlake */
  4111. #define   DISPPLANE_TILED                       (1<<10)
  4112. #define _DSPAADDR                               0x70184
  4113. #define _DSPASTRIDE                             0x70188
  4114. #define _DSPAPOS                                0x7018C /* reserved */
  4115. #define _DSPASIZE                               0x70190
  4116. #define _DSPASURF                               0x7019C /* 965+ only */
  4117. #define _DSPATILEOFF                            0x701A4 /* 965+ only */
  4118. #define _DSPAOFFSET                             0x701A4 /* HSW */
  4119. #define _DSPASURFLIVE                           0x701AC
  4120.  
  4121. #define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
  4122. #define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
  4123. #define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
  4124. #define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
  4125. #define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
  4126. #define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
  4127. #define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
  4128. #define DSPLINOFF(plane) DSPADDR(plane)
  4129. #define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
  4130. #define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
  4131.  
  4132. /* Display/Sprite base address macros */
  4133. #define DISP_BASEADDR_MASK      (0xfffff000)
  4134. #define I915_LO_DISPBASE(val)   (val & ~DISP_BASEADDR_MASK)
  4135. #define I915_HI_DISPBASE(val)   (val & DISP_BASEADDR_MASK)
  4136.  
  4137. /* VBIOS flags */
  4138. #define SWF00                   (dev_priv->info.display_mmio_offset + 0x71410)
  4139. #define SWF01                   (dev_priv->info.display_mmio_offset + 0x71414)
  4140. #define SWF02                   (dev_priv->info.display_mmio_offset + 0x71418)
  4141. #define SWF03                   (dev_priv->info.display_mmio_offset + 0x7141c)
  4142. #define SWF04                   (dev_priv->info.display_mmio_offset + 0x71420)
  4143. #define SWF05                   (dev_priv->info.display_mmio_offset + 0x71424)
  4144. #define SWF06                   (dev_priv->info.display_mmio_offset + 0x71428)
  4145. #define SWF10                   (dev_priv->info.display_mmio_offset + 0x70410)
  4146. #define SWF11                   (dev_priv->info.display_mmio_offset + 0x70414)
  4147. #define SWF14                   (dev_priv->info.display_mmio_offset + 0x71420)
  4148. #define SWF30                   (dev_priv->info.display_mmio_offset + 0x72414)
  4149. #define SWF31                   (dev_priv->info.display_mmio_offset + 0x72418)
  4150. #define SWF32                   (dev_priv->info.display_mmio_offset + 0x7241c)
  4151.  
  4152. /* Pipe B */
  4153. #define _PIPEBDSL               (dev_priv->info.display_mmio_offset + 0x71000)
  4154. #define _PIPEBCONF              (dev_priv->info.display_mmio_offset + 0x71008)
  4155. #define _PIPEBSTAT              (dev_priv->info.display_mmio_offset + 0x71024)
  4156. #define _PIPEBFRAMEHIGH         0x71040
  4157. #define _PIPEBFRAMEPIXEL        0x71044
  4158. #define _PIPEB_FRMCOUNT_GM45    (dev_priv->info.display_mmio_offset + 0x71040)
  4159. #define _PIPEB_FLIPCOUNT_GM45   (dev_priv->info.display_mmio_offset + 0x71044)
  4160.  
  4161.  
  4162. /* Display B control */
  4163. #define _DSPBCNTR               (dev_priv->info.display_mmio_offset + 0x71180)
  4164. #define   DISPPLANE_ALPHA_TRANS_ENABLE          (1<<15)
  4165. #define   DISPPLANE_ALPHA_TRANS_DISABLE         0
  4166. #define   DISPPLANE_SPRITE_ABOVE_DISPLAY        0
  4167. #define   DISPPLANE_SPRITE_ABOVE_OVERLAY        (1)
  4168. #define _DSPBADDR               (dev_priv->info.display_mmio_offset + 0x71184)
  4169. #define _DSPBSTRIDE             (dev_priv->info.display_mmio_offset + 0x71188)
  4170. #define _DSPBPOS                (dev_priv->info.display_mmio_offset + 0x7118C)
  4171. #define _DSPBSIZE               (dev_priv->info.display_mmio_offset + 0x71190)
  4172. #define _DSPBSURF               (dev_priv->info.display_mmio_offset + 0x7119C)
  4173. #define _DSPBTILEOFF            (dev_priv->info.display_mmio_offset + 0x711A4)
  4174. #define _DSPBOFFSET             (dev_priv->info.display_mmio_offset + 0x711A4)
  4175. #define _DSPBSURFLIVE           (dev_priv->info.display_mmio_offset + 0x711AC)
  4176.  
  4177. /* Sprite A control */
  4178. #define _DVSACNTR               0x72180
  4179. #define   DVS_ENABLE            (1<<31)
  4180. #define   DVS_GAMMA_ENABLE      (1<<30)
  4181. #define   DVS_PIXFORMAT_MASK    (3<<25)
  4182. #define   DVS_FORMAT_YUV422     (0<<25)
  4183. #define   DVS_FORMAT_RGBX101010 (1<<25)
  4184. #define   DVS_FORMAT_RGBX888    (2<<25)
  4185. #define   DVS_FORMAT_RGBX161616 (3<<25)
  4186. #define   DVS_PIPE_CSC_ENABLE   (1<<24)
  4187. #define   DVS_SOURCE_KEY        (1<<22)
  4188. #define   DVS_RGB_ORDER_XBGR    (1<<20)
  4189. #define   DVS_YUV_BYTE_ORDER_MASK (3<<16)
  4190. #define   DVS_YUV_ORDER_YUYV    (0<<16)
  4191. #define   DVS_YUV_ORDER_UYVY    (1<<16)
  4192. #define   DVS_YUV_ORDER_YVYU    (2<<16)
  4193. #define   DVS_YUV_ORDER_VYUY    (3<<16)
  4194. #define   DVS_DEST_KEY          (1<<2)
  4195. #define   DVS_TRICKLE_FEED_DISABLE (1<<14)
  4196. #define   DVS_TILED             (1<<10)
  4197. #define _DVSALINOFF             0x72184
  4198. #define _DVSASTRIDE             0x72188
  4199. #define _DVSAPOS                0x7218c
  4200. #define _DVSASIZE               0x72190
  4201. #define _DVSAKEYVAL             0x72194
  4202. #define _DVSAKEYMSK             0x72198
  4203. #define _DVSASURF               0x7219c
  4204. #define _DVSAKEYMAXVAL          0x721a0
  4205. #define _DVSATILEOFF            0x721a4
  4206. #define _DVSASURFLIVE           0x721ac
  4207. #define _DVSASCALE              0x72204
  4208. #define   DVS_SCALE_ENABLE      (1<<31)
  4209. #define   DVS_FILTER_MASK       (3<<29)
  4210. #define   DVS_FILTER_MEDIUM     (0<<29)
  4211. #define   DVS_FILTER_ENHANCING  (1<<29)
  4212. #define   DVS_FILTER_SOFTENING  (2<<29)
  4213. #define   DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
  4214. #define   DVS_VERTICAL_OFFSET_ENABLE (1<<27)
  4215. #define _DVSAGAMC               0x72300
  4216.  
  4217. #define _DVSBCNTR               0x73180
  4218. #define _DVSBLINOFF             0x73184
  4219. #define _DVSBSTRIDE             0x73188
  4220. #define _DVSBPOS                0x7318c
  4221. #define _DVSBSIZE               0x73190
  4222. #define _DVSBKEYVAL             0x73194
  4223. #define _DVSBKEYMSK             0x73198
  4224. #define _DVSBSURF               0x7319c
  4225. #define _DVSBKEYMAXVAL          0x731a0
  4226. #define _DVSBTILEOFF            0x731a4
  4227. #define _DVSBSURFLIVE           0x731ac
  4228. #define _DVSBSCALE              0x73204
  4229. #define _DVSBGAMC               0x73300
  4230.  
  4231. #define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
  4232. #define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
  4233. #define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
  4234. #define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
  4235. #define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
  4236. #define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
  4237. #define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
  4238. #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
  4239. #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
  4240. #define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
  4241. #define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
  4242. #define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
  4243.  
  4244. #define _SPRA_CTL               0x70280
  4245. #define   SPRITE_ENABLE                 (1<<31)
  4246. #define   SPRITE_GAMMA_ENABLE           (1<<30)
  4247. #define   SPRITE_PIXFORMAT_MASK         (7<<25)
  4248. #define   SPRITE_FORMAT_YUV422          (0<<25)
  4249. #define   SPRITE_FORMAT_RGBX101010      (1<<25)
  4250. #define   SPRITE_FORMAT_RGBX888         (2<<25)
  4251. #define   SPRITE_FORMAT_RGBX161616      (3<<25)
  4252. #define   SPRITE_FORMAT_YUV444          (4<<25)
  4253. #define   SPRITE_FORMAT_XR_BGR101010    (5<<25) /* Extended range */
  4254. #define   SPRITE_PIPE_CSC_ENABLE        (1<<24)
  4255. #define   SPRITE_SOURCE_KEY             (1<<22)
  4256. #define   SPRITE_RGB_ORDER_RGBX         (1<<20) /* only for 888 and 161616 */
  4257. #define   SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
  4258. #define   SPRITE_YUV_CSC_FORMAT_BT709   (1<<18) /* 0 is BT601 */
  4259. #define   SPRITE_YUV_BYTE_ORDER_MASK    (3<<16)
  4260. #define   SPRITE_YUV_ORDER_YUYV         (0<<16)
  4261. #define   SPRITE_YUV_ORDER_UYVY         (1<<16)
  4262. #define   SPRITE_YUV_ORDER_YVYU         (2<<16)
  4263. #define   SPRITE_YUV_ORDER_VYUY         (3<<16)
  4264. #define   SPRITE_TRICKLE_FEED_DISABLE   (1<<14)
  4265. #define   SPRITE_INT_GAMMA_ENABLE       (1<<13)
  4266. #define   SPRITE_TILED                  (1<<10)
  4267. #define   SPRITE_DEST_KEY               (1<<2)
  4268. #define _SPRA_LINOFF            0x70284
  4269. #define _SPRA_STRIDE            0x70288
  4270. #define _SPRA_POS               0x7028c
  4271. #define _SPRA_SIZE              0x70290
  4272. #define _SPRA_KEYVAL            0x70294
  4273. #define _SPRA_KEYMSK            0x70298
  4274. #define _SPRA_SURF              0x7029c
  4275. #define _SPRA_KEYMAX            0x702a0
  4276. #define _SPRA_TILEOFF           0x702a4
  4277. #define _SPRA_OFFSET            0x702a4
  4278. #define _SPRA_SURFLIVE          0x702ac
  4279. #define _SPRA_SCALE             0x70304
  4280. #define   SPRITE_SCALE_ENABLE   (1<<31)
  4281. #define   SPRITE_FILTER_MASK    (3<<29)
  4282. #define   SPRITE_FILTER_MEDIUM  (0<<29)
  4283. #define   SPRITE_FILTER_ENHANCING       (1<<29)
  4284. #define   SPRITE_FILTER_SOFTENING       (2<<29)
  4285. #define   SPRITE_VERTICAL_OFFSET_HALF   (1<<28) /* must be enabled below */
  4286. #define   SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
  4287. #define _SPRA_GAMC              0x70400
  4288.  
  4289. #define _SPRB_CTL               0x71280
  4290. #define _SPRB_LINOFF            0x71284
  4291. #define _SPRB_STRIDE            0x71288
  4292. #define _SPRB_POS               0x7128c
  4293. #define _SPRB_SIZE              0x71290
  4294. #define _SPRB_KEYVAL            0x71294
  4295. #define _SPRB_KEYMSK            0x71298
  4296. #define _SPRB_SURF              0x7129c
  4297. #define _SPRB_KEYMAX            0x712a0
  4298. #define _SPRB_TILEOFF           0x712a4
  4299. #define _SPRB_OFFSET            0x712a4
  4300. #define _SPRB_SURFLIVE          0x712ac
  4301. #define _SPRB_SCALE             0x71304
  4302. #define _SPRB_GAMC              0x71400
  4303.  
  4304. #define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
  4305. #define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
  4306. #define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
  4307. #define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
  4308. #define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
  4309. #define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
  4310. #define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
  4311. #define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
  4312. #define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
  4313. #define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
  4314. #define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
  4315. #define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
  4316. #define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
  4317. #define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
  4318.  
  4319. #define _SPACNTR                (VLV_DISPLAY_BASE + 0x72180)
  4320. #define   SP_ENABLE                     (1<<31)
  4321. #define   SP_GAMMA_ENABLE               (1<<30)
  4322. #define   SP_PIXFORMAT_MASK             (0xf<<26)
  4323. #define   SP_FORMAT_YUV422              (0<<26)
  4324. #define   SP_FORMAT_BGR565              (5<<26)
  4325. #define   SP_FORMAT_BGRX8888            (6<<26)
  4326. #define   SP_FORMAT_BGRA8888            (7<<26)
  4327. #define   SP_FORMAT_RGBX1010102         (8<<26)
  4328. #define   SP_FORMAT_RGBA1010102         (9<<26)
  4329. #define   SP_FORMAT_RGBX8888            (0xe<<26)
  4330. #define   SP_FORMAT_RGBA8888            (0xf<<26)
  4331. #define   SP_SOURCE_KEY                 (1<<22)
  4332. #define   SP_YUV_BYTE_ORDER_MASK        (3<<16)
  4333. #define   SP_YUV_ORDER_YUYV             (0<<16)
  4334. #define   SP_YUV_ORDER_UYVY             (1<<16)
  4335. #define   SP_YUV_ORDER_YVYU             (2<<16)
  4336. #define   SP_YUV_ORDER_VYUY             (3<<16)
  4337. #define   SP_TILED                      (1<<10)
  4338. #define _SPALINOFF              (VLV_DISPLAY_BASE + 0x72184)
  4339. #define _SPASTRIDE              (VLV_DISPLAY_BASE + 0x72188)
  4340. #define _SPAPOS                 (VLV_DISPLAY_BASE + 0x7218c)
  4341. #define _SPASIZE                (VLV_DISPLAY_BASE + 0x72190)
  4342. #define _SPAKEYMINVAL           (VLV_DISPLAY_BASE + 0x72194)
  4343. #define _SPAKEYMSK              (VLV_DISPLAY_BASE + 0x72198)
  4344. #define _SPASURF                (VLV_DISPLAY_BASE + 0x7219c)
  4345. #define _SPAKEYMAXVAL           (VLV_DISPLAY_BASE + 0x721a0)
  4346. #define _SPATILEOFF             (VLV_DISPLAY_BASE + 0x721a4)
  4347. #define _SPACONSTALPHA          (VLV_DISPLAY_BASE + 0x721a8)
  4348. #define _SPAGAMC                (VLV_DISPLAY_BASE + 0x721f4)
  4349.  
  4350. #define _SPBCNTR                (VLV_DISPLAY_BASE + 0x72280)
  4351. #define _SPBLINOFF              (VLV_DISPLAY_BASE + 0x72284)
  4352. #define _SPBSTRIDE              (VLV_DISPLAY_BASE + 0x72288)
  4353. #define _SPBPOS                 (VLV_DISPLAY_BASE + 0x7228c)
  4354. #define _SPBSIZE                (VLV_DISPLAY_BASE + 0x72290)
  4355. #define _SPBKEYMINVAL           (VLV_DISPLAY_BASE + 0x72294)
  4356. #define _SPBKEYMSK              (VLV_DISPLAY_BASE + 0x72298)
  4357. #define _SPBSURF                (VLV_DISPLAY_BASE + 0x7229c)
  4358. #define _SPBKEYMAXVAL           (VLV_DISPLAY_BASE + 0x722a0)
  4359. #define _SPBTILEOFF             (VLV_DISPLAY_BASE + 0x722a4)
  4360. #define _SPBCONSTALPHA          (VLV_DISPLAY_BASE + 0x722a8)
  4361. #define _SPBGAMC                (VLV_DISPLAY_BASE + 0x722f4)
  4362.  
  4363. #define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
  4364. #define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
  4365. #define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
  4366. #define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
  4367. #define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
  4368. #define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
  4369. #define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
  4370. #define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
  4371. #define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
  4372. #define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
  4373. #define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
  4374. #define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
  4375.  
  4376. /* VBIOS regs */
  4377. #define VGACNTRL                0x71400
  4378. # define VGA_DISP_DISABLE                       (1 << 31)
  4379. # define VGA_2X_MODE                            (1 << 30)
  4380. # define VGA_PIPE_B_SELECT                      (1 << 29)
  4381.  
  4382. #define VLV_VGACNTRL            (VLV_DISPLAY_BASE + 0x71400)
  4383.  
  4384. /* Ironlake */
  4385.  
  4386. #define CPU_VGACNTRL    0x41000
  4387.  
  4388. #define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
  4389. #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
  4390. #define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
  4391. #define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
  4392. #define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
  4393. #define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
  4394. #define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
  4395. #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
  4396. #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
  4397.  
  4398. /* refresh rate hardware control */
  4399. #define RR_HW_CTL       0x45300
  4400. #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
  4401. #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
  4402.  
  4403. #define FDI_PLL_BIOS_0  0x46000
  4404. #define  FDI_PLL_FB_CLOCK_MASK  0xff
  4405. #define FDI_PLL_BIOS_1  0x46004
  4406. #define FDI_PLL_BIOS_2  0x46008
  4407. #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
  4408. #define DISPLAY_PORT_PLL_BIOS_1         0x46010
  4409. #define DISPLAY_PORT_PLL_BIOS_2         0x46014
  4410.  
  4411. #define PCH_3DCGDIS0            0x46020
  4412. # define MARIUNIT_CLOCK_GATE_DISABLE            (1 << 18)
  4413. # define SVSMUNIT_CLOCK_GATE_DISABLE            (1 << 1)
  4414.  
  4415. #define PCH_3DCGDIS1            0x46024
  4416. # define VFMUNIT_CLOCK_GATE_DISABLE             (1 << 11)
  4417.  
  4418. #define FDI_PLL_FREQ_CTL        0x46030
  4419. #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
  4420. #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
  4421. #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
  4422.  
  4423.  
  4424. #define _PIPEA_DATA_M1          0x60030
  4425. #define  PIPE_DATA_M1_OFFSET    0
  4426. #define _PIPEA_DATA_N1          0x60034
  4427. #define  PIPE_DATA_N1_OFFSET    0
  4428.  
  4429. #define _PIPEA_DATA_M2          0x60038
  4430. #define  PIPE_DATA_M2_OFFSET    0
  4431. #define _PIPEA_DATA_N2          0x6003c
  4432. #define  PIPE_DATA_N2_OFFSET    0
  4433.  
  4434. #define _PIPEA_LINK_M1          0x60040
  4435. #define  PIPE_LINK_M1_OFFSET    0
  4436. #define _PIPEA_LINK_N1          0x60044
  4437. #define  PIPE_LINK_N1_OFFSET    0
  4438.  
  4439. #define _PIPEA_LINK_M2          0x60048
  4440. #define  PIPE_LINK_M2_OFFSET    0
  4441. #define _PIPEA_LINK_N2          0x6004c
  4442. #define  PIPE_LINK_N2_OFFSET    0
  4443.  
  4444. /* PIPEB timing regs are same start from 0x61000 */
  4445.  
  4446. #define _PIPEB_DATA_M1          0x61030
  4447. #define _PIPEB_DATA_N1          0x61034
  4448. #define _PIPEB_DATA_M2          0x61038
  4449. #define _PIPEB_DATA_N2          0x6103c
  4450. #define _PIPEB_LINK_M1          0x61040
  4451. #define _PIPEB_LINK_N1          0x61044
  4452. #define _PIPEB_LINK_M2          0x61048
  4453. #define _PIPEB_LINK_N2          0x6104c
  4454.  
  4455. #define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
  4456. #define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
  4457. #define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
  4458. #define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
  4459. #define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
  4460. #define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
  4461. #define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
  4462. #define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
  4463.  
  4464. /* CPU panel fitter */
  4465. /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
  4466. #define _PFA_CTL_1               0x68080
  4467. #define _PFB_CTL_1               0x68880
  4468. #define  PF_ENABLE              (1<<31)
  4469. #define  PF_PIPE_SEL_MASK_IVB   (3<<29)
  4470. #define  PF_PIPE_SEL_IVB(pipe)  ((pipe)<<29)
  4471. #define  PF_FILTER_MASK         (3<<23)
  4472. #define  PF_FILTER_PROGRAMMED   (0<<23)
  4473. #define  PF_FILTER_MED_3x3      (1<<23)
  4474. #define  PF_FILTER_EDGE_ENHANCE (2<<23)
  4475. #define  PF_FILTER_EDGE_SOFTEN  (3<<23)
  4476. #define _PFA_WIN_SZ             0x68074
  4477. #define _PFB_WIN_SZ             0x68874
  4478. #define _PFA_WIN_POS            0x68070
  4479. #define _PFB_WIN_POS            0x68870
  4480. #define _PFA_VSCALE             0x68084
  4481. #define _PFB_VSCALE             0x68884
  4482. #define _PFA_HSCALE             0x68090
  4483. #define _PFB_HSCALE             0x68890
  4484.  
  4485. #define PF_CTL(pipe)            _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
  4486. #define PF_WIN_SZ(pipe)         _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
  4487. #define PF_WIN_POS(pipe)        _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
  4488. #define PF_VSCALE(pipe)         _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
  4489. #define PF_HSCALE(pipe)         _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
  4490.  
  4491. /* legacy palette */
  4492. #define _LGC_PALETTE_A           0x4a000
  4493. #define _LGC_PALETTE_B           0x4a800
  4494. #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
  4495.  
  4496. #define _GAMMA_MODE_A           0x4a480
  4497. #define _GAMMA_MODE_B           0x4ac80
  4498. #define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
  4499. #define GAMMA_MODE_MODE_MASK    (3 << 0)
  4500. #define GAMMA_MODE_MODE_8BIT    (0 << 0)
  4501. #define GAMMA_MODE_MODE_10BIT   (1 << 0)
  4502. #define GAMMA_MODE_MODE_12BIT   (2 << 0)
  4503. #define GAMMA_MODE_MODE_SPLIT   (3 << 0)
  4504.  
  4505. /* interrupts */
  4506. #define DE_MASTER_IRQ_CONTROL   (1 << 31)
  4507. #define DE_SPRITEB_FLIP_DONE    (1 << 29)
  4508. #define DE_SPRITEA_FLIP_DONE    (1 << 28)
  4509. #define DE_PLANEB_FLIP_DONE     (1 << 27)
  4510. #define DE_PLANEA_FLIP_DONE     (1 << 26)
  4511. #define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
  4512. #define DE_PCU_EVENT            (1 << 25)
  4513. #define DE_GTT_FAULT            (1 << 24)
  4514. #define DE_POISON               (1 << 23)
  4515. #define DE_PERFORM_COUNTER      (1 << 22)
  4516. #define DE_PCH_EVENT            (1 << 21)
  4517. #define DE_AUX_CHANNEL_A        (1 << 20)
  4518. #define DE_DP_A_HOTPLUG         (1 << 19)
  4519. #define DE_GSE                  (1 << 18)
  4520. #define DE_PIPEB_VBLANK         (1 << 15)
  4521. #define DE_PIPEB_EVEN_FIELD     (1 << 14)
  4522. #define DE_PIPEB_ODD_FIELD      (1 << 13)
  4523. #define DE_PIPEB_LINE_COMPARE   (1 << 12)
  4524. #define DE_PIPEB_VSYNC          (1 << 11)
  4525. #define DE_PIPEB_CRC_DONE       (1 << 10)
  4526. #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
  4527. #define DE_PIPEA_VBLANK         (1 << 7)
  4528. #define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8*(pipe)))
  4529. #define DE_PIPEA_EVEN_FIELD     (1 << 6)
  4530. #define DE_PIPEA_ODD_FIELD      (1 << 5)
  4531. #define DE_PIPEA_LINE_COMPARE   (1 << 4)
  4532. #define DE_PIPEA_VSYNC          (1 << 3)
  4533. #define DE_PIPEA_CRC_DONE       (1 << 2)
  4534. #define DE_PIPE_CRC_DONE(pipe)  (1 << (2 + 8*(pipe)))
  4535. #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
  4536. #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8*(pipe)))
  4537.  
  4538. /* More Ivybridge lolz */
  4539. #define DE_ERR_INT_IVB                  (1<<30)
  4540. #define DE_GSE_IVB                      (1<<29)
  4541. #define DE_PCH_EVENT_IVB                (1<<28)
  4542. #define DE_DP_A_HOTPLUG_IVB             (1<<27)
  4543. #define DE_AUX_CHANNEL_A_IVB            (1<<26)
  4544. #define DE_SPRITEC_FLIP_DONE_IVB        (1<<14)
  4545. #define DE_PLANEC_FLIP_DONE_IVB         (1<<13)
  4546. #define DE_PIPEC_VBLANK_IVB             (1<<10)
  4547. #define DE_SPRITEB_FLIP_DONE_IVB        (1<<9)
  4548. #define DE_PLANEB_FLIP_DONE_IVB         (1<<8)
  4549. #define DE_PIPEB_VBLANK_IVB             (1<<5)
  4550. #define DE_SPRITEA_FLIP_DONE_IVB        (1<<4)
  4551. #define DE_PLANEA_FLIP_DONE_IVB         (1<<3)
  4552. #define DE_PLANE_FLIP_DONE_IVB(plane)   (1<< (3 + 5*(plane)))
  4553. #define DE_PIPEA_VBLANK_IVB             (1<<0)
  4554. #define DE_PIPE_VBLANK_IVB(pipe)        (1 << (pipe * 5))
  4555.  
  4556. #define VLV_MASTER_IER                  0x4400c /* Gunit master IER */
  4557. #define   MASTER_INTERRUPT_ENABLE       (1<<31)
  4558.  
  4559. #define DEISR   0x44000
  4560. #define DEIMR   0x44004
  4561. #define DEIIR   0x44008
  4562. #define DEIER   0x4400c
  4563.  
  4564. #define GTISR   0x44010
  4565. #define GTIMR   0x44014
  4566. #define GTIIR   0x44018
  4567. #define GTIER   0x4401c
  4568.  
  4569. #define GEN8_MASTER_IRQ                 0x44200
  4570. #define  GEN8_MASTER_IRQ_CONTROL        (1<<31)
  4571. #define  GEN8_PCU_IRQ                   (1<<30)
  4572. #define  GEN8_DE_PCH_IRQ                (1<<23)
  4573. #define  GEN8_DE_MISC_IRQ               (1<<22)
  4574. #define  GEN8_DE_PORT_IRQ               (1<<20)
  4575. #define  GEN8_DE_PIPE_C_IRQ             (1<<18)
  4576. #define  GEN8_DE_PIPE_B_IRQ             (1<<17)
  4577. #define  GEN8_DE_PIPE_A_IRQ             (1<<16)
  4578. #define  GEN8_DE_PIPE_IRQ(pipe)         (1<<(16+pipe))
  4579. #define  GEN8_GT_VECS_IRQ               (1<<6)
  4580. #define  GEN8_GT_PM_IRQ                 (1<<4)
  4581. #define  GEN8_GT_VCS2_IRQ               (1<<3)
  4582. #define  GEN8_GT_VCS1_IRQ               (1<<2)
  4583. #define  GEN8_GT_BCS_IRQ                (1<<1)
  4584. #define  GEN8_GT_RCS_IRQ                (1<<0)
  4585.  
  4586. #define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
  4587. #define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
  4588. #define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
  4589. #define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
  4590.  
  4591. #define GEN8_BCS_IRQ_SHIFT 16
  4592. #define GEN8_RCS_IRQ_SHIFT 0
  4593. #define GEN8_VCS2_IRQ_SHIFT 16
  4594. #define GEN8_VCS1_IRQ_SHIFT 0
  4595. #define GEN8_VECS_IRQ_SHIFT 0
  4596.  
  4597. #define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
  4598. #define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
  4599. #define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
  4600. #define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
  4601. #define  GEN8_PIPE_FIFO_UNDERRUN        (1 << 31)
  4602. #define  GEN8_PIPE_CDCLK_CRC_ERROR      (1 << 29)
  4603. #define  GEN8_PIPE_CDCLK_CRC_DONE       (1 << 28)
  4604. #define  GEN8_PIPE_CURSOR_FAULT         (1 << 10)
  4605. #define  GEN8_PIPE_SPRITE_FAULT         (1 << 9)
  4606. #define  GEN8_PIPE_PRIMARY_FAULT        (1 << 8)
  4607. #define  GEN8_PIPE_SPRITE_FLIP_DONE     (1 << 5)
  4608. #define  GEN8_PIPE_PRIMARY_FLIP_DONE    (1 << 4)
  4609. #define  GEN8_PIPE_SCAN_LINE_EVENT      (1 << 2)
  4610. #define  GEN8_PIPE_VSYNC                (1 << 1)
  4611. #define  GEN8_PIPE_VBLANK               (1 << 0)
  4612. #define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
  4613.         (GEN8_PIPE_CURSOR_FAULT | \
  4614.          GEN8_PIPE_SPRITE_FAULT | \
  4615.          GEN8_PIPE_PRIMARY_FAULT)
  4616.  
  4617. #define GEN8_DE_PORT_ISR 0x44440
  4618. #define GEN8_DE_PORT_IMR 0x44444
  4619. #define GEN8_DE_PORT_IIR 0x44448
  4620. #define GEN8_DE_PORT_IER 0x4444c
  4621. #define  GEN8_PORT_DP_A_HOTPLUG         (1 << 3)
  4622. #define  GEN8_AUX_CHANNEL_A             (1 << 0)
  4623.  
  4624. #define GEN8_DE_MISC_ISR 0x44460
  4625. #define GEN8_DE_MISC_IMR 0x44464
  4626. #define GEN8_DE_MISC_IIR 0x44468
  4627. #define GEN8_DE_MISC_IER 0x4446c
  4628. #define  GEN8_DE_MISC_GSE               (1 << 27)
  4629.  
  4630. #define GEN8_PCU_ISR 0x444e0
  4631. #define GEN8_PCU_IMR 0x444e4
  4632. #define GEN8_PCU_IIR 0x444e8
  4633. #define GEN8_PCU_IER 0x444ec
  4634.  
  4635. #define ILK_DISPLAY_CHICKEN2    0x42004
  4636. /* Required on all Ironlake and Sandybridge according to the B-Spec. */
  4637. #define  ILK_ELPIN_409_SELECT   (1 << 25)
  4638. #define  ILK_DPARB_GATE (1<<22)
  4639. #define  ILK_VSDPFD_FULL        (1<<21)
  4640. #define FUSE_STRAP                      0x42014
  4641. #define  ILK_INTERNAL_GRAPHICS_DISABLE  (1 << 31)
  4642. #define  ILK_INTERNAL_DISPLAY_DISABLE   (1 << 30)
  4643. #define  ILK_DISPLAY_DEBUG_DISABLE      (1 << 29)
  4644. #define  ILK_HDCP_DISABLE               (1 << 25)
  4645. #define  ILK_eDP_A_DISABLE              (1 << 24)
  4646. #define  HSW_CDCLK_LIMIT                (1 << 24)
  4647. #define  ILK_DESKTOP                    (1 << 23)
  4648.  
  4649. #define ILK_DSPCLK_GATE_D                       0x42020
  4650. #define   ILK_VRHUNIT_CLOCK_GATE_DISABLE        (1 << 28)
  4651. #define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE       (1 << 9)
  4652. #define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE      (1 << 8)
  4653. #define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE        (1 << 7)
  4654. #define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE       (1 << 5)
  4655.  
  4656. #define IVB_CHICKEN3    0x4200c
  4657. # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE      (1 << 5)
  4658. # define CHICKEN3_DGMG_DONE_FIX_DISABLE         (1 << 2)
  4659.  
  4660. #define CHICKEN_PAR1_1          0x42080
  4661. #define  DPA_MASK_VBLANK_SRD    (1 << 15)
  4662. #define  FORCE_ARB_IDLE_PLANES  (1 << 14)
  4663.  
  4664. #define _CHICKEN_PIPESL_1_A     0x420b0
  4665. #define _CHICKEN_PIPESL_1_B     0x420b4
  4666. #define  HSW_FBCQ_DIS                   (1 << 22)
  4667. #define  BDW_DPRS_MASK_VBLANK_SRD       (1 << 0)
  4668. #define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
  4669.  
  4670. #define DISP_ARB_CTL    0x45000
  4671. #define  DISP_TILE_SURFACE_SWIZZLING    (1<<13)
  4672. #define  DISP_FBC_WM_DIS                (1<<15)
  4673. #define DISP_ARB_CTL2   0x45004
  4674. #define  DISP_DATA_PARTITION_5_6        (1<<6)
  4675. #define GEN7_MSG_CTL    0x45010
  4676. #define  WAIT_FOR_PCH_RESET_ACK         (1<<1)
  4677. #define  WAIT_FOR_PCH_FLR_ACK           (1<<0)
  4678. #define HSW_NDE_RSTWRN_OPT      0x46408
  4679. #define  RESET_PCH_HANDSHAKE_ENABLE     (1<<4)
  4680.  
  4681. /* GEN7 chicken */
  4682. #define GEN7_COMMON_SLICE_CHICKEN1              0x7010
  4683. # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
  4684. #define COMMON_SLICE_CHICKEN2                   0x7014
  4685. # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE   (1<<0)
  4686.  
  4687. #define GEN7_L3SQCREG1                          0xB010
  4688. #define  VLV_B0_WA_L3SQCREG1_VALUE              0x00D30000
  4689.  
  4690. #define GEN7_L3CNTLREG1                         0xB01C
  4691. #define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C47FF8C
  4692. #define  GEN7_L3AGDIS                           (1<<19)
  4693. #define GEN7_L3CNTLREG2                         0xB020
  4694. #define GEN7_L3CNTLREG3                         0xB024
  4695.  
  4696. #define GEN7_L3_CHICKEN_MODE_REGISTER           0xB030
  4697. #define  GEN7_WA_L3_CHICKEN_MODE                                0x20000000
  4698.  
  4699. #define GEN7_L3SQCREG4                          0xb034
  4700. #define  L3SQ_URB_READ_CAM_MATCH_DISABLE        (1<<27)
  4701.  
  4702. /* GEN8 chicken */
  4703. #define HDC_CHICKEN0                            0x7300
  4704. #define  HDC_FORCE_NON_COHERENT                 (1<<4)
  4705.  
  4706. /* WaCatErrorRejectionIssue */
  4707. #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          0x9030
  4708. #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB       (1<<11)
  4709.  
  4710. #define HSW_SCRATCH1                            0xb038
  4711. #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE   (1<<27)
  4712.  
  4713. /* PCH */
  4714.  
  4715. /* south display engine interrupt: IBX */
  4716. #define SDE_AUDIO_POWER_D       (1 << 27)
  4717. #define SDE_AUDIO_POWER_C       (1 << 26)
  4718. #define SDE_AUDIO_POWER_B       (1 << 25)
  4719. #define SDE_AUDIO_POWER_SHIFT   (25)
  4720. #define SDE_AUDIO_POWER_MASK    (7 << SDE_AUDIO_POWER_SHIFT)
  4721. #define SDE_GMBUS               (1 << 24)
  4722. #define SDE_AUDIO_HDCP_TRANSB   (1 << 23)
  4723. #define SDE_AUDIO_HDCP_TRANSA   (1 << 22)
  4724. #define SDE_AUDIO_HDCP_MASK     (3 << 22)
  4725. #define SDE_AUDIO_TRANSB        (1 << 21)
  4726. #define SDE_AUDIO_TRANSA        (1 << 20)
  4727. #define SDE_AUDIO_TRANS_MASK    (3 << 20)
  4728. #define SDE_POISON              (1 << 19)
  4729. /* 18 reserved */
  4730. #define SDE_FDI_RXB             (1 << 17)
  4731. #define SDE_FDI_RXA             (1 << 16)
  4732. #define SDE_FDI_MASK            (3 << 16)
  4733. #define SDE_AUXD                (1 << 15)
  4734. #define SDE_AUXC                (1 << 14)
  4735. #define SDE_AUXB                (1 << 13)
  4736. #define SDE_AUX_MASK            (7 << 13)
  4737. /* 12 reserved */
  4738. #define SDE_CRT_HOTPLUG         (1 << 11)
  4739. #define SDE_PORTD_HOTPLUG       (1 << 10)
  4740. #define SDE_PORTC_HOTPLUG       (1 << 9)
  4741. #define SDE_PORTB_HOTPLUG       (1 << 8)
  4742. #define SDE_SDVOB_HOTPLUG       (1 << 6)
  4743. #define SDE_HOTPLUG_MASK        (SDE_CRT_HOTPLUG | \
  4744.                                  SDE_SDVOB_HOTPLUG |    \
  4745.                                  SDE_PORTB_HOTPLUG |    \
  4746.                                  SDE_PORTC_HOTPLUG |    \
  4747.                                  SDE_PORTD_HOTPLUG)
  4748. #define SDE_TRANSB_CRC_DONE     (1 << 5)
  4749. #define SDE_TRANSB_CRC_ERR      (1 << 4)
  4750. #define SDE_TRANSB_FIFO_UNDER   (1 << 3)
  4751. #define SDE_TRANSA_CRC_DONE     (1 << 2)
  4752. #define SDE_TRANSA_CRC_ERR      (1 << 1)
  4753. #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
  4754. #define SDE_TRANS_MASK          (0x3f)
  4755.  
  4756. /* south display engine interrupt: CPT/PPT */
  4757. #define SDE_AUDIO_POWER_D_CPT   (1 << 31)
  4758. #define SDE_AUDIO_POWER_C_CPT   (1 << 30)
  4759. #define SDE_AUDIO_POWER_B_CPT   (1 << 29)
  4760. #define SDE_AUDIO_POWER_SHIFT_CPT   29
  4761. #define SDE_AUDIO_POWER_MASK_CPT    (7 << 29)
  4762. #define SDE_AUXD_CPT            (1 << 27)
  4763. #define SDE_AUXC_CPT            (1 << 26)
  4764. #define SDE_AUXB_CPT            (1 << 25)
  4765. #define SDE_AUX_MASK_CPT        (7 << 25)
  4766. #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
  4767. #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
  4768. #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
  4769. #define SDE_CRT_HOTPLUG_CPT     (1 << 19)
  4770. #define SDE_SDVOB_HOTPLUG_CPT   (1 << 18)
  4771. #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
  4772.                                  SDE_SDVOB_HOTPLUG_CPT |        \
  4773.                                  SDE_PORTD_HOTPLUG_CPT |        \
  4774.                                  SDE_PORTC_HOTPLUG_CPT |        \
  4775.                                  SDE_PORTB_HOTPLUG_CPT)
  4776. #define SDE_GMBUS_CPT           (1 << 17)
  4777. #define SDE_ERROR_CPT           (1 << 16)
  4778. #define SDE_AUDIO_CP_REQ_C_CPT  (1 << 10)
  4779. #define SDE_AUDIO_CP_CHG_C_CPT  (1 << 9)
  4780. #define SDE_FDI_RXC_CPT         (1 << 8)
  4781. #define SDE_AUDIO_CP_REQ_B_CPT  (1 << 6)
  4782. #define SDE_AUDIO_CP_CHG_B_CPT  (1 << 5)
  4783. #define SDE_FDI_RXB_CPT         (1 << 4)
  4784. #define SDE_AUDIO_CP_REQ_A_CPT  (1 << 2)
  4785. #define SDE_AUDIO_CP_CHG_A_CPT  (1 << 1)
  4786. #define SDE_FDI_RXA_CPT         (1 << 0)
  4787. #define SDE_AUDIO_CP_REQ_CPT    (SDE_AUDIO_CP_REQ_C_CPT | \
  4788.                                  SDE_AUDIO_CP_REQ_B_CPT | \
  4789.                                  SDE_AUDIO_CP_REQ_A_CPT)
  4790. #define SDE_AUDIO_CP_CHG_CPT    (SDE_AUDIO_CP_CHG_C_CPT | \
  4791.                                  SDE_AUDIO_CP_CHG_B_CPT | \
  4792.                                  SDE_AUDIO_CP_CHG_A_CPT)
  4793. #define SDE_FDI_MASK_CPT        (SDE_FDI_RXC_CPT | \
  4794.                                  SDE_FDI_RXB_CPT | \
  4795.                                  SDE_FDI_RXA_CPT)
  4796.  
  4797. #define SDEISR  0xc4000
  4798. #define SDEIMR  0xc4004
  4799. #define SDEIIR  0xc4008
  4800. #define SDEIER  0xc400c
  4801.  
  4802. #define SERR_INT                        0xc4040
  4803. #define  SERR_INT_POISON                (1<<31)
  4804. #define  SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
  4805. #define  SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
  4806. #define  SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
  4807. #define  SERR_INT_TRANS_FIFO_UNDERRUN(pipe)     (1<<(pipe*3))
  4808.  
  4809. /* digital port hotplug */
  4810. #define PCH_PORT_HOTPLUG        0xc4030         /* SHOTPLUG_CTL */
  4811. #define PORTD_HOTPLUG_ENABLE            (1 << 20)
  4812. #define PORTD_PULSE_DURATION_2ms        (0)
  4813. #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
  4814. #define PORTD_PULSE_DURATION_6ms        (2 << 18)
  4815. #define PORTD_PULSE_DURATION_100ms      (3 << 18)
  4816. #define PORTD_PULSE_DURATION_MASK       (3 << 18)
  4817. #define PORTD_HOTPLUG_STATUS_MASK       (0x3 << 16)
  4818. #define  PORTD_HOTPLUG_NO_DETECT        (0 << 16)
  4819. #define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
  4820. #define  PORTD_HOTPLUG_LONG_DETECT      (2 << 16)
  4821. #define PORTC_HOTPLUG_ENABLE            (1 << 12)
  4822. #define PORTC_PULSE_DURATION_2ms        (0)
  4823. #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
  4824. #define PORTC_PULSE_DURATION_6ms        (2 << 10)
  4825. #define PORTC_PULSE_DURATION_100ms      (3 << 10)
  4826. #define PORTC_PULSE_DURATION_MASK       (3 << 10)
  4827. #define PORTC_HOTPLUG_STATUS_MASK       (0x3 << 8)
  4828. #define  PORTC_HOTPLUG_NO_DETECT        (0 << 8)
  4829. #define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
  4830. #define  PORTC_HOTPLUG_LONG_DETECT      (2 << 8)
  4831. #define PORTB_HOTPLUG_ENABLE            (1 << 4)
  4832. #define PORTB_PULSE_DURATION_2ms        (0)
  4833. #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
  4834. #define PORTB_PULSE_DURATION_6ms        (2 << 2)
  4835. #define PORTB_PULSE_DURATION_100ms      (3 << 2)
  4836. #define PORTB_PULSE_DURATION_MASK       (3 << 2)
  4837. #define PORTB_HOTPLUG_STATUS_MASK       (0x3 << 0)
  4838. #define  PORTB_HOTPLUG_NO_DETECT        (0 << 0)
  4839. #define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
  4840. #define  PORTB_HOTPLUG_LONG_DETECT      (2 << 0)
  4841.  
  4842. #define PCH_GPIOA               0xc5010
  4843. #define PCH_GPIOB               0xc5014
  4844. #define PCH_GPIOC               0xc5018
  4845. #define PCH_GPIOD               0xc501c
  4846. #define PCH_GPIOE               0xc5020
  4847. #define PCH_GPIOF               0xc5024
  4848.  
  4849. #define PCH_GMBUS0              0xc5100
  4850. #define PCH_GMBUS1              0xc5104
  4851. #define PCH_GMBUS2              0xc5108
  4852. #define PCH_GMBUS3              0xc510c
  4853. #define PCH_GMBUS4              0xc5110
  4854. #define PCH_GMBUS5              0xc5120
  4855.  
  4856. #define _PCH_DPLL_A              0xc6014
  4857. #define _PCH_DPLL_B              0xc6018
  4858. #define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
  4859.  
  4860. #define _PCH_FPA0                0xc6040
  4861. #define  FP_CB_TUNE             (0x3<<22)
  4862. #define _PCH_FPA1                0xc6044
  4863. #define _PCH_FPB0                0xc6048
  4864. #define _PCH_FPB1                0xc604c
  4865. #define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
  4866. #define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
  4867.  
  4868. #define PCH_DPLL_TEST           0xc606c
  4869.  
  4870. #define PCH_DREF_CONTROL        0xC6200
  4871. #define  DREF_CONTROL_MASK      0x7fc3
  4872. #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
  4873. #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
  4874. #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
  4875. #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3<<13)
  4876. #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
  4877. #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
  4878. #define  DREF_SSC_SOURCE_MASK                   (3<<11)
  4879. #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
  4880. #define  DREF_NONSPREAD_CK505_ENABLE            (1<<9)
  4881. #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
  4882. #define  DREF_NONSPREAD_SOURCE_MASK             (3<<9)
  4883. #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
  4884. #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
  4885. #define  DREF_SUPERSPREAD_SOURCE_MASK           (3<<7)
  4886. #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
  4887. #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
  4888. #define  DREF_SSC1_DISABLE                      (0<<1)
  4889. #define  DREF_SSC1_ENABLE                       (1<<1)
  4890. #define  DREF_SSC4_DISABLE                      (0)
  4891. #define  DREF_SSC4_ENABLE                       (1)
  4892.  
  4893. #define PCH_RAWCLK_FREQ         0xc6204
  4894. #define  FDL_TP1_TIMER_SHIFT    12
  4895. #define  FDL_TP1_TIMER_MASK     (3<<12)
  4896. #define  FDL_TP2_TIMER_SHIFT    10
  4897. #define  FDL_TP2_TIMER_MASK     (3<<10)
  4898. #define  RAWCLK_FREQ_MASK       0x3ff
  4899.  
  4900. #define PCH_DPLL_TMR_CFG        0xc6208
  4901.  
  4902. #define PCH_SSC4_PARMS          0xc6210
  4903. #define PCH_SSC4_AUX_PARMS      0xc6214
  4904.  
  4905. #define PCH_DPLL_SEL            0xc7000
  4906. #define  TRANS_DPLLB_SEL(pipe)          (1 << (pipe * 4))
  4907. #define  TRANS_DPLLA_SEL(pipe)          0
  4908. #define  TRANS_DPLL_ENABLE(pipe)        (1 << (pipe * 4 + 3))
  4909.  
  4910. /* transcoder */
  4911.  
  4912. #define _PCH_TRANS_HTOTAL_A             0xe0000
  4913. #define  TRANS_HTOTAL_SHIFT     16
  4914. #define  TRANS_HACTIVE_SHIFT    0
  4915. #define _PCH_TRANS_HBLANK_A             0xe0004
  4916. #define  TRANS_HBLANK_END_SHIFT 16
  4917. #define  TRANS_HBLANK_START_SHIFT 0
  4918. #define _PCH_TRANS_HSYNC_A              0xe0008
  4919. #define  TRANS_HSYNC_END_SHIFT  16
  4920. #define  TRANS_HSYNC_START_SHIFT 0
  4921. #define _PCH_TRANS_VTOTAL_A             0xe000c
  4922. #define  TRANS_VTOTAL_SHIFT     16
  4923. #define  TRANS_VACTIVE_SHIFT    0
  4924. #define _PCH_TRANS_VBLANK_A             0xe0010
  4925. #define  TRANS_VBLANK_END_SHIFT 16
  4926. #define  TRANS_VBLANK_START_SHIFT 0
  4927. #define _PCH_TRANS_VSYNC_A              0xe0014
  4928. #define  TRANS_VSYNC_END_SHIFT  16
  4929. #define  TRANS_VSYNC_START_SHIFT 0
  4930. #define _PCH_TRANS_VSYNCSHIFT_A         0xe0028
  4931.  
  4932. #define _PCH_TRANSA_DATA_M1     0xe0030
  4933. #define _PCH_TRANSA_DATA_N1     0xe0034
  4934. #define _PCH_TRANSA_DATA_M2     0xe0038
  4935. #define _PCH_TRANSA_DATA_N2     0xe003c
  4936. #define _PCH_TRANSA_LINK_M1     0xe0040
  4937. #define _PCH_TRANSA_LINK_N1     0xe0044
  4938. #define _PCH_TRANSA_LINK_M2     0xe0048
  4939. #define _PCH_TRANSA_LINK_N2     0xe004c
  4940.  
  4941. /* Per-transcoder DIP controls (PCH) */
  4942. #define _VIDEO_DIP_CTL_A         0xe0200
  4943. #define _VIDEO_DIP_DATA_A        0xe0208
  4944. #define _VIDEO_DIP_GCP_A         0xe0210
  4945.  
  4946. #define _VIDEO_DIP_CTL_B         0xe1200
  4947. #define _VIDEO_DIP_DATA_B        0xe1208
  4948. #define _VIDEO_DIP_GCP_B         0xe1210
  4949.  
  4950. #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
  4951. #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
  4952. #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
  4953.  
  4954. /* Per-transcoder DIP controls (VLV) */
  4955. #define VLV_VIDEO_DIP_CTL_A             (VLV_DISPLAY_BASE + 0x60200)
  4956. #define VLV_VIDEO_DIP_DATA_A            (VLV_DISPLAY_BASE + 0x60208)
  4957. #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A    (VLV_DISPLAY_BASE + 0x60210)
  4958.  
  4959. #define VLV_VIDEO_DIP_CTL_B             (VLV_DISPLAY_BASE + 0x61170)
  4960. #define VLV_VIDEO_DIP_DATA_B            (VLV_DISPLAY_BASE + 0x61174)
  4961. #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B    (VLV_DISPLAY_BASE + 0x61178)
  4962.  
  4963. #define CHV_VIDEO_DIP_CTL_C             (VLV_DISPLAY_BASE + 0x611f0)
  4964. #define CHV_VIDEO_DIP_DATA_C            (VLV_DISPLAY_BASE + 0x611f4)
  4965. #define CHV_VIDEO_DIP_GDCP_PAYLOAD_C    (VLV_DISPLAY_BASE + 0x611f8)
  4966.  
  4967. #define VLV_TVIDEO_DIP_CTL(pipe) \
  4968.         _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \
  4969.                VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C)
  4970. #define VLV_TVIDEO_DIP_DATA(pipe) \
  4971.         _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \
  4972.                VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C)
  4973. #define VLV_TVIDEO_DIP_GCP(pipe) \
  4974.         _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
  4975.                 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
  4976.  
  4977. /* Haswell DIP controls */
  4978. #define HSW_VIDEO_DIP_CTL_A             0x60200
  4979. #define HSW_VIDEO_DIP_AVI_DATA_A        0x60220
  4980. #define HSW_VIDEO_DIP_VS_DATA_A         0x60260
  4981. #define HSW_VIDEO_DIP_SPD_DATA_A        0x602A0
  4982. #define HSW_VIDEO_DIP_GMP_DATA_A        0x602E0
  4983. #define HSW_VIDEO_DIP_VSC_DATA_A        0x60320
  4984. #define HSW_VIDEO_DIP_AVI_ECC_A         0x60240
  4985. #define HSW_VIDEO_DIP_VS_ECC_A          0x60280
  4986. #define HSW_VIDEO_DIP_SPD_ECC_A         0x602C0
  4987. #define HSW_VIDEO_DIP_GMP_ECC_A         0x60300
  4988. #define HSW_VIDEO_DIP_VSC_ECC_A         0x60344
  4989. #define HSW_VIDEO_DIP_GCP_A             0x60210
  4990.  
  4991. #define HSW_VIDEO_DIP_CTL_B             0x61200
  4992. #define HSW_VIDEO_DIP_AVI_DATA_B        0x61220
  4993. #define HSW_VIDEO_DIP_VS_DATA_B         0x61260
  4994. #define HSW_VIDEO_DIP_SPD_DATA_B        0x612A0
  4995. #define HSW_VIDEO_DIP_GMP_DATA_B        0x612E0
  4996. #define HSW_VIDEO_DIP_VSC_DATA_B        0x61320
  4997. #define HSW_VIDEO_DIP_BVI_ECC_B         0x61240
  4998. #define HSW_VIDEO_DIP_VS_ECC_B          0x61280
  4999. #define HSW_VIDEO_DIP_SPD_ECC_B         0x612C0
  5000. #define HSW_VIDEO_DIP_GMP_ECC_B         0x61300
  5001. #define HSW_VIDEO_DIP_VSC_ECC_B         0x61344
  5002. #define HSW_VIDEO_DIP_GCP_B             0x61210
  5003.  
  5004. #define HSW_TVIDEO_DIP_CTL(trans) \
  5005.          _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
  5006. #define HSW_TVIDEO_DIP_AVI_DATA(trans) \
  5007.          _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
  5008. #define HSW_TVIDEO_DIP_VS_DATA(trans) \
  5009.          _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
  5010. #define HSW_TVIDEO_DIP_SPD_DATA(trans) \
  5011.          _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
  5012. #define HSW_TVIDEO_DIP_GCP(trans) \
  5013.         _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
  5014. #define HSW_TVIDEO_DIP_VSC_DATA(trans) \
  5015.          _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
  5016.  
  5017. #define HSW_STEREO_3D_CTL_A     0x70020
  5018. #define   S3D_ENABLE            (1<<31)
  5019. #define HSW_STEREO_3D_CTL_B     0x71020
  5020.  
  5021. #define HSW_STEREO_3D_CTL(trans) \
  5022.         _PIPE2(trans, HSW_STEREO_3D_CTL_A)
  5023.  
  5024. #define _PCH_TRANS_HTOTAL_B          0xe1000
  5025. #define _PCH_TRANS_HBLANK_B          0xe1004
  5026. #define _PCH_TRANS_HSYNC_B           0xe1008
  5027. #define _PCH_TRANS_VTOTAL_B          0xe100c
  5028. #define _PCH_TRANS_VBLANK_B          0xe1010
  5029. #define _PCH_TRANS_VSYNC_B           0xe1014
  5030. #define _PCH_TRANS_VSYNCSHIFT_B  0xe1028
  5031.  
  5032. #define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
  5033. #define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
  5034. #define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
  5035. #define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
  5036. #define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
  5037. #define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
  5038. #define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
  5039.                                          _PCH_TRANS_VSYNCSHIFT_B)
  5040.  
  5041. #define _PCH_TRANSB_DATA_M1     0xe1030
  5042. #define _PCH_TRANSB_DATA_N1     0xe1034
  5043. #define _PCH_TRANSB_DATA_M2     0xe1038
  5044. #define _PCH_TRANSB_DATA_N2     0xe103c
  5045. #define _PCH_TRANSB_LINK_M1     0xe1040
  5046. #define _PCH_TRANSB_LINK_N1     0xe1044
  5047. #define _PCH_TRANSB_LINK_M2     0xe1048
  5048. #define _PCH_TRANSB_LINK_N2     0xe104c
  5049.  
  5050. #define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
  5051. #define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
  5052. #define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
  5053. #define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
  5054. #define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
  5055. #define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
  5056. #define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
  5057. #define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
  5058.  
  5059. #define _PCH_TRANSACONF              0xf0008
  5060. #define _PCH_TRANSBCONF              0xf1008
  5061. #define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
  5062. #define LPT_TRANSCONF           _PCH_TRANSACONF /* lpt has only one transcoder */
  5063. #define  TRANS_DISABLE          (0<<31)
  5064. #define  TRANS_ENABLE           (1<<31)
  5065. #define  TRANS_STATE_MASK       (1<<30)
  5066. #define  TRANS_STATE_DISABLE    (0<<30)
  5067. #define  TRANS_STATE_ENABLE     (1<<30)
  5068. #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
  5069. #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
  5070. #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
  5071. #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
  5072. #define  TRANS_INTERLACE_MASK   (7<<21)
  5073. #define  TRANS_PROGRESSIVE      (0<<21)
  5074. #define  TRANS_INTERLACED       (3<<21)
  5075. #define  TRANS_LEGACY_INTERLACED_ILK (2<<21)
  5076. #define  TRANS_8BPC             (0<<5)
  5077. #define  TRANS_10BPC            (1<<5)
  5078. #define  TRANS_6BPC             (2<<5)
  5079. #define  TRANS_12BPC            (3<<5)
  5080.  
  5081. #define _TRANSA_CHICKEN1         0xf0060
  5082. #define _TRANSB_CHICKEN1         0xf1060
  5083. #define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
  5084. #define  TRANS_CHICKEN1_DP0UNIT_GC_DISABLE      (1<<4)
  5085. #define _TRANSA_CHICKEN2         0xf0064
  5086. #define _TRANSB_CHICKEN2         0xf1064
  5087. #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
  5088. #define  TRANS_CHICKEN2_TIMING_OVERRIDE         (1<<31)
  5089. #define  TRANS_CHICKEN2_FDI_POLARITY_REVERSED           (1<<29)
  5090. #define  TRANS_CHICKEN2_FRAME_START_DELAY_MASK          (3<<27)
  5091. #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER      (1<<26)
  5092. #define  TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH   (1<<25)
  5093.  
  5094. #define SOUTH_CHICKEN1          0xc2000
  5095. #define  FDIA_PHASE_SYNC_SHIFT_OVR      19
  5096. #define  FDIA_PHASE_SYNC_SHIFT_EN       18
  5097. #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
  5098. #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
  5099. #define  FDI_BC_BIFURCATION_SELECT      (1 << 12)
  5100. #define SOUTH_CHICKEN2          0xc2004
  5101. #define  FDI_MPHY_IOSFSB_RESET_STATUS   (1<<13)
  5102. #define  FDI_MPHY_IOSFSB_RESET_CTL      (1<<12)
  5103. #define  DPLS_EDP_PPS_FIX_DIS   (1<<0)
  5104.  
  5105. #define _FDI_RXA_CHICKEN         0xc200c
  5106. #define _FDI_RXB_CHICKEN         0xc2010
  5107. #define  FDI_RX_PHASE_SYNC_POINTER_OVR  (1<<1)
  5108. #define  FDI_RX_PHASE_SYNC_POINTER_EN   (1<<0)
  5109. #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
  5110.  
  5111. #define SOUTH_DSPCLK_GATE_D     0xc2020
  5112. #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
  5113. #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
  5114. #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
  5115. #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
  5116.  
  5117. /* CPU: FDI_TX */
  5118. #define _FDI_TXA_CTL             0x60100
  5119. #define _FDI_TXB_CTL             0x61100
  5120. #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
  5121. #define  FDI_TX_DISABLE         (0<<31)
  5122. #define  FDI_TX_ENABLE          (1<<31)
  5123. #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
  5124. #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
  5125. #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
  5126. #define  FDI_LINK_TRAIN_NONE            (3<<28)
  5127. #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
  5128. #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
  5129. #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
  5130. #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
  5131. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
  5132. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
  5133. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
  5134. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
  5135. /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
  5136.    SNB has different settings. */
  5137. /* SNB A-stepping */
  5138. #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
  5139. #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
  5140. #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
  5141. #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
  5142. /* SNB B-stepping */
  5143. #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B         (0x0<<22)
  5144. #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B         (0x3a<<22)
  5145. #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B       (0x39<<22)
  5146. #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B         (0x38<<22)
  5147. #define  FDI_LINK_TRAIN_VOL_EMP_MASK            (0x3f<<22)
  5148. #define  FDI_DP_PORT_WIDTH_SHIFT                19
  5149. #define  FDI_DP_PORT_WIDTH_MASK                 (7 << FDI_DP_PORT_WIDTH_SHIFT)
  5150. #define  FDI_DP_PORT_WIDTH(width)           (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
  5151. #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
  5152. /* Ironlake: hardwired to 1 */
  5153. #define  FDI_TX_PLL_ENABLE              (1<<14)
  5154.  
  5155. /* Ivybridge has different bits for lolz */
  5156. #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
  5157. #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
  5158. #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
  5159. #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
  5160.  
  5161. /* both Tx and Rx */
  5162. #define  FDI_COMPOSITE_SYNC             (1<<11)
  5163. #define  FDI_LINK_TRAIN_AUTO            (1<<10)
  5164. #define  FDI_SCRAMBLING_ENABLE          (0<<7)
  5165. #define  FDI_SCRAMBLING_DISABLE         (1<<7)
  5166.  
  5167. /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
  5168. #define _FDI_RXA_CTL             0xf000c
  5169. #define _FDI_RXB_CTL             0xf100c
  5170. #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
  5171. #define  FDI_RX_ENABLE          (1<<31)
  5172. /* train, dp width same as FDI_TX */
  5173. #define  FDI_FS_ERRC_ENABLE             (1<<27)
  5174. #define  FDI_FE_ERRC_ENABLE             (1<<26)
  5175. #define  FDI_RX_POLARITY_REVERSED_LPT   (1<<16)
  5176. #define  FDI_8BPC                       (0<<16)
  5177. #define  FDI_10BPC                      (1<<16)
  5178. #define  FDI_6BPC                       (2<<16)
  5179. #define  FDI_12BPC                      (3<<16)
  5180. #define  FDI_RX_LINK_REVERSAL_OVERRIDE  (1<<15)
  5181. #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
  5182. #define  FDI_RX_PLL_ENABLE              (1<<13)
  5183. #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
  5184. #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
  5185. #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
  5186. #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
  5187. #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
  5188. #define  FDI_PCDCLK                     (1<<4)
  5189. /* CPT */
  5190. #define  FDI_AUTO_TRAINING                      (1<<10)
  5191. #define  FDI_LINK_TRAIN_PATTERN_1_CPT           (0<<8)
  5192. #define  FDI_LINK_TRAIN_PATTERN_2_CPT           (1<<8)
  5193. #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT        (2<<8)
  5194. #define  FDI_LINK_TRAIN_NORMAL_CPT              (3<<8)
  5195. #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT        (3<<8)
  5196.  
  5197. #define _FDI_RXA_MISC            0xf0010
  5198. #define _FDI_RXB_MISC            0xf1010
  5199. #define  FDI_RX_PWRDN_LANE1_MASK        (3<<26)
  5200. #define  FDI_RX_PWRDN_LANE1_VAL(x)      ((x)<<26)
  5201. #define  FDI_RX_PWRDN_LANE0_MASK        (3<<24)
  5202. #define  FDI_RX_PWRDN_LANE0_VAL(x)      ((x)<<24)
  5203. #define  FDI_RX_TP1_TO_TP2_48           (2<<20)
  5204. #define  FDI_RX_TP1_TO_TP2_64           (3<<20)
  5205. #define  FDI_RX_FDI_DELAY_90            (0x90<<0)
  5206. #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
  5207.  
  5208. #define _FDI_RXA_TUSIZE1         0xf0030
  5209. #define _FDI_RXA_TUSIZE2         0xf0038
  5210. #define _FDI_RXB_TUSIZE1         0xf1030
  5211. #define _FDI_RXB_TUSIZE2         0xf1038
  5212. #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
  5213. #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
  5214.  
  5215. /* FDI_RX interrupt register format */
  5216. #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
  5217. #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
  5218. #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
  5219. #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
  5220. #define FDI_RX_FS_CODE_ERR              (1<<6)
  5221. #define FDI_RX_FE_CODE_ERR              (1<<5)
  5222. #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
  5223. #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
  5224. #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
  5225. #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
  5226. #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
  5227.  
  5228. #define _FDI_RXA_IIR             0xf0014
  5229. #define _FDI_RXA_IMR             0xf0018
  5230. #define _FDI_RXB_IIR             0xf1014
  5231. #define _FDI_RXB_IMR             0xf1018
  5232. #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
  5233. #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
  5234.  
  5235. #define FDI_PLL_CTL_1           0xfe000
  5236. #define FDI_PLL_CTL_2           0xfe004
  5237.  
  5238. #define PCH_LVDS        0xe1180
  5239. #define  LVDS_DETECTED  (1 << 1)
  5240.  
  5241. /* vlv has 2 sets of panel control regs. */
  5242. #define PIPEA_PP_STATUS         (VLV_DISPLAY_BASE + 0x61200)
  5243. #define PIPEA_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61204)
  5244. #define PIPEA_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61208)
  5245. #define  PANEL_PORT_SELECT_DPB_VLV      (1 << 30)
  5246. #define  PANEL_PORT_SELECT_DPC_VLV      (2 << 30)
  5247. #define PIPEA_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6120c)
  5248. #define PIPEA_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61210)
  5249.  
  5250. #define PIPEB_PP_STATUS         (VLV_DISPLAY_BASE + 0x61300)
  5251. #define PIPEB_PP_CONTROL        (VLV_DISPLAY_BASE + 0x61304)
  5252. #define PIPEB_PP_ON_DELAYS      (VLV_DISPLAY_BASE + 0x61308)
  5253. #define PIPEB_PP_OFF_DELAYS     (VLV_DISPLAY_BASE + 0x6130c)
  5254. #define PIPEB_PP_DIVISOR        (VLV_DISPLAY_BASE + 0x61310)
  5255.  
  5256. #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
  5257. #define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
  5258. #define VLV_PIPE_PP_ON_DELAYS(pipe) \
  5259.                 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
  5260. #define VLV_PIPE_PP_OFF_DELAYS(pipe) \
  5261.                 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
  5262. #define VLV_PIPE_PP_DIVISOR(pipe) \
  5263.                 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
  5264.  
  5265. #define PCH_PP_STATUS           0xc7200
  5266. #define PCH_PP_CONTROL          0xc7204
  5267. #define  PANEL_UNLOCK_REGS      (0xabcd << 16)
  5268. #define  PANEL_UNLOCK_MASK      (0xffff << 16)
  5269. #define  EDP_FORCE_VDD          (1 << 3)
  5270. #define  EDP_BLC_ENABLE         (1 << 2)
  5271. #define  PANEL_POWER_RESET      (1 << 1)
  5272. #define  PANEL_POWER_OFF        (0 << 0)
  5273. #define  PANEL_POWER_ON         (1 << 0)
  5274. #define PCH_PP_ON_DELAYS        0xc7208
  5275. #define  PANEL_PORT_SELECT_MASK (3 << 30)
  5276. #define  PANEL_PORT_SELECT_LVDS (0 << 30)
  5277. #define  PANEL_PORT_SELECT_DPA  (1 << 30)
  5278. #define  PANEL_PORT_SELECT_DPC  (2 << 30)
  5279. #define  PANEL_PORT_SELECT_DPD  (3 << 30)
  5280. #define  PANEL_POWER_UP_DELAY_MASK      (0x1fff0000)
  5281. #define  PANEL_POWER_UP_DELAY_SHIFT     16
  5282. #define  PANEL_LIGHT_ON_DELAY_MASK      (0x1fff)
  5283. #define  PANEL_LIGHT_ON_DELAY_SHIFT     0
  5284.  
  5285. #define PCH_PP_OFF_DELAYS       0xc720c
  5286. #define  PANEL_POWER_DOWN_DELAY_MASK    (0x1fff0000)
  5287. #define  PANEL_POWER_DOWN_DELAY_SHIFT   16
  5288. #define  PANEL_LIGHT_OFF_DELAY_MASK     (0x1fff)
  5289. #define  PANEL_LIGHT_OFF_DELAY_SHIFT    0
  5290.  
  5291. #define PCH_PP_DIVISOR          0xc7210
  5292. #define  PP_REFERENCE_DIVIDER_MASK      (0xffffff00)
  5293. #define  PP_REFERENCE_DIVIDER_SHIFT     8
  5294. #define  PANEL_POWER_CYCLE_DELAY_MASK   (0x1f)
  5295. #define  PANEL_POWER_CYCLE_DELAY_SHIFT  0
  5296.  
  5297. #define PCH_DP_B                0xe4100
  5298. #define PCH_DPB_AUX_CH_CTL      0xe4110
  5299. #define PCH_DPB_AUX_CH_DATA1    0xe4114
  5300. #define PCH_DPB_AUX_CH_DATA2    0xe4118
  5301. #define PCH_DPB_AUX_CH_DATA3    0xe411c
  5302. #define PCH_DPB_AUX_CH_DATA4    0xe4120
  5303. #define PCH_DPB_AUX_CH_DATA5    0xe4124
  5304.  
  5305. #define PCH_DP_C                0xe4200
  5306. #define PCH_DPC_AUX_CH_CTL      0xe4210
  5307. #define PCH_DPC_AUX_CH_DATA1    0xe4214
  5308. #define PCH_DPC_AUX_CH_DATA2    0xe4218
  5309. #define PCH_DPC_AUX_CH_DATA3    0xe421c
  5310. #define PCH_DPC_AUX_CH_DATA4    0xe4220
  5311. #define PCH_DPC_AUX_CH_DATA5    0xe4224
  5312.  
  5313. #define PCH_DP_D                0xe4300
  5314. #define PCH_DPD_AUX_CH_CTL      0xe4310
  5315. #define PCH_DPD_AUX_CH_DATA1    0xe4314
  5316. #define PCH_DPD_AUX_CH_DATA2    0xe4318
  5317. #define PCH_DPD_AUX_CH_DATA3    0xe431c
  5318. #define PCH_DPD_AUX_CH_DATA4    0xe4320
  5319. #define PCH_DPD_AUX_CH_DATA5    0xe4324
  5320.  
  5321. /* CPT */
  5322. #define  PORT_TRANS_A_SEL_CPT   0
  5323. #define  PORT_TRANS_B_SEL_CPT   (1<<29)
  5324. #define  PORT_TRANS_C_SEL_CPT   (2<<29)
  5325. #define  PORT_TRANS_SEL_MASK    (3<<29)
  5326. #define  PORT_TRANS_SEL_CPT(pipe)       ((pipe) << 29)
  5327. #define  PORT_TO_PIPE(val)      (((val) & (1<<30)) >> 30)
  5328. #define  PORT_TO_PIPE_CPT(val)  (((val) & PORT_TRANS_SEL_MASK) >> 29)
  5329. #define  SDVO_PORT_TO_PIPE_CHV(val)     (((val) & (3<<24)) >> 24)
  5330. #define  DP_PORT_TO_PIPE_CHV(val)       (((val) & (3<<16)) >> 16)
  5331.  
  5332. #define TRANS_DP_CTL_A          0xe0300
  5333. #define TRANS_DP_CTL_B          0xe1300
  5334. #define TRANS_DP_CTL_C          0xe2300
  5335. #define TRANS_DP_CTL(pipe)      _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
  5336. #define  TRANS_DP_OUTPUT_ENABLE (1<<31)
  5337. #define  TRANS_DP_PORT_SEL_B    (0<<29)
  5338. #define  TRANS_DP_PORT_SEL_C    (1<<29)
  5339. #define  TRANS_DP_PORT_SEL_D    (2<<29)
  5340. #define  TRANS_DP_PORT_SEL_NONE (3<<29)
  5341. #define  TRANS_DP_PORT_SEL_MASK (3<<29)
  5342. #define  TRANS_DP_AUDIO_ONLY    (1<<26)
  5343. #define  TRANS_DP_ENH_FRAMING   (1<<18)
  5344. #define  TRANS_DP_8BPC          (0<<9)
  5345. #define  TRANS_DP_10BPC         (1<<9)
  5346. #define  TRANS_DP_6BPC          (2<<9)
  5347. #define  TRANS_DP_12BPC         (3<<9)
  5348. #define  TRANS_DP_BPC_MASK      (3<<9)
  5349. #define  TRANS_DP_VSYNC_ACTIVE_HIGH     (1<<4)
  5350. #define  TRANS_DP_VSYNC_ACTIVE_LOW      0
  5351. #define  TRANS_DP_HSYNC_ACTIVE_HIGH     (1<<3)
  5352. #define  TRANS_DP_HSYNC_ACTIVE_LOW      0
  5353. #define  TRANS_DP_SYNC_MASK     (3<<3)
  5354.  
  5355. /* SNB eDP training params */
  5356. /* SNB A-stepping */
  5357. #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
  5358. #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
  5359. #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
  5360. #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
  5361. /* SNB B-stepping */
  5362. #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B     (0x0<<22)
  5363. #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B       (0x1<<22)
  5364. #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B     (0x3a<<22)
  5365. #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B   (0x39<<22)
  5366. #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B    (0x38<<22)
  5367. #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB        (0x3f<<22)
  5368.  
  5369. /* IVB */
  5370. #define EDP_LINK_TRAIN_400MV_0DB_IVB            (0x24 <<22)
  5371. #define EDP_LINK_TRAIN_400MV_3_5DB_IVB          (0x2a <<22)
  5372. #define EDP_LINK_TRAIN_400MV_6DB_IVB            (0x2f <<22)
  5373. #define EDP_LINK_TRAIN_600MV_0DB_IVB            (0x30 <<22)
  5374. #define EDP_LINK_TRAIN_600MV_3_5DB_IVB          (0x36 <<22)
  5375. #define EDP_LINK_TRAIN_800MV_0DB_IVB            (0x38 <<22)
  5376. #define EDP_LINK_TRAIN_800MV_3_5DB_IVB          (0x3e <<22)
  5377.  
  5378. /* legacy values */
  5379. #define EDP_LINK_TRAIN_500MV_0DB_IVB            (0x00 <<22)
  5380. #define EDP_LINK_TRAIN_1000MV_0DB_IVB           (0x20 <<22)
  5381. #define EDP_LINK_TRAIN_500MV_3_5DB_IVB          (0x02 <<22)
  5382. #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB         (0x22 <<22)
  5383. #define EDP_LINK_TRAIN_1000MV_6DB_IVB           (0x23 <<22)
  5384.  
  5385. #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB        (0x3f<<22)
  5386.  
  5387. #define  VLV_PMWGICZ                            0x1300a4
  5388.  
  5389. #define  FORCEWAKE                              0xA18C
  5390. #define  FORCEWAKE_VLV                          0x1300b0
  5391. #define  FORCEWAKE_ACK_VLV                      0x1300b4
  5392. #define  FORCEWAKE_MEDIA_VLV                    0x1300b8
  5393. #define  FORCEWAKE_ACK_MEDIA_VLV                0x1300bc
  5394. #define  FORCEWAKE_ACK_HSW                      0x130044
  5395. #define  FORCEWAKE_ACK                          0x130090
  5396. #define  VLV_GTLC_WAKE_CTRL                     0x130090
  5397. #define   VLV_GTLC_RENDER_CTX_EXISTS            (1 << 25)
  5398. #define   VLV_GTLC_MEDIA_CTX_EXISTS             (1 << 24)
  5399. #define   VLV_GTLC_ALLOWWAKEREQ                 (1 << 0)
  5400.  
  5401. #define  VLV_GTLC_PW_STATUS                     0x130094
  5402. #define   VLV_GTLC_ALLOWWAKEACK                 (1 << 0)
  5403. #define   VLV_GTLC_ALLOWWAKEERR                 (1 << 1)
  5404. #define   VLV_GTLC_PW_MEDIA_STATUS_MASK         (1 << 5)
  5405. #define   VLV_GTLC_PW_RENDER_STATUS_MASK        (1 << 7)
  5406. #define VLV_GTLC_SURVIVABILITY_REG              0x130098
  5407. #define  FORCEWAKE_MT                           0xa188 /* multi-threaded */
  5408. #define   FORCEWAKE_KERNEL                      0x1
  5409. #define   FORCEWAKE_USER                        0x2
  5410. #define  FORCEWAKE_MT_ACK                       0x130040
  5411. #define  ECOBUS                                 0xa180
  5412. #define    FORCEWAKE_MT_ENABLE                  (1<<5)
  5413. #define  VLV_SPAREG2H                           0xA194
  5414.  
  5415. #define  GTFIFODBG                              0x120000
  5416. #define    GT_FIFO_SBDROPERR                    (1<<6)
  5417. #define    GT_FIFO_BLOBDROPERR                  (1<<5)
  5418. #define    GT_FIFO_SB_READ_ABORTERR             (1<<4)
  5419. #define    GT_FIFO_DROPERR                      (1<<3)
  5420. #define    GT_FIFO_OVFERR                       (1<<2)
  5421. #define    GT_FIFO_IAWRERR                      (1<<1)
  5422. #define    GT_FIFO_IARDERR                      (1<<0)
  5423.  
  5424. #define  GTFIFOCTL                              0x120008
  5425. #define    GT_FIFO_FREE_ENTRIES_MASK            0x7f
  5426. #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
  5427.  
  5428. #define  HSW_IDICR                              0x9008
  5429. #define    IDIHASHMSK(x)                        (((x) & 0x3f) << 16)
  5430. #define  HSW_EDRAM_PRESENT                      0x120010
  5431.  
  5432. #define GEN6_UCGCTL1                            0x9400
  5433. # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE              (1 << 16)
  5434. # define GEN6_BLBUNIT_CLOCK_GATE_DISABLE                (1 << 5)
  5435. # define GEN6_CSUNIT_CLOCK_GATE_DISABLE                 (1 << 7)
  5436.  
  5437. #define GEN6_UCGCTL2                            0x9404
  5438. # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE                (1 << 30)
  5439. # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE                (1 << 22)
  5440. # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE                (1 << 13)
  5441. # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE               (1 << 12)
  5442. # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE                (1 << 11)
  5443.  
  5444. #define GEN6_UCGCTL3                            0x9408
  5445.  
  5446. #define GEN7_UCGCTL4                            0x940c
  5447. #define  GEN7_L3BANK2X_CLOCK_GATE_DISABLE       (1<<25)
  5448.  
  5449. #define GEN6_RCGCTL1                            0x9410
  5450. #define GEN6_RCGCTL2                            0x9414
  5451. #define GEN6_RSTCTL                             0x9420
  5452.  
  5453. #define GEN8_UCGCTL6                            0x9430
  5454. #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE       (1<<14)
  5455.  
  5456. #define GEN6_GFXPAUSE                           0xA000
  5457. #define GEN6_RPNSWREQ                           0xA008
  5458. #define   GEN6_TURBO_DISABLE                    (1<<31)
  5459. #define   GEN6_FREQUENCY(x)                     ((x)<<25)
  5460. #define   HSW_FREQUENCY(x)                      ((x)<<24)
  5461. #define   GEN6_OFFSET(x)                        ((x)<<19)
  5462. #define   GEN6_AGGRESSIVE_TURBO                 (0<<15)
  5463. #define GEN6_RC_VIDEO_FREQ                      0xA00C
  5464. #define GEN6_RC_CONTROL                         0xA090
  5465. #define   GEN6_RC_CTL_RC6pp_ENABLE              (1<<16)
  5466. #define   GEN6_RC_CTL_RC6p_ENABLE               (1<<17)
  5467. #define   GEN6_RC_CTL_RC6_ENABLE                (1<<18)
  5468. #define   GEN6_RC_CTL_RC1e_ENABLE               (1<<20)
  5469. #define   GEN6_RC_CTL_RC7_ENABLE                (1<<22)
  5470. #define   VLV_RC_CTL_CTX_RST_PARALLEL           (1<<24)
  5471. #define   GEN7_RC_CTL_TO_MODE                   (1<<28)
  5472. #define   GEN6_RC_CTL_EI_MODE(x)                ((x)<<27)
  5473. #define   GEN6_RC_CTL_HW_ENABLE                 (1<<31)
  5474. #define GEN6_RP_DOWN_TIMEOUT                    0xA010
  5475. #define GEN6_RP_INTERRUPT_LIMITS                0xA014
  5476. #define GEN6_RPSTAT1                            0xA01C
  5477. #define   GEN6_CAGF_SHIFT                       8
  5478. #define   HSW_CAGF_SHIFT                        7
  5479. #define   GEN6_CAGF_MASK                        (0x7f << GEN6_CAGF_SHIFT)
  5480. #define   HSW_CAGF_MASK                         (0x7f << HSW_CAGF_SHIFT)
  5481. #define GEN6_RP_CONTROL                         0xA024
  5482. #define   GEN6_RP_MEDIA_TURBO                   (1<<11)
  5483. #define   GEN6_RP_MEDIA_MODE_MASK               (3<<9)
  5484. #define   GEN6_RP_MEDIA_HW_TURBO_MODE           (3<<9)
  5485. #define   GEN6_RP_MEDIA_HW_NORMAL_MODE          (2<<9)
  5486. #define   GEN6_RP_MEDIA_HW_MODE                 (1<<9)
  5487. #define   GEN6_RP_MEDIA_SW_MODE                 (0<<9)
  5488. #define   GEN6_RP_MEDIA_IS_GFX                  (1<<8)
  5489. #define   GEN6_RP_ENABLE                        (1<<7)
  5490. #define   GEN6_RP_UP_IDLE_MIN                   (0x1<<3)
  5491. #define   GEN6_RP_UP_BUSY_AVG                   (0x2<<3)
  5492. #define   GEN6_RP_UP_BUSY_CONT                  (0x4<<3)
  5493. #define   GEN6_RP_DOWN_IDLE_AVG                 (0x2<<0)
  5494. #define   GEN6_RP_DOWN_IDLE_CONT                (0x1<<0)
  5495. #define GEN6_RP_UP_THRESHOLD                    0xA02C
  5496. #define GEN6_RP_DOWN_THRESHOLD                  0xA030
  5497. #define GEN6_RP_CUR_UP_EI                       0xA050
  5498. #define   GEN6_CURICONT_MASK                    0xffffff
  5499. #define GEN6_RP_CUR_UP                          0xA054
  5500. #define   GEN6_CURBSYTAVG_MASK                  0xffffff
  5501. #define GEN6_RP_PREV_UP                         0xA058
  5502. #define GEN6_RP_CUR_DOWN_EI                     0xA05C
  5503. #define   GEN6_CURIAVG_MASK                     0xffffff
  5504. #define GEN6_RP_CUR_DOWN                        0xA060
  5505. #define GEN6_RP_PREV_DOWN                       0xA064
  5506. #define GEN6_RP_UP_EI                           0xA068
  5507. #define GEN6_RP_DOWN_EI                         0xA06C
  5508. #define GEN6_RP_IDLE_HYSTERSIS                  0xA070
  5509. #define GEN6_RPDEUHWTC                          0xA080
  5510. #define GEN6_RPDEUC                             0xA084
  5511. #define GEN6_RPDEUCSW                           0xA088
  5512. #define GEN6_RC_STATE                           0xA094
  5513. #define GEN6_RC1_WAKE_RATE_LIMIT                0xA098
  5514. #define GEN6_RC6_WAKE_RATE_LIMIT                0xA09C
  5515. #define GEN6_RC6pp_WAKE_RATE_LIMIT              0xA0A0
  5516. #define GEN6_RC_EVALUATION_INTERVAL             0xA0A8
  5517. #define GEN6_RC_IDLE_HYSTERSIS                  0xA0AC
  5518. #define GEN6_RC_SLEEP                           0xA0B0
  5519. #define GEN6_RCUBMABDTMR                        0xA0B0
  5520. #define GEN6_RC1e_THRESHOLD                     0xA0B4
  5521. #define GEN6_RC6_THRESHOLD                      0xA0B8
  5522. #define GEN6_RC6p_THRESHOLD                     0xA0BC
  5523. #define VLV_RCEDATA                             0xA0BC
  5524. #define GEN6_RC6pp_THRESHOLD                    0xA0C0
  5525. #define GEN6_PMINTRMSK                          0xA168
  5526. #define GEN8_PMINTR_REDIRECT_TO_NON_DISP        (1<<31)
  5527. #define VLV_PWRDWNUPCTL                         0xA294
  5528.  
  5529. #define GEN6_PMISR                              0x44020
  5530. #define GEN6_PMIMR                              0x44024 /* rps_lock */
  5531. #define GEN6_PMIIR                              0x44028
  5532. #define GEN6_PMIER                              0x4402C
  5533. #define  GEN6_PM_MBOX_EVENT                     (1<<25)
  5534. #define  GEN6_PM_THERMAL_EVENT                  (1<<24)
  5535. #define  GEN6_PM_RP_DOWN_TIMEOUT                (1<<6)
  5536. #define  GEN6_PM_RP_UP_THRESHOLD                (1<<5)
  5537. #define  GEN6_PM_RP_DOWN_THRESHOLD              (1<<4)
  5538. #define  GEN6_PM_RP_UP_EI_EXPIRED               (1<<2)
  5539. #define  GEN6_PM_RP_DOWN_EI_EXPIRED             (1<<1)
  5540. #define  GEN6_PM_RPS_EVENTS                     (GEN6_PM_RP_UP_THRESHOLD | \
  5541.                                                  GEN6_PM_RP_DOWN_THRESHOLD | \
  5542.                                                  GEN6_PM_RP_DOWN_TIMEOUT)
  5543.  
  5544. #define CHV_CZ_CLOCK_FREQ_MODE_200                      200
  5545. #define CHV_CZ_CLOCK_FREQ_MODE_267                      267
  5546. #define CHV_CZ_CLOCK_FREQ_MODE_320                      320
  5547. #define CHV_CZ_CLOCK_FREQ_MODE_333                      333
  5548. #define CHV_CZ_CLOCK_FREQ_MODE_400                      400
  5549.  
  5550. #define GEN7_GT_SCRATCH_BASE                    0x4F100
  5551. #define GEN7_GT_SCRATCH_REG_NUM                 8
  5552.  
  5553. #define VLV_GTLC_SURVIVABILITY_REG              0x130098
  5554. #define VLV_GFX_CLK_STATUS_BIT                  (1<<3)
  5555. #define VLV_GFX_CLK_FORCE_ON_BIT                (1<<2)
  5556.  
  5557. #define GEN6_GT_GFX_RC6_LOCKED                  0x138104
  5558. #define VLV_COUNTER_CONTROL                     0x138104
  5559. #define   VLV_COUNT_RANGE_HIGH                  (1<<15)
  5560. #define   VLV_MEDIA_RC0_COUNT_EN                (1<<5)
  5561. #define   VLV_RENDER_RC0_COUNT_EN               (1<<4)
  5562. #define   VLV_MEDIA_RC6_COUNT_EN                (1<<1)
  5563. #define   VLV_RENDER_RC6_COUNT_EN               (1<<0)
  5564. #define GEN6_GT_GFX_RC6                         0x138108
  5565. #define VLV_GT_RENDER_RC6                       0x138108
  5566. #define VLV_GT_MEDIA_RC6                        0x13810C
  5567.  
  5568. #define GEN6_GT_GFX_RC6p                        0x13810C
  5569. #define GEN6_GT_GFX_RC6pp                       0x138110
  5570. #define VLV_RENDER_C0_COUNT_REG         0x138118
  5571. #define VLV_MEDIA_C0_COUNT_REG                  0x13811C
  5572.  
  5573. #define GEN6_PCODE_MAILBOX                      0x138124
  5574. #define   GEN6_PCODE_READY                      (1<<31)
  5575. #define   GEN6_READ_OC_PARAMS                   0xc
  5576. #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x8
  5577. #define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
  5578. #define   GEN6_PCODE_WRITE_RC6VIDS              0x4
  5579. #define   GEN6_PCODE_READ_RC6VIDS               0x5
  5580. #define   GEN6_PCODE_READ_D_COMP                0x10
  5581. #define   GEN6_PCODE_WRITE_D_COMP               0x11
  5582. #define   GEN6_ENCODE_RC6_VID(mv)               (((mv) - 245) / 5)
  5583. #define   GEN6_DECODE_RC6_VID(vids)             (((vids) * 5) + 245)
  5584. #define   DISPLAY_IPS_CONTROL                   0x19
  5585. #define GEN6_PCODE_DATA                         0x138128
  5586. #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT        8
  5587. #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT      16
  5588.  
  5589. #define GEN6_GT_CORE_STATUS             0x138060
  5590. #define   GEN6_CORE_CPD_STATE_MASK      (7<<4)
  5591. #define   GEN6_RCn_MASK                 7
  5592. #define   GEN6_RC0                      0
  5593. #define   GEN6_RC3                      2
  5594. #define   GEN6_RC6                      3
  5595. #define   GEN6_RC7                      4
  5596.  
  5597. #define GEN7_MISCCPCTL                  (0x9424)
  5598. #define   GEN7_DOP_CLOCK_GATE_ENABLE    (1<<0)
  5599.  
  5600. /* IVYBRIDGE DPF */
  5601. #define GEN7_L3CDERRST1                 0xB008 /* L3CD Error Status 1 */
  5602. #define HSW_L3CDERRST11                 0xB208 /* L3CD Error Status register 1 slice 1 */
  5603. #define   GEN7_L3CDERRST1_ROW_MASK      (0x7ff<<14)
  5604. #define   GEN7_PARITY_ERROR_VALID       (1<<13)
  5605. #define   GEN7_L3CDERRST1_BANK_MASK     (3<<11)
  5606. #define   GEN7_L3CDERRST1_SUBBANK_MASK  (7<<8)
  5607. #define GEN7_PARITY_ERROR_ROW(reg) \
  5608.                 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
  5609. #define GEN7_PARITY_ERROR_BANK(reg) \
  5610.                 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
  5611. #define GEN7_PARITY_ERROR_SUBBANK(reg) \
  5612.                 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
  5613. #define   GEN7_L3CDERRST1_ENABLE        (1<<7)
  5614.  
  5615. #define GEN7_L3LOG_BASE                 0xB070
  5616. #define HSW_L3LOG_BASE_SLICE1           0xB270
  5617. #define GEN7_L3LOG_SIZE                 0x80
  5618.  
  5619. #define GEN7_HALF_SLICE_CHICKEN1        0xe100 /* IVB GT1 + VLV */
  5620. #define GEN7_HALF_SLICE_CHICKEN1_GT2    0xf100
  5621. #define   GEN7_MAX_PS_THREAD_DEP                (8<<12)
  5622. #define   GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE   (1<<10)
  5623. #define   GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE  (1<<3)
  5624.  
  5625. #define GEN8_ROW_CHICKEN                0xe4f0
  5626. #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
  5627. #define   STALL_DOP_GATING_DISABLE              (1<<5)
  5628.  
  5629. #define GEN7_ROW_CHICKEN2               0xe4f4
  5630. #define GEN7_ROW_CHICKEN2_GT2           0xf4f4
  5631. #define   DOP_CLOCK_GATING_DISABLE      (1<<0)
  5632.  
  5633. #define HSW_ROW_CHICKEN3                0xe49c
  5634. #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
  5635.  
  5636. #define HALF_SLICE_CHICKEN3             0xe184
  5637. #define   GEN8_CENTROID_PIXEL_OPT_DIS   (1<<8)
  5638. #define   GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
  5639.  
  5640. #define G4X_AUD_VID_DID                 (dev_priv->info.display_mmio_offset + 0x62020)
  5641. #define INTEL_AUDIO_DEVCL               0x808629FB
  5642. #define INTEL_AUDIO_DEVBLC              0x80862801
  5643. #define INTEL_AUDIO_DEVCTG              0x80862802
  5644.  
  5645. #define G4X_AUD_CNTL_ST                 0x620B4
  5646. #define G4X_ELDV_DEVCL_DEVBLC           (1 << 13)
  5647. #define G4X_ELDV_DEVCTG                 (1 << 14)
  5648. #define G4X_ELD_ADDR                    (0xf << 5)
  5649. #define G4X_ELD_ACK                     (1 << 4)
  5650. #define G4X_HDMIW_HDMIEDID              0x6210C
  5651.  
  5652. #define IBX_HDMIW_HDMIEDID_A            0xE2050
  5653. #define IBX_HDMIW_HDMIEDID_B            0xE2150
  5654. #define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
  5655.                                         IBX_HDMIW_HDMIEDID_A, \
  5656.                                         IBX_HDMIW_HDMIEDID_B)
  5657. #define IBX_AUD_CNTL_ST_A               0xE20B4
  5658. #define IBX_AUD_CNTL_ST_B               0xE21B4
  5659. #define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
  5660.                                         IBX_AUD_CNTL_ST_A, \
  5661.                                         IBX_AUD_CNTL_ST_B)
  5662. #define IBX_ELD_BUFFER_SIZE             (0x1f << 10)
  5663. #define IBX_ELD_ADDRESS                 (0x1f << 5)
  5664. #define IBX_ELD_ACK                     (1 << 4)
  5665. #define IBX_AUD_CNTL_ST2                0xE20C0
  5666. #define IBX_ELD_VALIDB                  (1 << 0)
  5667. #define IBX_CP_READYB                   (1 << 1)
  5668.  
  5669. #define CPT_HDMIW_HDMIEDID_A            0xE5050
  5670. #define CPT_HDMIW_HDMIEDID_B            0xE5150
  5671. #define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
  5672.                                         CPT_HDMIW_HDMIEDID_A, \
  5673.                                         CPT_HDMIW_HDMIEDID_B)
  5674. #define CPT_AUD_CNTL_ST_A               0xE50B4
  5675. #define CPT_AUD_CNTL_ST_B               0xE51B4
  5676. #define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
  5677.                                         CPT_AUD_CNTL_ST_A, \
  5678.                                         CPT_AUD_CNTL_ST_B)
  5679. #define CPT_AUD_CNTRL_ST2               0xE50C0
  5680.  
  5681. #define VLV_HDMIW_HDMIEDID_A            (VLV_DISPLAY_BASE + 0x62050)
  5682. #define VLV_HDMIW_HDMIEDID_B            (VLV_DISPLAY_BASE + 0x62150)
  5683. #define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
  5684.                                         VLV_HDMIW_HDMIEDID_A, \
  5685.                                         VLV_HDMIW_HDMIEDID_B)
  5686. #define VLV_AUD_CNTL_ST_A               (VLV_DISPLAY_BASE + 0x620B4)
  5687. #define VLV_AUD_CNTL_ST_B               (VLV_DISPLAY_BASE + 0x621B4)
  5688. #define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
  5689.                                         VLV_AUD_CNTL_ST_A, \
  5690.                                         VLV_AUD_CNTL_ST_B)
  5691. #define VLV_AUD_CNTL_ST2                (VLV_DISPLAY_BASE + 0x620C0)
  5692.  
  5693. /* These are the 4 32-bit write offset registers for each stream
  5694.  * output buffer.  It determines the offset from the
  5695.  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
  5696.  */
  5697. #define GEN7_SO_WRITE_OFFSET(n)         (0x5280 + (n) * 4)
  5698.  
  5699. #define IBX_AUD_CONFIG_A                        0xe2000
  5700. #define IBX_AUD_CONFIG_B                        0xe2100
  5701. #define IBX_AUD_CFG(pipe) _PIPE(pipe, \
  5702.                                         IBX_AUD_CONFIG_A, \
  5703.                                         IBX_AUD_CONFIG_B)
  5704. #define CPT_AUD_CONFIG_A                        0xe5000
  5705. #define CPT_AUD_CONFIG_B                        0xe5100
  5706. #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
  5707.                                         CPT_AUD_CONFIG_A, \
  5708.                                         CPT_AUD_CONFIG_B)
  5709. #define VLV_AUD_CONFIG_A                (VLV_DISPLAY_BASE + 0x62000)
  5710. #define VLV_AUD_CONFIG_B                (VLV_DISPLAY_BASE + 0x62100)
  5711. #define VLV_AUD_CFG(pipe) _PIPE(pipe, \
  5712.                                         VLV_AUD_CONFIG_A, \
  5713.                                         VLV_AUD_CONFIG_B)
  5714.  
  5715. #define   AUD_CONFIG_N_VALUE_INDEX              (1 << 29)
  5716. #define   AUD_CONFIG_N_PROG_ENABLE              (1 << 28)
  5717. #define   AUD_CONFIG_UPPER_N_SHIFT              20
  5718. #define   AUD_CONFIG_UPPER_N_VALUE              (0xff << 20)
  5719. #define   AUD_CONFIG_LOWER_N_SHIFT              4
  5720. #define   AUD_CONFIG_LOWER_N_VALUE              (0xfff << 4)
  5721. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT     16
  5722. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK      (0xf << 16)
  5723. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175     (0 << 16)
  5724. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200     (1 << 16)
  5725. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000     (2 << 16)
  5726. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027     (3 << 16)
  5727. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000     (4 << 16)
  5728. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054     (5 << 16)
  5729. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176     (6 << 16)
  5730. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250     (7 << 16)
  5731. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352    (8 << 16)
  5732. #define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500    (9 << 16)
  5733. #define   AUD_CONFIG_DISABLE_NCTS               (1 << 3)
  5734.  
  5735. /* HSW Audio */
  5736. #define   HSW_AUD_CONFIG_A              0x65000 /* Audio Configuration Transcoder A */
  5737. #define   HSW_AUD_CONFIG_B              0x65100 /* Audio Configuration Transcoder B */
  5738. #define   HSW_AUD_CFG(pipe) _PIPE(pipe, \
  5739.                                         HSW_AUD_CONFIG_A, \
  5740.                                         HSW_AUD_CONFIG_B)
  5741.  
  5742. #define   HSW_AUD_MISC_CTRL_A           0x65010 /* Audio Misc Control Convert 1 */
  5743. #define   HSW_AUD_MISC_CTRL_B           0x65110 /* Audio Misc Control Convert 2 */
  5744. #define   HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
  5745.                                         HSW_AUD_MISC_CTRL_A, \
  5746.                                         HSW_AUD_MISC_CTRL_B)
  5747.  
  5748. #define   HSW_AUD_DIP_ELD_CTRL_ST_A     0x650b4 /* Audio DIP and ELD Control State Transcoder A */
  5749. #define   HSW_AUD_DIP_ELD_CTRL_ST_B     0x651b4 /* Audio DIP and ELD Control State Transcoder B */
  5750. #define   HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
  5751.                                         HSW_AUD_DIP_ELD_CTRL_ST_A, \
  5752.                                         HSW_AUD_DIP_ELD_CTRL_ST_B)
  5753.  
  5754. /* Audio Digital Converter */
  5755. #define   HSW_AUD_DIG_CNVT_1            0x65080 /* Audio Converter 1 */
  5756. #define   HSW_AUD_DIG_CNVT_2            0x65180 /* Audio Converter 1 */
  5757. #define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
  5758.                                         HSW_AUD_DIG_CNVT_1, \
  5759.                                         HSW_AUD_DIG_CNVT_2)
  5760. #define   DIP_PORT_SEL_MASK             0x3
  5761.  
  5762. #define   HSW_AUD_EDID_DATA_A           0x65050
  5763. #define   HSW_AUD_EDID_DATA_B           0x65150
  5764. #define   HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
  5765.                                         HSW_AUD_EDID_DATA_A, \
  5766.                                         HSW_AUD_EDID_DATA_B)
  5767.  
  5768. #define   HSW_AUD_PIPE_CONV_CFG         0x6507c /* Audio pipe and converter configs */
  5769. #define   HSW_AUD_PIN_ELD_CP_VLD        0x650c0 /* Audio ELD and CP Ready Status */
  5770. #define   AUDIO_INACTIVE_C              (1<<11)
  5771. #define   AUDIO_INACTIVE_B              (1<<7)
  5772. #define   AUDIO_INACTIVE_A              (1<<3)
  5773. #define   AUDIO_OUTPUT_ENABLE_A         (1<<2)
  5774. #define   AUDIO_OUTPUT_ENABLE_B         (1<<6)
  5775. #define   AUDIO_OUTPUT_ENABLE_C         (1<<10)
  5776. #define   AUDIO_ELD_VALID_A             (1<<0)
  5777. #define   AUDIO_ELD_VALID_B             (1<<4)
  5778. #define   AUDIO_ELD_VALID_C             (1<<8)
  5779. #define   AUDIO_CP_READY_A              (1<<1)
  5780. #define   AUDIO_CP_READY_B              (1<<5)
  5781. #define   AUDIO_CP_READY_C              (1<<9)
  5782.  
  5783. /* HSW Power Wells */
  5784. #define HSW_PWR_WELL_BIOS                       0x45400 /* CTL1 */
  5785. #define HSW_PWR_WELL_DRIVER                     0x45404 /* CTL2 */
  5786. #define HSW_PWR_WELL_KVMR                       0x45408 /* CTL3 */
  5787. #define HSW_PWR_WELL_DEBUG                      0x4540C /* CTL4 */
  5788. #define   HSW_PWR_WELL_ENABLE_REQUEST           (1<<31)
  5789. #define   HSW_PWR_WELL_STATE_ENABLED            (1<<30)
  5790. #define HSW_PWR_WELL_CTL5               0x45410
  5791. #define   HSW_PWR_WELL_ENABLE_SINGLE_STEP       (1<<31)
  5792. #define   HSW_PWR_WELL_PWR_GATE_OVERRIDE        (1<<20)
  5793. #define   HSW_PWR_WELL_FORCE_ON                         (1<<19)
  5794. #define HSW_PWR_WELL_CTL6               0x45414
  5795.  
  5796. /* Per-pipe DDI Function Control */
  5797. #define TRANS_DDI_FUNC_CTL_A            0x60400
  5798. #define TRANS_DDI_FUNC_CTL_B            0x61400
  5799. #define TRANS_DDI_FUNC_CTL_C            0x62400
  5800. #define TRANS_DDI_FUNC_CTL_EDP          0x6F400
  5801. #define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
  5802.  
  5803. #define  TRANS_DDI_FUNC_ENABLE          (1<<31)
  5804. /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
  5805. #define  TRANS_DDI_PORT_MASK            (7<<28)
  5806. #define  TRANS_DDI_PORT_SHIFT           28
  5807. #define  TRANS_DDI_SELECT_PORT(x)       ((x)<<28)
  5808. #define  TRANS_DDI_PORT_NONE            (0<<28)
  5809. #define  TRANS_DDI_MODE_SELECT_MASK     (7<<24)
  5810. #define  TRANS_DDI_MODE_SELECT_HDMI     (0<<24)
  5811. #define  TRANS_DDI_MODE_SELECT_DVI      (1<<24)
  5812. #define  TRANS_DDI_MODE_SELECT_DP_SST   (2<<24)
  5813. #define  TRANS_DDI_MODE_SELECT_DP_MST   (3<<24)
  5814. #define  TRANS_DDI_MODE_SELECT_FDI      (4<<24)
  5815. #define  TRANS_DDI_BPC_MASK             (7<<20)
  5816. #define  TRANS_DDI_BPC_8                (0<<20)
  5817. #define  TRANS_DDI_BPC_10               (1<<20)
  5818. #define  TRANS_DDI_BPC_6                (2<<20)
  5819. #define  TRANS_DDI_BPC_12               (3<<20)
  5820. #define  TRANS_DDI_PVSYNC               (1<<17)
  5821. #define  TRANS_DDI_PHSYNC               (1<<16)
  5822. #define  TRANS_DDI_EDP_INPUT_MASK       (7<<12)
  5823. #define  TRANS_DDI_EDP_INPUT_A_ON       (0<<12)
  5824. #define  TRANS_DDI_EDP_INPUT_A_ONOFF    (4<<12)
  5825. #define  TRANS_DDI_EDP_INPUT_B_ONOFF    (5<<12)
  5826. #define  TRANS_DDI_EDP_INPUT_C_ONOFF    (6<<12)
  5827. #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC  (1<<8)
  5828. #define  TRANS_DDI_BFI_ENABLE           (1<<4)
  5829.  
  5830. /* DisplayPort Transport Control */
  5831. #define DP_TP_CTL_A                     0x64040
  5832. #define DP_TP_CTL_B                     0x64140
  5833. #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
  5834. #define  DP_TP_CTL_ENABLE               (1<<31)
  5835. #define  DP_TP_CTL_MODE_SST     (0<<27)
  5836. #define  DP_TP_CTL_MODE_MST     (1<<27)
  5837. #define  DP_TP_CTL_FORCE_ACT                    (1<<25)
  5838. #define  DP_TP_CTL_ENHANCED_FRAME_ENABLE        (1<<18)
  5839. #define  DP_TP_CTL_FDI_AUTOTRAIN        (1<<15)
  5840. #define  DP_TP_CTL_LINK_TRAIN_MASK              (7<<8)
  5841. #define  DP_TP_CTL_LINK_TRAIN_PAT1              (0<<8)
  5842. #define  DP_TP_CTL_LINK_TRAIN_PAT2              (1<<8)
  5843. #define  DP_TP_CTL_LINK_TRAIN_PAT3              (4<<8)
  5844. #define  DP_TP_CTL_LINK_TRAIN_IDLE              (2<<8)
  5845. #define  DP_TP_CTL_LINK_TRAIN_NORMAL    (3<<8)
  5846. #define  DP_TP_CTL_SCRAMBLE_DISABLE             (1<<7)
  5847.  
  5848. /* DisplayPort Transport Status */
  5849. #define DP_TP_STATUS_A                  0x64044
  5850. #define DP_TP_STATUS_B                  0x64144
  5851. #define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
  5852. #define  DP_TP_STATUS_IDLE_DONE         (1<<25)
  5853. #define  DP_TP_STATUS_ACT_SENT                  (1<<24)
  5854. #define  DP_TP_STATUS_MODE_STATUS_MST           (1<<23)
  5855. #define  DP_TP_STATUS_AUTOTRAIN_DONE    (1<<12)
  5856. #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC2       (3 << 8)
  5857. #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC1       (3 << 4)
  5858. #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0       (3 << 0)
  5859.  
  5860. /* DDI Buffer Control */
  5861. #define DDI_BUF_CTL_A                           0x64000
  5862. #define DDI_BUF_CTL_B                           0x64100
  5863. #define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
  5864. #define  DDI_BUF_CTL_ENABLE                             (1<<31)
  5865. #define  DDI_BUF_EMP_400MV_0DB_HSW              (0<<24)   /* Sel0 */
  5866. #define  DDI_BUF_EMP_400MV_3_5DB_HSW    (1<<24)   /* Sel1 */
  5867. #define  DDI_BUF_EMP_400MV_6DB_HSW              (2<<24)   /* Sel2 */
  5868. #define  DDI_BUF_EMP_400MV_9_5DB_HSW    (3<<24)   /* Sel3 */
  5869. #define  DDI_BUF_EMP_600MV_0DB_HSW              (4<<24)   /* Sel4 */
  5870. #define  DDI_BUF_EMP_600MV_3_5DB_HSW    (5<<24)   /* Sel5 */
  5871. #define  DDI_BUF_EMP_600MV_6DB_HSW              (6<<24)   /* Sel6 */
  5872. #define  DDI_BUF_EMP_800MV_0DB_HSW              (7<<24)   /* Sel7 */
  5873. #define  DDI_BUF_EMP_800MV_3_5DB_HSW    (8<<24)   /* Sel8 */
  5874. #define  DDI_BUF_EMP_MASK                               (0xf<<24)
  5875. #define  DDI_BUF_PORT_REVERSAL                  (1<<16)
  5876. #define  DDI_BUF_IS_IDLE                                (1<<7)
  5877. #define  DDI_A_4_LANES                          (1<<4)
  5878. #define  DDI_PORT_WIDTH(width)                  (((width) - 1) << 1)
  5879. #define  DDI_INIT_DISPLAY_DETECTED              (1<<0)
  5880.  
  5881. /* DDI Buffer Translations */
  5882. #define DDI_BUF_TRANS_A                         0x64E00
  5883. #define DDI_BUF_TRANS_B                         0x64E60
  5884. #define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
  5885.  
  5886. /* Sideband Interface (SBI) is programmed indirectly, via
  5887.  * SBI_ADDR, which contains the register offset; and SBI_DATA,
  5888.  * which contains the payload */
  5889. #define SBI_ADDR                                0xC6000
  5890. #define SBI_DATA                                0xC6004
  5891. #define SBI_CTL_STAT                    0xC6008
  5892. #define  SBI_CTL_DEST_ICLK              (0x0<<16)
  5893. #define  SBI_CTL_DEST_MPHY              (0x1<<16)
  5894. #define  SBI_CTL_OP_IORD                (0x2<<8)
  5895. #define  SBI_CTL_OP_IOWR                (0x3<<8)
  5896. #define  SBI_CTL_OP_CRRD                (0x6<<8)
  5897. #define  SBI_CTL_OP_CRWR                (0x7<<8)
  5898. #define  SBI_RESPONSE_FAIL              (0x1<<1)
  5899. #define  SBI_RESPONSE_SUCCESS   (0x0<<1)
  5900. #define  SBI_BUSY                               (0x1<<0)
  5901. #define  SBI_READY                              (0x0<<0)
  5902.  
  5903. /* SBI offsets */
  5904. #define  SBI_SSCDIVINTPHASE6            0x0600
  5905. #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK        ((0x7f)<<1)
  5906. #define   SBI_SSCDIVINTPHASE_DIVSEL(x)          ((x)<<1)
  5907. #define   SBI_SSCDIVINTPHASE_INCVAL_MASK        ((0x7f)<<8)
  5908. #define   SBI_SSCDIVINTPHASE_INCVAL(x)          ((x)<<8)
  5909. #define   SBI_SSCDIVINTPHASE_DIR(x)                     ((x)<<15)
  5910. #define   SBI_SSCDIVINTPHASE_PROPAGATE          (1<<0)
  5911. #define  SBI_SSCCTL                                     0x020c
  5912. #define  SBI_SSCCTL6                            0x060C
  5913. #define   SBI_SSCCTL_PATHALT                    (1<<3)
  5914. #define   SBI_SSCCTL_DISABLE            (1<<0)
  5915. #define  SBI_SSCAUXDIV6                         0x0610
  5916. #define   SBI_SSCAUXDIV_FINALDIV2SEL(x)         ((x)<<4)
  5917. #define  SBI_DBUFF0                                     0x2a00
  5918. #define  SBI_GEN0                               0x1f00
  5919. #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE       (1<<0)
  5920.  
  5921. /* LPT PIXCLK_GATE */
  5922. #define PIXCLK_GATE                             0xC6020
  5923. #define  PIXCLK_GATE_UNGATE             (1<<0)
  5924. #define  PIXCLK_GATE_GATE               (0<<0)
  5925.  
  5926. /* SPLL */
  5927. #define SPLL_CTL                                0x46020
  5928. #define  SPLL_PLL_ENABLE                (1<<31)
  5929. #define  SPLL_PLL_SSC                   (1<<28)
  5930. #define  SPLL_PLL_NON_SSC               (2<<28)
  5931. #define  SPLL_PLL_LCPLL                 (3<<28)
  5932. #define  SPLL_PLL_REF_MASK              (3<<28)
  5933. #define  SPLL_PLL_FREQ_810MHz   (0<<26)
  5934. #define  SPLL_PLL_FREQ_1350MHz  (1<<26)
  5935. #define  SPLL_PLL_FREQ_2700MHz          (2<<26)
  5936. #define  SPLL_PLL_FREQ_MASK             (3<<26)
  5937.  
  5938. /* WRPLL */
  5939. #define WRPLL_CTL1                              0x46040
  5940. #define WRPLL_CTL2                              0x46060
  5941. #define WRPLL_CTL(pll)                  (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2)
  5942. #define  WRPLL_PLL_ENABLE                               (1<<31)
  5943. #define  WRPLL_PLL_SSC                  (1<<28)
  5944. #define  WRPLL_PLL_NON_SSC              (2<<28)
  5945. #define  WRPLL_PLL_LCPLL                (3<<28)
  5946. #define  WRPLL_PLL_REF_MASK             (3<<28)
  5947. /* WRPLL divider programming */
  5948. #define  WRPLL_DIVIDER_REFERENCE(x)             ((x)<<0)
  5949. #define  WRPLL_DIVIDER_REF_MASK         (0xff)
  5950. #define  WRPLL_DIVIDER_POST(x)                  ((x)<<8)
  5951. #define  WRPLL_DIVIDER_POST_MASK        (0x3f<<8)
  5952. #define  WRPLL_DIVIDER_POST_SHIFT       8
  5953. #define  WRPLL_DIVIDER_FEEDBACK(x)              ((x)<<16)
  5954. #define  WRPLL_DIVIDER_FB_SHIFT         16
  5955. #define  WRPLL_DIVIDER_FB_MASK          (0xff<<16)
  5956.  
  5957. /* Port clock selection */
  5958. #define PORT_CLK_SEL_A                  0x46100
  5959. #define PORT_CLK_SEL_B                  0x46104
  5960. #define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
  5961. #define  PORT_CLK_SEL_LCPLL_2700        (0<<29)
  5962. #define  PORT_CLK_SEL_LCPLL_1350        (1<<29)
  5963. #define  PORT_CLK_SEL_LCPLL_810         (2<<29)
  5964. #define  PORT_CLK_SEL_SPLL                      (3<<29)
  5965. #define  PORT_CLK_SEL_WRPLL(pll)        (((pll)+4)<<29)
  5966. #define  PORT_CLK_SEL_WRPLL1            (4<<29)
  5967. #define  PORT_CLK_SEL_WRPLL2            (5<<29)
  5968. #define  PORT_CLK_SEL_NONE              (7<<29)
  5969. #define  PORT_CLK_SEL_MASK              (7<<29)
  5970.  
  5971. /* Transcoder clock selection */
  5972. #define TRANS_CLK_SEL_A                 0x46140
  5973. #define TRANS_CLK_SEL_B                 0x46144
  5974. #define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
  5975. /* For each transcoder, we need to select the corresponding port clock */
  5976. #define  TRANS_CLK_SEL_DISABLED         (0x0<<29)
  5977. #define  TRANS_CLK_SEL_PORT(x)          ((x+1)<<29)
  5978.  
  5979. #define TRANSA_MSA_MISC                 0x60410
  5980. #define TRANSB_MSA_MISC                 0x61410
  5981. #define TRANSC_MSA_MISC                 0x62410
  5982. #define TRANS_EDP_MSA_MISC              0x6f410
  5983. #define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
  5984.  
  5985. #define  TRANS_MSA_SYNC_CLK             (1<<0)
  5986. #define  TRANS_MSA_6_BPC                (0<<5)
  5987. #define  TRANS_MSA_8_BPC                (1<<5)
  5988. #define  TRANS_MSA_10_BPC               (2<<5)
  5989. #define  TRANS_MSA_12_BPC               (3<<5)
  5990. #define  TRANS_MSA_16_BPC               (4<<5)
  5991.  
  5992. /* LCPLL Control */
  5993. #define LCPLL_CTL                               0x130040
  5994. #define  LCPLL_PLL_DISABLE              (1<<31)
  5995. #define  LCPLL_PLL_LOCK                 (1<<30)
  5996. #define  LCPLL_CLK_FREQ_MASK            (3<<26)
  5997. #define  LCPLL_CLK_FREQ_450             (0<<26)
  5998. #define  LCPLL_CLK_FREQ_54O_BDW         (1<<26)
  5999. #define  LCPLL_CLK_FREQ_337_5_BDW       (2<<26)
  6000. #define  LCPLL_CLK_FREQ_675_BDW         (3<<26)
  6001. #define  LCPLL_CD_CLOCK_DISABLE (1<<25)
  6002. #define  LCPLL_CD2X_CLOCK_DISABLE       (1<<23)
  6003. #define  LCPLL_POWER_DOWN_ALLOW         (1<<22)
  6004. #define  LCPLL_CD_SOURCE_FCLK           (1<<21)
  6005. #define  LCPLL_CD_SOURCE_FCLK_DONE      (1<<19)
  6006.  
  6007. /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  6008.  * since on HSW we can't write to it using I915_WRITE. */
  6009. #define D_COMP_HSW                      (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
  6010. #define D_COMP_BDW                      0x138144
  6011. #define  D_COMP_RCOMP_IN_PROGRESS       (1<<9)
  6012. #define  D_COMP_COMP_FORCE              (1<<8)
  6013. #define  D_COMP_COMP_DISABLE            (1<<0)
  6014.  
  6015. /* Pipe WM_LINETIME - watermark line time */
  6016. #define PIPE_WM_LINETIME_A              0x45270
  6017. #define PIPE_WM_LINETIME_B              0x45274
  6018. #define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
  6019.                                         PIPE_WM_LINETIME_B)
  6020. #define   PIPE_WM_LINETIME_MASK         (0x1ff)
  6021. #define   PIPE_WM_LINETIME_TIME(x)                      ((x))
  6022. #define   PIPE_WM_LINETIME_IPS_LINETIME_MASK    (0x1ff<<16)
  6023. #define   PIPE_WM_LINETIME_IPS_LINETIME(x)              ((x)<<16)
  6024.  
  6025. /* SFUSE_STRAP */
  6026. #define SFUSE_STRAP                             0xc2014
  6027. #define  SFUSE_STRAP_FUSE_LOCK          (1<<13)
  6028. #define  SFUSE_STRAP_DISPLAY_DISABLED   (1<<7)
  6029. #define  SFUSE_STRAP_DDIB_DETECTED      (1<<2)
  6030. #define  SFUSE_STRAP_DDIC_DETECTED      (1<<1)
  6031. #define  SFUSE_STRAP_DDID_DETECTED      (1<<0)
  6032.  
  6033. #define WM_MISC                         0x45260
  6034. #define  WM_MISC_DATA_PARTITION_5_6     (1 << 0)
  6035.  
  6036. #define WM_DBG                          0x45280
  6037. #define  WM_DBG_DISALLOW_MULTIPLE_LP    (1<<0)
  6038. #define  WM_DBG_DISALLOW_MAXFIFO        (1<<1)
  6039. #define  WM_DBG_DISALLOW_SPRITE         (1<<2)
  6040.  
  6041. /* pipe CSC */
  6042. #define _PIPE_A_CSC_COEFF_RY_GY 0x49010
  6043. #define _PIPE_A_CSC_COEFF_BY    0x49014
  6044. #define _PIPE_A_CSC_COEFF_RU_GU 0x49018
  6045. #define _PIPE_A_CSC_COEFF_BU    0x4901c
  6046. #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
  6047. #define _PIPE_A_CSC_COEFF_BV    0x49024
  6048. #define _PIPE_A_CSC_MODE        0x49028
  6049. #define   CSC_BLACK_SCREEN_OFFSET       (1 << 2)
  6050. #define   CSC_POSITION_BEFORE_GAMMA     (1 << 1)
  6051. #define   CSC_MODE_YUV_TO_RGB           (1 << 0)
  6052. #define _PIPE_A_CSC_PREOFF_HI   0x49030
  6053. #define _PIPE_A_CSC_PREOFF_ME   0x49034
  6054. #define _PIPE_A_CSC_PREOFF_LO   0x49038
  6055. #define _PIPE_A_CSC_POSTOFF_HI  0x49040
  6056. #define _PIPE_A_CSC_POSTOFF_ME  0x49044
  6057. #define _PIPE_A_CSC_POSTOFF_LO  0x49048
  6058.  
  6059. #define _PIPE_B_CSC_COEFF_RY_GY 0x49110
  6060. #define _PIPE_B_CSC_COEFF_BY    0x49114
  6061. #define _PIPE_B_CSC_COEFF_RU_GU 0x49118
  6062. #define _PIPE_B_CSC_COEFF_BU    0x4911c
  6063. #define _PIPE_B_CSC_COEFF_RV_GV 0x49120
  6064. #define _PIPE_B_CSC_COEFF_BV    0x49124
  6065. #define _PIPE_B_CSC_MODE        0x49128
  6066. #define _PIPE_B_CSC_PREOFF_HI   0x49130
  6067. #define _PIPE_B_CSC_PREOFF_ME   0x49134
  6068. #define _PIPE_B_CSC_PREOFF_LO   0x49138
  6069. #define _PIPE_B_CSC_POSTOFF_HI  0x49140
  6070. #define _PIPE_B_CSC_POSTOFF_ME  0x49144
  6071. #define _PIPE_B_CSC_POSTOFF_LO  0x49148
  6072.  
  6073. #define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
  6074. #define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
  6075. #define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
  6076. #define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
  6077. #define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
  6078. #define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
  6079. #define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
  6080. #define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
  6081. #define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
  6082. #define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
  6083. #define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
  6084. #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
  6085. #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
  6086.  
  6087. /* VLV MIPI registers */
  6088.  
  6089. #define _MIPIA_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61190)
  6090. #define _MIPIB_PORT_CTRL                        (VLV_DISPLAY_BASE + 0x61700)
  6091. #define MIPI_PORT_CTRL(tc)              _TRANSCODER(tc, _MIPIA_PORT_CTRL, \
  6092.                                                 _MIPIB_PORT_CTRL)
  6093. #define  DPI_ENABLE                                     (1 << 31) /* A + B */
  6094. #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT              27
  6095. #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 27)
  6096. #define  DUAL_LINK_MODE_MASK                            (1 << 26)
  6097. #define  DUAL_LINK_MODE_FRONT_BACK                      (0 << 26)
  6098. #define  DUAL_LINK_MODE_PIXEL_ALTERNATIVE               (1 << 26)
  6099. #define  DITHERING_ENABLE                               (1 << 25) /* A + B */
  6100. #define  FLOPPED_HSTX                                   (1 << 23)
  6101. #define  DE_INVERT                                      (1 << 19) /* XXX */
  6102. #define  MIPIA_FLISDSI_DELAY_COUNT_SHIFT                18
  6103. #define  MIPIA_FLISDSI_DELAY_COUNT_MASK                 (0xf << 18)
  6104. #define  AFE_LATCHOUT                                   (1 << 17)
  6105. #define  LP_OUTPUT_HOLD                                 (1 << 16)
  6106. #define  MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT           15
  6107. #define  MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK            (1 << 15)
  6108. #define  MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT              11
  6109. #define  MIPIB_MIPI4DPHY_DELAY_COUNT_MASK               (0xf << 11)
  6110. #define  CSB_SHIFT                                      9
  6111. #define  CSB_MASK                                       (3 << 9)
  6112. #define  CSB_20MHZ                                      (0 << 9)
  6113. #define  CSB_10MHZ                                      (1 << 9)
  6114. #define  CSB_40MHZ                                      (2 << 9)
  6115. #define  BANDGAP_MASK                                   (1 << 8)
  6116. #define  BANDGAP_PNW_CIRCUIT                            (0 << 8)
  6117. #define  BANDGAP_LNC_CIRCUIT                            (1 << 8)
  6118. #define  MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT            5
  6119. #define  MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK             (7 << 5)
  6120. #define  TEARING_EFFECT_DELAY                           (1 << 4) /* A + B */
  6121. #define  TEARING_EFFECT_SHIFT                           2 /* A + B */
  6122. #define  TEARING_EFFECT_MASK                            (3 << 2)
  6123. #define  TEARING_EFFECT_OFF                             (0 << 2)
  6124. #define  TEARING_EFFECT_DSI                             (1 << 2)
  6125. #define  TEARING_EFFECT_GPIO                            (2 << 2)
  6126. #define  LANE_CONFIGURATION_SHIFT                       0
  6127. #define  LANE_CONFIGURATION_MASK                        (3 << 0)
  6128. #define  LANE_CONFIGURATION_4LANE                       (0 << 0)
  6129. #define  LANE_CONFIGURATION_DUAL_LINK_A                 (1 << 0)
  6130. #define  LANE_CONFIGURATION_DUAL_LINK_B                 (2 << 0)
  6131.  
  6132. #define _MIPIA_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61194)
  6133. #define _MIPIB_TEARING_CTRL                     (VLV_DISPLAY_BASE + 0x61704)
  6134. #define MIPI_TEARING_CTRL(tc)                   _TRANSCODER(tc, \
  6135.                                 _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
  6136. #define  TEARING_EFFECT_DELAY_SHIFT                     0
  6137. #define  TEARING_EFFECT_DELAY_MASK                      (0xffff << 0)
  6138.  
  6139. /* XXX: all bits reserved */
  6140. #define _MIPIA_AUTOPWG                          (VLV_DISPLAY_BASE + 0x611a0)
  6141.  
  6142. /* MIPI DSI Controller and D-PHY registers */
  6143.  
  6144. #define _MIPIA_DEVICE_READY             (dev_priv->mipi_mmio_base + 0xb000)
  6145. #define _MIPIB_DEVICE_READY             (dev_priv->mipi_mmio_base + 0xb800)
  6146. #define MIPI_DEVICE_READY(tc)           _TRANSCODER(tc, _MIPIA_DEVICE_READY, \
  6147.                                                 _MIPIB_DEVICE_READY)
  6148. #define  BUS_POSSESSION                                 (1 << 3) /* set to give bus to receiver */
  6149. #define  ULPS_STATE_MASK                                (3 << 1)
  6150. #define  ULPS_STATE_ENTER                               (2 << 1)
  6151. #define  ULPS_STATE_EXIT                                (1 << 1)
  6152. #define  ULPS_STATE_NORMAL_OPERATION                    (0 << 1)
  6153. #define  DEVICE_READY                                   (1 << 0)
  6154.  
  6155. #define _MIPIA_INTR_STAT                (dev_priv->mipi_mmio_base + 0xb004)
  6156. #define _MIPIB_INTR_STAT                (dev_priv->mipi_mmio_base + 0xb804)
  6157. #define MIPI_INTR_STAT(tc)              _TRANSCODER(tc, _MIPIA_INTR_STAT, \
  6158.                                         _MIPIB_INTR_STAT)
  6159. #define _MIPIA_INTR_EN                  (dev_priv->mipi_mmio_base + 0xb008)
  6160. #define _MIPIB_INTR_EN                  (dev_priv->mipi_mmio_base + 0xb808)
  6161. #define MIPI_INTR_EN(tc)                _TRANSCODER(tc, _MIPIA_INTR_EN, \
  6162.                                         _MIPIB_INTR_EN)
  6163. #define  TEARING_EFFECT                                 (1 << 31)
  6164. #define  SPL_PKT_SENT_INTERRUPT                         (1 << 30)
  6165. #define  GEN_READ_DATA_AVAIL                            (1 << 29)
  6166. #define  LP_GENERIC_WR_FIFO_FULL                        (1 << 28)
  6167. #define  HS_GENERIC_WR_FIFO_FULL                        (1 << 27)
  6168. #define  RX_PROT_VIOLATION                              (1 << 26)
  6169. #define  RX_INVALID_TX_LENGTH                           (1 << 25)
  6170. #define  ACK_WITH_NO_ERROR                              (1 << 24)
  6171. #define  TURN_AROUND_ACK_TIMEOUT                        (1 << 23)
  6172. #define  LP_RX_TIMEOUT                                  (1 << 22)
  6173. #define  HS_TX_TIMEOUT                                  (1 << 21)
  6174. #define  DPI_FIFO_UNDERRUN                              (1 << 20)
  6175. #define  LOW_CONTENTION                                 (1 << 19)
  6176. #define  HIGH_CONTENTION                                (1 << 18)
  6177. #define  TXDSI_VC_ID_INVALID                            (1 << 17)
  6178. #define  TXDSI_DATA_TYPE_NOT_RECOGNISED                 (1 << 16)
  6179. #define  TXCHECKSUM_ERROR                               (1 << 15)
  6180. #define  TXECC_MULTIBIT_ERROR                           (1 << 14)
  6181. #define  TXECC_SINGLE_BIT_ERROR                         (1 << 13)
  6182. #define  TXFALSE_CONTROL_ERROR                          (1 << 12)
  6183. #define  RXDSI_VC_ID_INVALID                            (1 << 11)
  6184. #define  RXDSI_DATA_TYPE_NOT_REGOGNISED                 (1 << 10)
  6185. #define  RXCHECKSUM_ERROR                               (1 << 9)
  6186. #define  RXECC_MULTIBIT_ERROR                           (1 << 8)
  6187. #define  RXECC_SINGLE_BIT_ERROR                         (1 << 7)
  6188. #define  RXFALSE_CONTROL_ERROR                          (1 << 6)
  6189. #define  RXHS_RECEIVE_TIMEOUT_ERROR                     (1 << 5)
  6190. #define  RX_LP_TX_SYNC_ERROR                            (1 << 4)
  6191. #define  RXEXCAPE_MODE_ENTRY_ERROR                      (1 << 3)
  6192. #define  RXEOT_SYNC_ERROR                               (1 << 2)
  6193. #define  RXSOT_SYNC_ERROR                               (1 << 1)
  6194. #define  RXSOT_ERROR                                    (1 << 0)
  6195.  
  6196. #define _MIPIA_DSI_FUNC_PRG             (dev_priv->mipi_mmio_base + 0xb00c)
  6197. #define _MIPIB_DSI_FUNC_PRG             (dev_priv->mipi_mmio_base + 0xb80c)
  6198. #define MIPI_DSI_FUNC_PRG(tc)           _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \
  6199.                                                 _MIPIB_DSI_FUNC_PRG)
  6200. #define  CMD_MODE_DATA_WIDTH_MASK                       (7 << 13)
  6201. #define  CMD_MODE_NOT_SUPPORTED                         (0 << 13)
  6202. #define  CMD_MODE_DATA_WIDTH_16_BIT                     (1 << 13)
  6203. #define  CMD_MODE_DATA_WIDTH_9_BIT                      (2 << 13)
  6204. #define  CMD_MODE_DATA_WIDTH_8_BIT                      (3 << 13)
  6205. #define  CMD_MODE_DATA_WIDTH_OPTION1                    (4 << 13)
  6206. #define  CMD_MODE_DATA_WIDTH_OPTION2                    (5 << 13)
  6207. #define  VID_MODE_FORMAT_MASK                           (0xf << 7)
  6208. #define  VID_MODE_NOT_SUPPORTED                         (0 << 7)
  6209. #define  VID_MODE_FORMAT_RGB565                         (1 << 7)
  6210. #define  VID_MODE_FORMAT_RGB666                         (2 << 7)
  6211. #define  VID_MODE_FORMAT_RGB666_LOOSE                   (3 << 7)
  6212. #define  VID_MODE_FORMAT_RGB888                         (4 << 7)
  6213. #define  CMD_MODE_CHANNEL_NUMBER_SHIFT                  5
  6214. #define  CMD_MODE_CHANNEL_NUMBER_MASK                   (3 << 5)
  6215. #define  VID_MODE_CHANNEL_NUMBER_SHIFT                  3
  6216. #define  VID_MODE_CHANNEL_NUMBER_MASK                   (3 << 3)
  6217. #define  DATA_LANES_PRG_REG_SHIFT                       0
  6218. #define  DATA_LANES_PRG_REG_MASK                        (7 << 0)
  6219.  
  6220. #define _MIPIA_HS_TX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb010)
  6221. #define _MIPIB_HS_TX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb810)
  6222. #define MIPI_HS_TX_TIMEOUT(tc)  _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \
  6223.                                         _MIPIB_HS_TX_TIMEOUT)
  6224. #define  HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK             0xffffff
  6225.  
  6226. #define _MIPIA_LP_RX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb014)
  6227. #define _MIPIB_LP_RX_TIMEOUT            (dev_priv->mipi_mmio_base + 0xb814)
  6228. #define MIPI_LP_RX_TIMEOUT(tc)  _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \
  6229.                                         _MIPIB_LP_RX_TIMEOUT)
  6230. #define  LOW_POWER_RX_TIMEOUT_COUNTER_MASK              0xffffff
  6231.  
  6232. #define _MIPIA_TURN_AROUND_TIMEOUT      (dev_priv->mipi_mmio_base + 0xb018)
  6233. #define _MIPIB_TURN_AROUND_TIMEOUT      (dev_priv->mipi_mmio_base + 0xb818)
  6234. #define MIPI_TURN_AROUND_TIMEOUT(tc)    _TRANSCODER(tc, \
  6235.                         _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
  6236. #define  TURN_AROUND_TIMEOUT_MASK                       0x3f
  6237.  
  6238. #define _MIPIA_DEVICE_RESET_TIMER       (dev_priv->mipi_mmio_base + 0xb01c)
  6239. #define _MIPIB_DEVICE_RESET_TIMER       (dev_priv->mipi_mmio_base + 0xb81c)
  6240. #define MIPI_DEVICE_RESET_TIMER(tc)     _TRANSCODER(tc, \
  6241.                         _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
  6242. #define  DEVICE_RESET_TIMER_MASK                        0xffff
  6243.  
  6244. #define _MIPIA_DPI_RESOLUTION           (dev_priv->mipi_mmio_base + 0xb020)
  6245. #define _MIPIB_DPI_RESOLUTION           (dev_priv->mipi_mmio_base + 0xb820)
  6246. #define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \
  6247.                                         _MIPIB_DPI_RESOLUTION)
  6248. #define  VERTICAL_ADDRESS_SHIFT                         16
  6249. #define  VERTICAL_ADDRESS_MASK                          (0xffff << 16)
  6250. #define  HORIZONTAL_ADDRESS_SHIFT                       0
  6251. #define  HORIZONTAL_ADDRESS_MASK                        0xffff
  6252.  
  6253. #define _MIPIA_DBI_FIFO_THROTTLE        (dev_priv->mipi_mmio_base + 0xb024)
  6254. #define _MIPIB_DBI_FIFO_THROTTLE        (dev_priv->mipi_mmio_base + 0xb824)
  6255. #define MIPI_DBI_FIFO_THROTTLE(tc)      _TRANSCODER(tc, \
  6256.                         _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
  6257. #define  DBI_FIFO_EMPTY_HALF                            (0 << 0)
  6258. #define  DBI_FIFO_EMPTY_QUARTER                         (1 << 0)
  6259. #define  DBI_FIFO_EMPTY_7_LOCATIONS                     (2 << 0)
  6260.  
  6261. /* regs below are bits 15:0 */
  6262. #define _MIPIA_HSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb028)
  6263. #define _MIPIB_HSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb828)
  6264. #define MIPI_HSYNC_PADDING_COUNT(tc)    _TRANSCODER(tc, \
  6265.                         _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
  6266.  
  6267. #define _MIPIA_HBP_COUNT                (dev_priv->mipi_mmio_base + 0xb02c)
  6268. #define _MIPIB_HBP_COUNT                (dev_priv->mipi_mmio_base + 0xb82c)
  6269. #define MIPI_HBP_COUNT(tc)              _TRANSCODER(tc, _MIPIA_HBP_COUNT, \
  6270.                                         _MIPIB_HBP_COUNT)
  6271.  
  6272. #define _MIPIA_HFP_COUNT                (dev_priv->mipi_mmio_base + 0xb030)
  6273. #define _MIPIB_HFP_COUNT                (dev_priv->mipi_mmio_base + 0xb830)
  6274. #define MIPI_HFP_COUNT(tc)              _TRANSCODER(tc, _MIPIA_HFP_COUNT, \
  6275.                                         _MIPIB_HFP_COUNT)
  6276.  
  6277. #define _MIPIA_HACTIVE_AREA_COUNT       (dev_priv->mipi_mmio_base + 0xb034)
  6278. #define _MIPIB_HACTIVE_AREA_COUNT       (dev_priv->mipi_mmio_base + 0xb834)
  6279. #define MIPI_HACTIVE_AREA_COUNT(tc)     _TRANSCODER(tc, \
  6280.                         _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
  6281.  
  6282. #define _MIPIA_VSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb038)
  6283. #define _MIPIB_VSYNC_PADDING_COUNT      (dev_priv->mipi_mmio_base + 0xb838)
  6284. #define MIPI_VSYNC_PADDING_COUNT(tc)    _TRANSCODER(tc, \
  6285.                         _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
  6286.  
  6287. #define _MIPIA_VBP_COUNT                (dev_priv->mipi_mmio_base + 0xb03c)
  6288. #define _MIPIB_VBP_COUNT                (dev_priv->mipi_mmio_base + 0xb83c)
  6289. #define MIPI_VBP_COUNT(tc)              _TRANSCODER(tc, _MIPIA_VBP_COUNT, \
  6290.                                         _MIPIB_VBP_COUNT)
  6291.  
  6292. #define _MIPIA_VFP_COUNT                (dev_priv->mipi_mmio_base + 0xb040)
  6293. #define _MIPIB_VFP_COUNT                (dev_priv->mipi_mmio_base + 0xb840)
  6294. #define MIPI_VFP_COUNT(tc)              _TRANSCODER(tc, _MIPIA_VFP_COUNT, \
  6295.                                         _MIPIB_VFP_COUNT)
  6296.  
  6297. #define _MIPIA_HIGH_LOW_SWITCH_COUNT    (dev_priv->mipi_mmio_base + 0xb044)
  6298. #define _MIPIB_HIGH_LOW_SWITCH_COUNT    (dev_priv->mipi_mmio_base + 0xb844)
  6299. #define MIPI_HIGH_LOW_SWITCH_COUNT(tc)  _TRANSCODER(tc, \
  6300.                 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
  6301.  
  6302. /* regs above are bits 15:0 */
  6303.  
  6304. #define _MIPIA_DPI_CONTROL              (dev_priv->mipi_mmio_base + 0xb048)
  6305. #define _MIPIB_DPI_CONTROL              (dev_priv->mipi_mmio_base + 0xb848)
  6306. #define MIPI_DPI_CONTROL(tc)            _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \
  6307.                                         _MIPIB_DPI_CONTROL)
  6308. #define  DPI_LP_MODE                                    (1 << 6)
  6309. #define  BACKLIGHT_OFF                                  (1 << 5)
  6310. #define  BACKLIGHT_ON                                   (1 << 4)
  6311. #define  COLOR_MODE_OFF                                 (1 << 3)
  6312. #define  COLOR_MODE_ON                                  (1 << 2)
  6313. #define  TURN_ON                                        (1 << 1)
  6314. #define  SHUTDOWN                                       (1 << 0)
  6315.  
  6316. #define _MIPIA_DPI_DATA                 (dev_priv->mipi_mmio_base + 0xb04c)
  6317. #define _MIPIB_DPI_DATA                 (dev_priv->mipi_mmio_base + 0xb84c)
  6318. #define MIPI_DPI_DATA(tc)               _TRANSCODER(tc, _MIPIA_DPI_DATA, \
  6319.                                         _MIPIB_DPI_DATA)
  6320. #define  COMMAND_BYTE_SHIFT                             0
  6321. #define  COMMAND_BYTE_MASK                              (0x3f << 0)
  6322.  
  6323. #define _MIPIA_INIT_COUNT               (dev_priv->mipi_mmio_base + 0xb050)
  6324. #define _MIPIB_INIT_COUNT               (dev_priv->mipi_mmio_base + 0xb850)
  6325. #define MIPI_INIT_COUNT(tc)             _TRANSCODER(tc, _MIPIA_INIT_COUNT, \
  6326.                                         _MIPIB_INIT_COUNT)
  6327. #define  MASTER_INIT_TIMER_SHIFT                        0
  6328. #define  MASTER_INIT_TIMER_MASK                         (0xffff << 0)
  6329.  
  6330. #define _MIPIA_MAX_RETURN_PKT_SIZE      (dev_priv->mipi_mmio_base + 0xb054)
  6331. #define _MIPIB_MAX_RETURN_PKT_SIZE      (dev_priv->mipi_mmio_base + 0xb854)
  6332. #define MIPI_MAX_RETURN_PKT_SIZE(tc)    _TRANSCODER(tc, \
  6333.                         _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
  6334. #define  MAX_RETURN_PKT_SIZE_SHIFT                      0
  6335. #define  MAX_RETURN_PKT_SIZE_MASK                       (0x3ff << 0)
  6336.  
  6337. #define _MIPIA_VIDEO_MODE_FORMAT        (dev_priv->mipi_mmio_base + 0xb058)
  6338. #define _MIPIB_VIDEO_MODE_FORMAT        (dev_priv->mipi_mmio_base + 0xb858)
  6339. #define MIPI_VIDEO_MODE_FORMAT(tc)      _TRANSCODER(tc, \
  6340.                         _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
  6341. #define  RANDOM_DPI_DISPLAY_RESOLUTION                  (1 << 4)
  6342. #define  DISABLE_VIDEO_BTA                              (1 << 3)
  6343. #define  IP_TG_CONFIG                                   (1 << 2)
  6344. #define  VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE           (1 << 0)
  6345. #define  VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS          (2 << 0)
  6346. #define  VIDEO_MODE_BURST                               (3 << 0)
  6347.  
  6348. #define _MIPIA_EOT_DISABLE              (dev_priv->mipi_mmio_base + 0xb05c)
  6349. #define _MIPIB_EOT_DISABLE              (dev_priv->mipi_mmio_base + 0xb85c)
  6350. #define MIPI_EOT_DISABLE(tc)            _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \
  6351.                                         _MIPIB_EOT_DISABLE)
  6352. #define  LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 7)
  6353. #define  HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE           (1 << 6)
  6354. #define  LOW_CONTENTION_RECOVERY_DISABLE                (1 << 5)
  6355. #define  HIGH_CONTENTION_RECOVERY_DISABLE               (1 << 4)
  6356. #define  TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
  6357. #define  TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE          (1 << 2)
  6358. #define  CLOCKSTOP                                      (1 << 1)
  6359. #define  EOT_DISABLE                                    (1 << 0)
  6360.  
  6361. #define _MIPIA_LP_BYTECLK               (dev_priv->mipi_mmio_base + 0xb060)
  6362. #define _MIPIB_LP_BYTECLK               (dev_priv->mipi_mmio_base + 0xb860)
  6363. #define MIPI_LP_BYTECLK(tc)             _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \
  6364.                                         _MIPIB_LP_BYTECLK)
  6365. #define  LP_BYTECLK_SHIFT                               0
  6366. #define  LP_BYTECLK_MASK                                (0xffff << 0)
  6367.  
  6368. /* bits 31:0 */
  6369. #define _MIPIA_LP_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb064)
  6370. #define _MIPIB_LP_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb864)
  6371. #define MIPI_LP_GEN_DATA(tc)            _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \
  6372.                                         _MIPIB_LP_GEN_DATA)
  6373.  
  6374. /* bits 31:0 */
  6375. #define _MIPIA_HS_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb068)
  6376. #define _MIPIB_HS_GEN_DATA              (dev_priv->mipi_mmio_base + 0xb868)
  6377. #define MIPI_HS_GEN_DATA(tc)            _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \
  6378.                                         _MIPIB_HS_GEN_DATA)
  6379.  
  6380. #define _MIPIA_LP_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb06c)
  6381. #define _MIPIB_LP_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb86c)
  6382. #define MIPI_LP_GEN_CTRL(tc)            _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \
  6383.                                         _MIPIB_LP_GEN_CTRL)
  6384. #define _MIPIA_HS_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb070)
  6385. #define _MIPIB_HS_GEN_CTRL              (dev_priv->mipi_mmio_base + 0xb870)
  6386. #define MIPI_HS_GEN_CTRL(tc)            _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \
  6387.                                         _MIPIB_HS_GEN_CTRL)
  6388. #define  LONG_PACKET_WORD_COUNT_SHIFT                   8
  6389. #define  LONG_PACKET_WORD_COUNT_MASK                    (0xffff << 8)
  6390. #define  SHORT_PACKET_PARAM_SHIFT                       8
  6391. #define  SHORT_PACKET_PARAM_MASK                        (0xffff << 8)
  6392. #define  VIRTUAL_CHANNEL_SHIFT                          6
  6393. #define  VIRTUAL_CHANNEL_MASK                           (3 << 6)
  6394. #define  DATA_TYPE_SHIFT                                0
  6395. #define  DATA_TYPE_MASK                                 (3f << 0)
  6396. /* data type values, see include/video/mipi_display.h */
  6397.  
  6398. #define _MIPIA_GEN_FIFO_STAT            (dev_priv->mipi_mmio_base + 0xb074)
  6399. #define _MIPIB_GEN_FIFO_STAT            (dev_priv->mipi_mmio_base + 0xb874)
  6400. #define MIPI_GEN_FIFO_STAT(tc)  _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \
  6401.                                         _MIPIB_GEN_FIFO_STAT)
  6402. #define  DPI_FIFO_EMPTY                                 (1 << 28)
  6403. #define  DBI_FIFO_EMPTY                                 (1 << 27)
  6404. #define  LP_CTRL_FIFO_EMPTY                             (1 << 26)
  6405. #define  LP_CTRL_FIFO_HALF_EMPTY                        (1 << 25)
  6406. #define  LP_CTRL_FIFO_FULL                              (1 << 24)
  6407. #define  HS_CTRL_FIFO_EMPTY                             (1 << 18)
  6408. #define  HS_CTRL_FIFO_HALF_EMPTY                        (1 << 17)
  6409. #define  HS_CTRL_FIFO_FULL                              (1 << 16)
  6410. #define  LP_DATA_FIFO_EMPTY                             (1 << 10)
  6411. #define  LP_DATA_FIFO_HALF_EMPTY                        (1 << 9)
  6412. #define  LP_DATA_FIFO_FULL                              (1 << 8)
  6413. #define  HS_DATA_FIFO_EMPTY                             (1 << 2)
  6414. #define  HS_DATA_FIFO_HALF_EMPTY                        (1 << 1)
  6415. #define  HS_DATA_FIFO_FULL                              (1 << 0)
  6416.  
  6417. #define _MIPIA_HS_LS_DBI_ENABLE         (dev_priv->mipi_mmio_base + 0xb078)
  6418. #define _MIPIB_HS_LS_DBI_ENABLE         (dev_priv->mipi_mmio_base + 0xb878)
  6419. #define MIPI_HS_LP_DBI_ENABLE(tc)       _TRANSCODER(tc, \
  6420.                         _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
  6421. #define  DBI_HS_LP_MODE_MASK                            (1 << 0)
  6422. #define  DBI_LP_MODE                                    (1 << 0)
  6423. #define  DBI_HS_MODE                                    (0 << 0)
  6424.  
  6425. #define _MIPIA_DPHY_PARAM               (dev_priv->mipi_mmio_base + 0xb080)
  6426. #define _MIPIB_DPHY_PARAM               (dev_priv->mipi_mmio_base + 0xb880)
  6427. #define MIPI_DPHY_PARAM(tc)             _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \
  6428.                                         _MIPIB_DPHY_PARAM)
  6429. #define  EXIT_ZERO_COUNT_SHIFT                          24
  6430. #define  EXIT_ZERO_COUNT_MASK                           (0x3f << 24)
  6431. #define  TRAIL_COUNT_SHIFT                              16
  6432. #define  TRAIL_COUNT_MASK                               (0x1f << 16)
  6433. #define  CLK_ZERO_COUNT_SHIFT                           8
  6434. #define  CLK_ZERO_COUNT_MASK                            (0xff << 8)
  6435. #define  PREPARE_COUNT_SHIFT                            0
  6436. #define  PREPARE_COUNT_MASK                             (0x3f << 0)
  6437.  
  6438. /* bits 31:0 */
  6439. #define _MIPIA_DBI_BW_CTRL              (dev_priv->mipi_mmio_base + 0xb084)
  6440. #define _MIPIB_DBI_BW_CTRL              (dev_priv->mipi_mmio_base + 0xb884)
  6441. #define MIPI_DBI_BW_CTRL(tc)            _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \
  6442.                                         _MIPIB_DBI_BW_CTRL)
  6443.  
  6444. #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT         (dev_priv->mipi_mmio_base \
  6445.                                                         + 0xb088)
  6446. #define _MIPIB_CLK_LANE_SWITCH_TIME_CNT         (dev_priv->mipi_mmio_base \
  6447.                                                         + 0xb888)
  6448. #define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc)       _TRANSCODER(tc, \
  6449.         _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
  6450. #define  LP_HS_SSW_CNT_SHIFT                            16
  6451. #define  LP_HS_SSW_CNT_MASK                             (0xffff << 16)
  6452. #define  HS_LP_PWR_SW_CNT_SHIFT                         0
  6453. #define  HS_LP_PWR_SW_CNT_MASK                          (0xffff << 0)
  6454.  
  6455. #define _MIPIA_STOP_STATE_STALL         (dev_priv->mipi_mmio_base + 0xb08c)
  6456. #define _MIPIB_STOP_STATE_STALL         (dev_priv->mipi_mmio_base + 0xb88c)
  6457. #define MIPI_STOP_STATE_STALL(tc)       _TRANSCODER(tc, \
  6458.                         _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
  6459. #define  STOP_STATE_STALL_COUNTER_SHIFT                 0
  6460. #define  STOP_STATE_STALL_COUNTER_MASK                  (0xff << 0)
  6461.  
  6462. #define _MIPIA_INTR_STAT_REG_1          (dev_priv->mipi_mmio_base + 0xb090)
  6463. #define _MIPIB_INTR_STAT_REG_1          (dev_priv->mipi_mmio_base + 0xb890)
  6464. #define MIPI_INTR_STAT_REG_1(tc)        _TRANSCODER(tc, \
  6465.                                 _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
  6466. #define _MIPIA_INTR_EN_REG_1            (dev_priv->mipi_mmio_base + 0xb094)
  6467. #define _MIPIB_INTR_EN_REG_1            (dev_priv->mipi_mmio_base + 0xb894)
  6468. #define MIPI_INTR_EN_REG_1(tc)  _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \
  6469.                                         _MIPIB_INTR_EN_REG_1)
  6470. #define  RX_CONTENTION_DETECTED                         (1 << 0)
  6471.  
  6472. /* XXX: only pipe A ?!? */
  6473. #define MIPIA_DBI_TYPEC_CTRL            (dev_priv->mipi_mmio_base + 0xb100)
  6474. #define  DBI_TYPEC_ENABLE                               (1 << 31)
  6475. #define  DBI_TYPEC_WIP                                  (1 << 30)
  6476. #define  DBI_TYPEC_OPTION_SHIFT                         28
  6477. #define  DBI_TYPEC_OPTION_MASK                          (3 << 28)
  6478. #define  DBI_TYPEC_FREQ_SHIFT                           24
  6479. #define  DBI_TYPEC_FREQ_MASK                            (0xf << 24)
  6480. #define  DBI_TYPEC_OVERRIDE                             (1 << 8)
  6481. #define  DBI_TYPEC_OVERRIDE_COUNTER_SHIFT               0
  6482. #define  DBI_TYPEC_OVERRIDE_COUNTER_MASK                (0xff << 0)
  6483.  
  6484.  
  6485. /* MIPI adapter registers */
  6486.  
  6487. #define _MIPIA_CTRL                     (dev_priv->mipi_mmio_base + 0xb104)
  6488. #define _MIPIB_CTRL                     (dev_priv->mipi_mmio_base + 0xb904)
  6489. #define MIPI_CTRL(tc)                   _TRANSCODER(tc, _MIPIA_CTRL, \
  6490.                                         _MIPIB_CTRL)
  6491. #define  ESCAPE_CLOCK_DIVIDER_SHIFT                     5 /* A only */
  6492. #define  ESCAPE_CLOCK_DIVIDER_MASK                      (3 << 5)
  6493. #define  ESCAPE_CLOCK_DIVIDER_1                         (0 << 5)
  6494. #define  ESCAPE_CLOCK_DIVIDER_2                         (1 << 5)
  6495. #define  ESCAPE_CLOCK_DIVIDER_4                         (2 << 5)
  6496. #define  READ_REQUEST_PRIORITY_SHIFT                    3
  6497. #define  READ_REQUEST_PRIORITY_MASK                     (3 << 3)
  6498. #define  READ_REQUEST_PRIORITY_LOW                      (0 << 3)
  6499. #define  READ_REQUEST_PRIORITY_HIGH                     (3 << 3)
  6500. #define  RGB_FLIP_TO_BGR                                (1 << 2)
  6501.  
  6502. #define _MIPIA_DATA_ADDRESS             (dev_priv->mipi_mmio_base + 0xb108)
  6503. #define _MIPIB_DATA_ADDRESS             (dev_priv->mipi_mmio_base + 0xb908)
  6504. #define MIPI_DATA_ADDRESS(tc)           _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \
  6505.                                         _MIPIB_DATA_ADDRESS)
  6506. #define  DATA_MEM_ADDRESS_SHIFT                         5
  6507. #define  DATA_MEM_ADDRESS_MASK                          (0x7ffffff << 5)
  6508. #define  DATA_VALID                                     (1 << 0)
  6509.  
  6510. #define _MIPIA_DATA_LENGTH              (dev_priv->mipi_mmio_base + 0xb10c)
  6511. #define _MIPIB_DATA_LENGTH              (dev_priv->mipi_mmio_base + 0xb90c)
  6512. #define MIPI_DATA_LENGTH(tc)            _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \
  6513.                                         _MIPIB_DATA_LENGTH)
  6514. #define  DATA_LENGTH_SHIFT                              0
  6515. #define  DATA_LENGTH_MASK                               (0xfffff << 0)
  6516.  
  6517. #define _MIPIA_COMMAND_ADDRESS          (dev_priv->mipi_mmio_base + 0xb110)
  6518. #define _MIPIB_COMMAND_ADDRESS          (dev_priv->mipi_mmio_base + 0xb910)
  6519. #define MIPI_COMMAND_ADDRESS(tc)        _TRANSCODER(tc, \
  6520.                                 _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
  6521. #define  COMMAND_MEM_ADDRESS_SHIFT                      5
  6522. #define  COMMAND_MEM_ADDRESS_MASK                       (0x7ffffff << 5)
  6523. #define  AUTO_PWG_ENABLE                                (1 << 2)
  6524. #define  MEMORY_WRITE_DATA_FROM_PIPE_RENDERING          (1 << 1)
  6525. #define  COMMAND_VALID                                  (1 << 0)
  6526.  
  6527. #define _MIPIA_COMMAND_LENGTH           (dev_priv->mipi_mmio_base + 0xb114)
  6528. #define _MIPIB_COMMAND_LENGTH           (dev_priv->mipi_mmio_base + 0xb914)
  6529. #define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \
  6530.                                         _MIPIB_COMMAND_LENGTH)
  6531. #define  COMMAND_LENGTH_SHIFT(n)                        (8 * (n)) /* n: 0...3 */
  6532. #define  COMMAND_LENGTH_MASK(n)                         (0xff << (8 * (n)))
  6533.  
  6534. #define _MIPIA_READ_DATA_RETURN0        (dev_priv->mipi_mmio_base + 0xb118)
  6535. #define _MIPIB_READ_DATA_RETURN0        (dev_priv->mipi_mmio_base + 0xb918)
  6536. #define MIPI_READ_DATA_RETURN(tc, n) \
  6537.         (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \
  6538.                                         + 4 * (n)) /* n: 0...7 */
  6539.  
  6540. #define _MIPIA_READ_DATA_VALID          (dev_priv->mipi_mmio_base + 0xb138)
  6541. #define _MIPIB_READ_DATA_VALID          (dev_priv->mipi_mmio_base + 0xb938)
  6542. #define MIPI_READ_DATA_VALID(tc)        _TRANSCODER(tc, \
  6543.                                 _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
  6544. #define  READ_DATA_VALID(n)                             (1 << (n))
  6545.  
  6546. /* For UMS only (deprecated): */
  6547. #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
  6548. #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
  6549.  
  6550. #endif /* _I915_REG_H_ */
  6551.