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  1. /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  2.  * All Rights Reserved.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  */
  24.  
  25. #ifndef _I915_REG_H_
  26. #define _I915_REG_H_
  27.  
  28. #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
  29.  
  30. /*
  31.  * The Bridge device's PCI config space has information about the
  32.  * fb aperture size and the amount of pre-reserved memory.
  33.  * This is all handled in the intel-gtt.ko module. i915.ko only
  34.  * cares about the vga bit for the vga rbiter.
  35.  */
  36. #define INTEL_GMCH_CTRL         0x52
  37. #define INTEL_GMCH_VGA_DISABLE  (1 << 1)
  38.  
  39. /* PCI config space */
  40.  
  41. #define HPLLCC  0xc0 /* 855 only */
  42. #define   GC_CLOCK_CONTROL_MASK         (0xf << 0)
  43. #define   GC_CLOCK_133_200              (0 << 0)
  44. #define   GC_CLOCK_100_200              (1 << 0)
  45. #define   GC_CLOCK_100_133              (2 << 0)
  46. #define   GC_CLOCK_166_250              (3 << 0)
  47. #define GCFGC2  0xda
  48. #define GCFGC   0xf0 /* 915+ only */
  49. #define   GC_LOW_FREQUENCY_ENABLE       (1 << 7)
  50. #define   GC_DISPLAY_CLOCK_190_200_MHZ  (0 << 4)
  51. #define   GC_DISPLAY_CLOCK_333_MHZ      (4 << 4)
  52. #define   GC_DISPLAY_CLOCK_MASK         (7 << 4)
  53. #define   GM45_GC_RENDER_CLOCK_MASK     (0xf << 0)
  54. #define   GM45_GC_RENDER_CLOCK_266_MHZ  (8 << 0)
  55. #define   GM45_GC_RENDER_CLOCK_320_MHZ  (9 << 0)
  56. #define   GM45_GC_RENDER_CLOCK_400_MHZ  (0xb << 0)
  57. #define   GM45_GC_RENDER_CLOCK_533_MHZ  (0xc << 0)
  58. #define   I965_GC_RENDER_CLOCK_MASK     (0xf << 0)
  59. #define   I965_GC_RENDER_CLOCK_267_MHZ  (2 << 0)
  60. #define   I965_GC_RENDER_CLOCK_333_MHZ  (3 << 0)
  61. #define   I965_GC_RENDER_CLOCK_444_MHZ  (4 << 0)
  62. #define   I965_GC_RENDER_CLOCK_533_MHZ  (5 << 0)
  63. #define   I945_GC_RENDER_CLOCK_MASK     (7 << 0)
  64. #define   I945_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
  65. #define   I945_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
  66. #define   I945_GC_RENDER_CLOCK_250_MHZ  (3 << 0)
  67. #define   I945_GC_RENDER_CLOCK_400_MHZ  (5 << 0)
  68. #define   I915_GC_RENDER_CLOCK_MASK     (7 << 0)
  69. #define   I915_GC_RENDER_CLOCK_166_MHZ  (0 << 0)
  70. #define   I915_GC_RENDER_CLOCK_200_MHZ  (1 << 0)
  71. #define   I915_GC_RENDER_CLOCK_333_MHZ  (4 << 0)
  72. #define LBB     0xf4
  73.  
  74. /* Graphics reset regs */
  75. #define I965_GDRST 0xc0 /* PCI config register */
  76. #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
  77. #define  GRDOM_FULL     (0<<2)
  78. #define  GRDOM_RENDER   (1<<2)
  79. #define  GRDOM_MEDIA    (3<<2)
  80.  
  81. #define GEN6_MBCUNIT_SNPCR      0x900c /* for LLC config */
  82. #define   GEN6_MBC_SNPCR_SHIFT  21
  83. #define   GEN6_MBC_SNPCR_MASK   (3<<21)
  84. #define   GEN6_MBC_SNPCR_MAX    (0<<21)
  85. #define   GEN6_MBC_SNPCR_MED    (1<<21)
  86. #define   GEN6_MBC_SNPCR_LOW    (2<<21)
  87. #define   GEN6_MBC_SNPCR_MIN    (3<<21) /* only 1/16th of the cache is shared */
  88.  
  89. #define GEN6_GDRST      0x941c
  90. #define  GEN6_GRDOM_FULL                (1 << 0)
  91. #define  GEN6_GRDOM_RENDER              (1 << 1)
  92. #define  GEN6_GRDOM_MEDIA               (1 << 2)
  93. #define  GEN6_GRDOM_BLT                 (1 << 3)
  94.  
  95. /* VGA stuff */
  96.  
  97. #define VGA_ST01_MDA 0x3ba
  98. #define VGA_ST01_CGA 0x3da
  99.  
  100. #define VGA_MSR_WRITE 0x3c2
  101. #define VGA_MSR_READ 0x3cc
  102. #define   VGA_MSR_MEM_EN (1<<1)
  103. #define   VGA_MSR_CGA_MODE (1<<0)
  104.  
  105. #define VGA_SR_INDEX 0x3c4
  106. #define VGA_SR_DATA 0x3c5
  107.  
  108. #define VGA_AR_INDEX 0x3c0
  109. #define   VGA_AR_VID_EN (1<<5)
  110. #define VGA_AR_DATA_WRITE 0x3c0
  111. #define VGA_AR_DATA_READ 0x3c1
  112.  
  113. #define VGA_GR_INDEX 0x3ce
  114. #define VGA_GR_DATA 0x3cf
  115. /* GR05 */
  116. #define   VGA_GR_MEM_READ_MODE_SHIFT 3
  117. #define     VGA_GR_MEM_READ_MODE_PLANE 1
  118. /* GR06 */
  119. #define   VGA_GR_MEM_MODE_MASK 0xc
  120. #define   VGA_GR_MEM_MODE_SHIFT 2
  121. #define   VGA_GR_MEM_A0000_AFFFF 0
  122. #define   VGA_GR_MEM_A0000_BFFFF 1
  123. #define   VGA_GR_MEM_B0000_B7FFF 2
  124. #define   VGA_GR_MEM_B0000_BFFFF 3
  125.  
  126. #define VGA_DACMASK 0x3c6
  127. #define VGA_DACRX 0x3c7
  128. #define VGA_DACWX 0x3c8
  129. #define VGA_DACDATA 0x3c9
  130.  
  131. #define VGA_CR_INDEX_MDA 0x3b4
  132. #define VGA_CR_DATA_MDA 0x3b5
  133. #define VGA_CR_INDEX_CGA 0x3d4
  134. #define VGA_CR_DATA_CGA 0x3d5
  135.  
  136. /*
  137.  * Memory interface instructions used by the kernel
  138.  */
  139. #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
  140.  
  141. #define MI_NOOP                 MI_INSTR(0, 0)
  142. #define MI_USER_INTERRUPT       MI_INSTR(0x02, 0)
  143. #define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
  144. #define   MI_WAIT_FOR_OVERLAY_FLIP      (1<<16)
  145. #define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
  146. #define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
  147. #define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  148. #define MI_FLUSH                MI_INSTR(0x04, 0)
  149. #define   MI_READ_FLUSH         (1 << 0)
  150. #define   MI_EXE_FLUSH          (1 << 1)
  151. #define   MI_NO_WRITE_FLUSH     (1 << 2)
  152. #define   MI_SCENE_COUNT        (1 << 3) /* just increment scene count */
  153. #define   MI_END_SCENE          (1 << 4) /* flush binner and incr scene count */
  154. #define   MI_INVALIDATE_ISP     (1 << 5) /* invalidate indirect state pointers */
  155. #define MI_BATCH_BUFFER_END     MI_INSTR(0x0a, 0)
  156. #define MI_SUSPEND_FLUSH        MI_INSTR(0x0b, 0)
  157. #define   MI_SUSPEND_FLUSH_EN   (1<<0)
  158. #define MI_REPORT_HEAD          MI_INSTR(0x07, 0)
  159. #define MI_OVERLAY_FLIP         MI_INSTR(0x11,0)
  160. #define   MI_OVERLAY_CONTINUE   (0x0<<21)
  161. #define   MI_OVERLAY_ON         (0x1<<21)
  162. #define   MI_OVERLAY_OFF        (0x2<<21)
  163. #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
  164. #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
  165. #define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
  166. #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
  167. #define MI_SET_CONTEXT          MI_INSTR(0x18, 0)
  168. #define   MI_MM_SPACE_GTT               (1<<8)
  169. #define   MI_MM_SPACE_PHYSICAL          (0<<8)
  170. #define   MI_SAVE_EXT_STATE_EN          (1<<3)
  171. #define   MI_RESTORE_EXT_STATE_EN       (1<<2)
  172. #define   MI_FORCE_RESTORE              (1<<1)
  173. #define   MI_RESTORE_INHIBIT            (1<<0)
  174. #define MI_STORE_DWORD_IMM      MI_INSTR(0x20, 1)
  175. #define   MI_MEM_VIRTUAL        (1 << 22) /* 965+ only */
  176. #define MI_STORE_DWORD_INDEX    MI_INSTR(0x21, 1)
  177. #define   MI_STORE_DWORD_INDEX_SHIFT 2
  178. /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
  179.  * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
  180.  *   simply ignores the register load under certain conditions.
  181.  * - One can actually load arbitrary many arbitrary registers: Simply issue x
  182.  *   address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
  183.  */
  184. #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
  185. #define MI_FLUSH_DW             MI_INSTR(0x26, 1) /* for GEN6 */
  186. #define   MI_INVALIDATE_TLB     (1<<18)
  187. #define   MI_INVALIDATE_BSD     (1<<7)
  188. #define MI_BATCH_BUFFER         MI_INSTR(0x30, 1)
  189. #define   MI_BATCH_NON_SECURE   (1)
  190. #define   MI_BATCH_NON_SECURE_I965 (1<<8)
  191. #define MI_BATCH_BUFFER_START   MI_INSTR(0x31, 0)
  192. #define MI_SEMAPHORE_MBOX       MI_INSTR(0x16, 1) /* gen6+ */
  193. #define  MI_SEMAPHORE_GLOBAL_GTT    (1<<22)
  194. #define  MI_SEMAPHORE_UPDATE        (1<<21)
  195. #define  MI_SEMAPHORE_COMPARE       (1<<20)
  196. #define  MI_SEMAPHORE_REGISTER      (1<<18)
  197. /*
  198.  * 3D instructions used by the kernel
  199.  */
  200. #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
  201.  
  202. #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
  203. #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  204. #define   SC_UPDATE_SCISSOR       (0x1<<1)
  205. #define   SC_ENABLE_MASK          (0x1<<0)
  206. #define   SC_ENABLE               (0x1<<0)
  207. #define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
  208. #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  209. #define   SCI_YMIN_MASK      (0xffff<<16)
  210. #define   SCI_XMIN_MASK      (0xffff<<0)
  211. #define   SCI_YMAX_MASK      (0xffff<<16)
  212. #define   SCI_XMAX_MASK      (0xffff<<0)
  213. #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  214. #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
  215. #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  216. #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  217. #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
  218. #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  219. #define GFX_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
  220. #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  221. #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
  222. #define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
  223. #define XY_SRC_COPY_BLT_CMD             ((2<<29)|(0x53<<22)|6)
  224. #define XY_MONO_SRC_COPY_IMM_BLT        ((2<<29)|(0x71<<22)|5)
  225. #define XY_SRC_COPY_BLT_WRITE_ALPHA     (1<<21)
  226. #define XY_SRC_COPY_BLT_WRITE_RGB       (1<<20)
  227. #define   BLT_DEPTH_8                   (0<<24)
  228. #define   BLT_DEPTH_16_565              (1<<24)
  229. #define   BLT_DEPTH_16_1555             (2<<24)
  230. #define   BLT_DEPTH_32                  (3<<24)
  231. #define   BLT_ROP_GXCOPY                (0xcc<<16)
  232. #define XY_SRC_COPY_BLT_SRC_TILED       (1<<15) /* 965+ only */
  233. #define XY_SRC_COPY_BLT_DST_TILED       (1<<11) /* 965+ only */
  234. #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
  235. #define   ASYNC_FLIP                (1<<22)
  236. #define   DISPLAY_PLANE_A           (0<<20)
  237. #define   DISPLAY_PLANE_B           (1<<20)
  238. #define GFX_OP_PIPE_CONTROL     ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
  239. #define   PIPE_CONTROL_QW_WRITE (1<<14)
  240. #define   PIPE_CONTROL_DEPTH_STALL (1<<13)
  241. #define   PIPE_CONTROL_WC_FLUSH (1<<12)
  242. #define   PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
  243. #define   PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
  244. #define   PIPE_CONTROL_ISP_DIS  (1<<9)
  245. #define   PIPE_CONTROL_NOTIFY   (1<<8)
  246. #define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
  247. #define   PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
  248.  
  249.  
  250. /*
  251.  * Reset registers
  252.  */
  253. #define DEBUG_RESET_I830                0x6070
  254. #define  DEBUG_RESET_FULL               (1<<7)
  255. #define  DEBUG_RESET_RENDER             (1<<8)
  256. #define  DEBUG_RESET_DISPLAY            (1<<9)
  257.  
  258.  
  259. /*
  260.  * Fence registers
  261.  */
  262. #define FENCE_REG_830_0                 0x2000
  263. #define FENCE_REG_945_8                 0x3000
  264. #define   I830_FENCE_START_MASK         0x07f80000
  265. #define   I830_FENCE_TILING_Y_SHIFT     12
  266. #define   I830_FENCE_SIZE_BITS(size)    ((ffs((size) >> 19) - 1) << 8)
  267. #define   I830_FENCE_PITCH_SHIFT        4
  268. #define   I830_FENCE_REG_VALID          (1<<0)
  269. #define   I915_FENCE_MAX_PITCH_VAL      4
  270. #define   I830_FENCE_MAX_PITCH_VAL      6
  271. #define   I830_FENCE_MAX_SIZE_VAL       (1<<8)
  272.  
  273. #define   I915_FENCE_START_MASK         0x0ff00000
  274. #define   I915_FENCE_SIZE_BITS(size)    ((ffs((size) >> 20) - 1) << 8)
  275.  
  276. #define FENCE_REG_965_0                 0x03000
  277. #define   I965_FENCE_PITCH_SHIFT        2
  278. #define   I965_FENCE_TILING_Y_SHIFT     1
  279. #define   I965_FENCE_REG_VALID          (1<<0)
  280. #define   I965_FENCE_MAX_PITCH_VAL      0x0400
  281.  
  282. #define FENCE_REG_SANDYBRIDGE_0         0x100000
  283. #define   SANDYBRIDGE_FENCE_PITCH_SHIFT 32
  284.  
  285. /*
  286.  * Instruction and interrupt control regs
  287.  */
  288. #define PGTBL_ER        0x02024
  289. #define RENDER_RING_BASE        0x02000
  290. #define BSD_RING_BASE           0x04000
  291. #define GEN6_BSD_RING_BASE      0x12000
  292. #define BLT_RING_BASE           0x22000
  293. #define RING_TAIL(base)         ((base)+0x30)
  294. #define RING_HEAD(base)         ((base)+0x34)
  295. #define RING_START(base)        ((base)+0x38)
  296. #define RING_CTL(base)          ((base)+0x3c)
  297. #define RING_SYNC_0(base)       ((base)+0x40)
  298. #define RING_SYNC_1(base)       ((base)+0x44)
  299. #define RING_MAX_IDLE(base)     ((base)+0x54)
  300. #define RING_HWS_PGA(base)      ((base)+0x80)
  301. #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
  302. #define RENDER_HWS_PGA_GEN7     (0x04080)
  303. #define BSD_HWS_PGA_GEN7        (0x04180)
  304. #define BLT_HWS_PGA_GEN7        (0x04280)
  305. #define RING_ACTHD(base)        ((base)+0x74)
  306. #define RING_NOPID(base)        ((base)+0x94)
  307. #define RING_IMR(base)          ((base)+0xa8)
  308. #define   TAIL_ADDR             0x001FFFF8
  309. #define   HEAD_WRAP_COUNT       0xFFE00000
  310. #define   HEAD_WRAP_ONE         0x00200000
  311. #define   HEAD_ADDR             0x001FFFFC
  312. #define   RING_NR_PAGES         0x001FF000
  313. #define   RING_REPORT_MASK      0x00000006
  314. #define   RING_REPORT_64K       0x00000002
  315. #define   RING_REPORT_128K      0x00000004
  316. #define   RING_NO_REPORT        0x00000000
  317. #define   RING_VALID_MASK       0x00000001
  318. #define   RING_VALID            0x00000001
  319. #define   RING_INVALID          0x00000000
  320. #define   RING_WAIT_I8XX        (1<<0) /* gen2, PRBx_HEAD */
  321. #define   RING_WAIT             (1<<11) /* gen3+, PRBx_CTL */
  322. #define   RING_WAIT_SEMAPHORE   (1<<10) /* gen6+ */
  323. #if 0
  324. #define PRB0_TAIL       0x02030
  325. #define PRB0_HEAD       0x02034
  326. #define PRB0_START      0x02038
  327. #define PRB0_CTL        0x0203c
  328. #define PRB1_TAIL       0x02040 /* 915+ only */
  329. #define PRB1_HEAD       0x02044 /* 915+ only */
  330. #define PRB1_START      0x02048 /* 915+ only */
  331. #define PRB1_CTL        0x0204c /* 915+ only */
  332. #endif
  333. #define IPEIR_I965      0x02064
  334. #define IPEHR_I965      0x02068
  335. #define INSTDONE_I965   0x0206c
  336. #define INSTPS          0x02070 /* 965+ only */
  337. #define INSTDONE1       0x0207c /* 965+ only */
  338. #define ACTHD_I965      0x02074
  339. #define HWS_PGA         0x02080
  340. #define HWS_ADDRESS_MASK        0xfffff000
  341. #define HWS_START_ADDRESS_SHIFT 4
  342. #define PWRCTXA         0x2088 /* 965GM+ only */
  343. #define   PWRCTX_EN     (1<<0)
  344. #define IPEIR           0x02088
  345. #define IPEHR           0x0208c
  346. #define INSTDONE        0x02090
  347. #define NOPID           0x02094
  348. #define HWSTAM          0x02098
  349. #define VCS_INSTDONE    0x1206C
  350. #define VCS_IPEIR       0x12064
  351. #define VCS_IPEHR       0x12068
  352. #define VCS_ACTHD       0x12074
  353. #define BCS_INSTDONE    0x2206C
  354. #define BCS_IPEIR       0x22064
  355. #define BCS_IPEHR       0x22068
  356. #define BCS_ACTHD       0x22074
  357.  
  358. #define ERROR_GEN6      0x040a0
  359.  
  360. /* GM45+ chicken bits -- debug workaround bits that may be required
  361.  * for various sorts of correct behavior.  The top 16 bits of each are
  362.  * the enables for writing to the corresponding low bit.
  363.  */
  364. #define _3D_CHICKEN     0x02084
  365. #define _3D_CHICKEN2    0x0208c
  366. /* Disables pipelining of read flushes past the SF-WIZ interface.
  367.  * Required on all Ironlake steppings according to the B-Spec, but the
  368.  * particular danger of not doing so is not specified.
  369.  */
  370. # define _3D_CHICKEN2_WM_READ_PIPELINED                 (1 << 14)
  371. #define _3D_CHICKEN3    0x02090
  372.  
  373. #define MI_MODE         0x0209c
  374. # define VS_TIMER_DISPATCH                              (1 << 6)
  375. # define MI_FLUSH_ENABLE                                (1 << 11)
  376.  
  377. #define GFX_MODE        0x02520
  378. #define GFX_MODE_GEN7   0x0229c
  379. #define   GFX_RUN_LIST_ENABLE           (1<<15)
  380. #define   GFX_TLB_INVALIDATE_ALWAYS     (1<<13)
  381. #define   GFX_SURFACE_FAULT_ENABLE      (1<<12)
  382. #define   GFX_REPLAY_MODE               (1<<11)
  383. #define   GFX_PSMI_GRANULARITY          (1<<10)
  384. #define   GFX_PPGTT_ENABLE              (1<<9)
  385.  
  386. #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
  387. #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
  388.  
  389. #define SCPD0           0x0209c /* 915+ only */
  390. #define IER             0x020a0
  391. #define IIR             0x020a4
  392. #define IMR             0x020a8
  393. #define ISR             0x020ac
  394. #define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT            (1<<18)
  395. #define   I915_DISPLAY_PORT_INTERRUPT                   (1<<17)
  396. #define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT    (1<<15)
  397. #define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT      (1<<14) /* p-state */
  398. #define   I915_HWB_OOM_INTERRUPT                        (1<<13)
  399. #define   I915_SYNC_STATUS_INTERRUPT                    (1<<12)
  400. #define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT   (1<<11)
  401. #define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT   (1<<10)
  402. #define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT     (1<<9)
  403. #define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT   (1<<8)
  404. #define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT          (1<<7)
  405. #define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT           (1<<6)
  406. #define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT          (1<<5)
  407. #define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT           (1<<4)
  408. #define   I915_DEBUG_INTERRUPT                          (1<<2)
  409. #define   I915_USER_INTERRUPT                           (1<<1)
  410. #define   I915_ASLE_INTERRUPT                           (1<<0)
  411. #define   I915_BSD_USER_INTERRUPT                      (1<<25)
  412. #define EIR             0x020b0
  413. #define EMR             0x020b4
  414. #define ESR             0x020b8
  415. #define   GM45_ERROR_PAGE_TABLE                         (1<<5)
  416. #define   GM45_ERROR_MEM_PRIV                           (1<<4)
  417. #define   I915_ERROR_PAGE_TABLE                         (1<<4)
  418. #define   GM45_ERROR_CP_PRIV                            (1<<3)
  419. #define   I915_ERROR_MEMORY_REFRESH                     (1<<1)
  420. #define   I915_ERROR_INSTRUCTION                        (1<<0)
  421. #define INSTPM          0x020c0
  422. #define   INSTPM_SELF_EN (1<<12) /* 915GM only */
  423. #define   INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
  424.                                         will not assert AGPBUSY# and will only
  425.                                         be delivered when out of C3. */
  426. #define ACTHD           0x020c8
  427. #define FW_BLC          0x020d8
  428. #define FW_BLC2         0x020dc
  429. #define FW_BLC_SELF     0x020e0 /* 915+ only */
  430. #define   FW_BLC_SELF_EN_MASK      (1<<31)
  431. #define   FW_BLC_SELF_FIFO_MASK    (1<<16) /* 945 only */
  432. #define   FW_BLC_SELF_EN           (1<<15) /* 945 only */
  433. #define MM_BURST_LENGTH     0x00700000
  434. #define MM_FIFO_WATERMARK   0x0001F000
  435. #define LM_BURST_LENGTH     0x00000700
  436. #define LM_FIFO_WATERMARK   0x0000001F
  437. #define MI_ARB_STATE    0x020e4 /* 915+ only */
  438. #define   MI_ARB_MASK_SHIFT       16    /* shift for enable bits */
  439.  
  440. /* Make render/texture TLB fetches lower priorty than associated data
  441.  *   fetches. This is not turned on by default
  442.  */
  443. #define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
  444.  
  445. /* Isoch request wait on GTT enable (Display A/B/C streams).
  446.  * Make isoch requests stall on the TLB update. May cause
  447.  * display underruns (test mode only)
  448.  */
  449. #define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
  450.  
  451. /* Block grant count for isoch requests when block count is
  452.  * set to a finite value.
  453.  */
  454. #define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
  455. #define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
  456. #define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
  457. #define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
  458. #define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
  459.  
  460. /* Enable render writes to complete in C2/C3/C4 power states.
  461.  * If this isn't enabled, render writes are prevented in low
  462.  * power states. That seems bad to me.
  463.  */
  464. #define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
  465.  
  466. /* This acknowledges an async flip immediately instead
  467.  * of waiting for 2TLB fetches.
  468.  */
  469. #define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
  470.  
  471. /* Enables non-sequential data reads through arbiter
  472.  */
  473. #define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
  474.  
  475. /* Disable FSB snooping of cacheable write cycles from binner/render
  476.  * command stream
  477.  */
  478. #define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
  479.  
  480. /* Arbiter time slice for non-isoch streams */
  481. #define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
  482. #define   MI_ARB_TIME_SLICE_1                   (0 << 5)
  483. #define   MI_ARB_TIME_SLICE_2                   (1 << 5)
  484. #define   MI_ARB_TIME_SLICE_4                   (2 << 5)
  485. #define   MI_ARB_TIME_SLICE_6                   (3 << 5)
  486. #define   MI_ARB_TIME_SLICE_8                   (4 << 5)
  487. #define   MI_ARB_TIME_SLICE_10                  (5 << 5)
  488. #define   MI_ARB_TIME_SLICE_14                  (6 << 5)
  489. #define   MI_ARB_TIME_SLICE_16                  (7 << 5)
  490.  
  491. /* Low priority grace period page size */
  492. #define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
  493. #define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
  494.  
  495. /* Disable display A/B trickle feed */
  496. #define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
  497.  
  498. /* Set display plane priority */
  499. #define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
  500. #define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
  501.  
  502. #define CACHE_MODE_0    0x02120 /* 915+ only */
  503. #define   CM0_MASK_SHIFT          16
  504. #define   CM0_IZ_OPT_DISABLE      (1<<6)
  505. #define   CM0_ZR_OPT_DISABLE      (1<<5)
  506. #define   CM0_DEPTH_EVICT_DISABLE (1<<4)
  507. #define   CM0_COLOR_EVICT_DISABLE (1<<3)
  508. #define   CM0_DEPTH_WRITE_DISABLE (1<<1)
  509. #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
  510. #define BB_ADDR         0x02140 /* 8 bytes */
  511. #define GFX_FLSH_CNTL   0x02170 /* 915+ only */
  512. #define ECOSKPD         0x021d0
  513. #define   ECO_GATING_CX_ONLY    (1<<3)
  514. #define   ECO_FLIP_DONE         (1<<0)
  515.  
  516. /* GEN6 interrupt control */
  517. #define GEN6_RENDER_HWSTAM      0x2098
  518. #define GEN6_RENDER_IMR         0x20a8
  519. #define   GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT          (1 << 8)
  520. #define   GEN6_RENDER_PPGTT_PAGE_FAULT                  (1 << 7)
  521. #define   GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED           (1 << 6)
  522. #define   GEN6_RENDER_L3_PARITY_ERROR                   (1 << 5)
  523. #define   GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT     (1 << 4)
  524. #define   GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR       (1 << 3)
  525. #define   GEN6_RENDER_SYNC_STATUS                       (1 << 2)
  526. #define   GEN6_RENDER_DEBUG_INTERRUPT                   (1 << 1)
  527. #define   GEN6_RENDER_USER_INTERRUPT                    (1 << 0)
  528.  
  529. #define GEN6_BLITTER_HWSTAM     0x22098
  530. #define GEN6_BLITTER_IMR        0x220a8
  531. #define   GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT     (1 << 26)
  532. #define   GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR      (1 << 25)
  533. #define   GEN6_BLITTER_SYNC_STATUS                      (1 << 24)
  534. #define   GEN6_BLITTER_USER_INTERRUPT                   (1 << 22)
  535.  
  536. #define GEN6_BLITTER_ECOSKPD    0x221d0
  537. #define   GEN6_BLITTER_LOCK_SHIFT                       16
  538. #define   GEN6_BLITTER_FBC_NOTIFY                       (1<<3)
  539.  
  540. #define GEN6_BSD_SLEEP_PSMI_CONTROL     0x12050
  541. #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK       (1 << 16)
  542. #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE           (1 << 0)
  543. #define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE            0
  544. #define   GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR                    (1 << 3)
  545.  
  546. #define GEN6_BSD_HWSTAM                 0x12098
  547. #define GEN6_BSD_IMR                    0x120a8
  548. #define   GEN6_BSD_USER_INTERRUPT       (1 << 12)
  549.  
  550. #define GEN6_BSD_RNCID                  0x12198
  551.  
  552. /*
  553.  * Framebuffer compression (915+ only)
  554.  */
  555.  
  556. #define FBC_CFB_BASE            0x03200 /* 4k page aligned */
  557. #define FBC_LL_BASE             0x03204 /* 4k page aligned */
  558. #define FBC_CONTROL             0x03208
  559. #define   FBC_CTL_EN            (1<<31)
  560. #define   FBC_CTL_PERIODIC      (1<<30)
  561. #define   FBC_CTL_INTERVAL_SHIFT (16)
  562. #define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
  563. #define   FBC_CTL_C3_IDLE       (1<<13)
  564. #define   FBC_CTL_STRIDE_SHIFT  (5)
  565. #define   FBC_CTL_FENCENO       (1<<0)
  566. #define FBC_COMMAND             0x0320c
  567. #define   FBC_CMD_COMPRESS      (1<<0)
  568. #define FBC_STATUS              0x03210
  569. #define   FBC_STAT_COMPRESSING  (1<<31)
  570. #define   FBC_STAT_COMPRESSED   (1<<30)
  571. #define   FBC_STAT_MODIFIED     (1<<29)
  572. #define   FBC_STAT_CURRENT_LINE (1<<0)
  573. #define FBC_CONTROL2            0x03214
  574. #define   FBC_CTL_FENCE_DBL     (0<<4)
  575. #define   FBC_CTL_IDLE_IMM      (0<<2)
  576. #define   FBC_CTL_IDLE_FULL     (1<<2)
  577. #define   FBC_CTL_IDLE_LINE     (2<<2)
  578. #define   FBC_CTL_IDLE_DEBUG    (3<<2)
  579. #define   FBC_CTL_CPU_FENCE     (1<<1)
  580. #define   FBC_CTL_PLANEA        (0<<0)
  581. #define   FBC_CTL_PLANEB        (1<<0)
  582. #define FBC_FENCE_OFF           0x0321b
  583. #define FBC_TAG                 0x03300
  584.  
  585. #define FBC_LL_SIZE             (1536)
  586.  
  587. /* Framebuffer compression for GM45+ */
  588. #define DPFC_CB_BASE            0x3200
  589. #define DPFC_CONTROL            0x3208
  590. #define   DPFC_CTL_EN           (1<<31)
  591. #define   DPFC_CTL_PLANEA       (0<<30)
  592. #define   DPFC_CTL_PLANEB       (1<<30)
  593. #define   DPFC_CTL_FENCE_EN     (1<<29)
  594. #define   DPFC_CTL_PERSISTENT_MODE      (1<<25)
  595. #define   DPFC_SR_EN            (1<<10)
  596. #define   DPFC_CTL_LIMIT_1X     (0<<6)
  597. #define   DPFC_CTL_LIMIT_2X     (1<<6)
  598. #define   DPFC_CTL_LIMIT_4X     (2<<6)
  599. #define DPFC_RECOMP_CTL         0x320c
  600. #define   DPFC_RECOMP_STALL_EN  (1<<27)
  601. #define   DPFC_RECOMP_STALL_WM_SHIFT (16)
  602. #define   DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
  603. #define   DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
  604. #define   DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
  605. #define DPFC_STATUS             0x3210
  606. #define   DPFC_INVAL_SEG_SHIFT  (16)
  607. #define   DPFC_INVAL_SEG_MASK   (0x07ff0000)
  608. #define   DPFC_COMP_SEG_SHIFT   (0)
  609. #define   DPFC_COMP_SEG_MASK    (0x000003ff)
  610. #define DPFC_STATUS2            0x3214
  611. #define DPFC_FENCE_YOFF         0x3218
  612. #define DPFC_CHICKEN            0x3224
  613. #define   DPFC_HT_MODIFY        (1<<31)
  614.  
  615. /* Framebuffer compression for Ironlake */
  616. #define ILK_DPFC_CB_BASE        0x43200
  617. #define ILK_DPFC_CONTROL        0x43208
  618. /* The bit 28-8 is reserved */
  619. #define   DPFC_RESERVED         (0x1FFFFF00)
  620. #define ILK_DPFC_RECOMP_CTL     0x4320c
  621. #define ILK_DPFC_STATUS         0x43210
  622. #define ILK_DPFC_FENCE_YOFF     0x43218
  623. #define ILK_DPFC_CHICKEN        0x43224
  624. #define ILK_FBC_RT_BASE         0x2128
  625. #define   ILK_FBC_RT_VALID      (1<<0)
  626.  
  627. #define ILK_DISPLAY_CHICKEN1    0x42000
  628. #define   ILK_FBCQ_DIS          (1<<22)
  629. #define   ILK_PABSTRETCH_DIS    (1<<21)
  630.  
  631.  
  632. /*
  633.  * Framebuffer compression for Sandybridge
  634.  *
  635.  * The following two registers are of type GTTMMADR
  636.  */
  637. #define SNB_DPFC_CTL_SA         0x100100
  638. #define   SNB_CPU_FENCE_ENABLE  (1<<29)
  639. #define DPFC_CPU_FENCE_OFFSET   0x100104
  640.  
  641.  
  642. /*
  643.  * GPIO regs
  644.  */
  645. #define GPIOA                   0x5010
  646. #define GPIOB                   0x5014
  647. #define GPIOC                   0x5018
  648. #define GPIOD                   0x501c
  649. #define GPIOE                   0x5020
  650. #define GPIOF                   0x5024
  651. #define GPIOG                   0x5028
  652. #define GPIOH                   0x502c
  653. # define GPIO_CLOCK_DIR_MASK            (1 << 0)
  654. # define GPIO_CLOCK_DIR_IN              (0 << 1)
  655. # define GPIO_CLOCK_DIR_OUT             (1 << 1)
  656. # define GPIO_CLOCK_VAL_MASK            (1 << 2)
  657. # define GPIO_CLOCK_VAL_OUT             (1 << 3)
  658. # define GPIO_CLOCK_VAL_IN              (1 << 4)
  659. # define GPIO_CLOCK_PULLUP_DISABLE      (1 << 5)
  660. # define GPIO_DATA_DIR_MASK             (1 << 8)
  661. # define GPIO_DATA_DIR_IN               (0 << 9)
  662. # define GPIO_DATA_DIR_OUT              (1 << 9)
  663. # define GPIO_DATA_VAL_MASK             (1 << 10)
  664. # define GPIO_DATA_VAL_OUT              (1 << 11)
  665. # define GPIO_DATA_VAL_IN               (1 << 12)
  666. # define GPIO_DATA_PULLUP_DISABLE       (1 << 13)
  667.  
  668. #define GMBUS0                  0x5100 /* clock/port select */
  669. #define   GMBUS_RATE_100KHZ     (0<<8)
  670. #define   GMBUS_RATE_50KHZ      (1<<8)
  671. #define   GMBUS_RATE_400KHZ     (2<<8) /* reserved on Pineview */
  672. #define   GMBUS_RATE_1MHZ       (3<<8) /* reserved on Pineview */
  673. #define   GMBUS_HOLD_EXT        (1<<7) /* 300ns hold time, rsvd on Pineview */
  674. #define   GMBUS_PORT_DISABLED   0
  675. #define   GMBUS_PORT_SSC        1
  676. #define   GMBUS_PORT_VGADDC     2
  677. #define   GMBUS_PORT_PANEL      3
  678. #define   GMBUS_PORT_DPC        4 /* HDMIC */
  679. #define   GMBUS_PORT_DPB        5 /* SDVO, HDMIB */
  680.                                   /* 6 reserved */
  681. #define   GMBUS_PORT_DPD        7 /* HDMID */
  682. #define   GMBUS_NUM_PORTS       8
  683. #define GMBUS1                  0x5104 /* command/status */
  684. #define   GMBUS_SW_CLR_INT      (1<<31)
  685. #define   GMBUS_SW_RDY          (1<<30)
  686. #define   GMBUS_ENT             (1<<29) /* enable timeout */
  687. #define   GMBUS_CYCLE_NONE      (0<<25)
  688. #define   GMBUS_CYCLE_WAIT      (1<<25)
  689. #define   GMBUS_CYCLE_INDEX     (2<<25)
  690. #define   GMBUS_CYCLE_STOP      (4<<25)
  691. #define   GMBUS_BYTE_COUNT_SHIFT 16
  692. #define   GMBUS_SLAVE_INDEX_SHIFT 8
  693. #define   GMBUS_SLAVE_ADDR_SHIFT 1
  694. #define   GMBUS_SLAVE_READ      (1<<0)
  695. #define   GMBUS_SLAVE_WRITE     (0<<0)
  696. #define GMBUS2                  0x5108 /* status */
  697. #define   GMBUS_INUSE           (1<<15)
  698. #define   GMBUS_HW_WAIT_PHASE   (1<<14)
  699. #define   GMBUS_STALL_TIMEOUT   (1<<13)
  700. #define   GMBUS_INT             (1<<12)
  701. #define   GMBUS_HW_RDY          (1<<11)
  702. #define   GMBUS_SATOER          (1<<10)
  703. #define   GMBUS_ACTIVE          (1<<9)
  704. #define GMBUS3                  0x510c /* data buffer bytes 3-0 */
  705. #define GMBUS4                  0x5110 /* interrupt mask (Pineview+) */
  706. #define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
  707. #define   GMBUS_NAK_EN          (1<<3)
  708. #define   GMBUS_IDLE_EN         (1<<2)
  709. #define   GMBUS_HW_WAIT_EN      (1<<1)
  710. #define   GMBUS_HW_RDY_EN       (1<<0)
  711. #define GMBUS5                  0x5120 /* byte index */
  712. #define   GMBUS_2BYTE_INDEX_EN  (1<<31)
  713.  
  714. /*
  715.  * Clock control & power management
  716.  */
  717.  
  718. #define VGA0    0x6000
  719. #define VGA1    0x6004
  720. #define VGA_PD  0x6010
  721. #define   VGA0_PD_P2_DIV_4      (1 << 7)
  722. #define   VGA0_PD_P1_DIV_2      (1 << 5)
  723. #define   VGA0_PD_P1_SHIFT      0
  724. #define   VGA0_PD_P1_MASK       (0x1f << 0)
  725. #define   VGA1_PD_P2_DIV_4      (1 << 15)
  726. #define   VGA1_PD_P1_DIV_2      (1 << 13)
  727. #define   VGA1_PD_P1_SHIFT      8
  728. #define   VGA1_PD_P1_MASK       (0x1f << 8)
  729. #define _DPLL_A 0x06014
  730. #define _DPLL_B 0x06018
  731. #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
  732. #define   DPLL_VCO_ENABLE               (1 << 31)
  733. #define   DPLL_DVO_HIGH_SPEED           (1 << 30)
  734. #define   DPLL_SYNCLOCK_ENABLE          (1 << 29)
  735. #define   DPLL_VGA_MODE_DIS             (1 << 28)
  736. #define   DPLLB_MODE_DAC_SERIAL         (1 << 26) /* i915 */
  737. #define   DPLLB_MODE_LVDS               (2 << 26) /* i915 */
  738. #define   DPLL_MODE_MASK                (3 << 26)
  739. #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
  740. #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
  741. #define   DPLLB_LVDS_P2_CLOCK_DIV_14    (0 << 24) /* i915 */
  742. #define   DPLLB_LVDS_P2_CLOCK_DIV_7     (1 << 24) /* i915 */
  743. #define   DPLL_P2_CLOCK_DIV_MASK        0x03000000 /* i915 */
  744. #define   DPLL_FPA01_P1_POST_DIV_MASK   0x00ff0000 /* i915 */
  745. #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW  0x00ff8000 /* Pineview */
  746.  
  747. #define SRX_INDEX               0x3c4
  748. #define SRX_DATA                0x3c5
  749. #define SR01                    1
  750. #define SR01_SCREEN_OFF         (1<<5)
  751.  
  752. #define PPCR                    0x61204
  753. #define PPCR_ON                 (1<<0)
  754.  
  755. #define DVOB                    0x61140
  756. #define DVOB_ON                 (1<<31)
  757. #define DVOC                    0x61160
  758. #define DVOC_ON                 (1<<31)
  759. #define LVDS                    0x61180
  760. #define LVDS_ON                 (1<<31)
  761.  
  762. /* Scratch pad debug 0 reg:
  763.  */
  764. #define   DPLL_FPA01_P1_POST_DIV_MASK_I830      0x001f0000
  765. /*
  766.  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
  767.  * this field (only one bit may be set).
  768.  */
  769. #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
  770. #define   DPLL_FPA01_P1_POST_DIV_SHIFT  16
  771. #define   DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
  772. /* i830, required in DVO non-gang */
  773. #define   PLL_P2_DIVIDE_BY_4            (1 << 23)
  774. #define   PLL_P1_DIVIDE_BY_TWO          (1 << 21) /* i830 */
  775. #define   PLL_REF_INPUT_DREFCLK         (0 << 13)
  776. #define   PLL_REF_INPUT_TVCLKINA        (1 << 13) /* i830 */
  777. #define   PLL_REF_INPUT_TVCLKINBC       (2 << 13) /* SDVO TVCLKIN */
  778. #define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
  779. #define   PLL_REF_INPUT_MASK            (3 << 13)
  780. #define   PLL_LOAD_PULSE_PHASE_SHIFT            9
  781. /* Ironlake */
  782. # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT     9
  783. # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK      (7 << 9)
  784. # define PLL_REF_SDVO_HDMI_MULTIPLIER(x)        (((x)-1) << 9)
  785. # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
  786. # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
  787.  
  788. /*
  789.  * Parallel to Serial Load Pulse phase selection.
  790.  * Selects the phase for the 10X DPLL clock for the PCIe
  791.  * digital display port. The range is 4 to 13; 10 or more
  792.  * is just a flip delay. The default is 6
  793.  */
  794. #define   PLL_LOAD_PULSE_PHASE_MASK             (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
  795. #define   DISPLAY_RATE_SELECT_FPA1              (1 << 8)
  796. /*
  797.  * SDVO multiplier for 945G/GM. Not used on 965.
  798.  */
  799. #define   SDVO_MULTIPLIER_MASK                  0x000000ff
  800. #define   SDVO_MULTIPLIER_SHIFT_HIRES           4
  801. #define   SDVO_MULTIPLIER_SHIFT_VGA             0
  802. #define _DPLL_A_MD 0x0601c /* 965+ only */
  803. /*
  804.  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  805.  *
  806.  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
  807.  */
  808. #define   DPLL_MD_UDI_DIVIDER_MASK              0x3f000000
  809. #define   DPLL_MD_UDI_DIVIDER_SHIFT             24
  810. /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
  811. #define   DPLL_MD_VGA_UDI_DIVIDER_MASK          0x003f0000
  812. #define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT         16
  813. /*
  814.  * SDVO/UDI pixel multiplier.
  815.  *
  816.  * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
  817.  * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
  818.  * modes, the bus rate would be below the limits, so SDVO allows for stuffing
  819.  * dummy bytes in the datastream at an increased clock rate, with both sides of
  820.  * the link knowing how many bytes are fill.
  821.  *
  822.  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
  823.  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
  824.  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
  825.  * through an SDVO command.
  826.  *
  827.  * This register field has values of multiplication factor minus 1, with
  828.  * a maximum multiplier of 5 for SDVO.
  829.  */
  830. #define   DPLL_MD_UDI_MULTIPLIER_MASK           0x00003f00
  831. #define   DPLL_MD_UDI_MULTIPLIER_SHIFT          8
  832. /*
  833.  * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
  834.  * This best be set to the default value (3) or the CRT won't work. No,
  835.  * I don't entirely understand what this does...
  836.  */
  837. #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK       0x0000003f
  838. #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT      0
  839. #define _DPLL_B_MD 0x06020 /* 965+ only */
  840. #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
  841. #define _FPA0   0x06040
  842. #define _FPA1   0x06044
  843. #define _FPB0   0x06048
  844. #define _FPB1   0x0604c
  845. #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
  846. #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
  847. #define   FP_N_DIV_MASK         0x003f0000
  848. #define   FP_N_PINEVIEW_DIV_MASK        0x00ff0000
  849. #define   FP_N_DIV_SHIFT                16
  850. #define   FP_M1_DIV_MASK        0x00003f00
  851. #define   FP_M1_DIV_SHIFT                8
  852. #define   FP_M2_DIV_MASK        0x0000003f
  853. #define   FP_M2_PINEVIEW_DIV_MASK       0x000000ff
  854. #define   FP_M2_DIV_SHIFT                0
  855. #define DPLL_TEST       0x606c
  856. #define   DPLLB_TEST_SDVO_DIV_1         (0 << 22)
  857. #define   DPLLB_TEST_SDVO_DIV_2         (1 << 22)
  858. #define   DPLLB_TEST_SDVO_DIV_4         (2 << 22)
  859. #define   DPLLB_TEST_SDVO_DIV_MASK      (3 << 22)
  860. #define   DPLLB_TEST_N_BYPASS           (1 << 19)
  861. #define   DPLLB_TEST_M_BYPASS           (1 << 18)
  862. #define   DPLLB_INPUT_BUFFER_ENABLE     (1 << 16)
  863. #define   DPLLA_TEST_N_BYPASS           (1 << 3)
  864. #define   DPLLA_TEST_M_BYPASS           (1 << 2)
  865. #define   DPLLA_INPUT_BUFFER_ENABLE     (1 << 0)
  866. #define D_STATE         0x6104
  867. #define  DSTATE_GFX_RESET_I830                  (1<<6)
  868. #define  DSTATE_PLL_D3_OFF                      (1<<3)
  869. #define  DSTATE_GFX_CLOCK_GATING                (1<<1)
  870. #define  DSTATE_DOT_CLOCK_GATING                (1<<0)
  871. #define DSPCLK_GATE_D           0x6200
  872. # define DPUNIT_B_CLOCK_GATE_DISABLE            (1 << 30) /* 965 */
  873. # define VSUNIT_CLOCK_GATE_DISABLE              (1 << 29) /* 965 */
  874. # define VRHUNIT_CLOCK_GATE_DISABLE             (1 << 28) /* 965 */
  875. # define VRDUNIT_CLOCK_GATE_DISABLE             (1 << 27) /* 965 */
  876. # define AUDUNIT_CLOCK_GATE_DISABLE             (1 << 26) /* 965 */
  877. # define DPUNIT_A_CLOCK_GATE_DISABLE            (1 << 25) /* 965 */
  878. # define DPCUNIT_CLOCK_GATE_DISABLE             (1 << 24) /* 965 */
  879. # define TVRUNIT_CLOCK_GATE_DISABLE             (1 << 23) /* 915-945 */
  880. # define TVCUNIT_CLOCK_GATE_DISABLE             (1 << 22) /* 915-945 */
  881. # define TVFUNIT_CLOCK_GATE_DISABLE             (1 << 21) /* 915-945 */
  882. # define TVEUNIT_CLOCK_GATE_DISABLE             (1 << 20) /* 915-945 */
  883. # define DVSUNIT_CLOCK_GATE_DISABLE             (1 << 19) /* 915-945 */
  884. # define DSSUNIT_CLOCK_GATE_DISABLE             (1 << 18) /* 915-945 */
  885. # define DDBUNIT_CLOCK_GATE_DISABLE             (1 << 17) /* 915-945 */
  886. # define DPRUNIT_CLOCK_GATE_DISABLE             (1 << 16) /* 915-945 */
  887. # define DPFUNIT_CLOCK_GATE_DISABLE             (1 << 15) /* 915-945 */
  888. # define DPBMUNIT_CLOCK_GATE_DISABLE            (1 << 14) /* 915-945 */
  889. # define DPLSUNIT_CLOCK_GATE_DISABLE            (1 << 13) /* 915-945 */
  890. # define DPLUNIT_CLOCK_GATE_DISABLE             (1 << 12) /* 915-945 */
  891. # define DPOUNIT_CLOCK_GATE_DISABLE             (1 << 11)
  892. # define DPBUNIT_CLOCK_GATE_DISABLE             (1 << 10)
  893. # define DCUNIT_CLOCK_GATE_DISABLE              (1 << 9)
  894. # define DPUNIT_CLOCK_GATE_DISABLE              (1 << 8)
  895. # define VRUNIT_CLOCK_GATE_DISABLE              (1 << 7) /* 915+: reserved */
  896. # define OVHUNIT_CLOCK_GATE_DISABLE             (1 << 6) /* 830-865 */
  897. # define DPIOUNIT_CLOCK_GATE_DISABLE            (1 << 6) /* 915-945 */
  898. # define OVFUNIT_CLOCK_GATE_DISABLE             (1 << 5)
  899. # define OVBUNIT_CLOCK_GATE_DISABLE             (1 << 4)
  900. /**
  901.  * This bit must be set on the 830 to prevent hangs when turning off the
  902.  * overlay scaler.
  903.  */
  904. # define OVRUNIT_CLOCK_GATE_DISABLE             (1 << 3)
  905. # define OVCUNIT_CLOCK_GATE_DISABLE             (1 << 2)
  906. # define OVUUNIT_CLOCK_GATE_DISABLE             (1 << 1)
  907. # define ZVUNIT_CLOCK_GATE_DISABLE              (1 << 0) /* 830 */
  908. # define OVLUNIT_CLOCK_GATE_DISABLE             (1 << 0) /* 845,865 */
  909.  
  910. #define RENCLK_GATE_D1          0x6204
  911. # define BLITTER_CLOCK_GATE_DISABLE             (1 << 13) /* 945GM only */
  912. # define MPEG_CLOCK_GATE_DISABLE                (1 << 12) /* 945GM only */
  913. # define PC_FE_CLOCK_GATE_DISABLE               (1 << 11)
  914. # define PC_BE_CLOCK_GATE_DISABLE               (1 << 10)
  915. # define WINDOWER_CLOCK_GATE_DISABLE            (1 << 9)
  916. # define INTERPOLATOR_CLOCK_GATE_DISABLE        (1 << 8)
  917. # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE    (1 << 7)
  918. # define MOTION_COMP_CLOCK_GATE_DISABLE         (1 << 6)
  919. # define MAG_CLOCK_GATE_DISABLE                 (1 << 5)
  920. /** This bit must be unset on 855,865 */
  921. # define MECI_CLOCK_GATE_DISABLE                (1 << 4)
  922. # define DCMP_CLOCK_GATE_DISABLE                (1 << 3)
  923. # define MEC_CLOCK_GATE_DISABLE                 (1 << 2)
  924. # define MECO_CLOCK_GATE_DISABLE                (1 << 1)
  925. /** This bit must be set on 855,865. */
  926. # define SV_CLOCK_GATE_DISABLE                  (1 << 0)
  927. # define I915_MPEG_CLOCK_GATE_DISABLE           (1 << 16)
  928. # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE      (1 << 15)
  929. # define I915_MOTION_COMP_CLOCK_GATE_DISABLE    (1 << 14)
  930. # define I915_BD_BF_CLOCK_GATE_DISABLE          (1 << 13)
  931. # define I915_SF_SE_CLOCK_GATE_DISABLE          (1 << 12)
  932. # define I915_WM_CLOCK_GATE_DISABLE             (1 << 11)
  933. # define I915_IZ_CLOCK_GATE_DISABLE             (1 << 10)
  934. # define I915_PI_CLOCK_GATE_DISABLE             (1 << 9)
  935. # define I915_DI_CLOCK_GATE_DISABLE             (1 << 8)
  936. # define I915_SH_SV_CLOCK_GATE_DISABLE          (1 << 7)
  937. # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE    (1 << 6)
  938. # define I915_SC_CLOCK_GATE_DISABLE             (1 << 5)
  939. # define I915_FL_CLOCK_GATE_DISABLE             (1 << 4)
  940. # define I915_DM_CLOCK_GATE_DISABLE             (1 << 3)
  941. # define I915_PS_CLOCK_GATE_DISABLE             (1 << 2)
  942. # define I915_CC_CLOCK_GATE_DISABLE             (1 << 1)
  943. # define I915_BY_CLOCK_GATE_DISABLE             (1 << 0)
  944.  
  945. # define I965_RCZ_CLOCK_GATE_DISABLE            (1 << 30)
  946. /** This bit must always be set on 965G/965GM */
  947. # define I965_RCC_CLOCK_GATE_DISABLE            (1 << 29)
  948. # define I965_RCPB_CLOCK_GATE_DISABLE           (1 << 28)
  949. # define I965_DAP_CLOCK_GATE_DISABLE            (1 << 27)
  950. # define I965_ROC_CLOCK_GATE_DISABLE            (1 << 26)
  951. # define I965_GW_CLOCK_GATE_DISABLE             (1 << 25)
  952. # define I965_TD_CLOCK_GATE_DISABLE             (1 << 24)
  953. /** This bit must always be set on 965G */
  954. # define I965_ISC_CLOCK_GATE_DISABLE            (1 << 23)
  955. # define I965_IC_CLOCK_GATE_DISABLE             (1 << 22)
  956. # define I965_EU_CLOCK_GATE_DISABLE             (1 << 21)
  957. # define I965_IF_CLOCK_GATE_DISABLE             (1 << 20)
  958. # define I965_TC_CLOCK_GATE_DISABLE             (1 << 19)
  959. # define I965_SO_CLOCK_GATE_DISABLE             (1 << 17)
  960. # define I965_FBC_CLOCK_GATE_DISABLE            (1 << 16)
  961. # define I965_MARI_CLOCK_GATE_DISABLE           (1 << 15)
  962. # define I965_MASF_CLOCK_GATE_DISABLE           (1 << 14)
  963. # define I965_MAWB_CLOCK_GATE_DISABLE           (1 << 13)
  964. # define I965_EM_CLOCK_GATE_DISABLE             (1 << 12)
  965. # define I965_UC_CLOCK_GATE_DISABLE             (1 << 11)
  966. # define I965_SI_CLOCK_GATE_DISABLE             (1 << 6)
  967. # define I965_MT_CLOCK_GATE_DISABLE             (1 << 5)
  968. # define I965_PL_CLOCK_GATE_DISABLE             (1 << 4)
  969. # define I965_DG_CLOCK_GATE_DISABLE             (1 << 3)
  970. # define I965_QC_CLOCK_GATE_DISABLE             (1 << 2)
  971. # define I965_FT_CLOCK_GATE_DISABLE             (1 << 1)
  972. # define I965_DM_CLOCK_GATE_DISABLE             (1 << 0)
  973.  
  974. #define RENCLK_GATE_D2          0x6208
  975. #define VF_UNIT_CLOCK_GATE_DISABLE              (1 << 9)
  976. #define GS_UNIT_CLOCK_GATE_DISABLE              (1 << 7)
  977. #define CL_UNIT_CLOCK_GATE_DISABLE              (1 << 6)
  978. #define RAMCLK_GATE_D           0x6210          /* CRL only */
  979. #define DEUC                    0x6214          /* CRL only */
  980.  
  981. /*
  982.  * Palette regs
  983.  */
  984.  
  985. #define _PALETTE_A              0x0a000
  986. #define _PALETTE_B              0x0a800
  987. #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
  988.  
  989. /* MCH MMIO space */
  990.  
  991. /*
  992.  * MCHBAR mirror.
  993.  *
  994.  * This mirrors the MCHBAR MMIO space whose location is determined by
  995.  * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
  996.  * every way.  It is not accessible from the CP register read instructions.
  997.  *
  998.  */
  999. #define MCHBAR_MIRROR_BASE      0x10000
  1000.  
  1001. #define MCHBAR_MIRROR_BASE_SNB  0x140000
  1002.  
  1003. /** 915-945 and GM965 MCH register controlling DRAM channel access */
  1004. #define DCC                     0x10200
  1005. #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL              (0 << 0)
  1006. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC     (1 << 0)
  1007. #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED    (2 << 0)
  1008. #define DCC_ADDRESSING_MODE_MASK                        (3 << 0)
  1009. #define DCC_CHANNEL_XOR_DISABLE                         (1 << 10)
  1010. #define DCC_CHANNEL_XOR_BIT_17                          (1 << 9)
  1011.  
  1012. /** Pineview MCH register contains DDR3 setting */
  1013. #define CSHRDDR3CTL            0x101a8
  1014. #define CSHRDDR3CTL_DDR3       (1 << 2)
  1015.  
  1016. /** 965 MCH register controlling DRAM channel configuration */
  1017. #define C0DRB3                  0x10206
  1018. #define C1DRB3                  0x10606
  1019.  
  1020. /* Clocking configuration register */
  1021. #define CLKCFG                  0x10c00
  1022. #define CLKCFG_FSB_400                                  (5 << 0)        /* hrawclk 100 */
  1023. #define CLKCFG_FSB_533                                  (1 << 0)        /* hrawclk 133 */
  1024. #define CLKCFG_FSB_667                                  (3 << 0)        /* hrawclk 166 */
  1025. #define CLKCFG_FSB_800                                  (2 << 0)        /* hrawclk 200 */
  1026. #define CLKCFG_FSB_1067                                 (6 << 0)        /* hrawclk 266 */
  1027. #define CLKCFG_FSB_1333                                 (7 << 0)        /* hrawclk 333 */
  1028. /* Note, below two are guess */
  1029. #define CLKCFG_FSB_1600                                 (4 << 0)        /* hrawclk 400 */
  1030. #define CLKCFG_FSB_1600_ALT                             (0 << 0)        /* hrawclk 400 */
  1031. #define CLKCFG_FSB_MASK                                 (7 << 0)
  1032. #define CLKCFG_MEM_533                                  (1 << 4)
  1033. #define CLKCFG_MEM_667                                  (2 << 4)
  1034. #define CLKCFG_MEM_800                                  (3 << 4)
  1035. #define CLKCFG_MEM_MASK                                 (7 << 4)
  1036.  
  1037. #define TSC1                    0x11001
  1038. #define   TSE                   (1<<0)
  1039. #define TR1                     0x11006
  1040. #define TSFS                    0x11020
  1041. #define   TSFS_SLOPE_MASK       0x0000ff00
  1042. #define   TSFS_SLOPE_SHIFT      8
  1043. #define   TSFS_INTR_MASK        0x000000ff
  1044.  
  1045. #define CRSTANDVID              0x11100
  1046. #define PXVFREQ_BASE            0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
  1047. #define   PXVFREQ_PX_MASK       0x7f000000
  1048. #define   PXVFREQ_PX_SHIFT      24
  1049. #define VIDFREQ_BASE            0x11110
  1050. #define VIDFREQ1                0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
  1051. #define VIDFREQ2                0x11114
  1052. #define VIDFREQ3                0x11118
  1053. #define VIDFREQ4                0x1111c
  1054. #define   VIDFREQ_P0_MASK       0x1f000000
  1055. #define   VIDFREQ_P0_SHIFT      24
  1056. #define   VIDFREQ_P0_CSCLK_MASK 0x00f00000
  1057. #define   VIDFREQ_P0_CSCLK_SHIFT 20
  1058. #define   VIDFREQ_P0_CRCLK_MASK 0x000f0000
  1059. #define   VIDFREQ_P0_CRCLK_SHIFT 16
  1060. #define   VIDFREQ_P1_MASK       0x00001f00
  1061. #define   VIDFREQ_P1_SHIFT      8
  1062. #define   VIDFREQ_P1_CSCLK_MASK 0x000000f0
  1063. #define   VIDFREQ_P1_CSCLK_SHIFT 4
  1064. #define   VIDFREQ_P1_CRCLK_MASK 0x0000000f
  1065. #define INTTOEXT_BASE_ILK       0x11300
  1066. #define INTTOEXT_BASE           0x11120 /* INTTOEXT1-8 (0x1113c) */
  1067. #define   INTTOEXT_MAP3_SHIFT   24
  1068. #define   INTTOEXT_MAP3_MASK    (0x1f << INTTOEXT_MAP3_SHIFT)
  1069. #define   INTTOEXT_MAP2_SHIFT   16
  1070. #define   INTTOEXT_MAP2_MASK    (0x1f << INTTOEXT_MAP2_SHIFT)
  1071. #define   INTTOEXT_MAP1_SHIFT   8
  1072. #define   INTTOEXT_MAP1_MASK    (0x1f << INTTOEXT_MAP1_SHIFT)
  1073. #define   INTTOEXT_MAP0_SHIFT   0
  1074. #define   INTTOEXT_MAP0_MASK    (0x1f << INTTOEXT_MAP0_SHIFT)
  1075. #define MEMSWCTL                0x11170 /* Ironlake only */
  1076. #define   MEMCTL_CMD_MASK       0xe000
  1077. #define   MEMCTL_CMD_SHIFT      13
  1078. #define   MEMCTL_CMD_RCLK_OFF   0
  1079. #define   MEMCTL_CMD_RCLK_ON    1
  1080. #define   MEMCTL_CMD_CHFREQ     2
  1081. #define   MEMCTL_CMD_CHVID      3
  1082. #define   MEMCTL_CMD_VMMOFF     4
  1083. #define   MEMCTL_CMD_VMMON      5
  1084. #define   MEMCTL_CMD_STS        (1<<12) /* write 1 triggers command, clears
  1085.                                            when command complete */
  1086. #define   MEMCTL_FREQ_MASK      0x0f00 /* jitter, from 0-15 */
  1087. #define   MEMCTL_FREQ_SHIFT     8
  1088. #define   MEMCTL_SFCAVM         (1<<7)
  1089. #define   MEMCTL_TGT_VID_MASK   0x007f
  1090. #define MEMIHYST                0x1117c
  1091. #define MEMINTREN               0x11180 /* 16 bits */
  1092. #define   MEMINT_RSEXIT_EN      (1<<8)
  1093. #define   MEMINT_CX_SUPR_EN     (1<<7)
  1094. #define   MEMINT_CONT_BUSY_EN   (1<<6)
  1095. #define   MEMINT_AVG_BUSY_EN    (1<<5)
  1096. #define   MEMINT_EVAL_CHG_EN    (1<<4)
  1097. #define   MEMINT_MON_IDLE_EN    (1<<3)
  1098. #define   MEMINT_UP_EVAL_EN     (1<<2)
  1099. #define   MEMINT_DOWN_EVAL_EN   (1<<1)
  1100. #define   MEMINT_SW_CMD_EN      (1<<0)
  1101. #define MEMINTRSTR              0x11182 /* 16 bits */
  1102. #define   MEM_RSEXIT_MASK       0xc000
  1103. #define   MEM_RSEXIT_SHIFT      14
  1104. #define   MEM_CONT_BUSY_MASK    0x3000
  1105. #define   MEM_CONT_BUSY_SHIFT   12
  1106. #define   MEM_AVG_BUSY_MASK     0x0c00
  1107. #define   MEM_AVG_BUSY_SHIFT    10
  1108. #define   MEM_EVAL_CHG_MASK     0x0300
  1109. #define   MEM_EVAL_BUSY_SHIFT   8
  1110. #define   MEM_MON_IDLE_MASK     0x00c0
  1111. #define   MEM_MON_IDLE_SHIFT    6
  1112. #define   MEM_UP_EVAL_MASK      0x0030
  1113. #define   MEM_UP_EVAL_SHIFT     4
  1114. #define   MEM_DOWN_EVAL_MASK    0x000c
  1115. #define   MEM_DOWN_EVAL_SHIFT   2
  1116. #define   MEM_SW_CMD_MASK       0x0003
  1117. #define   MEM_INT_STEER_GFX     0
  1118. #define   MEM_INT_STEER_CMR     1
  1119. #define   MEM_INT_STEER_SMI     2
  1120. #define   MEM_INT_STEER_SCI     3
  1121. #define MEMINTRSTS              0x11184
  1122. #define   MEMINT_RSEXIT         (1<<7)
  1123. #define   MEMINT_CONT_BUSY      (1<<6)
  1124. #define   MEMINT_AVG_BUSY       (1<<5)
  1125. #define   MEMINT_EVAL_CHG       (1<<4)
  1126. #define   MEMINT_MON_IDLE       (1<<3)
  1127. #define   MEMINT_UP_EVAL        (1<<2)
  1128. #define   MEMINT_DOWN_EVAL      (1<<1)
  1129. #define   MEMINT_SW_CMD         (1<<0)
  1130. #define MEMMODECTL              0x11190
  1131. #define   MEMMODE_BOOST_EN      (1<<31)
  1132. #define   MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
  1133. #define   MEMMODE_BOOST_FREQ_SHIFT 24
  1134. #define   MEMMODE_IDLE_MODE_MASK 0x00030000
  1135. #define   MEMMODE_IDLE_MODE_SHIFT 16
  1136. #define   MEMMODE_IDLE_MODE_EVAL 0
  1137. #define   MEMMODE_IDLE_MODE_CONT 1
  1138. #define   MEMMODE_HWIDLE_EN     (1<<15)
  1139. #define   MEMMODE_SWMODE_EN     (1<<14)
  1140. #define   MEMMODE_RCLK_GATE     (1<<13)
  1141. #define   MEMMODE_HW_UPDATE     (1<<12)
  1142. #define   MEMMODE_FSTART_MASK   0x00000f00 /* starting jitter, 0-15 */
  1143. #define   MEMMODE_FSTART_SHIFT  8
  1144. #define   MEMMODE_FMAX_MASK     0x000000f0 /* max jitter, 0-15 */
  1145. #define   MEMMODE_FMAX_SHIFT    4
  1146. #define   MEMMODE_FMIN_MASK     0x0000000f /* min jitter, 0-15 */
  1147. #define RCBMAXAVG               0x1119c
  1148. #define MEMSWCTL2               0x1119e /* Cantiga only */
  1149. #define   SWMEMCMD_RENDER_OFF   (0 << 13)
  1150. #define   SWMEMCMD_RENDER_ON    (1 << 13)
  1151. #define   SWMEMCMD_SWFREQ       (2 << 13)
  1152. #define   SWMEMCMD_TARVID       (3 << 13)
  1153. #define   SWMEMCMD_VRM_OFF      (4 << 13)
  1154. #define   SWMEMCMD_VRM_ON       (5 << 13)
  1155. #define   CMDSTS                (1<<12)
  1156. #define   SFCAVM                (1<<11)
  1157. #define   SWFREQ_MASK           0x0380 /* P0-7 */
  1158. #define   SWFREQ_SHIFT          7
  1159. #define   TARVID_MASK           0x001f
  1160. #define MEMSTAT_CTG             0x111a0
  1161. #define RCBMINAVG               0x111a0
  1162. #define RCUPEI                  0x111b0
  1163. #define RCDNEI                  0x111b4
  1164. #define RSTDBYCTL               0x111b8
  1165. #define   RS1EN                 (1<<31)
  1166. #define   RS2EN                 (1<<30)
  1167. #define   RS3EN                 (1<<29)
  1168. #define   D3RS3EN               (1<<28) /* Display D3 imlies RS3 */
  1169. #define   SWPROMORSX            (1<<27) /* RSx promotion timers ignored */
  1170. #define   RCWAKERW              (1<<26) /* Resetwarn from PCH causes wakeup */
  1171. #define   DPRSLPVREN            (1<<25) /* Fast voltage ramp enable */
  1172. #define   GFXTGHYST             (1<<24) /* Hysteresis to allow trunk gating */
  1173. #define   RCX_SW_EXIT           (1<<23) /* Leave RSx and prevent re-entry */
  1174. #define   RSX_STATUS_MASK       (7<<20)
  1175. #define   RSX_STATUS_ON         (0<<20)
  1176. #define   RSX_STATUS_RC1        (1<<20)
  1177. #define   RSX_STATUS_RC1E       (2<<20)
  1178. #define   RSX_STATUS_RS1        (3<<20)
  1179. #define   RSX_STATUS_RS2        (4<<20) /* aka rc6 */
  1180. #define   RSX_STATUS_RSVD       (5<<20) /* deep rc6 unsupported on ilk */
  1181. #define   RSX_STATUS_RS3        (6<<20) /* rs3 unsupported on ilk */
  1182. #define   RSX_STATUS_RSVD2      (7<<20)
  1183. #define   UWRCRSXE              (1<<19) /* wake counter limit prevents rsx */
  1184. #define   RSCRP                 (1<<18) /* rs requests control on rs1/2 reqs */
  1185. #define   JRSC                  (1<<17) /* rsx coupled to cpu c-state */
  1186. #define   RS2INC0               (1<<16) /* allow rs2 in cpu c0 */
  1187. #define   RS1CONTSAV_MASK       (3<<14)
  1188. #define   RS1CONTSAV_NO_RS1     (0<<14) /* rs1 doesn't save/restore context */
  1189. #define   RS1CONTSAV_RSVD       (1<<14)
  1190. #define   RS1CONTSAV_SAVE_RS1   (2<<14) /* rs1 saves context */
  1191. #define   RS1CONTSAV_FULL_RS1   (3<<14) /* rs1 saves and restores context */
  1192. #define   NORMSLEXLAT_MASK      (3<<12)
  1193. #define   SLOW_RS123            (0<<12)
  1194. #define   SLOW_RS23             (1<<12)
  1195. #define   SLOW_RS3              (2<<12)
  1196. #define   NORMAL_RS123          (3<<12)
  1197. #define   RCMODE_TIMEOUT        (1<<11) /* 0 is eval interval method */
  1198. #define   IMPROMOEN             (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
  1199. #define   RCENTSYNC             (1<<9) /* rs coupled to cpu c-state (3/6/7) */
  1200. #define   STATELOCK             (1<<7) /* locked to rs_cstate if 0 */
  1201. #define   RS_CSTATE_MASK        (3<<4)
  1202. #define   RS_CSTATE_C367_RS1    (0<<4)
  1203. #define   RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
  1204. #define   RS_CSTATE_RSVD        (2<<4)
  1205. #define   RS_CSTATE_C367_RS2    (3<<4)
  1206. #define   REDSAVES              (1<<3) /* no context save if was idle during rs0 */
  1207. #define   REDRESTORES           (1<<2) /* no restore if was idle during rs0 */
  1208. #define VIDCTL                  0x111c0
  1209. #define VIDSTS                  0x111c8
  1210. #define VIDSTART                0x111cc /* 8 bits */
  1211. #define MEMSTAT_ILK                     0x111f8
  1212. #define   MEMSTAT_VID_MASK      0x7f00
  1213. #define   MEMSTAT_VID_SHIFT     8
  1214. #define   MEMSTAT_PSTATE_MASK   0x00f8
  1215. #define   MEMSTAT_PSTATE_SHIFT  3
  1216. #define   MEMSTAT_MON_ACTV      (1<<2)
  1217. #define   MEMSTAT_SRC_CTL_MASK  0x0003
  1218. #define   MEMSTAT_SRC_CTL_CORE  0
  1219. #define   MEMSTAT_SRC_CTL_TRB   1
  1220. #define   MEMSTAT_SRC_CTL_THM   2
  1221. #define   MEMSTAT_SRC_CTL_STDBY 3
  1222. #define RCPREVBSYTUPAVG         0x113b8
  1223. #define RCPREVBSYTDNAVG         0x113bc
  1224. #define PMMISC                  0x11214
  1225. #define   MCPPCE_EN             (1<<0) /* enable PM_MSG from PCH->MPC */
  1226. #define SDEW                    0x1124c
  1227. #define CSIEW0                  0x11250
  1228. #define CSIEW1                  0x11254
  1229. #define CSIEW2                  0x11258
  1230. #define PEW                     0x1125c
  1231. #define DEW                     0x11270
  1232. #define MCHAFE                  0x112c0
  1233. #define CSIEC                   0x112e0
  1234. #define DMIEC                   0x112e4
  1235. #define DDREC                   0x112e8
  1236. #define PEG0EC                  0x112ec
  1237. #define PEG1EC                  0x112f0
  1238. #define GFXEC                   0x112f4
  1239. #define RPPREVBSYTUPAVG         0x113b8
  1240. #define RPPREVBSYTDNAVG         0x113bc
  1241. #define ECR                     0x11600
  1242. #define   ECR_GPFE              (1<<31)
  1243. #define   ECR_IMONE             (1<<30)
  1244. #define   ECR_CAP_MASK          0x0000001f /* Event range, 0-31 */
  1245. #define OGW0                    0x11608
  1246. #define OGW1                    0x1160c
  1247. #define EG0                     0x11610
  1248. #define EG1                     0x11614
  1249. #define EG2                     0x11618
  1250. #define EG3                     0x1161c
  1251. #define EG4                     0x11620
  1252. #define EG5                     0x11624
  1253. #define EG6                     0x11628
  1254. #define EG7                     0x1162c
  1255. #define PXW                     0x11664
  1256. #define PXWL                    0x11680
  1257. #define LCFUSE02                0x116c0
  1258. #define   LCFUSE_HIV_MASK       0x000000ff
  1259. #define CSIPLL0                 0x12c10
  1260. #define DDRMPLL1                0X12c20
  1261. #define PEG_BAND_GAP_DATA       0x14d68
  1262.  
  1263. #define GEN6_GT_PERF_STATUS     0x145948
  1264. #define GEN6_RP_STATE_LIMITS    0x145994
  1265. #define GEN6_RP_STATE_CAP       0x145998
  1266.  
  1267. /*
  1268.  * Logical Context regs
  1269.  */
  1270. #define CCID                    0x2180
  1271. #define   CCID_EN               (1<<0)
  1272. /*
  1273.  * Overlay regs
  1274.  */
  1275.  
  1276. #define OVADD                   0x30000
  1277. #define DOVSTA                  0x30008
  1278. #define OC_BUF                  (0x3<<20)
  1279. #define OGAMC5                  0x30010
  1280. #define OGAMC4                  0x30014
  1281. #define OGAMC3                  0x30018
  1282. #define OGAMC2                  0x3001c
  1283. #define OGAMC1                  0x30020
  1284. #define OGAMC0                  0x30024
  1285.  
  1286. /*
  1287.  * Display engine regs
  1288.  */
  1289.  
  1290. /* Pipe A timing regs */
  1291. #define _HTOTAL_A       0x60000
  1292. #define _HBLANK_A       0x60004
  1293. #define _HSYNC_A                0x60008
  1294. #define _VTOTAL_A       0x6000c
  1295. #define _VBLANK_A       0x60010
  1296. #define _VSYNC_A                0x60014
  1297. #define _PIPEASRC       0x6001c
  1298. #define _BCLRPAT_A      0x60020
  1299.  
  1300. /* Pipe B timing regs */
  1301. #define _HTOTAL_B       0x61000
  1302. #define _HBLANK_B       0x61004
  1303. #define _HSYNC_B                0x61008
  1304. #define _VTOTAL_B       0x6100c
  1305. #define _VBLANK_B       0x61010
  1306. #define _VSYNC_B                0x61014
  1307. #define _PIPEBSRC       0x6101c
  1308. #define _BCLRPAT_B      0x61020
  1309.  
  1310. #define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
  1311. #define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
  1312. #define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
  1313. #define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
  1314. #define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
  1315. #define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
  1316. #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
  1317.  
  1318. /* VGA port control */
  1319. #define ADPA                    0x61100
  1320. #define   ADPA_DAC_ENABLE       (1<<31)
  1321. #define   ADPA_DAC_DISABLE      0
  1322. #define   ADPA_PIPE_SELECT_MASK (1<<30)
  1323. #define   ADPA_PIPE_A_SELECT    0
  1324. #define   ADPA_PIPE_B_SELECT    (1<<30)
  1325. #define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
  1326. #define   ADPA_USE_VGA_HVPOLARITY (1<<15)
  1327. #define   ADPA_SETS_HVPOLARITY  0
  1328. #define   ADPA_VSYNC_CNTL_DISABLE (1<<11)
  1329. #define   ADPA_VSYNC_CNTL_ENABLE 0
  1330. #define   ADPA_HSYNC_CNTL_DISABLE (1<<10)
  1331. #define   ADPA_HSYNC_CNTL_ENABLE 0
  1332. #define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
  1333. #define   ADPA_VSYNC_ACTIVE_LOW 0
  1334. #define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
  1335. #define   ADPA_HSYNC_ACTIVE_LOW 0
  1336. #define   ADPA_DPMS_MASK        (~(3<<10))
  1337. #define   ADPA_DPMS_ON          (0<<10)
  1338. #define   ADPA_DPMS_SUSPEND     (1<<10)
  1339. #define   ADPA_DPMS_STANDBY     (2<<10)
  1340. #define   ADPA_DPMS_OFF         (3<<10)
  1341.  
  1342.  
  1343. /* Hotplug control (945+ only) */
  1344. #define PORT_HOTPLUG_EN         0x61110
  1345. #define   HDMIB_HOTPLUG_INT_EN                  (1 << 29)
  1346. #define   DPB_HOTPLUG_INT_EN                    (1 << 29)
  1347. #define   HDMIC_HOTPLUG_INT_EN                  (1 << 28)
  1348. #define   DPC_HOTPLUG_INT_EN                    (1 << 28)
  1349. #define   HDMID_HOTPLUG_INT_EN                  (1 << 27)
  1350. #define   DPD_HOTPLUG_INT_EN                    (1 << 27)
  1351. #define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
  1352. #define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
  1353. #define   TV_HOTPLUG_INT_EN                     (1 << 18)
  1354. #define   CRT_HOTPLUG_INT_EN                    (1 << 9)
  1355. #define   CRT_HOTPLUG_FORCE_DETECT              (1 << 3)
  1356. #define CRT_HOTPLUG_ACTIVATION_PERIOD_32        (0 << 8)
  1357. /* must use period 64 on GM45 according to docs */
  1358. #define CRT_HOTPLUG_ACTIVATION_PERIOD_64        (1 << 8)
  1359. #define CRT_HOTPLUG_DAC_ON_TIME_2M              (0 << 7)
  1360. #define CRT_HOTPLUG_DAC_ON_TIME_4M              (1 << 7)
  1361. #define CRT_HOTPLUG_VOLTAGE_COMPARE_40          (0 << 5)
  1362. #define CRT_HOTPLUG_VOLTAGE_COMPARE_50          (1 << 5)
  1363. #define CRT_HOTPLUG_VOLTAGE_COMPARE_60          (2 << 5)
  1364. #define CRT_HOTPLUG_VOLTAGE_COMPARE_70          (3 << 5)
  1365. #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK        (3 << 5)
  1366. #define CRT_HOTPLUG_DETECT_DELAY_1G             (0 << 4)
  1367. #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
  1368. #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
  1369. #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
  1370.  
  1371. #define PORT_HOTPLUG_STAT       0x61114
  1372. #define   HDMIB_HOTPLUG_INT_STATUS              (1 << 29)
  1373. #define   DPB_HOTPLUG_INT_STATUS                (1 << 29)
  1374. #define   HDMIC_HOTPLUG_INT_STATUS              (1 << 28)
  1375. #define   DPC_HOTPLUG_INT_STATUS                (1 << 28)
  1376. #define   HDMID_HOTPLUG_INT_STATUS              (1 << 27)
  1377. #define   DPD_HOTPLUG_INT_STATUS                (1 << 27)
  1378. #define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
  1379. #define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
  1380. #define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
  1381. #define   CRT_HOTPLUG_MONITOR_COLOR             (3 << 8)
  1382. #define   CRT_HOTPLUG_MONITOR_MONO              (2 << 8)
  1383. #define   CRT_HOTPLUG_MONITOR_NONE              (0 << 8)
  1384. #define   SDVOC_HOTPLUG_INT_STATUS              (1 << 7)
  1385. #define   SDVOB_HOTPLUG_INT_STATUS              (1 << 6)
  1386.  
  1387. /* SDVO port control */
  1388. #define SDVOB                   0x61140
  1389. #define SDVOC                   0x61160
  1390. #define   SDVO_ENABLE           (1 << 31)
  1391. #define   SDVO_PIPE_B_SELECT    (1 << 30)
  1392. #define   SDVO_STALL_SELECT     (1 << 29)
  1393. #define   SDVO_INTERRUPT_ENABLE (1 << 26)
  1394. /**
  1395.  * 915G/GM SDVO pixel multiplier.
  1396.  *
  1397.  * Programmed value is multiplier - 1, up to 5x.
  1398.  *
  1399.  * \sa DPLL_MD_UDI_MULTIPLIER_MASK
  1400.  */
  1401. #define   SDVO_PORT_MULTIPLY_MASK       (7 << 23)
  1402. #define   SDVO_PORT_MULTIPLY_SHIFT              23
  1403. #define   SDVO_PHASE_SELECT_MASK        (15 << 19)
  1404. #define   SDVO_PHASE_SELECT_DEFAULT     (6 << 19)
  1405. #define   SDVO_CLOCK_OUTPUT_INVERT      (1 << 18)
  1406. #define   SDVOC_GANG_MODE               (1 << 16)
  1407. #define   SDVO_ENCODING_SDVO            (0x0 << 10)
  1408. #define   SDVO_ENCODING_HDMI            (0x2 << 10)
  1409. /** Requird for HDMI operation */
  1410. #define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
  1411. #define   SDVO_COLOR_RANGE_16_235       (1 << 8)
  1412. #define   SDVO_BORDER_ENABLE            (1 << 7)
  1413. #define   SDVO_AUDIO_ENABLE             (1 << 6)
  1414. /** New with 965, default is to be set */
  1415. #define   SDVO_VSYNC_ACTIVE_HIGH        (1 << 4)
  1416. /** New with 965, default is to be set */
  1417. #define   SDVO_HSYNC_ACTIVE_HIGH        (1 << 3)
  1418. #define   SDVOB_PCIE_CONCURRENCY        (1 << 3)
  1419. #define   SDVO_DETECTED                 (1 << 2)
  1420. /* Bits to be preserved when writing */
  1421. #define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
  1422. #define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
  1423.  
  1424. /* DVO port control */
  1425. #define DVOA                    0x61120
  1426. #define DVOB                    0x61140
  1427. #define DVOC                    0x61160
  1428. #define   DVO_ENABLE                    (1 << 31)
  1429. #define   DVO_PIPE_B_SELECT             (1 << 30)
  1430. #define   DVO_PIPE_STALL_UNUSED         (0 << 28)
  1431. #define   DVO_PIPE_STALL                (1 << 28)
  1432. #define   DVO_PIPE_STALL_TV             (2 << 28)
  1433. #define   DVO_PIPE_STALL_MASK           (3 << 28)
  1434. #define   DVO_USE_VGA_SYNC              (1 << 15)
  1435. #define   DVO_DATA_ORDER_I740           (0 << 14)
  1436. #define   DVO_DATA_ORDER_FP             (1 << 14)
  1437. #define   DVO_VSYNC_DISABLE             (1 << 11)
  1438. #define   DVO_HSYNC_DISABLE             (1 << 10)
  1439. #define   DVO_VSYNC_TRISTATE            (1 << 9)
  1440. #define   DVO_HSYNC_TRISTATE            (1 << 8)
  1441. #define   DVO_BORDER_ENABLE             (1 << 7)
  1442. #define   DVO_DATA_ORDER_GBRG           (1 << 6)
  1443. #define   DVO_DATA_ORDER_RGGB           (0 << 6)
  1444. #define   DVO_DATA_ORDER_GBRG_ERRATA    (0 << 6)
  1445. #define   DVO_DATA_ORDER_RGGB_ERRATA    (1 << 6)
  1446. #define   DVO_VSYNC_ACTIVE_HIGH         (1 << 4)
  1447. #define   DVO_HSYNC_ACTIVE_HIGH         (1 << 3)
  1448. #define   DVO_BLANK_ACTIVE_HIGH         (1 << 2)
  1449. #define   DVO_OUTPUT_CSTATE_PIXELS      (1 << 1)        /* SDG only */
  1450. #define   DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0)        /* SDG only */
  1451. #define   DVO_PRESERVE_MASK             (0x7<<24)
  1452. #define DVOA_SRCDIM             0x61124
  1453. #define DVOB_SRCDIM             0x61144
  1454. #define DVOC_SRCDIM             0x61164
  1455. #define   DVO_SRCDIM_HORIZONTAL_SHIFT   12
  1456. #define   DVO_SRCDIM_VERTICAL_SHIFT     0
  1457.  
  1458. /* LVDS port control */
  1459. #define LVDS                    0x61180
  1460. /*
  1461.  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
  1462.  * the DPLL semantics change when the LVDS is assigned to that pipe.
  1463.  */
  1464. #define   LVDS_PORT_EN                  (1 << 31)
  1465. /* Selects pipe B for LVDS data.  Must be set on pre-965. */
  1466. #define   LVDS_PIPEB_SELECT             (1 << 30)
  1467. #define   LVDS_PIPE_MASK                (1 << 30)
  1468. #define   LVDS_PIPE(pipe)               ((pipe) << 30)
  1469. /* LVDS dithering flag on 965/g4x platform */
  1470. #define   LVDS_ENABLE_DITHER            (1 << 25)
  1471. /* LVDS sync polarity flags. Set to invert (i.e. negative) */
  1472. #define   LVDS_VSYNC_POLARITY           (1 << 21)
  1473. #define   LVDS_HSYNC_POLARITY           (1 << 20)
  1474.  
  1475. /* Enable border for unscaled (or aspect-scaled) display */
  1476. #define   LVDS_BORDER_ENABLE            (1 << 15)
  1477. /*
  1478.  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
  1479.  * pixel.
  1480.  */
  1481. #define   LVDS_A0A2_CLKA_POWER_MASK     (3 << 8)
  1482. #define   LVDS_A0A2_CLKA_POWER_DOWN     (0 << 8)
  1483. #define   LVDS_A0A2_CLKA_POWER_UP       (3 << 8)
  1484. /*
  1485.  * Controls the A3 data pair, which contains the additional LSBs for 24 bit
  1486.  * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
  1487.  * on.
  1488.  */
  1489. #define   LVDS_A3_POWER_MASK            (3 << 6)
  1490. #define   LVDS_A3_POWER_DOWN            (0 << 6)
  1491. #define   LVDS_A3_POWER_UP              (3 << 6)
  1492. /*
  1493.  * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
  1494.  * is set.
  1495.  */
  1496. #define   LVDS_CLKB_POWER_MASK          (3 << 4)
  1497. #define   LVDS_CLKB_POWER_DOWN          (0 << 4)
  1498. #define   LVDS_CLKB_POWER_UP            (3 << 4)
  1499. /*
  1500.  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
  1501.  * setting for whether we are in dual-channel mode.  The B3 pair will
  1502.  * additionally only be powered up when LVDS_A3_POWER_UP is set.
  1503.  */
  1504. #define   LVDS_B0B3_POWER_MASK          (3 << 2)
  1505. #define   LVDS_B0B3_POWER_DOWN          (0 << 2)
  1506. #define   LVDS_B0B3_POWER_UP            (3 << 2)
  1507.  
  1508. /* Video Data Island Packet control */
  1509. #define VIDEO_DIP_DATA          0x61178
  1510. #define VIDEO_DIP_CTL           0x61170
  1511. #define   VIDEO_DIP_ENABLE              (1 << 31)
  1512. #define   VIDEO_DIP_PORT_B              (1 << 29)
  1513. #define   VIDEO_DIP_PORT_C              (2 << 29)
  1514. #define   VIDEO_DIP_ENABLE_AVI          (1 << 21)
  1515. #define   VIDEO_DIP_ENABLE_VENDOR       (2 << 21)
  1516. #define   VIDEO_DIP_ENABLE_SPD          (8 << 21)
  1517. #define   VIDEO_DIP_SELECT_AVI          (0 << 19)
  1518. #define   VIDEO_DIP_SELECT_VENDOR       (1 << 19)
  1519. #define   VIDEO_DIP_SELECT_SPD          (3 << 19)
  1520. #define   VIDEO_DIP_SELECT_MASK         (3 << 19)
  1521. #define   VIDEO_DIP_FREQ_ONCE           (0 << 16)
  1522. #define   VIDEO_DIP_FREQ_VSYNC          (1 << 16)
  1523. #define   VIDEO_DIP_FREQ_2VSYNC         (2 << 16)
  1524.  
  1525. /* Panel power sequencing */
  1526. #define PP_STATUS       0x61200
  1527. #define   PP_ON         (1 << 31)
  1528. /*
  1529.  * Indicates that all dependencies of the panel are on:
  1530.  *
  1531.  * - PLL enabled
  1532.  * - pipe enabled
  1533.  * - LVDS/DVOB/DVOC on
  1534.  */
  1535. #define   PP_READY              (1 << 30)
  1536. #define   PP_SEQUENCE_NONE      (0 << 28)
  1537. #define   PP_SEQUENCE_ON        (1 << 28)
  1538. #define   PP_SEQUENCE_OFF       (2 << 28)
  1539. #define   PP_SEQUENCE_MASK      0x30000000
  1540. #define   PP_CYCLE_DELAY_ACTIVE (1 << 27)
  1541. #define   PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
  1542. #define   PP_SEQUENCE_STATE_MASK 0x0000000f
  1543. #define PP_CONTROL      0x61204
  1544. #define   POWER_TARGET_ON       (1 << 0)
  1545. #define PP_ON_DELAYS    0x61208
  1546. #define PP_OFF_DELAYS   0x6120c
  1547. #define PP_DIVISOR      0x61210
  1548.  
  1549. /* Panel fitting */
  1550. #define PFIT_CONTROL    0x61230
  1551. #define   PFIT_ENABLE           (1 << 31)
  1552. #define   PFIT_PIPE_MASK        (3 << 29)
  1553. #define   PFIT_PIPE_SHIFT       29
  1554. #define   VERT_INTERP_DISABLE   (0 << 10)
  1555. #define   VERT_INTERP_BILINEAR  (1 << 10)
  1556. #define   VERT_INTERP_MASK      (3 << 10)
  1557. #define   VERT_AUTO_SCALE       (1 << 9)
  1558. #define   HORIZ_INTERP_DISABLE  (0 << 6)
  1559. #define   HORIZ_INTERP_BILINEAR (1 << 6)
  1560. #define   HORIZ_INTERP_MASK     (3 << 6)
  1561. #define   HORIZ_AUTO_SCALE      (1 << 5)
  1562. #define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
  1563. #define   PFIT_FILTER_FUZZY     (0 << 24)
  1564. #define   PFIT_SCALING_AUTO     (0 << 26)
  1565. #define   PFIT_SCALING_PROGRAMMED (1 << 26)
  1566. #define   PFIT_SCALING_PILLAR   (2 << 26)
  1567. #define   PFIT_SCALING_LETTER   (3 << 26)
  1568. #define PFIT_PGM_RATIOS 0x61234
  1569. #define   PFIT_VERT_SCALE_MASK                  0xfff00000
  1570. #define   PFIT_HORIZ_SCALE_MASK                 0x0000fff0
  1571. /* Pre-965 */
  1572. #define         PFIT_VERT_SCALE_SHIFT           20
  1573. #define         PFIT_VERT_SCALE_MASK            0xfff00000
  1574. #define         PFIT_HORIZ_SCALE_SHIFT          4
  1575. #define         PFIT_HORIZ_SCALE_MASK           0x0000fff0
  1576. /* 965+ */
  1577. #define         PFIT_VERT_SCALE_SHIFT_965       16
  1578. #define         PFIT_VERT_SCALE_MASK_965        0x1fff0000
  1579. #define         PFIT_HORIZ_SCALE_SHIFT_965      0
  1580. #define         PFIT_HORIZ_SCALE_MASK_965       0x00001fff
  1581.  
  1582. #define PFIT_AUTO_RATIOS 0x61238
  1583.  
  1584. /* Backlight control */
  1585. #define BLC_PWM_CTL             0x61254
  1586. #define   BACKLIGHT_MODULATION_FREQ_SHIFT               (17)
  1587. #define BLC_PWM_CTL2            0x61250 /* 965+ only */
  1588. #define   BLM_COMBINATION_MODE (1 << 30)
  1589. /*
  1590.  * This is the most significant 15 bits of the number of backlight cycles in a
  1591.  * complete cycle of the modulated backlight control.
  1592.  *
  1593.  * The actual value is this field multiplied by two.
  1594.  */
  1595. #define   BACKLIGHT_MODULATION_FREQ_MASK                (0x7fff << 17)
  1596. #define   BLM_LEGACY_MODE                               (1 << 16)
  1597. /*
  1598.  * This is the number of cycles out of the backlight modulation cycle for which
  1599.  * the backlight is on.
  1600.  *
  1601.  * This field must be no greater than the number of cycles in the complete
  1602.  * backlight modulation cycle.
  1603.  */
  1604. #define   BACKLIGHT_DUTY_CYCLE_SHIFT            (0)
  1605. #define   BACKLIGHT_DUTY_CYCLE_MASK             (0xffff)
  1606.  
  1607. #define BLC_HIST_CTL            0x61260
  1608.  
  1609. /* TV port control */
  1610. #define TV_CTL                  0x68000
  1611. /** Enables the TV encoder */
  1612. # define TV_ENC_ENABLE                  (1 << 31)
  1613. /** Sources the TV encoder input from pipe B instead of A. */
  1614. # define TV_ENC_PIPEB_SELECT            (1 << 30)
  1615. /** Outputs composite video (DAC A only) */
  1616. # define TV_ENC_OUTPUT_COMPOSITE        (0 << 28)
  1617. /** Outputs SVideo video (DAC B/C) */
  1618. # define TV_ENC_OUTPUT_SVIDEO           (1 << 28)
  1619. /** Outputs Component video (DAC A/B/C) */
  1620. # define TV_ENC_OUTPUT_COMPONENT        (2 << 28)
  1621. /** Outputs Composite and SVideo (DAC A/B/C) */
  1622. # define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
  1623. # define TV_TRILEVEL_SYNC               (1 << 21)
  1624. /** Enables slow sync generation (945GM only) */
  1625. # define TV_SLOW_SYNC                   (1 << 20)
  1626. /** Selects 4x oversampling for 480i and 576p */
  1627. # define TV_OVERSAMPLE_4X               (0 << 18)
  1628. /** Selects 2x oversampling for 720p and 1080i */
  1629. # define TV_OVERSAMPLE_2X               (1 << 18)
  1630. /** Selects no oversampling for 1080p */
  1631. # define TV_OVERSAMPLE_NONE             (2 << 18)
  1632. /** Selects 8x oversampling */
  1633. # define TV_OVERSAMPLE_8X               (3 << 18)
  1634. /** Selects progressive mode rather than interlaced */
  1635. # define TV_PROGRESSIVE                 (1 << 17)
  1636. /** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
  1637. # define TV_PAL_BURST                   (1 << 16)
  1638. /** Field for setting delay of Y compared to C */
  1639. # define TV_YC_SKEW_MASK                (7 << 12)
  1640. /** Enables a fix for 480p/576p standard definition modes on the 915GM only */
  1641. # define TV_ENC_SDP_FIX                 (1 << 11)
  1642. /**
  1643.  * Enables a fix for the 915GM only.
  1644.  *
  1645.  * Not sure what it does.
  1646.  */
  1647. # define TV_ENC_C0_FIX                  (1 << 10)
  1648. /** Bits that must be preserved by software */
  1649. # define TV_CTL_SAVE                    ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
  1650. # define TV_FUSE_STATE_MASK             (3 << 4)
  1651. /** Read-only state that reports all features enabled */
  1652. # define TV_FUSE_STATE_ENABLED          (0 << 4)
  1653. /** Read-only state that reports that Macrovision is disabled in hardware*/
  1654. # define TV_FUSE_STATE_NO_MACROVISION   (1 << 4)
  1655. /** Read-only state that reports that TV-out is disabled in hardware. */
  1656. # define TV_FUSE_STATE_DISABLED         (2 << 4)
  1657. /** Normal operation */
  1658. # define TV_TEST_MODE_NORMAL            (0 << 0)
  1659. /** Encoder test pattern 1 - combo pattern */
  1660. # define TV_TEST_MODE_PATTERN_1         (1 << 0)
  1661. /** Encoder test pattern 2 - full screen vertical 75% color bars */
  1662. # define TV_TEST_MODE_PATTERN_2         (2 << 0)
  1663. /** Encoder test pattern 3 - full screen horizontal 75% color bars */
  1664. # define TV_TEST_MODE_PATTERN_3         (3 << 0)
  1665. /** Encoder test pattern 4 - random noise */
  1666. # define TV_TEST_MODE_PATTERN_4         (4 << 0)
  1667. /** Encoder test pattern 5 - linear color ramps */
  1668. # define TV_TEST_MODE_PATTERN_5         (5 << 0)
  1669. /**
  1670.  * This test mode forces the DACs to 50% of full output.
  1671.  *
  1672.  * This is used for load detection in combination with TVDAC_SENSE_MASK
  1673.  */
  1674. # define TV_TEST_MODE_MONITOR_DETECT    (7 << 0)
  1675. # define TV_TEST_MODE_MASK              (7 << 0)
  1676.  
  1677. #define TV_DAC                  0x68004
  1678. # define TV_DAC_SAVE            0x00ffff00
  1679. /**
  1680.  * Reports that DAC state change logic has reported change (RO).
  1681.  *
  1682.  * This gets cleared when TV_DAC_STATE_EN is cleared
  1683. */
  1684. # define TVDAC_STATE_CHG                (1 << 31)
  1685. # define TVDAC_SENSE_MASK               (7 << 28)
  1686. /** Reports that DAC A voltage is above the detect threshold */
  1687. # define TVDAC_A_SENSE                  (1 << 30)
  1688. /** Reports that DAC B voltage is above the detect threshold */
  1689. # define TVDAC_B_SENSE                  (1 << 29)
  1690. /** Reports that DAC C voltage is above the detect threshold */
  1691. # define TVDAC_C_SENSE                  (1 << 28)
  1692. /**
  1693.  * Enables DAC state detection logic, for load-based TV detection.
  1694.  *
  1695.  * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
  1696.  * to off, for load detection to work.
  1697.  */
  1698. # define TVDAC_STATE_CHG_EN             (1 << 27)
  1699. /** Sets the DAC A sense value to high */
  1700. # define TVDAC_A_SENSE_CTL              (1 << 26)
  1701. /** Sets the DAC B sense value to high */
  1702. # define TVDAC_B_SENSE_CTL              (1 << 25)
  1703. /** Sets the DAC C sense value to high */
  1704. # define TVDAC_C_SENSE_CTL              (1 << 24)
  1705. /** Overrides the ENC_ENABLE and DAC voltage levels */
  1706. # define DAC_CTL_OVERRIDE               (1 << 7)
  1707. /** Sets the slew rate.  Must be preserved in software */
  1708. # define ENC_TVDAC_SLEW_FAST            (1 << 6)
  1709. # define DAC_A_1_3_V                    (0 << 4)
  1710. # define DAC_A_1_1_V                    (1 << 4)
  1711. # define DAC_A_0_7_V                    (2 << 4)
  1712. # define DAC_A_MASK                     (3 << 4)
  1713. # define DAC_B_1_3_V                    (0 << 2)
  1714. # define DAC_B_1_1_V                    (1 << 2)
  1715. # define DAC_B_0_7_V                    (2 << 2)
  1716. # define DAC_B_MASK                     (3 << 2)
  1717. # define DAC_C_1_3_V                    (0 << 0)
  1718. # define DAC_C_1_1_V                    (1 << 0)
  1719. # define DAC_C_0_7_V                    (2 << 0)
  1720. # define DAC_C_MASK                     (3 << 0)
  1721.  
  1722. /**
  1723.  * CSC coefficients are stored in a floating point format with 9 bits of
  1724.  * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
  1725.  * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
  1726.  * -1 (0x3) being the only legal negative value.
  1727.  */
  1728. #define TV_CSC_Y                0x68010
  1729. # define TV_RY_MASK                     0x07ff0000
  1730. # define TV_RY_SHIFT                    16
  1731. # define TV_GY_MASK                     0x00000fff
  1732. # define TV_GY_SHIFT                    0
  1733.  
  1734. #define TV_CSC_Y2               0x68014
  1735. # define TV_BY_MASK                     0x07ff0000
  1736. # define TV_BY_SHIFT                    16
  1737. /**
  1738.  * Y attenuation for component video.
  1739.  *
  1740.  * Stored in 1.9 fixed point.
  1741.  */
  1742. # define TV_AY_MASK                     0x000003ff
  1743. # define TV_AY_SHIFT                    0
  1744.  
  1745. #define TV_CSC_U                0x68018
  1746. # define TV_RU_MASK                     0x07ff0000
  1747. # define TV_RU_SHIFT                    16
  1748. # define TV_GU_MASK                     0x000007ff
  1749. # define TV_GU_SHIFT                    0
  1750.  
  1751. #define TV_CSC_U2               0x6801c
  1752. # define TV_BU_MASK                     0x07ff0000
  1753. # define TV_BU_SHIFT                    16
  1754. /**
  1755.  * U attenuation for component video.
  1756.  *
  1757.  * Stored in 1.9 fixed point.
  1758.  */
  1759. # define TV_AU_MASK                     0x000003ff
  1760. # define TV_AU_SHIFT                    0
  1761.  
  1762. #define TV_CSC_V                0x68020
  1763. # define TV_RV_MASK                     0x0fff0000
  1764. # define TV_RV_SHIFT                    16
  1765. # define TV_GV_MASK                     0x000007ff
  1766. # define TV_GV_SHIFT                    0
  1767.  
  1768. #define TV_CSC_V2               0x68024
  1769. # define TV_BV_MASK                     0x07ff0000
  1770. # define TV_BV_SHIFT                    16
  1771. /**
  1772.  * V attenuation for component video.
  1773.  *
  1774.  * Stored in 1.9 fixed point.
  1775.  */
  1776. # define TV_AV_MASK                     0x000007ff
  1777. # define TV_AV_SHIFT                    0
  1778.  
  1779. #define TV_CLR_KNOBS            0x68028
  1780. /** 2s-complement brightness adjustment */
  1781. # define TV_BRIGHTNESS_MASK             0xff000000
  1782. # define TV_BRIGHTNESS_SHIFT            24
  1783. /** Contrast adjustment, as a 2.6 unsigned floating point number */
  1784. # define TV_CONTRAST_MASK               0x00ff0000
  1785. # define TV_CONTRAST_SHIFT              16
  1786. /** Saturation adjustment, as a 2.6 unsigned floating point number */
  1787. # define TV_SATURATION_MASK             0x0000ff00
  1788. # define TV_SATURATION_SHIFT            8
  1789. /** Hue adjustment, as an integer phase angle in degrees */
  1790. # define TV_HUE_MASK                    0x000000ff
  1791. # define TV_HUE_SHIFT                   0
  1792.  
  1793. #define TV_CLR_LEVEL            0x6802c
  1794. /** Controls the DAC level for black */
  1795. # define TV_BLACK_LEVEL_MASK            0x01ff0000
  1796. # define TV_BLACK_LEVEL_SHIFT           16
  1797. /** Controls the DAC level for blanking */
  1798. # define TV_BLANK_LEVEL_MASK            0x000001ff
  1799. # define TV_BLANK_LEVEL_SHIFT           0
  1800.  
  1801. #define TV_H_CTL_1              0x68030
  1802. /** Number of pixels in the hsync. */
  1803. # define TV_HSYNC_END_MASK              0x1fff0000
  1804. # define TV_HSYNC_END_SHIFT             16
  1805. /** Total number of pixels minus one in the line (display and blanking). */
  1806. # define TV_HTOTAL_MASK                 0x00001fff
  1807. # define TV_HTOTAL_SHIFT                0
  1808.  
  1809. #define TV_H_CTL_2              0x68034
  1810. /** Enables the colorburst (needed for non-component color) */
  1811. # define TV_BURST_ENA                   (1 << 31)
  1812. /** Offset of the colorburst from the start of hsync, in pixels minus one. */
  1813. # define TV_HBURST_START_SHIFT          16
  1814. # define TV_HBURST_START_MASK           0x1fff0000
  1815. /** Length of the colorburst */
  1816. # define TV_HBURST_LEN_SHIFT            0
  1817. # define TV_HBURST_LEN_MASK             0x0001fff
  1818.  
  1819. #define TV_H_CTL_3              0x68038
  1820. /** End of hblank, measured in pixels minus one from start of hsync */
  1821. # define TV_HBLANK_END_SHIFT            16
  1822. # define TV_HBLANK_END_MASK             0x1fff0000
  1823. /** Start of hblank, measured in pixels minus one from start of hsync */
  1824. # define TV_HBLANK_START_SHIFT          0
  1825. # define TV_HBLANK_START_MASK           0x0001fff
  1826.  
  1827. #define TV_V_CTL_1              0x6803c
  1828. /** XXX */
  1829. # define TV_NBR_END_SHIFT               16
  1830. # define TV_NBR_END_MASK                0x07ff0000
  1831. /** XXX */
  1832. # define TV_VI_END_F1_SHIFT             8
  1833. # define TV_VI_END_F1_MASK              0x00003f00
  1834. /** XXX */
  1835. # define TV_VI_END_F2_SHIFT             0
  1836. # define TV_VI_END_F2_MASK              0x0000003f
  1837.  
  1838. #define TV_V_CTL_2              0x68040
  1839. /** Length of vsync, in half lines */
  1840. # define TV_VSYNC_LEN_MASK              0x07ff0000
  1841. # define TV_VSYNC_LEN_SHIFT             16
  1842. /** Offset of the start of vsync in field 1, measured in one less than the
  1843.  * number of half lines.
  1844.  */
  1845. # define TV_VSYNC_START_F1_MASK         0x00007f00
  1846. # define TV_VSYNC_START_F1_SHIFT        8
  1847. /**
  1848.  * Offset of the start of vsync in field 2, measured in one less than the
  1849.  * number of half lines.
  1850.  */
  1851. # define TV_VSYNC_START_F2_MASK         0x0000007f
  1852. # define TV_VSYNC_START_F2_SHIFT        0
  1853.  
  1854. #define TV_V_CTL_3              0x68044
  1855. /** Enables generation of the equalization signal */
  1856. # define TV_EQUAL_ENA                   (1 << 31)
  1857. /** Length of vsync, in half lines */
  1858. # define TV_VEQ_LEN_MASK                0x007f0000
  1859. # define TV_VEQ_LEN_SHIFT               16
  1860. /** Offset of the start of equalization in field 1, measured in one less than
  1861.  * the number of half lines.
  1862.  */
  1863. # define TV_VEQ_START_F1_MASK           0x0007f00
  1864. # define TV_VEQ_START_F1_SHIFT          8
  1865. /**
  1866.  * Offset of the start of equalization in field 2, measured in one less than
  1867.  * the number of half lines.
  1868.  */
  1869. # define TV_VEQ_START_F2_MASK           0x000007f
  1870. # define TV_VEQ_START_F2_SHIFT          0
  1871.  
  1872. #define TV_V_CTL_4              0x68048
  1873. /**
  1874.  * Offset to start of vertical colorburst, measured in one less than the
  1875.  * number of lines from vertical start.
  1876.  */
  1877. # define TV_VBURST_START_F1_MASK        0x003f0000
  1878. # define TV_VBURST_START_F1_SHIFT       16
  1879. /**
  1880.  * Offset to the end of vertical colorburst, measured in one less than the
  1881.  * number of lines from the start of NBR.
  1882.  */
  1883. # define TV_VBURST_END_F1_MASK          0x000000ff
  1884. # define TV_VBURST_END_F1_SHIFT         0
  1885.  
  1886. #define TV_V_CTL_5              0x6804c
  1887. /**
  1888.  * Offset to start of vertical colorburst, measured in one less than the
  1889.  * number of lines from vertical start.
  1890.  */
  1891. # define TV_VBURST_START_F2_MASK        0x003f0000
  1892. # define TV_VBURST_START_F2_SHIFT       16
  1893. /**
  1894.  * Offset to the end of vertical colorburst, measured in one less than the
  1895.  * number of lines from the start of NBR.
  1896.  */
  1897. # define TV_VBURST_END_F2_MASK          0x000000ff
  1898. # define TV_VBURST_END_F2_SHIFT         0
  1899.  
  1900. #define TV_V_CTL_6              0x68050
  1901. /**
  1902.  * Offset to start of vertical colorburst, measured in one less than the
  1903.  * number of lines from vertical start.
  1904.  */
  1905. # define TV_VBURST_START_F3_MASK        0x003f0000
  1906. # define TV_VBURST_START_F3_SHIFT       16
  1907. /**
  1908.  * Offset to the end of vertical colorburst, measured in one less than the
  1909.  * number of lines from the start of NBR.
  1910.  */
  1911. # define TV_VBURST_END_F3_MASK          0x000000ff
  1912. # define TV_VBURST_END_F3_SHIFT         0
  1913.  
  1914. #define TV_V_CTL_7              0x68054
  1915. /**
  1916.  * Offset to start of vertical colorburst, measured in one less than the
  1917.  * number of lines from vertical start.
  1918.  */
  1919. # define TV_VBURST_START_F4_MASK        0x003f0000
  1920. # define TV_VBURST_START_F4_SHIFT       16
  1921. /**
  1922.  * Offset to the end of vertical colorburst, measured in one less than the
  1923.  * number of lines from the start of NBR.
  1924.  */
  1925. # define TV_VBURST_END_F4_MASK          0x000000ff
  1926. # define TV_VBURST_END_F4_SHIFT         0
  1927.  
  1928. #define TV_SC_CTL_1             0x68060
  1929. /** Turns on the first subcarrier phase generation DDA */
  1930. # define TV_SC_DDA1_EN                  (1 << 31)
  1931. /** Turns on the first subcarrier phase generation DDA */
  1932. # define TV_SC_DDA2_EN                  (1 << 30)
  1933. /** Turns on the first subcarrier phase generation DDA */
  1934. # define TV_SC_DDA3_EN                  (1 << 29)
  1935. /** Sets the subcarrier DDA to reset frequency every other field */
  1936. # define TV_SC_RESET_EVERY_2            (0 << 24)
  1937. /** Sets the subcarrier DDA to reset frequency every fourth field */
  1938. # define TV_SC_RESET_EVERY_4            (1 << 24)
  1939. /** Sets the subcarrier DDA to reset frequency every eighth field */
  1940. # define TV_SC_RESET_EVERY_8            (2 << 24)
  1941. /** Sets the subcarrier DDA to never reset the frequency */
  1942. # define TV_SC_RESET_NEVER              (3 << 24)
  1943. /** Sets the peak amplitude of the colorburst.*/
  1944. # define TV_BURST_LEVEL_MASK            0x00ff0000
  1945. # define TV_BURST_LEVEL_SHIFT           16
  1946. /** Sets the increment of the first subcarrier phase generation DDA */
  1947. # define TV_SCDDA1_INC_MASK             0x00000fff
  1948. # define TV_SCDDA1_INC_SHIFT            0
  1949.  
  1950. #define TV_SC_CTL_2             0x68064
  1951. /** Sets the rollover for the second subcarrier phase generation DDA */
  1952. # define TV_SCDDA2_SIZE_MASK            0x7fff0000
  1953. # define TV_SCDDA2_SIZE_SHIFT           16
  1954. /** Sets the increent of the second subcarrier phase generation DDA */
  1955. # define TV_SCDDA2_INC_MASK             0x00007fff
  1956. # define TV_SCDDA2_INC_SHIFT            0
  1957.  
  1958. #define TV_SC_CTL_3             0x68068
  1959. /** Sets the rollover for the third subcarrier phase generation DDA */
  1960. # define TV_SCDDA3_SIZE_MASK            0x7fff0000
  1961. # define TV_SCDDA3_SIZE_SHIFT           16
  1962. /** Sets the increent of the third subcarrier phase generation DDA */
  1963. # define TV_SCDDA3_INC_MASK             0x00007fff
  1964. # define TV_SCDDA3_INC_SHIFT            0
  1965.  
  1966. #define TV_WIN_POS              0x68070
  1967. /** X coordinate of the display from the start of horizontal active */
  1968. # define TV_XPOS_MASK                   0x1fff0000
  1969. # define TV_XPOS_SHIFT                  16
  1970. /** Y coordinate of the display from the start of vertical active (NBR) */
  1971. # define TV_YPOS_MASK                   0x00000fff
  1972. # define TV_YPOS_SHIFT                  0
  1973.  
  1974. #define TV_WIN_SIZE             0x68074
  1975. /** Horizontal size of the display window, measured in pixels*/
  1976. # define TV_XSIZE_MASK                  0x1fff0000
  1977. # define TV_XSIZE_SHIFT                 16
  1978. /**
  1979.  * Vertical size of the display window, measured in pixels.
  1980.  *
  1981.  * Must be even for interlaced modes.
  1982.  */
  1983. # define TV_YSIZE_MASK                  0x00000fff
  1984. # define TV_YSIZE_SHIFT                 0
  1985.  
  1986. #define TV_FILTER_CTL_1         0x68080
  1987. /**
  1988.  * Enables automatic scaling calculation.
  1989.  *
  1990.  * If set, the rest of the registers are ignored, and the calculated values can
  1991.  * be read back from the register.
  1992.  */
  1993. # define TV_AUTO_SCALE                  (1 << 31)
  1994. /**
  1995.  * Disables the vertical filter.
  1996.  *
  1997.  * This is required on modes more than 1024 pixels wide */
  1998. # define TV_V_FILTER_BYPASS             (1 << 29)
  1999. /** Enables adaptive vertical filtering */
  2000. # define TV_VADAPT                      (1 << 28)
  2001. # define TV_VADAPT_MODE_MASK            (3 << 26)
  2002. /** Selects the least adaptive vertical filtering mode */
  2003. # define TV_VADAPT_MODE_LEAST           (0 << 26)
  2004. /** Selects the moderately adaptive vertical filtering mode */
  2005. # define TV_VADAPT_MODE_MODERATE        (1 << 26)
  2006. /** Selects the most adaptive vertical filtering mode */
  2007. # define TV_VADAPT_MODE_MOST            (3 << 26)
  2008. /**
  2009.  * Sets the horizontal scaling factor.
  2010.  *
  2011.  * This should be the fractional part of the horizontal scaling factor divided
  2012.  * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
  2013.  *
  2014.  * (src width - 1) / ((oversample * dest width) - 1)
  2015.  */
  2016. # define TV_HSCALE_FRAC_MASK            0x00003fff
  2017. # define TV_HSCALE_FRAC_SHIFT           0
  2018.  
  2019. #define TV_FILTER_CTL_2         0x68084
  2020. /**
  2021.  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  2022.  *
  2023.  * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
  2024.  */
  2025. # define TV_VSCALE_INT_MASK             0x00038000
  2026. # define TV_VSCALE_INT_SHIFT            15
  2027. /**
  2028.  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  2029.  *
  2030.  * \sa TV_VSCALE_INT_MASK
  2031.  */
  2032. # define TV_VSCALE_FRAC_MASK            0x00007fff
  2033. # define TV_VSCALE_FRAC_SHIFT           0
  2034.  
  2035. #define TV_FILTER_CTL_3         0x68088
  2036. /**
  2037.  * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
  2038.  *
  2039.  * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
  2040.  *
  2041.  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  2042.  */
  2043. # define TV_VSCALE_IP_INT_MASK          0x00038000
  2044. # define TV_VSCALE_IP_INT_SHIFT         15
  2045. /**
  2046.  * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
  2047.  *
  2048.  * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
  2049.  *
  2050.  * \sa TV_VSCALE_IP_INT_MASK
  2051.  */
  2052. # define TV_VSCALE_IP_FRAC_MASK         0x00007fff
  2053. # define TV_VSCALE_IP_FRAC_SHIFT                0
  2054.  
  2055. #define TV_CC_CONTROL           0x68090
  2056. # define TV_CC_ENABLE                   (1 << 31)
  2057. /**
  2058.  * Specifies which field to send the CC data in.
  2059.  *
  2060.  * CC data is usually sent in field 0.
  2061.  */
  2062. # define TV_CC_FID_MASK                 (1 << 27)
  2063. # define TV_CC_FID_SHIFT                27
  2064. /** Sets the horizontal position of the CC data.  Usually 135. */
  2065. # define TV_CC_HOFF_MASK                0x03ff0000
  2066. # define TV_CC_HOFF_SHIFT               16
  2067. /** Sets the vertical position of the CC data.  Usually 21 */
  2068. # define TV_CC_LINE_MASK                0x0000003f
  2069. # define TV_CC_LINE_SHIFT               0
  2070.  
  2071. #define TV_CC_DATA              0x68094
  2072. # define TV_CC_RDY                      (1 << 31)
  2073. /** Second word of CC data to be transmitted. */
  2074. # define TV_CC_DATA_2_MASK              0x007f0000
  2075. # define TV_CC_DATA_2_SHIFT             16
  2076. /** First word of CC data to be transmitted. */
  2077. # define TV_CC_DATA_1_MASK              0x0000007f
  2078. # define TV_CC_DATA_1_SHIFT             0
  2079.  
  2080. #define TV_H_LUMA_0             0x68100
  2081. #define TV_H_LUMA_59            0x681ec
  2082. #define TV_H_CHROMA_0           0x68200
  2083. #define TV_H_CHROMA_59          0x682ec
  2084. #define TV_V_LUMA_0             0x68300
  2085. #define TV_V_LUMA_42            0x683a8
  2086. #define TV_V_CHROMA_0           0x68400
  2087. #define TV_V_CHROMA_42          0x684a8
  2088.  
  2089. /* Display Port */
  2090. #define DP_A                            0x64000 /* eDP */
  2091. #define DP_B                            0x64100
  2092. #define DP_C                            0x64200
  2093. #define DP_D                            0x64300
  2094.  
  2095. #define   DP_PORT_EN                    (1 << 31)
  2096. #define   DP_PIPEB_SELECT               (1 << 30)
  2097. #define   DP_PIPE_MASK                  (1 << 30)
  2098.  
  2099. /* Link training mode - select a suitable mode for each stage */
  2100. #define   DP_LINK_TRAIN_PAT_1           (0 << 28)
  2101. #define   DP_LINK_TRAIN_PAT_2           (1 << 28)
  2102. #define   DP_LINK_TRAIN_PAT_IDLE        (2 << 28)
  2103. #define   DP_LINK_TRAIN_OFF             (3 << 28)
  2104. #define   DP_LINK_TRAIN_MASK            (3 << 28)
  2105. #define   DP_LINK_TRAIN_SHIFT           28
  2106.  
  2107. /* CPT Link training mode */
  2108. #define   DP_LINK_TRAIN_PAT_1_CPT       (0 << 8)
  2109. #define   DP_LINK_TRAIN_PAT_2_CPT       (1 << 8)
  2110. #define   DP_LINK_TRAIN_PAT_IDLE_CPT    (2 << 8)
  2111. #define   DP_LINK_TRAIN_OFF_CPT         (3 << 8)
  2112. #define   DP_LINK_TRAIN_MASK_CPT        (7 << 8)
  2113. #define   DP_LINK_TRAIN_SHIFT_CPT       8
  2114.  
  2115. /* Signal voltages. These are mostly controlled by the other end */
  2116. #define   DP_VOLTAGE_0_4                (0 << 25)
  2117. #define   DP_VOLTAGE_0_6                (1 << 25)
  2118. #define   DP_VOLTAGE_0_8                (2 << 25)
  2119. #define   DP_VOLTAGE_1_2                (3 << 25)
  2120. #define   DP_VOLTAGE_MASK               (7 << 25)
  2121. #define   DP_VOLTAGE_SHIFT              25
  2122.  
  2123. /* Signal pre-emphasis levels, like voltages, the other end tells us what
  2124.  * they want
  2125.  */
  2126. #define   DP_PRE_EMPHASIS_0             (0 << 22)
  2127. #define   DP_PRE_EMPHASIS_3_5           (1 << 22)
  2128. #define   DP_PRE_EMPHASIS_6             (2 << 22)
  2129. #define   DP_PRE_EMPHASIS_9_5           (3 << 22)
  2130. #define   DP_PRE_EMPHASIS_MASK          (7 << 22)
  2131. #define   DP_PRE_EMPHASIS_SHIFT         22
  2132.  
  2133. /* How many wires to use. I guess 3 was too hard */
  2134. #define   DP_PORT_WIDTH_1               (0 << 19)
  2135. #define   DP_PORT_WIDTH_2               (1 << 19)
  2136. #define   DP_PORT_WIDTH_4               (3 << 19)
  2137. #define   DP_PORT_WIDTH_MASK            (7 << 19)
  2138.  
  2139. /* Mystic DPCD version 1.1 special mode */
  2140. #define   DP_ENHANCED_FRAMING           (1 << 18)
  2141.  
  2142. /* eDP */
  2143. #define   DP_PLL_FREQ_270MHZ            (0 << 16)
  2144. #define   DP_PLL_FREQ_160MHZ            (1 << 16)
  2145. #define   DP_PLL_FREQ_MASK              (3 << 16)
  2146.  
  2147. /** locked once port is enabled */
  2148. #define   DP_PORT_REVERSAL              (1 << 15)
  2149.  
  2150. /* eDP */
  2151. #define   DP_PLL_ENABLE                 (1 << 14)
  2152.  
  2153. /** sends the clock on lane 15 of the PEG for debug */
  2154. #define   DP_CLOCK_OUTPUT_ENABLE        (1 << 13)
  2155.  
  2156. #define   DP_SCRAMBLING_DISABLE         (1 << 12)
  2157. #define   DP_SCRAMBLING_DISABLE_IRONLAKE        (1 << 7)
  2158.  
  2159. /** limit RGB values to avoid confusing TVs */
  2160. #define   DP_COLOR_RANGE_16_235         (1 << 8)
  2161.  
  2162. /** Turn on the audio link */
  2163. #define   DP_AUDIO_OUTPUT_ENABLE        (1 << 6)
  2164.  
  2165. /** vs and hs sync polarity */
  2166. #define   DP_SYNC_VS_HIGH               (1 << 4)
  2167. #define   DP_SYNC_HS_HIGH               (1 << 3)
  2168.  
  2169. /** A fantasy */
  2170. #define   DP_DETECTED                   (1 << 2)
  2171.  
  2172. /** The aux channel provides a way to talk to the
  2173.  * signal sink for DDC etc. Max packet size supported
  2174.  * is 20 bytes in each direction, hence the 5 fixed
  2175.  * data registers
  2176.  */
  2177. #define DPA_AUX_CH_CTL                  0x64010
  2178. #define DPA_AUX_CH_DATA1                0x64014
  2179. #define DPA_AUX_CH_DATA2                0x64018
  2180. #define DPA_AUX_CH_DATA3                0x6401c
  2181. #define DPA_AUX_CH_DATA4                0x64020
  2182. #define DPA_AUX_CH_DATA5                0x64024
  2183.  
  2184. #define DPB_AUX_CH_CTL                  0x64110
  2185. #define DPB_AUX_CH_DATA1                0x64114
  2186. #define DPB_AUX_CH_DATA2                0x64118
  2187. #define DPB_AUX_CH_DATA3                0x6411c
  2188. #define DPB_AUX_CH_DATA4                0x64120
  2189. #define DPB_AUX_CH_DATA5                0x64124
  2190.  
  2191. #define DPC_AUX_CH_CTL                  0x64210
  2192. #define DPC_AUX_CH_DATA1                0x64214
  2193. #define DPC_AUX_CH_DATA2                0x64218
  2194. #define DPC_AUX_CH_DATA3                0x6421c
  2195. #define DPC_AUX_CH_DATA4                0x64220
  2196. #define DPC_AUX_CH_DATA5                0x64224
  2197.  
  2198. #define DPD_AUX_CH_CTL                  0x64310
  2199. #define DPD_AUX_CH_DATA1                0x64314
  2200. #define DPD_AUX_CH_DATA2                0x64318
  2201. #define DPD_AUX_CH_DATA3                0x6431c
  2202. #define DPD_AUX_CH_DATA4                0x64320
  2203. #define DPD_AUX_CH_DATA5                0x64324
  2204.  
  2205. #define   DP_AUX_CH_CTL_SEND_BUSY           (1 << 31)
  2206. #define   DP_AUX_CH_CTL_DONE                (1 << 30)
  2207. #define   DP_AUX_CH_CTL_INTERRUPT           (1 << 29)
  2208. #define   DP_AUX_CH_CTL_TIME_OUT_ERROR      (1 << 28)
  2209. #define   DP_AUX_CH_CTL_TIME_OUT_400us      (0 << 26)
  2210. #define   DP_AUX_CH_CTL_TIME_OUT_600us      (1 << 26)
  2211. #define   DP_AUX_CH_CTL_TIME_OUT_800us      (2 << 26)
  2212. #define   DP_AUX_CH_CTL_TIME_OUT_1600us     (3 << 26)
  2213. #define   DP_AUX_CH_CTL_TIME_OUT_MASK       (3 << 26)
  2214. #define   DP_AUX_CH_CTL_RECEIVE_ERROR       (1 << 25)
  2215. #define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
  2216. #define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
  2217. #define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
  2218. #define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
  2219. #define   DP_AUX_CH_CTL_AUX_AKSV_SELECT     (1 << 15)
  2220. #define   DP_AUX_CH_CTL_MANCHESTER_TEST     (1 << 14)
  2221. #define   DP_AUX_CH_CTL_SYNC_TEST           (1 << 13)
  2222. #define   DP_AUX_CH_CTL_DEGLITCH_TEST       (1 << 12)
  2223. #define   DP_AUX_CH_CTL_PRECHARGE_TEST      (1 << 11)
  2224. #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
  2225. #define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
  2226.  
  2227. /*
  2228.  * Computing GMCH M and N values for the Display Port link
  2229.  *
  2230.  * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
  2231.  *
  2232.  * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
  2233.  *
  2234.  * The GMCH value is used internally
  2235.  *
  2236.  * bytes_per_pixel is the number of bytes coming out of the plane,
  2237.  * which is after the LUTs, so we want the bytes for our color format.
  2238.  * For our current usage, this is always 3, one byte for R, G and B.
  2239.  */
  2240. #define _PIPEA_GMCH_DATA_M                      0x70050
  2241. #define _PIPEB_GMCH_DATA_M                      0x71050
  2242.  
  2243. /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
  2244. #define   PIPE_GMCH_DATA_M_TU_SIZE_MASK         (0x3f << 25)
  2245. #define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT        25
  2246.  
  2247. #define   PIPE_GMCH_DATA_M_MASK                 (0xffffff)
  2248.  
  2249. #define _PIPEA_GMCH_DATA_N                      0x70054
  2250. #define _PIPEB_GMCH_DATA_N                      0x71054
  2251. #define   PIPE_GMCH_DATA_N_MASK                 (0xffffff)
  2252.  
  2253. /*
  2254.  * Computing Link M and N values for the Display Port link
  2255.  *
  2256.  * Link M / N = pixel_clock / ls_clk
  2257.  *
  2258.  * (the DP spec calls pixel_clock the 'strm_clk')
  2259.  *
  2260.  * The Link value is transmitted in the Main Stream
  2261.  * Attributes and VB-ID.
  2262.  */
  2263.  
  2264. #define _PIPEA_DP_LINK_M                                0x70060
  2265. #define _PIPEB_DP_LINK_M                                0x71060
  2266. #define   PIPEA_DP_LINK_M_MASK                  (0xffffff)
  2267.  
  2268. #define _PIPEA_DP_LINK_N                                0x70064
  2269. #define _PIPEB_DP_LINK_N                                0x71064
  2270. #define   PIPEA_DP_LINK_N_MASK                  (0xffffff)
  2271.  
  2272. #define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
  2273. #define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
  2274. #define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
  2275. #define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
  2276.  
  2277. /* Display & cursor control */
  2278.  
  2279. /* Pipe A */
  2280. #define _PIPEADSL               0x70000
  2281. #define   DSL_LINEMASK          0x00000fff
  2282. #define _PIPEACONF              0x70008
  2283. #define   PIPECONF_ENABLE       (1<<31)
  2284. #define   PIPECONF_DISABLE      0
  2285. #define   PIPECONF_DOUBLE_WIDE  (1<<30)
  2286. #define   I965_PIPECONF_ACTIVE  (1<<30)
  2287. #define   PIPECONF_SINGLE_WIDE  0
  2288. #define   PIPECONF_PIPE_UNLOCKED 0
  2289. #define   PIPECONF_PIPE_LOCKED  (1<<25)
  2290. #define   PIPECONF_PALETTE      0
  2291. #define   PIPECONF_GAMMA                (1<<24)
  2292. #define   PIPECONF_FORCE_BORDER (1<<25)
  2293. #define   PIPECONF_PROGRESSIVE  (0 << 21)
  2294. #define   PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
  2295. #define   PIPECONF_INTERLACE_FIELD_0_ONLY               (7 << 21)
  2296. #define   PIPECONF_CXSR_DOWNCLOCK       (1<<16)
  2297. #define   PIPECONF_BPP_MASK     (0x000000e0)
  2298. #define   PIPECONF_BPP_8        (0<<5)
  2299. #define   PIPECONF_BPP_10       (1<<5)
  2300. #define   PIPECONF_BPP_6        (2<<5)
  2301. #define   PIPECONF_BPP_12       (3<<5)
  2302. #define   PIPECONF_DITHER_EN    (1<<4)
  2303. #define   PIPECONF_DITHER_TYPE_MASK (0x0000000c)
  2304. #define   PIPECONF_DITHER_TYPE_SP (0<<2)
  2305. #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
  2306. #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
  2307. #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
  2308. #define _PIPEASTAT              0x70024
  2309. #define   PIPE_FIFO_UNDERRUN_STATUS             (1UL<<31)
  2310. #define   PIPE_CRC_ERROR_ENABLE                 (1UL<<29)
  2311. #define   PIPE_CRC_DONE_ENABLE                  (1UL<<28)
  2312. #define   PIPE_GMBUS_EVENT_ENABLE               (1UL<<27)
  2313. #define   PIPE_HOTPLUG_INTERRUPT_ENABLE         (1UL<<26)
  2314. #define   PIPE_VSYNC_INTERRUPT_ENABLE           (1UL<<25)
  2315. #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE      (1UL<<24)
  2316. #define   PIPE_DPST_EVENT_ENABLE                (1UL<<23)
  2317. #define   PIPE_LEGACY_BLC_EVENT_ENABLE          (1UL<<22)
  2318. #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE       (1UL<<21)
  2319. #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE      (1UL<<20)
  2320. #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE      (1UL<<18) /* pre-965 */
  2321. #define   PIPE_START_VBLANK_INTERRUPT_ENABLE    (1UL<<18) /* 965 or later */
  2322. #define   PIPE_VBLANK_INTERRUPT_ENABLE          (1UL<<17)
  2323. #define   PIPE_OVERLAY_UPDATED_ENABLE           (1UL<<16)
  2324. #define   PIPE_CRC_ERROR_INTERRUPT_STATUS       (1UL<<13)
  2325. #define   PIPE_CRC_DONE_INTERRUPT_STATUS        (1UL<<12)
  2326. #define   PIPE_GMBUS_INTERRUPT_STATUS           (1UL<<11)
  2327. #define   PIPE_HOTPLUG_INTERRUPT_STATUS         (1UL<<10)
  2328. #define   PIPE_VSYNC_INTERRUPT_STATUS           (1UL<<9)
  2329. #define   PIPE_DISPLAY_LINE_COMPARE_STATUS      (1UL<<8)
  2330. #define   PIPE_DPST_EVENT_STATUS                (1UL<<7)
  2331. #define   PIPE_LEGACY_BLC_EVENT_STATUS          (1UL<<6)
  2332. #define   PIPE_ODD_FIELD_INTERRUPT_STATUS       (1UL<<5)
  2333. #define   PIPE_EVEN_FIELD_INTERRUPT_STATUS      (1UL<<4)
  2334. #define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS      (1UL<<2) /* pre-965 */
  2335. #define   PIPE_START_VBLANK_INTERRUPT_STATUS    (1UL<<2) /* 965 or later */
  2336. #define   PIPE_VBLANK_INTERRUPT_STATUS          (1UL<<1)
  2337. #define   PIPE_OVERLAY_UPDATED_STATUS           (1UL<<0)
  2338. #define   PIPE_BPC_MASK                         (7 << 5) /* Ironlake */
  2339. #define   PIPE_8BPC                             (0 << 5)
  2340. #define   PIPE_10BPC                            (1 << 5)
  2341. #define   PIPE_6BPC                             (2 << 5)
  2342. #define   PIPE_12BPC                            (3 << 5)
  2343.  
  2344. #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
  2345. #define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
  2346. #define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
  2347. #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
  2348. #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
  2349. #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
  2350.  
  2351. #define DSPARB                  0x70030
  2352. #define   DSPARB_CSTART_MASK    (0x7f << 7)
  2353. #define   DSPARB_CSTART_SHIFT   7
  2354. #define   DSPARB_BSTART_MASK    (0x7f)
  2355. #define   DSPARB_BSTART_SHIFT   0
  2356. #define   DSPARB_BEND_SHIFT     9 /* on 855 */
  2357. #define   DSPARB_AEND_SHIFT     0
  2358.  
  2359. #define DSPFW1                  0x70034
  2360. #define   DSPFW_SR_SHIFT        23
  2361. #define   DSPFW_SR_MASK         (0x1ff<<23)
  2362. #define   DSPFW_CURSORB_SHIFT   16
  2363. #define   DSPFW_CURSORB_MASK    (0x3f<<16)
  2364. #define   DSPFW_PLANEB_SHIFT    8
  2365. #define   DSPFW_PLANEB_MASK     (0x7f<<8)
  2366. #define   DSPFW_PLANEA_MASK     (0x7f)
  2367. #define DSPFW2                  0x70038
  2368. #define   DSPFW_CURSORA_MASK    0x00003f00
  2369. #define   DSPFW_CURSORA_SHIFT   8
  2370. #define   DSPFW_PLANEC_MASK     (0x7f)
  2371. #define DSPFW3                  0x7003c
  2372. #define   DSPFW_HPLL_SR_EN      (1<<31)
  2373. #define   DSPFW_CURSOR_SR_SHIFT 24
  2374. #define   PINEVIEW_SELF_REFRESH_EN      (1<<30)
  2375. #define   DSPFW_CURSOR_SR_MASK          (0x3f<<24)
  2376. #define   DSPFW_HPLL_CURSOR_SHIFT       16
  2377. #define   DSPFW_HPLL_CURSOR_MASK        (0x3f<<16)
  2378. #define   DSPFW_HPLL_SR_MASK            (0x1ff)
  2379.  
  2380. /* FIFO watermark sizes etc */
  2381. #define G4X_FIFO_LINE_SIZE      64
  2382. #define I915_FIFO_LINE_SIZE     64
  2383. #define I830_FIFO_LINE_SIZE     32
  2384.  
  2385. #define G4X_FIFO_SIZE           127
  2386. #define I965_FIFO_SIZE          512
  2387. #define I945_FIFO_SIZE          127
  2388. #define I915_FIFO_SIZE          95
  2389. #define I855GM_FIFO_SIZE        127 /* In cachelines */
  2390. #define I830_FIFO_SIZE          95
  2391.  
  2392. #define G4X_MAX_WM              0x3f
  2393. #define I915_MAX_WM             0x3f
  2394.  
  2395. #define PINEVIEW_DISPLAY_FIFO   512 /* in 64byte unit */
  2396. #define PINEVIEW_FIFO_LINE_SIZE 64
  2397. #define PINEVIEW_MAX_WM         0x1ff
  2398. #define PINEVIEW_DFT_WM         0x3f
  2399. #define PINEVIEW_DFT_HPLLOFF_WM 0
  2400. #define PINEVIEW_GUARD_WM               10
  2401. #define PINEVIEW_CURSOR_FIFO            64
  2402. #define PINEVIEW_CURSOR_MAX_WM  0x3f
  2403. #define PINEVIEW_CURSOR_DFT_WM  0
  2404. #define PINEVIEW_CURSOR_GUARD_WM        5
  2405.  
  2406. #define I965_CURSOR_FIFO        64
  2407. #define I965_CURSOR_MAX_WM      32
  2408. #define I965_CURSOR_DFT_WM      8
  2409.  
  2410. /* define the Watermark register on Ironlake */
  2411. #define WM0_PIPEA_ILK           0x45100
  2412. #define  WM0_PIPE_PLANE_MASK    (0x7f<<16)
  2413. #define  WM0_PIPE_PLANE_SHIFT   16
  2414. #define  WM0_PIPE_SPRITE_MASK   (0x3f<<8)
  2415. #define  WM0_PIPE_SPRITE_SHIFT  8
  2416. #define  WM0_PIPE_CURSOR_MASK   (0x1f)
  2417.  
  2418. #define WM0_PIPEB_ILK           0x45104
  2419. #define WM1_LP_ILK              0x45108
  2420. #define  WM1_LP_SR_EN           (1<<31)
  2421. #define  WM1_LP_LATENCY_SHIFT   24
  2422. #define  WM1_LP_LATENCY_MASK    (0x7f<<24)
  2423. #define  WM1_LP_FBC_MASK        (0xf<<20)
  2424. #define  WM1_LP_FBC_SHIFT       20
  2425. #define  WM1_LP_SR_MASK         (0x1ff<<8)
  2426. #define  WM1_LP_SR_SHIFT        8
  2427. #define  WM1_LP_CURSOR_MASK     (0x3f)
  2428. #define WM2_LP_ILK              0x4510c
  2429. #define  WM2_LP_EN              (1<<31)
  2430. #define WM3_LP_ILK              0x45110
  2431. #define  WM3_LP_EN              (1<<31)
  2432. #define WM1S_LP_ILK             0x45120
  2433. #define  WM1S_LP_EN             (1<<31)
  2434.  
  2435. /* Memory latency timer register */
  2436. #define MLTR_ILK                0x11222
  2437. #define  MLTR_WM1_SHIFT         0
  2438. #define  MLTR_WM2_SHIFT         8
  2439. /* the unit of memory self-refresh latency time is 0.5us */
  2440. #define  ILK_SRLT_MASK          0x3f
  2441. #define ILK_LATENCY(shift)      (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
  2442. #define ILK_READ_WM1_LATENCY()  ILK_LATENCY(MLTR_WM1_SHIFT)
  2443. #define ILK_READ_WM2_LATENCY()  ILK_LATENCY(MLTR_WM2_SHIFT)
  2444.  
  2445. /* define the fifo size on Ironlake */
  2446. #define ILK_DISPLAY_FIFO        128
  2447. #define ILK_DISPLAY_MAXWM       64
  2448. #define ILK_DISPLAY_DFTWM       8
  2449. #define ILK_CURSOR_FIFO         32
  2450. #define ILK_CURSOR_MAXWM        16
  2451. #define ILK_CURSOR_DFTWM        8
  2452.  
  2453. #define ILK_DISPLAY_SR_FIFO     512
  2454. #define ILK_DISPLAY_MAX_SRWM    0x1ff
  2455. #define ILK_DISPLAY_DFT_SRWM    0x3f
  2456. #define ILK_CURSOR_SR_FIFO      64
  2457. #define ILK_CURSOR_MAX_SRWM     0x3f
  2458. #define ILK_CURSOR_DFT_SRWM     8
  2459.  
  2460. #define ILK_FIFO_LINE_SIZE      64
  2461.  
  2462. /* define the WM info on Sandybridge */
  2463. #define SNB_DISPLAY_FIFO        128
  2464. #define SNB_DISPLAY_MAXWM       0x7f    /* bit 16:22 */
  2465. #define SNB_DISPLAY_DFTWM       8
  2466. #define SNB_CURSOR_FIFO         32
  2467. #define SNB_CURSOR_MAXWM        0x1f    /* bit 4:0 */
  2468. #define SNB_CURSOR_DFTWM        8
  2469.  
  2470. #define SNB_DISPLAY_SR_FIFO     512
  2471. #define SNB_DISPLAY_MAX_SRWM    0x1ff   /* bit 16:8 */
  2472. #define SNB_DISPLAY_DFT_SRWM    0x3f
  2473. #define SNB_CURSOR_SR_FIFO      64
  2474. #define SNB_CURSOR_MAX_SRWM     0x3f    /* bit 5:0 */
  2475. #define SNB_CURSOR_DFT_SRWM     8
  2476.  
  2477. #define SNB_FBC_MAX_SRWM        0xf     /* bit 23:20 */
  2478.  
  2479. #define SNB_FIFO_LINE_SIZE      64
  2480.  
  2481.  
  2482. /* the address where we get all kinds of latency value */
  2483. #define SSKPD                   0x5d10
  2484. #define SSKPD_WM_MASK           0x3f
  2485. #define SSKPD_WM0_SHIFT         0
  2486. #define SSKPD_WM1_SHIFT         8
  2487. #define SSKPD_WM2_SHIFT         16
  2488. #define SSKPD_WM3_SHIFT         24
  2489.  
  2490. #define SNB_LATENCY(shift)      (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
  2491. #define SNB_READ_WM0_LATENCY()          SNB_LATENCY(SSKPD_WM0_SHIFT)
  2492. #define SNB_READ_WM1_LATENCY()          SNB_LATENCY(SSKPD_WM1_SHIFT)
  2493. #define SNB_READ_WM2_LATENCY()          SNB_LATENCY(SSKPD_WM2_SHIFT)
  2494. #define SNB_READ_WM3_LATENCY()          SNB_LATENCY(SSKPD_WM3_SHIFT)
  2495.  
  2496. /*
  2497.  * The two pipe frame counter registers are not synchronized, so
  2498.  * reading a stable value is somewhat tricky. The following code
  2499.  * should work:
  2500.  *
  2501.  *  do {
  2502.  *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  2503.  *             PIPE_FRAME_HIGH_SHIFT;
  2504.  *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
  2505.  *             PIPE_FRAME_LOW_SHIFT);
  2506.  *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
  2507.  *             PIPE_FRAME_HIGH_SHIFT);
  2508.  *  } while (high1 != high2);
  2509.  *  frame = (high1 << 8) | low1;
  2510.  */
  2511. #define _PIPEAFRAMEHIGH          0x70040
  2512. #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
  2513. #define   PIPE_FRAME_HIGH_SHIFT   0
  2514. #define _PIPEAFRAMEPIXEL         0x70044
  2515. #define   PIPE_FRAME_LOW_MASK     0xff000000
  2516. #define   PIPE_FRAME_LOW_SHIFT    24
  2517. #define   PIPE_PIXEL_MASK         0x00ffffff
  2518. #define   PIPE_PIXEL_SHIFT        0
  2519. /* GM45+ just has to be different */
  2520. #define _PIPEA_FRMCOUNT_GM45    0x70040
  2521. #define _PIPEA_FLIPCOUNT_GM45   0x70044
  2522. #define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
  2523.  
  2524. /* Cursor A & B regs */
  2525. #define _CURACNTR               0x70080
  2526. /* Old style CUR*CNTR flags (desktop 8xx) */
  2527. #define   CURSOR_ENABLE         0x80000000
  2528. #define   CURSOR_GAMMA_ENABLE   0x40000000
  2529. #define   CURSOR_STRIDE_MASK    0x30000000
  2530. #define   CURSOR_FORMAT_SHIFT   24
  2531. #define   CURSOR_FORMAT_MASK    (0x07 << CURSOR_FORMAT_SHIFT)
  2532. #define   CURSOR_FORMAT_2C      (0x00 << CURSOR_FORMAT_SHIFT)
  2533. #define   CURSOR_FORMAT_3C      (0x01 << CURSOR_FORMAT_SHIFT)
  2534. #define   CURSOR_FORMAT_4C      (0x02 << CURSOR_FORMAT_SHIFT)
  2535. #define   CURSOR_FORMAT_ARGB    (0x04 << CURSOR_FORMAT_SHIFT)
  2536. #define   CURSOR_FORMAT_XRGB    (0x05 << CURSOR_FORMAT_SHIFT)
  2537. /* New style CUR*CNTR flags */
  2538. #define   CURSOR_MODE           0x27
  2539. #define   CURSOR_MODE_DISABLE   0x00
  2540. #define   CURSOR_MODE_64_32B_AX 0x07
  2541. #define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
  2542. #define   MCURSOR_PIPE_SELECT   (1 << 28)
  2543. #define   MCURSOR_PIPE_A        0x00
  2544. #define   MCURSOR_PIPE_B        (1 << 28)
  2545. #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
  2546. #define _CURABASE               0x70084
  2547. #define _CURAPOS                        0x70088
  2548. #define   CURSOR_POS_MASK       0x007FF
  2549. #define   CURSOR_POS_SIGN       0x8000
  2550. #define   CURSOR_X_SHIFT        0
  2551. #define   CURSOR_Y_SHIFT        16
  2552. #define CURSIZE                 0x700a0
  2553. #define _CURBCNTR               0x700c0
  2554. #define _CURBBASE               0x700c4
  2555. #define _CURBPOS                        0x700c8
  2556.  
  2557. #define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
  2558. #define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
  2559. #define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
  2560.  
  2561. /* Display A control */
  2562. #define _DSPACNTR                0x70180
  2563. #define   DISPLAY_PLANE_ENABLE                  (1<<31)
  2564. #define   DISPLAY_PLANE_DISABLE                 0
  2565. #define   DISPPLANE_GAMMA_ENABLE                (1<<30)
  2566. #define   DISPPLANE_GAMMA_DISABLE               0
  2567. #define   DISPPLANE_PIXFORMAT_MASK              (0xf<<26)
  2568. #define   DISPPLANE_8BPP                        (0x2<<26)
  2569. #define   DISPPLANE_15_16BPP                    (0x4<<26)
  2570. #define   DISPPLANE_16BPP                       (0x5<<26)
  2571. #define   DISPPLANE_32BPP_NO_ALPHA              (0x6<<26)
  2572. #define   DISPPLANE_32BPP                       (0x7<<26)
  2573. #define   DISPPLANE_32BPP_30BIT_NO_ALPHA        (0xa<<26)
  2574. #define   DISPPLANE_STEREO_ENABLE               (1<<25)
  2575. #define   DISPPLANE_STEREO_DISABLE              0
  2576. #define   DISPPLANE_SEL_PIPE_SHIFT              24
  2577. #define   DISPPLANE_SEL_PIPE_MASK               (3<<DISPPLANE_SEL_PIPE_SHIFT)
  2578. #define   DISPPLANE_SEL_PIPE_A                  0
  2579. #define   DISPPLANE_SEL_PIPE_B                  (1<<DISPPLANE_SEL_PIPE_SHIFT)
  2580. #define   DISPPLANE_SRC_KEY_ENABLE              (1<<22)
  2581. #define   DISPPLANE_SRC_KEY_DISABLE             0
  2582. #define   DISPPLANE_LINE_DOUBLE                 (1<<20)
  2583. #define   DISPPLANE_NO_LINE_DOUBLE              0
  2584. #define   DISPPLANE_STEREO_POLARITY_FIRST       0
  2585. #define   DISPPLANE_STEREO_POLARITY_SECOND      (1<<18)
  2586. #define   DISPPLANE_TRICKLE_FEED_DISABLE        (1<<14) /* Ironlake */
  2587. #define   DISPPLANE_TILED                       (1<<10)
  2588. #define _DSPAADDR               0x70184
  2589. #define _DSPASTRIDE             0x70188
  2590. #define _DSPAPOS                        0x7018C /* reserved */
  2591. #define _DSPASIZE               0x70190
  2592. #define _DSPASURF               0x7019C /* 965+ only */
  2593. #define _DSPATILEOFF            0x701A4 /* 965+ only */
  2594.  
  2595. #define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
  2596. #define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
  2597. #define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
  2598. #define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
  2599. #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
  2600. #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
  2601. #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
  2602.  
  2603. /* VBIOS flags */
  2604. #define SWF00                   0x71410
  2605. #define SWF01                   0x71414
  2606. #define SWF02                   0x71418
  2607. #define SWF03                   0x7141c
  2608. #define SWF04                   0x71420
  2609. #define SWF05                   0x71424
  2610. #define SWF06                   0x71428
  2611. #define SWF10                   0x70410
  2612. #define SWF11                   0x70414
  2613. #define SWF14                   0x71420
  2614. #define SWF30                   0x72414
  2615. #define SWF31                   0x72418
  2616. #define SWF32                   0x7241c
  2617.  
  2618. /* Pipe B */
  2619. #define _PIPEBDSL               0x71000
  2620. #define _PIPEBCONF              0x71008
  2621. #define _PIPEBSTAT              0x71024
  2622. #define _PIPEBFRAMEHIGH         0x71040
  2623. #define _PIPEBFRAMEPIXEL                0x71044
  2624. #define _PIPEB_FRMCOUNT_GM45    0x71040
  2625. #define _PIPEB_FLIPCOUNT_GM45   0x71044
  2626.  
  2627.  
  2628. /* Display B control */
  2629. #define _DSPBCNTR               0x71180
  2630. #define   DISPPLANE_ALPHA_TRANS_ENABLE          (1<<15)
  2631. #define   DISPPLANE_ALPHA_TRANS_DISABLE         0
  2632. #define   DISPPLANE_SPRITE_ABOVE_DISPLAY        0
  2633. #define   DISPPLANE_SPRITE_ABOVE_OVERLAY        (1)
  2634. #define _DSPBADDR               0x71184
  2635. #define _DSPBSTRIDE             0x71188
  2636. #define _DSPBPOS                        0x7118C
  2637. #define _DSPBSIZE               0x71190
  2638. #define _DSPBSURF               0x7119C
  2639. #define _DSPBTILEOFF            0x711A4
  2640.  
  2641. /* VBIOS regs */
  2642. #define VGACNTRL                0x71400
  2643. # define VGA_DISP_DISABLE                       (1 << 31)
  2644. # define VGA_2X_MODE                            (1 << 30)
  2645. # define VGA_PIPE_B_SELECT                      (1 << 29)
  2646.  
  2647. /* Ironlake */
  2648.  
  2649. #define CPU_VGACNTRL    0x41000
  2650.  
  2651. #define DIGITAL_PORT_HOTPLUG_CNTRL      0x44030
  2652. #define  DIGITAL_PORTA_HOTPLUG_ENABLE           (1 << 4)
  2653. #define  DIGITAL_PORTA_SHORT_PULSE_2MS          (0 << 2)
  2654. #define  DIGITAL_PORTA_SHORT_PULSE_4_5MS        (1 << 2)
  2655. #define  DIGITAL_PORTA_SHORT_PULSE_6MS          (2 << 2)
  2656. #define  DIGITAL_PORTA_SHORT_PULSE_100MS        (3 << 2)
  2657. #define  DIGITAL_PORTA_NO_DETECT                (0 << 0)
  2658. #define  DIGITAL_PORTA_LONG_PULSE_DETECT_MASK   (1 << 1)
  2659. #define  DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK  (1 << 0)
  2660.  
  2661. /* refresh rate hardware control */
  2662. #define RR_HW_CTL       0x45300
  2663. #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
  2664. #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
  2665.  
  2666. #define FDI_PLL_BIOS_0  0x46000
  2667. #define  FDI_PLL_FB_CLOCK_MASK  0xff
  2668. #define FDI_PLL_BIOS_1  0x46004
  2669. #define FDI_PLL_BIOS_2  0x46008
  2670. #define DISPLAY_PORT_PLL_BIOS_0         0x4600c
  2671. #define DISPLAY_PORT_PLL_BIOS_1         0x46010
  2672. #define DISPLAY_PORT_PLL_BIOS_2         0x46014
  2673.  
  2674. #define PCH_DSPCLK_GATE_D       0x42020
  2675. # define DPFCUNIT_CLOCK_GATE_DISABLE            (1 << 9)
  2676. # define DPFCRUNIT_CLOCK_GATE_DISABLE           (1 << 8)
  2677. # define DPFDUNIT_CLOCK_GATE_DISABLE            (1 << 7)
  2678. # define DPARBUNIT_CLOCK_GATE_DISABLE           (1 << 5)
  2679.  
  2680. #define PCH_3DCGDIS0            0x46020
  2681. # define MARIUNIT_CLOCK_GATE_DISABLE            (1 << 18)
  2682. # define SVSMUNIT_CLOCK_GATE_DISABLE            (1 << 1)
  2683.  
  2684. #define PCH_3DCGDIS1            0x46024
  2685. # define VFMUNIT_CLOCK_GATE_DISABLE             (1 << 11)
  2686.  
  2687. #define FDI_PLL_FREQ_CTL        0x46030
  2688. #define  FDI_PLL_FREQ_CHANGE_REQUEST    (1<<24)
  2689. #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
  2690. #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
  2691.  
  2692.  
  2693. #define _PIPEA_DATA_M1           0x60030
  2694. #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
  2695. #define  TU_SIZE_MASK           0x7e000000
  2696. #define  PIPE_DATA_M1_OFFSET    0
  2697. #define _PIPEA_DATA_N1           0x60034
  2698. #define  PIPE_DATA_N1_OFFSET    0
  2699.  
  2700. #define _PIPEA_DATA_M2           0x60038
  2701. #define  PIPE_DATA_M2_OFFSET    0
  2702. #define _PIPEA_DATA_N2           0x6003c
  2703. #define  PIPE_DATA_N2_OFFSET    0
  2704.  
  2705. #define _PIPEA_LINK_M1           0x60040
  2706. #define  PIPE_LINK_M1_OFFSET    0
  2707. #define _PIPEA_LINK_N1           0x60044
  2708. #define  PIPE_LINK_N1_OFFSET    0
  2709.  
  2710. #define _PIPEA_LINK_M2           0x60048
  2711. #define  PIPE_LINK_M2_OFFSET    0
  2712. #define _PIPEA_LINK_N2           0x6004c
  2713. #define  PIPE_LINK_N2_OFFSET    0
  2714.  
  2715. /* PIPEB timing regs are same start from 0x61000 */
  2716.  
  2717. #define _PIPEB_DATA_M1           0x61030
  2718. #define _PIPEB_DATA_N1           0x61034
  2719.  
  2720. #define _PIPEB_DATA_M2           0x61038
  2721. #define _PIPEB_DATA_N2           0x6103c
  2722.  
  2723. #define _PIPEB_LINK_M1           0x61040
  2724. #define _PIPEB_LINK_N1           0x61044
  2725.  
  2726. #define _PIPEB_LINK_M2           0x61048
  2727. #define _PIPEB_LINK_N2           0x6104c
  2728.  
  2729. #define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
  2730. #define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
  2731. #define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
  2732. #define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
  2733. #define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
  2734. #define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
  2735. #define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
  2736. #define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
  2737.  
  2738. /* CPU panel fitter */
  2739. /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
  2740. #define _PFA_CTL_1               0x68080
  2741. #define _PFB_CTL_1               0x68880
  2742. #define  PF_ENABLE              (1<<31)
  2743. #define  PF_FILTER_MASK         (3<<23)
  2744. #define  PF_FILTER_PROGRAMMED   (0<<23)
  2745. #define  PF_FILTER_MED_3x3      (1<<23)
  2746. #define  PF_FILTER_EDGE_ENHANCE (2<<23)
  2747. #define  PF_FILTER_EDGE_SOFTEN  (3<<23)
  2748. #define _PFA_WIN_SZ             0x68074
  2749. #define _PFB_WIN_SZ             0x68874
  2750. #define _PFA_WIN_POS            0x68070
  2751. #define _PFB_WIN_POS            0x68870
  2752. #define _PFA_VSCALE             0x68084
  2753. #define _PFB_VSCALE             0x68884
  2754. #define _PFA_HSCALE             0x68090
  2755. #define _PFB_HSCALE             0x68890
  2756.  
  2757. #define PF_CTL(pipe)            _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
  2758. #define PF_WIN_SZ(pipe)         _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
  2759. #define PF_WIN_POS(pipe)        _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
  2760. #define PF_VSCALE(pipe)         _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
  2761. #define PF_HSCALE(pipe)         _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
  2762.  
  2763. /* legacy palette */
  2764. #define _LGC_PALETTE_A           0x4a000
  2765. #define _LGC_PALETTE_B           0x4a800
  2766. #define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
  2767.  
  2768. /* interrupts */
  2769. #define DE_MASTER_IRQ_CONTROL   (1 << 31)
  2770. #define DE_SPRITEB_FLIP_DONE    (1 << 29)
  2771. #define DE_SPRITEA_FLIP_DONE    (1 << 28)
  2772. #define DE_PLANEB_FLIP_DONE     (1 << 27)
  2773. #define DE_PLANEA_FLIP_DONE     (1 << 26)
  2774. #define DE_PCU_EVENT            (1 << 25)
  2775. #define DE_GTT_FAULT            (1 << 24)
  2776. #define DE_POISON               (1 << 23)
  2777. #define DE_PERFORM_COUNTER      (1 << 22)
  2778. #define DE_PCH_EVENT            (1 << 21)
  2779. #define DE_AUX_CHANNEL_A        (1 << 20)
  2780. #define DE_DP_A_HOTPLUG         (1 << 19)
  2781. #define DE_GSE                  (1 << 18)
  2782. #define DE_PIPEB_VBLANK         (1 << 15)
  2783. #define DE_PIPEB_EVEN_FIELD     (1 << 14)
  2784. #define DE_PIPEB_ODD_FIELD      (1 << 13)
  2785. #define DE_PIPEB_LINE_COMPARE   (1 << 12)
  2786. #define DE_PIPEB_VSYNC          (1 << 11)
  2787. #define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
  2788. #define DE_PIPEA_VBLANK         (1 << 7)
  2789. #define DE_PIPEA_EVEN_FIELD     (1 << 6)
  2790. #define DE_PIPEA_ODD_FIELD      (1 << 5)
  2791. #define DE_PIPEA_LINE_COMPARE   (1 << 4)
  2792. #define DE_PIPEA_VSYNC          (1 << 3)
  2793. #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
  2794.  
  2795. /* More Ivybridge lolz */
  2796. #define DE_ERR_DEBUG_IVB                (1<<30)
  2797. #define DE_GSE_IVB                      (1<<29)
  2798. #define DE_PCH_EVENT_IVB                (1<<28)
  2799. #define DE_DP_A_HOTPLUG_IVB             (1<<27)
  2800. #define DE_AUX_CHANNEL_A_IVB            (1<<26)
  2801. #define DE_SPRITEB_FLIP_DONE_IVB        (1<<9)
  2802. #define DE_SPRITEA_FLIP_DONE_IVB        (1<<4)
  2803. #define DE_PLANEB_FLIP_DONE_IVB         (1<<8)
  2804. #define DE_PLANEA_FLIP_DONE_IVB         (1<<3)
  2805. #define DE_PIPEB_VBLANK_IVB             (1<<5)
  2806. #define DE_PIPEA_VBLANK_IVB             (1<<0)
  2807.  
  2808. #define DEISR   0x44000
  2809. #define DEIMR   0x44004
  2810. #define DEIIR   0x44008
  2811. #define DEIER   0x4400c
  2812.  
  2813. /* GT interrupt */
  2814. #define GT_PIPE_NOTIFY          (1 << 4)
  2815. #define GT_SYNC_STATUS          (1 << 2)
  2816. #define GT_USER_INTERRUPT       (1 << 0)
  2817. #define GT_BSD_USER_INTERRUPT   (1 << 5)
  2818. #define GT_GEN6_BSD_USER_INTERRUPT      (1 << 12)
  2819. #define GT_BLT_USER_INTERRUPT   (1 << 22)
  2820.  
  2821. #define GTISR   0x44010
  2822. #define GTIMR   0x44014
  2823. #define GTIIR   0x44018
  2824. #define GTIER   0x4401c
  2825.  
  2826. #define ILK_DISPLAY_CHICKEN2    0x42004
  2827. /* Required on all Ironlake and Sandybridge according to the B-Spec. */
  2828. #define  ILK_ELPIN_409_SELECT   (1 << 25)
  2829. #define  ILK_DPARB_GATE (1<<22)
  2830. #define  ILK_VSDPFD_FULL        (1<<21)
  2831. #define ILK_DISPLAY_CHICKEN_FUSES       0x42014
  2832. #define  ILK_INTERNAL_GRAPHICS_DISABLE  (1<<31)
  2833. #define  ILK_INTERNAL_DISPLAY_DISABLE   (1<<30)
  2834. #define  ILK_DISPLAY_DEBUG_DISABLE      (1<<29)
  2835. #define  ILK_HDCP_DISABLE               (1<<25)
  2836. #define  ILK_eDP_A_DISABLE              (1<<24)
  2837. #define  ILK_DESKTOP                    (1<<23)
  2838. #define ILK_DSPCLK_GATE         0x42020
  2839. #define  IVB_VRHUNIT_CLK_GATE   (1<<28)
  2840. #define  ILK_DPARB_CLK_GATE     (1<<5)
  2841. #define  ILK_DPFD_CLK_GATE      (1<<7)
  2842.  
  2843. /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
  2844. #define   ILK_CLK_FBC           (1<<7)
  2845. #define   ILK_DPFC_DIS1         (1<<8)
  2846. #define   ILK_DPFC_DIS2         (1<<9)
  2847.  
  2848. #define DISP_ARB_CTL    0x45000
  2849. #define  DISP_TILE_SURFACE_SWIZZLING    (1<<13)
  2850. #define  DISP_FBC_WM_DIS                (1<<15)
  2851.  
  2852. /* PCH */
  2853.  
  2854. /* south display engine interrupt */
  2855. #define SDE_AUDIO_POWER_D       (1 << 27)
  2856. #define SDE_AUDIO_POWER_C       (1 << 26)
  2857. #define SDE_AUDIO_POWER_B       (1 << 25)
  2858. #define SDE_AUDIO_POWER_SHIFT   (25)
  2859. #define SDE_AUDIO_POWER_MASK    (7 << SDE_AUDIO_POWER_SHIFT)
  2860. #define SDE_GMBUS               (1 << 24)
  2861. #define SDE_AUDIO_HDCP_TRANSB   (1 << 23)
  2862. #define SDE_AUDIO_HDCP_TRANSA   (1 << 22)
  2863. #define SDE_AUDIO_HDCP_MASK     (3 << 22)
  2864. #define SDE_AUDIO_TRANSB        (1 << 21)
  2865. #define SDE_AUDIO_TRANSA        (1 << 20)
  2866. #define SDE_AUDIO_TRANS_MASK    (3 << 20)
  2867. #define SDE_POISON              (1 << 19)
  2868. /* 18 reserved */
  2869. #define SDE_FDI_RXB             (1 << 17)
  2870. #define SDE_FDI_RXA             (1 << 16)
  2871. #define SDE_FDI_MASK            (3 << 16)
  2872. #define SDE_AUXD                (1 << 15)
  2873. #define SDE_AUXC                (1 << 14)
  2874. #define SDE_AUXB                (1 << 13)
  2875. #define SDE_AUX_MASK            (7 << 13)
  2876. /* 12 reserved */
  2877. #define SDE_CRT_HOTPLUG         (1 << 11)
  2878. #define SDE_PORTD_HOTPLUG       (1 << 10)
  2879. #define SDE_PORTC_HOTPLUG       (1 << 9)
  2880. #define SDE_PORTB_HOTPLUG       (1 << 8)
  2881. #define SDE_SDVOB_HOTPLUG       (1 << 6)
  2882. #define SDE_HOTPLUG_MASK        (0xf << 8)
  2883. #define SDE_TRANSB_CRC_DONE     (1 << 5)
  2884. #define SDE_TRANSB_CRC_ERR      (1 << 4)
  2885. #define SDE_TRANSB_FIFO_UNDER   (1 << 3)
  2886. #define SDE_TRANSA_CRC_DONE     (1 << 2)
  2887. #define SDE_TRANSA_CRC_ERR      (1 << 1)
  2888. #define SDE_TRANSA_FIFO_UNDER   (1 << 0)
  2889. #define SDE_TRANS_MASK          (0x3f)
  2890. /* CPT */
  2891. #define SDE_CRT_HOTPLUG_CPT     (1 << 19)
  2892. #define SDE_PORTD_HOTPLUG_CPT   (1 << 23)
  2893. #define SDE_PORTC_HOTPLUG_CPT   (1 << 22)
  2894. #define SDE_PORTB_HOTPLUG_CPT   (1 << 21)
  2895. #define SDE_HOTPLUG_MASK_CPT    (SDE_CRT_HOTPLUG_CPT |          \
  2896.                                  SDE_PORTD_HOTPLUG_CPT |        \
  2897.                                  SDE_PORTC_HOTPLUG_CPT |        \
  2898.                                  SDE_PORTB_HOTPLUG_CPT)
  2899.  
  2900. #define SDEISR  0xc4000
  2901. #define SDEIMR  0xc4004
  2902. #define SDEIIR  0xc4008
  2903. #define SDEIER  0xc400c
  2904.  
  2905. /* digital port hotplug */
  2906. #define PCH_PORT_HOTPLUG        0xc4030
  2907. #define PORTD_HOTPLUG_ENABLE            (1 << 20)
  2908. #define PORTD_PULSE_DURATION_2ms        (0)
  2909. #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
  2910. #define PORTD_PULSE_DURATION_6ms        (2 << 18)
  2911. #define PORTD_PULSE_DURATION_100ms      (3 << 18)
  2912. #define PORTD_HOTPLUG_NO_DETECT         (0)
  2913. #define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
  2914. #define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
  2915. #define PORTC_HOTPLUG_ENABLE            (1 << 12)
  2916. #define PORTC_PULSE_DURATION_2ms        (0)
  2917. #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
  2918. #define PORTC_PULSE_DURATION_6ms        (2 << 10)
  2919. #define PORTC_PULSE_DURATION_100ms      (3 << 10)
  2920. #define PORTC_HOTPLUG_NO_DETECT         (0)
  2921. #define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
  2922. #define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
  2923. #define PORTB_HOTPLUG_ENABLE            (1 << 4)
  2924. #define PORTB_PULSE_DURATION_2ms        (0)
  2925. #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
  2926. #define PORTB_PULSE_DURATION_6ms        (2 << 2)
  2927. #define PORTB_PULSE_DURATION_100ms      (3 << 2)
  2928. #define PORTB_HOTPLUG_NO_DETECT         (0)
  2929. #define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
  2930. #define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
  2931.  
  2932. #define PCH_GPIOA               0xc5010
  2933. #define PCH_GPIOB               0xc5014
  2934. #define PCH_GPIOC               0xc5018
  2935. #define PCH_GPIOD               0xc501c
  2936. #define PCH_GPIOE               0xc5020
  2937. #define PCH_GPIOF               0xc5024
  2938.  
  2939. #define PCH_GMBUS0              0xc5100
  2940. #define PCH_GMBUS1              0xc5104
  2941. #define PCH_GMBUS2              0xc5108
  2942. #define PCH_GMBUS3              0xc510c
  2943. #define PCH_GMBUS4              0xc5110
  2944. #define PCH_GMBUS5              0xc5120
  2945.  
  2946. #define _PCH_DPLL_A              0xc6014
  2947. #define _PCH_DPLL_B              0xc6018
  2948. #define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
  2949.  
  2950. #define _PCH_FPA0                0xc6040
  2951. #define  FP_CB_TUNE             (0x3<<22)
  2952. #define _PCH_FPA1                0xc6044
  2953. #define _PCH_FPB0                0xc6048
  2954. #define _PCH_FPB1                0xc604c
  2955. #define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
  2956. #define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
  2957.  
  2958. #define PCH_DPLL_TEST           0xc606c
  2959.  
  2960. #define PCH_DREF_CONTROL        0xC6200
  2961. #define  DREF_CONTROL_MASK      0x7fc3
  2962. #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
  2963. #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
  2964. #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
  2965. #define  DREF_CPU_SOURCE_OUTPUT_MASK            (3<<13)
  2966. #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
  2967. #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
  2968. #define  DREF_SSC_SOURCE_MASK                   (3<<11)
  2969. #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
  2970. #define  DREF_NONSPREAD_CK505_ENABLE            (1<<9)
  2971. #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
  2972. #define  DREF_NONSPREAD_SOURCE_MASK             (3<<9)
  2973. #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
  2974. #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
  2975. #define  DREF_SUPERSPREAD_SOURCE_MASK           (3<<7)
  2976. #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
  2977. #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
  2978. #define  DREF_SSC1_DISABLE                      (0<<1)
  2979. #define  DREF_SSC1_ENABLE                       (1<<1)
  2980. #define  DREF_SSC4_DISABLE                      (0)
  2981. #define  DREF_SSC4_ENABLE                       (1)
  2982.  
  2983. #define PCH_RAWCLK_FREQ         0xc6204
  2984. #define  FDL_TP1_TIMER_SHIFT    12
  2985. #define  FDL_TP1_TIMER_MASK     (3<<12)
  2986. #define  FDL_TP2_TIMER_SHIFT    10
  2987. #define  FDL_TP2_TIMER_MASK     (3<<10)
  2988. #define  RAWCLK_FREQ_MASK       0x3ff
  2989.  
  2990. #define PCH_DPLL_TMR_CFG        0xc6208
  2991.  
  2992. #define PCH_SSC4_PARMS          0xc6210
  2993. #define PCH_SSC4_AUX_PARMS      0xc6214
  2994.  
  2995. #define PCH_DPLL_SEL            0xc7000
  2996. #define  TRANSA_DPLL_ENABLE     (1<<3)
  2997. #define  TRANSA_DPLLB_SEL       (1<<0)
  2998. #define  TRANSA_DPLLA_SEL       0
  2999. #define  TRANSB_DPLL_ENABLE     (1<<7)
  3000. #define  TRANSB_DPLLB_SEL       (1<<4)
  3001. #define  TRANSB_DPLLA_SEL       (0)
  3002. #define  TRANSC_DPLL_ENABLE     (1<<11)
  3003. #define  TRANSC_DPLLB_SEL       (1<<8)
  3004. #define  TRANSC_DPLLA_SEL       (0)
  3005.  
  3006. /* transcoder */
  3007.  
  3008. #define _TRANS_HTOTAL_A          0xe0000
  3009. #define  TRANS_HTOTAL_SHIFT     16
  3010. #define  TRANS_HACTIVE_SHIFT    0
  3011. #define _TRANS_HBLANK_A          0xe0004
  3012. #define  TRANS_HBLANK_END_SHIFT 16
  3013. #define  TRANS_HBLANK_START_SHIFT 0
  3014. #define _TRANS_HSYNC_A           0xe0008
  3015. #define  TRANS_HSYNC_END_SHIFT  16
  3016. #define  TRANS_HSYNC_START_SHIFT 0
  3017. #define _TRANS_VTOTAL_A          0xe000c
  3018. #define  TRANS_VTOTAL_SHIFT     16
  3019. #define  TRANS_VACTIVE_SHIFT    0
  3020. #define _TRANS_VBLANK_A          0xe0010
  3021. #define  TRANS_VBLANK_END_SHIFT 16
  3022. #define  TRANS_VBLANK_START_SHIFT 0
  3023. #define _TRANS_VSYNC_A           0xe0014
  3024. #define  TRANS_VSYNC_END_SHIFT  16
  3025. #define  TRANS_VSYNC_START_SHIFT 0
  3026.  
  3027. #define _TRANSA_DATA_M1          0xe0030
  3028. #define _TRANSA_DATA_N1          0xe0034
  3029. #define _TRANSA_DATA_M2          0xe0038
  3030. #define _TRANSA_DATA_N2          0xe003c
  3031. #define _TRANSA_DP_LINK_M1       0xe0040
  3032. #define _TRANSA_DP_LINK_N1       0xe0044
  3033. #define _TRANSA_DP_LINK_M2       0xe0048
  3034. #define _TRANSA_DP_LINK_N2       0xe004c
  3035.  
  3036. /* Per-transcoder DIP controls */
  3037.  
  3038. #define _VIDEO_DIP_CTL_A         0xe0200
  3039. #define _VIDEO_DIP_DATA_A        0xe0208
  3040. #define _VIDEO_DIP_GCP_A         0xe0210
  3041.  
  3042. #define _VIDEO_DIP_CTL_B         0xe1200
  3043. #define _VIDEO_DIP_DATA_B        0xe1208
  3044. #define _VIDEO_DIP_GCP_B         0xe1210
  3045.  
  3046. #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
  3047. #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
  3048. #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
  3049.  
  3050. #define _TRANS_HTOTAL_B          0xe1000
  3051. #define _TRANS_HBLANK_B          0xe1004
  3052. #define _TRANS_HSYNC_B           0xe1008
  3053. #define _TRANS_VTOTAL_B          0xe100c
  3054. #define _TRANS_VBLANK_B          0xe1010
  3055. #define _TRANS_VSYNC_B           0xe1014
  3056.  
  3057. #define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
  3058. #define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
  3059. #define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
  3060. #define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
  3061. #define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
  3062. #define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
  3063.  
  3064. #define _TRANSB_DATA_M1          0xe1030
  3065. #define _TRANSB_DATA_N1          0xe1034
  3066. #define _TRANSB_DATA_M2          0xe1038
  3067. #define _TRANSB_DATA_N2          0xe103c
  3068. #define _TRANSB_DP_LINK_M1       0xe1040
  3069. #define _TRANSB_DP_LINK_N1       0xe1044
  3070. #define _TRANSB_DP_LINK_M2       0xe1048
  3071. #define _TRANSB_DP_LINK_N2       0xe104c
  3072.  
  3073. #define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
  3074. #define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
  3075. #define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
  3076. #define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
  3077. #define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
  3078. #define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
  3079. #define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
  3080. #define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
  3081.  
  3082. #define _TRANSACONF              0xf0008
  3083. #define _TRANSBCONF              0xf1008
  3084. #define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
  3085. #define  TRANS_DISABLE          (0<<31)
  3086. #define  TRANS_ENABLE           (1<<31)
  3087. #define  TRANS_STATE_MASK       (1<<30)
  3088. #define  TRANS_STATE_DISABLE    (0<<30)
  3089. #define  TRANS_STATE_ENABLE     (1<<30)
  3090. #define  TRANS_FSYNC_DELAY_HB1  (0<<27)
  3091. #define  TRANS_FSYNC_DELAY_HB2  (1<<27)
  3092. #define  TRANS_FSYNC_DELAY_HB3  (2<<27)
  3093. #define  TRANS_FSYNC_DELAY_HB4  (3<<27)
  3094. #define  TRANS_DP_AUDIO_ONLY    (1<<26)
  3095. #define  TRANS_DP_VIDEO_AUDIO   (0<<26)
  3096. #define  TRANS_PROGRESSIVE      (0<<21)
  3097. #define  TRANS_8BPC             (0<<5)
  3098. #define  TRANS_10BPC            (1<<5)
  3099. #define  TRANS_6BPC             (2<<5)
  3100. #define  TRANS_12BPC            (3<<5)
  3101.  
  3102. #define _TRANSA_CHICKEN2         0xf0064
  3103. #define _TRANSB_CHICKEN2         0xf1064
  3104. #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
  3105. #define   TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
  3106.  
  3107. #define SOUTH_CHICKEN1          0xc2000
  3108. #define  FDIA_PHASE_SYNC_SHIFT_OVR      19
  3109. #define  FDIA_PHASE_SYNC_SHIFT_EN       18
  3110. #define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
  3111. #define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
  3112. #define SOUTH_CHICKEN2          0xc2004
  3113. #define  DPLS_EDP_PPS_FIX_DIS   (1<<0)
  3114.  
  3115. #define _FDI_RXA_CHICKEN         0xc200c
  3116. #define _FDI_RXB_CHICKEN         0xc2010
  3117. #define  FDI_RX_PHASE_SYNC_POINTER_OVR  (1<<1)
  3118. #define  FDI_RX_PHASE_SYNC_POINTER_EN   (1<<0)
  3119. #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
  3120.  
  3121. #define SOUTH_DSPCLK_GATE_D     0xc2020
  3122. #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
  3123.  
  3124. /* CPU: FDI_TX */
  3125. #define _FDI_TXA_CTL             0x60100
  3126. #define _FDI_TXB_CTL             0x61100
  3127. #define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
  3128. #define  FDI_TX_DISABLE         (0<<31)
  3129. #define  FDI_TX_ENABLE          (1<<31)
  3130. #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
  3131. #define  FDI_LINK_TRAIN_PATTERN_2       (1<<28)
  3132. #define  FDI_LINK_TRAIN_PATTERN_IDLE    (2<<28)
  3133. #define  FDI_LINK_TRAIN_NONE            (3<<28)
  3134. #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0<<25)
  3135. #define  FDI_LINK_TRAIN_VOLTAGE_0_6V    (1<<25)
  3136. #define  FDI_LINK_TRAIN_VOLTAGE_0_8V    (2<<25)
  3137. #define  FDI_LINK_TRAIN_VOLTAGE_1_2V    (3<<25)
  3138. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
  3139. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
  3140. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_2X   (2<<22)
  3141. #define  FDI_LINK_TRAIN_PRE_EMPHASIS_3X   (3<<22)
  3142. /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
  3143.    SNB has different settings. */
  3144. /* SNB A-stepping */
  3145. #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
  3146. #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
  3147. #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
  3148. #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
  3149. /* SNB B-stepping */
  3150. #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B         (0x0<<22)
  3151. #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B         (0x3a<<22)
  3152. #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B       (0x39<<22)
  3153. #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B         (0x38<<22)
  3154. #define  FDI_LINK_TRAIN_VOL_EMP_MASK            (0x3f<<22)
  3155. #define  FDI_DP_PORT_WIDTH_X1           (0<<19)
  3156. #define  FDI_DP_PORT_WIDTH_X2           (1<<19)
  3157. #define  FDI_DP_PORT_WIDTH_X3           (2<<19)
  3158. #define  FDI_DP_PORT_WIDTH_X4           (3<<19)
  3159. #define  FDI_TX_ENHANCE_FRAME_ENABLE    (1<<18)
  3160. /* Ironlake: hardwired to 1 */
  3161. #define  FDI_TX_PLL_ENABLE              (1<<14)
  3162.  
  3163. /* Ivybridge has different bits for lolz */
  3164. #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0<<8)
  3165. #define  FDI_LINK_TRAIN_PATTERN_2_IVB       (1<<8)
  3166. #define  FDI_LINK_TRAIN_PATTERN_IDLE_IVB    (2<<8)
  3167. #define  FDI_LINK_TRAIN_NONE_IVB            (3<<8)
  3168.  
  3169. /* both Tx and Rx */
  3170. #define  FDI_LINK_TRAIN_AUTO            (1<<10)
  3171. #define  FDI_SCRAMBLING_ENABLE          (0<<7)
  3172. #define  FDI_SCRAMBLING_DISABLE         (1<<7)
  3173.  
  3174. /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
  3175. #define _FDI_RXA_CTL             0xf000c
  3176. #define _FDI_RXB_CTL             0xf100c
  3177. #define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
  3178. #define  FDI_RX_ENABLE          (1<<31)
  3179. /* train, dp width same as FDI_TX */
  3180. #define  FDI_FS_ERRC_ENABLE             (1<<27)
  3181. #define  FDI_FE_ERRC_ENABLE             (1<<26)
  3182. #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
  3183. #define  FDI_8BPC                       (0<<16)
  3184. #define  FDI_10BPC                      (1<<16)
  3185. #define  FDI_6BPC                       (2<<16)
  3186. #define  FDI_12BPC                      (3<<16)
  3187. #define  FDI_LINK_REVERSE_OVERWRITE     (1<<15)
  3188. #define  FDI_DMI_LINK_REVERSE_MASK      (1<<14)
  3189. #define  FDI_RX_PLL_ENABLE              (1<<13)
  3190. #define  FDI_FS_ERR_CORRECT_ENABLE      (1<<11)
  3191. #define  FDI_FE_ERR_CORRECT_ENABLE      (1<<10)
  3192. #define  FDI_FS_ERR_REPORT_ENABLE       (1<<9)
  3193. #define  FDI_FE_ERR_REPORT_ENABLE       (1<<8)
  3194. #define  FDI_RX_ENHANCE_FRAME_ENABLE    (1<<6)
  3195. #define  FDI_PCDCLK                     (1<<4)
  3196. /* CPT */
  3197. #define  FDI_AUTO_TRAINING                      (1<<10)
  3198. #define  FDI_LINK_TRAIN_PATTERN_1_CPT           (0<<8)
  3199. #define  FDI_LINK_TRAIN_PATTERN_2_CPT           (1<<8)
  3200. #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT        (2<<8)
  3201. #define  FDI_LINK_TRAIN_NORMAL_CPT              (3<<8)
  3202. #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT        (3<<8)
  3203.  
  3204. #define _FDI_RXA_MISC            0xf0010
  3205. #define _FDI_RXB_MISC            0xf1010
  3206. #define _FDI_RXA_TUSIZE1         0xf0030
  3207. #define _FDI_RXA_TUSIZE2         0xf0038
  3208. #define _FDI_RXB_TUSIZE1         0xf1030
  3209. #define _FDI_RXB_TUSIZE2         0xf1038
  3210. #define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
  3211. #define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
  3212. #define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
  3213.  
  3214. /* FDI_RX interrupt register format */
  3215. #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
  3216. #define FDI_RX_SYMBOL_LOCK              (1<<9) /* train 2 */
  3217. #define FDI_RX_BIT_LOCK                 (1<<8) /* train 1 */
  3218. #define FDI_RX_TRAIN_PATTERN_2_FAIL     (1<<7)
  3219. #define FDI_RX_FS_CODE_ERR              (1<<6)
  3220. #define FDI_RX_FE_CODE_ERR              (1<<5)
  3221. #define FDI_RX_SYMBOL_ERR_RATE_ABOVE    (1<<4)
  3222. #define FDI_RX_HDCP_LINK_FAIL           (1<<3)
  3223. #define FDI_RX_PIXEL_FIFO_OVERFLOW      (1<<2)
  3224. #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
  3225. #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
  3226.  
  3227. #define _FDI_RXA_IIR             0xf0014
  3228. #define _FDI_RXA_IMR             0xf0018
  3229. #define _FDI_RXB_IIR             0xf1014
  3230. #define _FDI_RXB_IMR             0xf1018
  3231. #define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
  3232. #define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
  3233.  
  3234. #define FDI_PLL_CTL_1           0xfe000
  3235. #define FDI_PLL_CTL_2           0xfe004
  3236.  
  3237. /* CRT */
  3238. #define PCH_ADPA                0xe1100
  3239. #define  ADPA_TRANS_SELECT_MASK (1<<30)
  3240. #define  ADPA_TRANS_A_SELECT    0
  3241. #define  ADPA_TRANS_B_SELECT    (1<<30)
  3242. #define  ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
  3243. #define  ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
  3244. #define  ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
  3245. #define  ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
  3246. #define  ADPA_CRT_HOTPLUG_MONITOR_MONO  (2<<24)
  3247. #define  ADPA_CRT_HOTPLUG_ENABLE        (1<<23)
  3248. #define  ADPA_CRT_HOTPLUG_PERIOD_64     (0<<22)
  3249. #define  ADPA_CRT_HOTPLUG_PERIOD_128    (1<<22)
  3250. #define  ADPA_CRT_HOTPLUG_WARMUP_5MS    (0<<21)
  3251. #define  ADPA_CRT_HOTPLUG_WARMUP_10MS   (1<<21)
  3252. #define  ADPA_CRT_HOTPLUG_SAMPLE_2S     (0<<20)
  3253. #define  ADPA_CRT_HOTPLUG_SAMPLE_4S     (1<<20)
  3254. #define  ADPA_CRT_HOTPLUG_VOLTAGE_40    (0<<18)
  3255. #define  ADPA_CRT_HOTPLUG_VOLTAGE_50    (1<<18)
  3256. #define  ADPA_CRT_HOTPLUG_VOLTAGE_60    (2<<18)
  3257. #define  ADPA_CRT_HOTPLUG_VOLTAGE_70    (3<<18)
  3258. #define  ADPA_CRT_HOTPLUG_VOLREF_325MV  (0<<17)
  3259. #define  ADPA_CRT_HOTPLUG_VOLREF_475MV  (1<<17)
  3260. #define  ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
  3261.  
  3262. /* or SDVOB */
  3263. #define HDMIB   0xe1140
  3264. #define  PORT_ENABLE    (1 << 31)
  3265. #define  TRANSCODER_A   (0)
  3266. #define  TRANSCODER_B   (1 << 30)
  3267. #define  TRANSCODER(pipe)       ((pipe) << 30)
  3268. #define  TRANSCODER_MASK   (1 << 30)
  3269. #define  COLOR_FORMAT_8bpc      (0)
  3270. #define  COLOR_FORMAT_12bpc     (3 << 26)
  3271. #define  SDVOB_HOTPLUG_ENABLE   (1 << 23)
  3272. #define  SDVO_ENCODING          (0)
  3273. #define  TMDS_ENCODING          (2 << 10)
  3274. #define  NULL_PACKET_VSYNC_ENABLE       (1 << 9)
  3275. /* CPT */
  3276. #define  HDMI_MODE_SELECT       (1 << 9)
  3277. #define  DVI_MODE_SELECT        (0)
  3278. #define  SDVOB_BORDER_ENABLE    (1 << 7)
  3279. #define  AUDIO_ENABLE           (1 << 6)
  3280. #define  VSYNC_ACTIVE_HIGH      (1 << 4)
  3281. #define  HSYNC_ACTIVE_HIGH      (1 << 3)
  3282. #define  PORT_DETECTED          (1 << 2)
  3283.  
  3284. /* PCH SDVOB multiplex with HDMIB */
  3285. #define PCH_SDVOB       HDMIB
  3286.  
  3287. #define HDMIC   0xe1150
  3288. #define HDMID   0xe1160
  3289.  
  3290. #define PCH_LVDS        0xe1180
  3291. #define  LVDS_DETECTED  (1 << 1)
  3292.  
  3293. #define BLC_PWM_CPU_CTL2        0x48250
  3294. #define  PWM_ENABLE             (1 << 31)
  3295. #define  PWM_PIPE_A             (0 << 29)
  3296. #define  PWM_PIPE_B             (1 << 29)
  3297. #define BLC_PWM_CPU_CTL         0x48254
  3298.  
  3299. #define BLC_PWM_PCH_CTL1        0xc8250
  3300. #define  PWM_PCH_ENABLE         (1 << 31)
  3301. #define  PWM_POLARITY_ACTIVE_LOW        (1 << 29)
  3302. #define  PWM_POLARITY_ACTIVE_HIGH       (0 << 29)
  3303. #define  PWM_POLARITY_ACTIVE_LOW2       (1 << 28)
  3304. #define  PWM_POLARITY_ACTIVE_HIGH2      (0 << 28)
  3305.  
  3306. #define BLC_PWM_PCH_CTL2        0xc8254
  3307.  
  3308. #define PCH_PP_STATUS           0xc7200
  3309. #define PCH_PP_CONTROL          0xc7204
  3310. #define  PANEL_UNLOCK_REGS      (0xabcd << 16)
  3311. #define  EDP_FORCE_VDD          (1 << 3)
  3312. #define  EDP_BLC_ENABLE         (1 << 2)
  3313. #define  PANEL_POWER_RESET      (1 << 1)
  3314. #define  PANEL_POWER_OFF        (0 << 0)
  3315. #define  PANEL_POWER_ON         (1 << 0)
  3316. #define PCH_PP_ON_DELAYS        0xc7208
  3317. #define  EDP_PANEL              (1 << 30)
  3318. #define PCH_PP_OFF_DELAYS       0xc720c
  3319. #define PCH_PP_DIVISOR          0xc7210
  3320.  
  3321. #define PCH_DP_B                0xe4100
  3322. #define PCH_DPB_AUX_CH_CTL      0xe4110
  3323. #define PCH_DPB_AUX_CH_DATA1    0xe4114
  3324. #define PCH_DPB_AUX_CH_DATA2    0xe4118
  3325. #define PCH_DPB_AUX_CH_DATA3    0xe411c
  3326. #define PCH_DPB_AUX_CH_DATA4    0xe4120
  3327. #define PCH_DPB_AUX_CH_DATA5    0xe4124
  3328.  
  3329. #define PCH_DP_C                0xe4200
  3330. #define PCH_DPC_AUX_CH_CTL      0xe4210
  3331. #define PCH_DPC_AUX_CH_DATA1    0xe4214
  3332. #define PCH_DPC_AUX_CH_DATA2    0xe4218
  3333. #define PCH_DPC_AUX_CH_DATA3    0xe421c
  3334. #define PCH_DPC_AUX_CH_DATA4    0xe4220
  3335. #define PCH_DPC_AUX_CH_DATA5    0xe4224
  3336.  
  3337. #define PCH_DP_D                0xe4300
  3338. #define PCH_DPD_AUX_CH_CTL      0xe4310
  3339. #define PCH_DPD_AUX_CH_DATA1    0xe4314
  3340. #define PCH_DPD_AUX_CH_DATA2    0xe4318
  3341. #define PCH_DPD_AUX_CH_DATA3    0xe431c
  3342. #define PCH_DPD_AUX_CH_DATA4    0xe4320
  3343. #define PCH_DPD_AUX_CH_DATA5    0xe4324
  3344.  
  3345. /* CPT */
  3346. #define  PORT_TRANS_A_SEL_CPT   0
  3347. #define  PORT_TRANS_B_SEL_CPT   (1<<29)
  3348. #define  PORT_TRANS_C_SEL_CPT   (2<<29)
  3349. #define  PORT_TRANS_SEL_MASK    (3<<29)
  3350. #define  PORT_TRANS_SEL_CPT(pipe)       ((pipe) << 29)
  3351.  
  3352. #define TRANS_DP_CTL_A          0xe0300
  3353. #define TRANS_DP_CTL_B          0xe1300
  3354. #define TRANS_DP_CTL_C          0xe2300
  3355. #define TRANS_DP_CTL(pipe)      (TRANS_DP_CTL_A + (pipe) * 0x01000)
  3356. #define  TRANS_DP_OUTPUT_ENABLE (1<<31)
  3357. #define  TRANS_DP_PORT_SEL_B    (0<<29)
  3358. #define  TRANS_DP_PORT_SEL_C    (1<<29)
  3359. #define  TRANS_DP_PORT_SEL_D    (2<<29)
  3360. #define  TRANS_DP_PORT_SEL_NONE (3<<29)
  3361. #define  TRANS_DP_PORT_SEL_MASK (3<<29)
  3362. #define  TRANS_DP_AUDIO_ONLY    (1<<26)
  3363. #define  TRANS_DP_ENH_FRAMING   (1<<18)
  3364. #define  TRANS_DP_8BPC          (0<<9)
  3365. #define  TRANS_DP_10BPC         (1<<9)
  3366. #define  TRANS_DP_6BPC          (2<<9)
  3367. #define  TRANS_DP_12BPC         (3<<9)
  3368. #define  TRANS_DP_BPC_MASK      (3<<9)
  3369. #define  TRANS_DP_VSYNC_ACTIVE_HIGH     (1<<4)
  3370. #define  TRANS_DP_VSYNC_ACTIVE_LOW      0
  3371. #define  TRANS_DP_HSYNC_ACTIVE_HIGH     (1<<3)
  3372. #define  TRANS_DP_HSYNC_ACTIVE_LOW      0
  3373. #define  TRANS_DP_SYNC_MASK     (3<<3)
  3374.  
  3375. /* SNB eDP training params */
  3376. /* SNB A-stepping */
  3377. #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A         (0x38<<22)
  3378. #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A         (0x02<<22)
  3379. #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A       (0x01<<22)
  3380. #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A         (0x0<<22)
  3381. /* SNB B-stepping */
  3382. #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B     (0x0<<22)
  3383. #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B       (0x1<<22)
  3384. #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B     (0x3a<<22)
  3385. #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B   (0x39<<22)
  3386. #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B    (0x38<<22)
  3387. #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB        (0x3f<<22)
  3388.  
  3389. #define  FORCEWAKE                              0xA18C
  3390. #define  FORCEWAKE_ACK                          0x130090
  3391.  
  3392. #define  GT_FIFO_FREE_ENTRIES                   0x120008
  3393. #define    GT_FIFO_NUM_RESERVED_ENTRIES         20
  3394.  
  3395. #define GEN6_RPNSWREQ                           0xA008
  3396. #define   GEN6_TURBO_DISABLE                    (1<<31)
  3397. #define   GEN6_FREQUENCY(x)                     ((x)<<25)
  3398. #define   GEN6_OFFSET(x)                        ((x)<<19)
  3399. #define   GEN6_AGGRESSIVE_TURBO                 (0<<15)
  3400. #define GEN6_RC_VIDEO_FREQ                      0xA00C
  3401. #define GEN6_RC_CONTROL                         0xA090
  3402. #define   GEN6_RC_CTL_RC6pp_ENABLE              (1<<16)
  3403. #define   GEN6_RC_CTL_RC6p_ENABLE               (1<<17)
  3404. #define   GEN6_RC_CTL_RC6_ENABLE                (1<<18)
  3405. #define   GEN6_RC_CTL_RC1e_ENABLE               (1<<20)
  3406. #define   GEN6_RC_CTL_RC7_ENABLE                (1<<22)
  3407. #define   GEN6_RC_CTL_EI_MODE(x)                ((x)<<27)
  3408. #define   GEN6_RC_CTL_HW_ENABLE                 (1<<31)
  3409. #define GEN6_RP_DOWN_TIMEOUT                    0xA010
  3410. #define GEN6_RP_INTERRUPT_LIMITS                0xA014
  3411. #define GEN6_RPSTAT1                            0xA01C
  3412. #define   GEN6_CAGF_SHIFT                       8
  3413. #define   GEN6_CAGF_MASK                        (0x7f << GEN6_CAGF_SHIFT)
  3414. #define GEN6_RP_CONTROL                         0xA024
  3415. #define   GEN6_RP_MEDIA_TURBO                   (1<<11)
  3416. #define   GEN6_RP_USE_NORMAL_FREQ               (1<<9)
  3417. #define   GEN6_RP_MEDIA_IS_GFX                  (1<<8)
  3418. #define   GEN6_RP_ENABLE                        (1<<7)
  3419. #define   GEN6_RP_UP_IDLE_MIN                   (0x1<<3)
  3420. #define   GEN6_RP_UP_BUSY_AVG                   (0x2<<3)
  3421. #define   GEN6_RP_UP_BUSY_CONT                  (0x4<<3)
  3422. #define   GEN6_RP_DOWN_IDLE_CONT                (0x1<<0)
  3423. #define GEN6_RP_UP_THRESHOLD                    0xA02C
  3424. #define GEN6_RP_DOWN_THRESHOLD                  0xA030
  3425. #define GEN6_RP_CUR_UP_EI                       0xA050
  3426. #define   GEN6_CURICONT_MASK                    0xffffff
  3427. #define GEN6_RP_CUR_UP                          0xA054
  3428. #define   GEN6_CURBSYTAVG_MASK                  0xffffff
  3429. #define GEN6_RP_PREV_UP                         0xA058
  3430. #define GEN6_RP_CUR_DOWN_EI                     0xA05C
  3431. #define   GEN6_CURIAVG_MASK                     0xffffff
  3432. #define GEN6_RP_CUR_DOWN                        0xA060
  3433. #define GEN6_RP_PREV_DOWN                       0xA064
  3434. #define GEN6_RP_UP_EI                           0xA068
  3435. #define GEN6_RP_DOWN_EI                         0xA06C
  3436. #define GEN6_RP_IDLE_HYSTERSIS                  0xA070
  3437. #define GEN6_RC_STATE                           0xA094
  3438. #define GEN6_RC1_WAKE_RATE_LIMIT                0xA098
  3439. #define GEN6_RC6_WAKE_RATE_LIMIT                0xA09C
  3440. #define GEN6_RC6pp_WAKE_RATE_LIMIT              0xA0A0
  3441. #define GEN6_RC_EVALUATION_INTERVAL             0xA0A8
  3442. #define GEN6_RC_IDLE_HYSTERSIS                  0xA0AC
  3443. #define GEN6_RC_SLEEP                           0xA0B0
  3444. #define GEN6_RC1e_THRESHOLD                     0xA0B4
  3445. #define GEN6_RC6_THRESHOLD                      0xA0B8
  3446. #define GEN6_RC6p_THRESHOLD                     0xA0BC
  3447. #define GEN6_RC6pp_THRESHOLD                    0xA0C0
  3448. #define GEN6_PMINTRMSK                          0xA168
  3449.  
  3450. #define GEN6_PMISR                              0x44020
  3451. #define GEN6_PMIMR                              0x44024 /* rps_lock */
  3452. #define GEN6_PMIIR                              0x44028
  3453. #define GEN6_PMIER                              0x4402C
  3454. #define  GEN6_PM_MBOX_EVENT                     (1<<25)
  3455. #define  GEN6_PM_THERMAL_EVENT                  (1<<24)
  3456. #define  GEN6_PM_RP_DOWN_TIMEOUT                (1<<6)
  3457. #define  GEN6_PM_RP_UP_THRESHOLD                (1<<5)
  3458. #define  GEN6_PM_RP_DOWN_THRESHOLD              (1<<4)
  3459. #define  GEN6_PM_RP_UP_EI_EXPIRED               (1<<2)
  3460. #define  GEN6_PM_RP_DOWN_EI_EXPIRED             (1<<1)
  3461. #define  GEN6_PM_DEFERRED_EVENTS                (GEN6_PM_RP_UP_THRESHOLD | \
  3462.                                                  GEN6_PM_RP_DOWN_THRESHOLD | \
  3463.                                                  GEN6_PM_RP_DOWN_TIMEOUT)
  3464.  
  3465. #define GEN6_PCODE_MAILBOX                      0x138124
  3466. #define   GEN6_PCODE_READY                      (1<<31)
  3467. #define   GEN6_READ_OC_PARAMS                   0xc
  3468. #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE       0x8
  3469. #define   GEN6_PCODE_READ_MIN_FREQ_TABLE        0x9
  3470. #define GEN6_PCODE_DATA                         0x138128
  3471. #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT        8
  3472.  
  3473. #endif /* _I915_REG_H_ */
  3474.