Subversion Repositories Kolibri OS

Rev

Rev 6084 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  */
  24. #ifndef _I915_GUC_REG_H_
  25. #define _I915_GUC_REG_H_
  26.  
  27. /* Definitions of GuC H/W registers, bits, etc */
  28.  
  29. #define GUC_STATUS                      _MMIO(0xc000)
  30. #define   GS_BOOTROM_SHIFT              1
  31. #define   GS_BOOTROM_MASK                 (0x7F << GS_BOOTROM_SHIFT)
  32. #define   GS_BOOTROM_RSA_FAILED           (0x50 << GS_BOOTROM_SHIFT)
  33. #define   GS_UKERNEL_SHIFT              8
  34. #define   GS_UKERNEL_MASK                 (0xFF << GS_UKERNEL_SHIFT)
  35. #define   GS_UKERNEL_LAPIC_DONE           (0x30 << GS_UKERNEL_SHIFT)
  36. #define   GS_UKERNEL_DPC_ERROR            (0x60 << GS_UKERNEL_SHIFT)
  37. #define   GS_UKERNEL_READY                (0xF0 << GS_UKERNEL_SHIFT)
  38. #define   GS_MIA_SHIFT                  16
  39. #define   GS_MIA_MASK                     (0x07 << GS_MIA_SHIFT)
  40. #define   GS_MIA_CORE_STATE               (1 << GS_MIA_SHIFT)
  41.  
  42. #define SOFT_SCRATCH(n)                 _MMIO(0xc180 + (n) * 4)
  43.  
  44. #define UOS_RSA_SCRATCH(i)              _MMIO(0xc200 + (i) * 4)
  45. #define   UOS_RSA_SCRATCH_MAX_COUNT       64
  46. #define DMA_ADDR_0_LOW                  _MMIO(0xc300)
  47. #define DMA_ADDR_0_HIGH                 _MMIO(0xc304)
  48. #define DMA_ADDR_1_LOW                  _MMIO(0xc308)
  49. #define DMA_ADDR_1_HIGH                 _MMIO(0xc30c)
  50. #define   DMA_ADDRESS_SPACE_WOPCM         (7 << 16)
  51. #define   DMA_ADDRESS_SPACE_GTT           (8 << 16)
  52. #define DMA_COPY_SIZE                   _MMIO(0xc310)
  53. #define DMA_CTRL                        _MMIO(0xc314)
  54. #define   UOS_MOVE                        (1<<4)
  55. #define   START_DMA                       (1<<0)
  56. #define DMA_GUC_WOPCM_OFFSET            _MMIO(0xc340)
  57. #define   GUC_WOPCM_OFFSET_VALUE          0x80000       /* 512KB */
  58. #define GUC_MAX_IDLE_COUNT              _MMIO(0xC3E4)
  59.  
  60. #define GUC_WOPCM_SIZE                  _MMIO(0xc050)
  61. #define   GUC_WOPCM_SIZE_VALUE            (0x80 << 12)  /* 512KB */
  62.  
  63. /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
  64. #define GUC_WOPCM_TOP                   (GUC_WOPCM_SIZE_VALUE)
  65.  
  66. #define GEN8_GT_PM_CONFIG               _MMIO(0x138140)
  67. #define GEN9LP_GT_PM_CONFIG             _MMIO(0x138140)
  68. #define GEN9_GT_PM_CONFIG               _MMIO(0x13816c)
  69. #define   GT_DOORBELL_ENABLE              (1<<0)
  70.  
  71. #define GEN8_GTCR                       _MMIO(0x4274)
  72. #define   GEN8_GTCR_INVALIDATE            (1<<0)
  73.  
  74. #define GUC_ARAT_C6DIS                  _MMIO(0xA178)
  75.  
  76. #define GUC_SHIM_CONTROL                _MMIO(0xc064)
  77. #define   GUC_DISABLE_SRAM_INIT_TO_ZEROES       (1<<0)
  78. #define   GUC_ENABLE_READ_CACHE_LOGIC           (1<<1)
  79. #define   GUC_ENABLE_MIA_CACHING                (1<<2)
  80. #define   GUC_GEN10_MSGCH_ENABLE                (1<<4)
  81. #define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA   (1<<9)
  82. #define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA  (1<<10)
  83. #define   GUC_ENABLE_MIA_CLOCK_GATING           (1<<15)
  84. #define   GUC_GEN10_SHIM_WC_ENABLE              (1<<21)
  85.  
  86. #define GUC_SHIM_CONTROL_VALUE  (GUC_DISABLE_SRAM_INIT_TO_ZEROES        | \
  87.                                  GUC_ENABLE_READ_CACHE_LOGIC            | \
  88.                                  GUC_ENABLE_MIA_CACHING                 | \
  89.                                  GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA    | \
  90.                                  GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA   | \
  91.                                  GUC_ENABLE_MIA_CLOCK_GATING)
  92.  
  93. #define HOST2GUC_INTERRUPT              _MMIO(0xc4c8)
  94. #define   HOST2GUC_TRIGGER                (1<<0)
  95.  
  96. #define DRBMISC1                        0x1984
  97. #define   DOORBELL_ENABLE                 (1<<0)
  98.  
  99. #define GEN8_DRBREGL(x)                 _MMIO(0x1000 + (x) * 8)
  100. #define   GEN8_DRB_VALID                  (1<<0)
  101. #define GEN8_DRBREGU(x)                 _MMIO(0x1000 + (x) * 8 + 4)
  102.  
  103. #define DE_GUCRMR                       _MMIO(0x44054)
  104.  
  105. #define GUC_BCS_RCS_IER                 _MMIO(0xC550)
  106. #define GUC_VCS2_VCS1_IER               _MMIO(0xC554)
  107. #define GUC_WD_VECS_IER                 _MMIO(0xC558)
  108. #define GUC_PM_P24C_IER                 _MMIO(0xC55C)
  109.  
  110. #endif
  111.