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  1. /*
  2.  * Copyright © 2008 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #include "linux/string.h"
  29. #include "linux/bitops.h"
  30. #include "drmP.h"
  31. #include "drm.h"
  32. #include "i915_drm.h"
  33. #include "i915_drv.h"
  34.  
  35. /** @file i915_gem_tiling.c
  36.  *
  37.  * Support for managing tiling state of buffer objects.
  38.  *
  39.  * The idea behind tiling is to increase cache hit rates by rearranging
  40.  * pixel data so that a group of pixel accesses are in the same cacheline.
  41.  * Performance improvement from doing this on the back/depth buffer are on
  42.  * the order of 30%.
  43.  *
  44.  * Intel architectures make this somewhat more complicated, though, by
  45.  * adjustments made to addressing of data when the memory is in interleaved
  46.  * mode (matched pairs of DIMMS) to improve memory bandwidth.
  47.  * For interleaved memory, the CPU sends every sequential 64 bytes
  48.  * to an alternate memory channel so it can get the bandwidth from both.
  49.  *
  50.  * The GPU also rearranges its accesses for increased bandwidth to interleaved
  51.  * memory, and it matches what the CPU does for non-tiled.  However, when tiled
  52.  * it does it a little differently, since one walks addresses not just in the
  53.  * X direction but also Y.  So, along with alternating channels when bit
  54.  * 6 of the address flips, it also alternates when other bits flip --  Bits 9
  55.  * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
  56.  * are common to both the 915 and 965-class hardware.
  57.  *
  58.  * The CPU also sometimes XORs in higher bits as well, to improve
  59.  * bandwidth doing strided access like we do so frequently in graphics.  This
  60.  * is called "Channel XOR Randomization" in the MCH documentation.  The result
  61.  * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
  62.  * decode.
  63.  *
  64.  * All of this bit 6 XORing has an effect on our memory management,
  65.  * as we need to make sure that the 3d driver can correctly address object
  66.  * contents.
  67.  *
  68.  * If we don't have interleaved memory, all tiling is safe and no swizzling is
  69.  * required.
  70.  *
  71.  * When bit 17 is XORed in, we simply refuse to tile at all.  Bit
  72.  * 17 is not just a page offset, so as we page an objet out and back in,
  73.  * individual pages in it will have different bit 17 addresses, resulting in
  74.  * each 64 bytes being swapped with its neighbor!
  75.  *
  76.  * Otherwise, if interleaved, we have to tell the 3d driver what the address
  77.  * swizzling it needs to do is, since it's writing with the CPU to the pages
  78.  * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
  79.  * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
  80.  * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
  81.  * to match what the GPU expects.
  82.  */
  83.  
  84. #define I915_TILING_NONE   0
  85. #define I915_TILING_X       1
  86. #define I915_TILING_Y       2
  87.  
  88. #define I915_BIT_6_SWIZZLE_NONE     0
  89. #define I915_BIT_6_SWIZZLE_9        1
  90. #define I915_BIT_6_SWIZZLE_9_10     2
  91. #define I915_BIT_6_SWIZZLE_9_11     3
  92. #define I915_BIT_6_SWIZZLE_9_10_11  4
  93. /* Not seen by userland */
  94. #define I915_BIT_6_SWIZZLE_UNKNOWN  5
  95. /* Seen by userland. */
  96. #define I915_BIT_6_SWIZZLE_9_17     6
  97. #define I915_BIT_6_SWIZZLE_9_10_17  7
  98.  
  99.  
  100.  
  101.  
  102. /**
  103.  * Detects bit 6 swizzling of address lookup between IGD access and CPU
  104.  * access through main memory.
  105.  */
  106. void
  107. i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
  108. {
  109.         drm_i915_private_t *dev_priv = dev->dev_private;
  110.         uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
  111.         uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
  112.  
  113.         if (INTEL_INFO(dev)->gen >= 5) {
  114.                 /* On Ironlake whatever DRAM config, GPU always do
  115.                  * same swizzling setup.
  116.                  */
  117.                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
  118.                 swizzle_y = I915_BIT_6_SWIZZLE_9;
  119.         } else if (IS_GEN2(dev)) {
  120.                 /* As far as we know, the 865 doesn't have these bit 6
  121.                  * swizzling issues.
  122.                  */
  123.                 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
  124.                 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
  125.         } else if (IS_MOBILE(dev)) {
  126.                 uint32_t dcc;
  127.  
  128.                 /* On mobile 9xx chipsets, channel interleave by the CPU is
  129.                  * determined by DCC.  For single-channel, neither the CPU
  130.                  * nor the GPU do swizzling.  For dual channel interleaved,
  131.                  * the GPU's interleave is bit 9 and 10 for X tiled, and bit
  132.                  * 9 for Y tiled.  The CPU's interleave is independent, and
  133.                  * can be based on either bit 11 (haven't seen this yet) or
  134.                  * bit 17 (common).
  135.                  */
  136.                 dcc = I915_READ(DCC);
  137.                 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
  138.                 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
  139.                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
  140.                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
  141.                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
  142.                         break;
  143.                 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
  144.                         if (dcc & DCC_CHANNEL_XOR_DISABLE) {
  145.                                 /* This is the base swizzling by the GPU for
  146.                                  * tiled buffers.
  147.                                  */
  148.                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
  149.                                 swizzle_y = I915_BIT_6_SWIZZLE_9;
  150.                         } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
  151.                                 /* Bit 11 swizzling by the CPU in addition. */
  152.                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
  153.                                 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
  154.                         } else {
  155.                                 /* Bit 17 swizzling by the CPU in addition. */
  156.                                 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
  157.                                 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
  158.                         }
  159.                         break;
  160.                 }
  161.                 if (dcc == 0xffffffff) {
  162.                         DRM_ERROR("Couldn't read from MCHBAR.  "
  163.                                   "Disabling tiling.\n");
  164.                         swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
  165.                         swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
  166.                 }
  167.         } else {
  168.                 /* The 965, G33, and newer, have a very flexible memory
  169.                  * configuration.  It will enable dual-channel mode
  170.                  * (interleaving) on as much memory as it can, and the GPU
  171.                  * will additionally sometimes enable different bit 6
  172.                  * swizzling for tiled objects from the CPU.
  173.                  *
  174.                  * Here's what I found on the G965:
  175.                  *    slot fill         memory size  swizzling
  176.                  * 0A   0B   1A   1B    1-ch   2-ch
  177.                  * 512  0    0    0     512    0     O
  178.                  * 512  0    512  0     16     1008  X
  179.                  * 512  0    0    512   16     1008  X
  180.                  * 0    512  0    512   16     1008  X
  181.                  * 1024 1024 1024 0     2048   1024  O
  182.                  *
  183.                  * We could probably detect this based on either the DRB
  184.                  * matching, which was the case for the swizzling required in
  185.                  * the table above, or from the 1-ch value being less than
  186.                  * the minimum size of a rank.
  187.                  */
  188.                 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
  189.                         swizzle_x = I915_BIT_6_SWIZZLE_NONE;
  190.                         swizzle_y = I915_BIT_6_SWIZZLE_NONE;
  191.                 } else {
  192.                         swizzle_x = I915_BIT_6_SWIZZLE_9_10;
  193.                         swizzle_y = I915_BIT_6_SWIZZLE_9;
  194.                 }
  195.         }
  196.  
  197.         dev_priv->mm.bit_6_swizzle_x = swizzle_x;
  198.         dev_priv->mm.bit_6_swizzle_y = swizzle_y;
  199. }
  200.  
  201. #if 0
  202. /* Check pitch constriants for all chips & tiling formats */
  203. static bool
  204. i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
  205. {
  206.         int tile_width;
  207.  
  208.         /* Linear is always fine */
  209.         if (tiling_mode == I915_TILING_NONE)
  210.                 return true;
  211.  
  212.         if (IS_GEN2(dev) ||
  213.             (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
  214.                 tile_width = 128;
  215.         else
  216.                 tile_width = 512;
  217.  
  218.         /* check maximum stride & object size */
  219.         if (INTEL_INFO(dev)->gen >= 4) {
  220.                 /* i965 stores the end address of the gtt mapping in the fence
  221.                  * reg, so dont bother to check the size */
  222.                 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
  223.                         return false;
  224.         } else {
  225.                 if (stride > 8192)
  226.                         return false;
  227.  
  228.                 if (IS_GEN3(dev)) {
  229.                         if (size > I830_FENCE_MAX_SIZE_VAL << 20)
  230.                                 return false;
  231.                 } else {
  232.                         if (size > I830_FENCE_MAX_SIZE_VAL << 19)
  233.                                 return false;
  234.                 }
  235.         }
  236.  
  237.         /* 965+ just needs multiples of tile width */
  238.         if (INTEL_INFO(dev)->gen >= 4) {
  239.                 if (stride & (tile_width - 1))
  240.                         return false;
  241.                 return true;
  242.         }
  243.  
  244.         /* Pre-965 needs power of two tile widths */
  245.         if (stride < tile_width)
  246.                 return false;
  247.  
  248.         if (stride & (stride - 1))
  249.                 return false;
  250.  
  251.         return true;
  252. }
  253.  
  254. /* Is the current GTT allocation valid for the change in tiling? */
  255. static bool
  256. i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
  257. {
  258.         u32 size;
  259.  
  260.         if (tiling_mode == I915_TILING_NONE)
  261.                 return true;
  262.  
  263.         if (INTEL_INFO(obj->base.dev)->gen >= 4)
  264.                 return true;
  265.  
  266.         if (INTEL_INFO(obj->base.dev)->gen == 3) {
  267.                 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
  268.                         return false;
  269.         } else {
  270.                 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
  271.                         return false;
  272.         }
  273.  
  274.         /*
  275.          * Previous chips need to be aligned to the size of the smallest
  276.          * fence register that can contain the object.
  277.          */
  278.         if (INTEL_INFO(obj->base.dev)->gen == 3)
  279.                 size = 1024*1024;
  280.         else
  281.                 size = 512*1024;
  282.  
  283.         while (size < obj->base.size)
  284.                 size <<= 1;
  285.  
  286.         if (obj->gtt_space->size != size)
  287.                 return false;
  288.  
  289.         if (obj->gtt_offset & (size - 1))
  290.                 return false;
  291.  
  292.         return true;
  293. }
  294.  
  295. /**
  296.  * Sets the tiling mode of an object, returning the required swizzling of
  297.  * bit 6 of addresses in the object.
  298.  */
  299. int
  300. i915_gem_set_tiling(struct drm_device *dev, void *data,
  301.                    struct drm_file *file)
  302. {
  303.         struct drm_i915_gem_set_tiling *args = data;
  304.         drm_i915_private_t *dev_priv = dev->dev_private;
  305.         struct drm_i915_gem_object *obj;
  306.         int ret = 0;
  307.  
  308.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  309.         if (&obj->base == NULL)
  310.                 return -ENOENT;
  311.  
  312.         if (!i915_tiling_ok(dev,
  313.                             args->stride, obj->base.size, args->tiling_mode)) {
  314.                 drm_gem_object_unreference_unlocked(&obj->base);
  315.                 return -EINVAL;
  316.         }
  317.  
  318.         if (obj->pin_count) {
  319.                 drm_gem_object_unreference_unlocked(&obj->base);
  320.                 return -EBUSY;
  321.         }
  322.  
  323.         if (args->tiling_mode == I915_TILING_NONE) {
  324.                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
  325.                 args->stride = 0;
  326.         } else {
  327.                 if (args->tiling_mode == I915_TILING_X)
  328.                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
  329.                 else
  330.                         args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
  331.  
  332.                 /* Hide bit 17 swizzling from the user.  This prevents old Mesa
  333.                  * from aborting the application on sw fallbacks to bit 17,
  334.                  * and we use the pread/pwrite bit17 paths to swizzle for it.
  335.                  * If there was a user that was relying on the swizzle
  336.                  * information for drm_intel_bo_map()ed reads/writes this would
  337.                  * break it, but we don't have any of those.
  338.                  */
  339.                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
  340.                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
  341.                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
  342.                         args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
  343.  
  344.                 /* If we can't handle the swizzling, make it untiled. */
  345.                 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
  346.                         args->tiling_mode = I915_TILING_NONE;
  347.                         args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
  348.                         args->stride = 0;
  349.                 }
  350.         }
  351.  
  352.         mutex_lock(&dev->struct_mutex);
  353.         if (args->tiling_mode != obj->tiling_mode ||
  354.             args->stride != obj->stride) {
  355.                 /* We need to rebind the object if its current allocation
  356.                  * no longer meets the alignment restrictions for its new
  357.                  * tiling mode. Otherwise we can just leave it alone, but
  358.                  * need to ensure that any fence register is cleared.
  359.                  */
  360.                 i915_gem_release_mmap(obj);
  361.  
  362.                 obj->map_and_fenceable =
  363.                         obj->gtt_space == NULL ||
  364.                         (obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end &&
  365.                          i915_gem_object_fence_ok(obj, args->tiling_mode));
  366.  
  367.                 /* Rebind if we need a change of alignment */
  368.                 if (!obj->map_and_fenceable) {
  369.                         u32 unfenced_alignment =
  370.                                 i915_gem_get_unfenced_gtt_alignment(dev,
  371.                                                                     obj->base.size,
  372.                                                                     args->tiling_mode);
  373.                         if (obj->gtt_offset & (unfenced_alignment - 1))
  374.                                 ret = i915_gem_object_unbind(obj);
  375.                 }
  376.  
  377.                 if (ret == 0) {
  378.                         obj->tiling_changed = true;
  379.                         obj->tiling_mode = args->tiling_mode;
  380.                         obj->stride = args->stride;
  381.                 }
  382.         }
  383.         /* we have to maintain this existing ABI... */
  384.         args->stride = obj->stride;
  385.         args->tiling_mode = obj->tiling_mode;
  386.         drm_gem_object_unreference(&obj->base);
  387.         mutex_unlock(&dev->struct_mutex);
  388.  
  389.         return ret;
  390. }
  391.  
  392. /**
  393.  * Returns the current tiling mode and required bit 6 swizzling for the object.
  394.  */
  395. int
  396. i915_gem_get_tiling(struct drm_device *dev, void *data,
  397.                    struct drm_file *file)
  398. {
  399.         struct drm_i915_gem_get_tiling *args = data;
  400.         drm_i915_private_t *dev_priv = dev->dev_private;
  401.         struct drm_i915_gem_object *obj;
  402.  
  403.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  404.         if (&obj->base == NULL)
  405.                 return -ENOENT;
  406.  
  407.         mutex_lock(&dev->struct_mutex);
  408.  
  409.         args->tiling_mode = obj->tiling_mode;
  410.         switch (obj->tiling_mode) {
  411.         case I915_TILING_X:
  412.                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
  413.                 break;
  414.         case I915_TILING_Y:
  415.                 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
  416.                 break;
  417.         case I915_TILING_NONE:
  418.                 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
  419.                 break;
  420.         default:
  421.                 DRM_ERROR("unknown tiling mode\n");
  422.         }
  423.  
  424.         /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
  425.         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
  426.                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
  427.         if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
  428.                 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
  429.  
  430.         drm_gem_object_unreference(&obj->base);
  431.         mutex_unlock(&dev->struct_mutex);
  432.  
  433.         return 0;
  434. }
  435.  
  436. /**
  437.  * Swap every 64 bytes of this page around, to account for it having a new
  438.  * bit 17 of its physical address and therefore being interpreted differently
  439.  * by the GPU.
  440.  */
  441. static void
  442. i915_gem_swizzle_page(struct page *page)
  443. {
  444.         char temp[64];
  445.         char *vaddr;
  446.         int i;
  447.  
  448.         vaddr = kmap(page);
  449.  
  450.         for (i = 0; i < PAGE_SIZE; i += 128) {
  451.                 memcpy(temp, &vaddr[i], 64);
  452.                 memcpy(&vaddr[i], &vaddr[i + 64], 64);
  453.                 memcpy(&vaddr[i + 64], temp, 64);
  454.         }
  455.  
  456.         kunmap(page);
  457. }
  458.  
  459. void
  460. i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
  461. {
  462.         struct drm_device *dev = obj->base.dev;
  463.         drm_i915_private_t *dev_priv = dev->dev_private;
  464.         int page_count = obj->base.size >> PAGE_SHIFT;
  465.         int i;
  466.  
  467.         if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
  468.                 return;
  469.  
  470.         if (obj->bit_17 == NULL)
  471.                 return;
  472.  
  473.         for (i = 0; i < page_count; i++) {
  474.                 char new_bit_17 = page_to_phys(obj->pages[i]) >> 17;
  475.                 if ((new_bit_17 & 0x1) !=
  476.                     (test_bit(i, obj->bit_17) != 0)) {
  477.                         i915_gem_swizzle_page(obj->pages[i]);
  478.                         set_page_dirty(obj->pages[i]);
  479.                 }
  480.         }
  481. }
  482.  
  483. void
  484. i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
  485. {
  486.         struct drm_device *dev = obj->base.dev;
  487.         drm_i915_private_t *dev_priv = dev->dev_private;
  488.         int page_count = obj->base.size >> PAGE_SHIFT;
  489.         int i;
  490.  
  491.         if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
  492.                 return;
  493.  
  494.         if (obj->bit_17 == NULL) {
  495.                 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
  496.                                            sizeof(long), GFP_KERNEL);
  497.                 if (obj->bit_17 == NULL) {
  498.                         DRM_ERROR("Failed to allocate memory for bit 17 "
  499.                                   "record\n");
  500.                         return;
  501.                 }
  502.         }
  503.  
  504.         for (i = 0; i < page_count; i++) {
  505.                 if (page_to_phys(obj->pages[i]) & (1 << 17))
  506.                         __set_bit(i, obj->bit_17);
  507.                 else
  508.                         __clear_bit(i, obj->bit_17);
  509.         }
  510. }
  511.  
  512. #endif
  513.