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  1. /*
  2.  * Copyright © 2008 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21.  * IN THE SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *    Eric Anholt <eric@anholt.net>
  25.  *
  26.  */
  27.  
  28. #include <drm/drmP.h>
  29. #include <drm/i915_drm.h>
  30. #include "i915_drv.h"
  31. #include "i915_trace.h"
  32. #include "intel_drv.h"
  33. #include <linux/shmem_fs.h>
  34. #include <linux/slab.h>
  35. //#include <linux/swap.h>
  36. #include <linux/scatterlist.h>
  37. #include <linux/pci.h>
  38.  
  39. extern int x86_clflush_size;
  40.  
  41. #define PROT_READ       0x1             /* page can be read */
  42. #define PROT_WRITE      0x2             /* page can be written */
  43. #define MAP_SHARED      0x01            /* Share changes */
  44.  
  45. #undef mb
  46. #undef rmb
  47. #undef wmb
  48. #define mb() asm volatile("mfence")
  49. #define rmb() asm volatile ("lfence")
  50. #define wmb() asm volatile ("sfence")
  51.  
  52. struct drm_i915_gem_object *get_fb_obj();
  53.  
  54. unsigned long vm_mmap(struct file *file, unsigned long addr,
  55.          unsigned long len, unsigned long prot,
  56.          unsigned long flag, unsigned long offset);
  57.  
  58. static inline void clflush(volatile void *__p)
  59. {
  60.     asm volatile("clflush %0" : "+m" (*(volatile char*)__p));
  61. }
  62.  
  63. #define MAX_ERRNO       4095
  64.  
  65. #define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
  66.  
  67.  
  68. #define I915_EXEC_CONSTANTS_MASK        (3<<6)
  69. #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
  70. #define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
  71. #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
  72.  
  73. static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  74. static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  75.                                                    bool force);
  76. static __must_check int
  77. i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
  78.                            struct i915_address_space *vm,
  79.                                                     unsigned alignment,
  80.                                                     bool map_and_fenceable,
  81.                                                     bool nonblocking);
  82. static int i915_gem_phys_pwrite(struct drm_device *dev,
  83.                                 struct drm_i915_gem_object *obj,
  84.                                 struct drm_i915_gem_pwrite *args,
  85.                                 struct drm_file *file);
  86.  
  87. static void i915_gem_write_fence(struct drm_device *dev, int reg,
  88.                                  struct drm_i915_gem_object *obj);
  89. static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  90.                                          struct drm_i915_fence_reg *fence,
  91.                                          bool enable);
  92.  
  93. static long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  94. static long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  95. static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  96.  
  97. static bool cpu_cache_is_coherent(struct drm_device *dev,
  98.                                   enum i915_cache_level level)
  99. {
  100.         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  101. }
  102.  
  103. static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  104. {
  105.         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  106.                 return true;
  107.  
  108.         return obj->pin_display;
  109. }
  110.  
  111. static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  112. {
  113.         if (obj->tiling_mode)
  114.                 i915_gem_release_mmap(obj);
  115.  
  116.         /* As we do not have an associated fence register, we will force
  117.          * a tiling change if we ever need to acquire one.
  118.          */
  119.         obj->fence_dirty = false;
  120.         obj->fence_reg = I915_FENCE_REG_NONE;
  121. }
  122.  
  123. /* some bookkeeping */
  124. static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  125.                                   size_t size)
  126. {
  127.         spin_lock(&dev_priv->mm.object_stat_lock);
  128.         dev_priv->mm.object_count++;
  129.         dev_priv->mm.object_memory += size;
  130.         spin_unlock(&dev_priv->mm.object_stat_lock);
  131. }
  132.  
  133. static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  134.                                      size_t size)
  135. {
  136.         spin_lock(&dev_priv->mm.object_stat_lock);
  137.         dev_priv->mm.object_count--;
  138.         dev_priv->mm.object_memory -= size;
  139.         spin_unlock(&dev_priv->mm.object_stat_lock);
  140. }
  141.  
  142. static int
  143. i915_gem_wait_for_error(struct i915_gpu_error *error)
  144. {
  145.         int ret;
  146.  
  147. #define EXIT_COND (!i915_reset_in_progress(error))
  148.         if (EXIT_COND)
  149.                 return 0;
  150. #if 0
  151.         /*
  152.          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
  153.          * userspace. If it takes that long something really bad is going on and
  154.          * we should simply try to bail out and fail as gracefully as possible.
  155.          */
  156.         ret = wait_event_interruptible_timeout(error->reset_queue,
  157.                                                EXIT_COND,
  158.                                                10*HZ);
  159.         if (ret == 0) {
  160.                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
  161.                 return -EIO;
  162.         } else if (ret < 0) {
  163.                 return ret;
  164.         }
  165.  
  166. #endif
  167. #undef EXIT_COND
  168.  
  169.         return 0;
  170. }
  171.  
  172. int i915_mutex_lock_interruptible(struct drm_device *dev)
  173. {
  174.         struct drm_i915_private *dev_priv = dev->dev_private;
  175.         int ret;
  176.  
  177.         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
  178.         if (ret)
  179.                 return ret;
  180.  
  181.         ret = mutex_lock_interruptible(&dev->struct_mutex);
  182.         if (ret)
  183.                 return ret;
  184.  
  185.         WARN_ON(i915_verify_lists(dev));
  186.         return 0;
  187. }
  188.  
  189. static inline bool
  190. i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
  191. {
  192.         return i915_gem_obj_bound_any(obj) && !obj->active;
  193. }
  194.  
  195.  
  196. #if 0
  197.  
  198. int
  199. i915_gem_init_ioctl(struct drm_device *dev, void *data,
  200.                     struct drm_file *file)
  201. {
  202.         struct drm_i915_private *dev_priv = dev->dev_private;
  203.         struct drm_i915_gem_init *args = data;
  204.  
  205.         if (drm_core_check_feature(dev, DRIVER_MODESET))
  206.                 return -ENODEV;
  207.  
  208.         if (args->gtt_start >= args->gtt_end ||
  209.             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
  210.                 return -EINVAL;
  211.  
  212.         /* GEM with user mode setting was never supported on ilk and later. */
  213.         if (INTEL_INFO(dev)->gen >= 5)
  214.                 return -ENODEV;
  215.  
  216.         mutex_lock(&dev->struct_mutex);
  217.         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
  218.                                   args->gtt_end);
  219.         dev_priv->gtt.mappable_end = args->gtt_end;
  220.         mutex_unlock(&dev->struct_mutex);
  221.  
  222.         return 0;
  223. }
  224. #endif
  225.  
  226. int
  227. i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  228.                             struct drm_file *file)
  229. {
  230.         struct drm_i915_private *dev_priv = dev->dev_private;
  231.         struct drm_i915_gem_get_aperture *args = data;
  232.         struct drm_i915_gem_object *obj;
  233.         size_t pinned;
  234.  
  235.         pinned = 0;
  236.         mutex_lock(&dev->struct_mutex);
  237.         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
  238.                 if (obj->pin_count)
  239.                         pinned += i915_gem_obj_ggtt_size(obj);
  240.         mutex_unlock(&dev->struct_mutex);
  241.  
  242.         args->aper_size = dev_priv->gtt.base.total;
  243.         args->aper_available_size = args->aper_size - pinned;
  244.  
  245.         return 0;
  246. }
  247.  
  248. void *i915_gem_object_alloc(struct drm_device *dev)
  249. {
  250.         struct drm_i915_private *dev_priv = dev->dev_private;
  251.         return kmalloc(sizeof(struct drm_i915_gem_object), 0);
  252. }
  253.  
  254. void i915_gem_object_free(struct drm_i915_gem_object *obj)
  255. {
  256.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  257.         kfree(obj);
  258. }
  259.  
  260. static int
  261. i915_gem_create(struct drm_file *file,
  262.                 struct drm_device *dev,
  263.                 uint64_t size,
  264.                 uint32_t *handle_p)
  265. {
  266.         struct drm_i915_gem_object *obj;
  267.         int ret;
  268.         u32 handle;
  269.  
  270.         size = roundup(size, PAGE_SIZE);
  271.         if (size == 0)
  272.                 return -EINVAL;
  273.  
  274.         /* Allocate the new object */
  275.         obj = i915_gem_alloc_object(dev, size);
  276.         if (obj == NULL)
  277.                 return -ENOMEM;
  278.  
  279.         ret = drm_gem_handle_create(file, &obj->base, &handle);
  280.         /* drop reference from allocate - handle holds it now */
  281.         drm_gem_object_unreference_unlocked(&obj->base);
  282.         if (ret)
  283.                 return ret;
  284.  
  285.         *handle_p = handle;
  286.         return 0;
  287. }
  288.  
  289. int
  290. i915_gem_dumb_create(struct drm_file *file,
  291.                      struct drm_device *dev,
  292.                      struct drm_mode_create_dumb *args)
  293. {
  294.         /* have to work out size/pitch and return them */
  295.         args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
  296.         args->size = args->pitch * args->height;
  297.         return i915_gem_create(file, dev,
  298.                                args->size, &args->handle);
  299. }
  300.  
  301. /**
  302.  * Creates a new mm object and returns a handle to it.
  303.  */
  304. int
  305. i915_gem_create_ioctl(struct drm_device *dev, void *data,
  306.                       struct drm_file *file)
  307. {
  308.         struct drm_i915_gem_create *args = data;
  309.  
  310.         return i915_gem_create(file, dev,
  311.                                args->size, &args->handle);
  312. }
  313.  
  314.  
  315. #if 0
  316.  
  317. static inline int
  318. __copy_to_user_swizzled(char __user *cpu_vaddr,
  319.                         const char *gpu_vaddr, int gpu_offset,
  320.                 int length)
  321. {
  322.         int ret, cpu_offset = 0;
  323.  
  324.         while (length > 0) {
  325.                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
  326.                 int this_length = min(cacheline_end - gpu_offset, length);
  327.                 int swizzled_gpu_offset = gpu_offset ^ 64;
  328.  
  329.                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
  330.                                      gpu_vaddr + swizzled_gpu_offset,
  331.                                      this_length);
  332.                 if (ret)
  333.                         return ret + length;
  334.  
  335.                 cpu_offset += this_length;
  336.                 gpu_offset += this_length;
  337.                 length -= this_length;
  338.         }
  339.  
  340.         return 0;
  341. }
  342.  
  343. static inline int
  344. __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
  345.                           const char __user *cpu_vaddr,
  346.                           int length)
  347. {
  348.         int ret, cpu_offset = 0;
  349.  
  350.         while (length > 0) {
  351.                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
  352.                 int this_length = min(cacheline_end - gpu_offset, length);
  353.                 int swizzled_gpu_offset = gpu_offset ^ 64;
  354.  
  355.                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
  356.                                cpu_vaddr + cpu_offset,
  357.                                this_length);
  358.                 if (ret)
  359.                         return ret + length;
  360.  
  361.                 cpu_offset += this_length;
  362.                 gpu_offset += this_length;
  363.                 length -= this_length;
  364.         }
  365.  
  366.         return 0;
  367. }
  368.  
  369. /* Per-page copy function for the shmem pread fastpath.
  370.  * Flushes invalid cachelines before reading the target if
  371.  * needs_clflush is set. */
  372. static int
  373. shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
  374.                  char __user *user_data,
  375.                  bool page_do_bit17_swizzling, bool needs_clflush)
  376. {
  377.                 char *vaddr;
  378.                 int ret;
  379.  
  380.         if (unlikely(page_do_bit17_swizzling))
  381.                 return -EINVAL;
  382.  
  383.                 vaddr = kmap_atomic(page);
  384.         if (needs_clflush)
  385.                 drm_clflush_virt_range(vaddr + shmem_page_offset,
  386.                                        page_length);
  387.                 ret = __copy_to_user_inatomic(user_data,
  388.                                       vaddr + shmem_page_offset,
  389.                                               page_length);
  390.                 kunmap_atomic(vaddr);
  391.  
  392.         return ret ? -EFAULT : 0;
  393. }
  394.  
  395. static void
  396. shmem_clflush_swizzled_range(char *addr, unsigned long length,
  397.                              bool swizzled)
  398. {
  399.         if (unlikely(swizzled)) {
  400.                 unsigned long start = (unsigned long) addr;
  401.                 unsigned long end = (unsigned long) addr + length;
  402.  
  403.                 /* For swizzling simply ensure that we always flush both
  404.                  * channels. Lame, but simple and it works. Swizzled
  405.                  * pwrite/pread is far from a hotpath - current userspace
  406.                  * doesn't use it at all. */
  407.                 start = round_down(start, 128);
  408.                 end = round_up(end, 128);
  409.  
  410.                 drm_clflush_virt_range((void *)start, end - start);
  411.         } else {
  412.                 drm_clflush_virt_range(addr, length);
  413.         }
  414.  
  415. }
  416.  
  417. /* Only difference to the fast-path function is that this can handle bit17
  418.  * and uses non-atomic copy and kmap functions. */
  419. static int
  420. shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
  421.                  char __user *user_data,
  422.                  bool page_do_bit17_swizzling, bool needs_clflush)
  423. {
  424.         char *vaddr;
  425.         int ret;
  426.  
  427.         vaddr = kmap(page);
  428.         if (needs_clflush)
  429.                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
  430.                                              page_length,
  431.                                              page_do_bit17_swizzling);
  432.  
  433.         if (page_do_bit17_swizzling)
  434.                 ret = __copy_to_user_swizzled(user_data,
  435.                                               vaddr, shmem_page_offset,
  436.                                               page_length);
  437.         else
  438.                 ret = __copy_to_user(user_data,
  439.                                      vaddr + shmem_page_offset,
  440.                                      page_length);
  441.         kunmap(page);
  442.  
  443.         return ret ? - EFAULT : 0;
  444. }
  445.  
  446. static int
  447. i915_gem_shmem_pread(struct drm_device *dev,
  448.                           struct drm_i915_gem_object *obj,
  449.                           struct drm_i915_gem_pread *args,
  450.                           struct drm_file *file)
  451. {
  452.         char __user *user_data;
  453.         ssize_t remain;
  454.         loff_t offset;
  455.         int shmem_page_offset, page_length, ret = 0;
  456.         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
  457.         int prefaulted = 0;
  458.         int needs_clflush = 0;
  459.         struct sg_page_iter sg_iter;
  460.  
  461.         user_data = to_user_ptr(args->data_ptr);
  462.         remain = args->size;
  463.  
  464.         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
  465.  
  466.         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
  467.                 /* If we're not in the cpu read domain, set ourself into the gtt
  468.                  * read domain and manually flush cachelines (if required). This
  469.                  * optimizes for the case when the gpu will dirty the data
  470.                  * anyway again before the next pread happens. */
  471.                 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
  472.                 if (i915_gem_obj_bound_any(obj)) {
  473.                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
  474.                         if (ret)
  475.                                 return ret;
  476.                 }
  477.         }
  478.  
  479.         ret = i915_gem_object_get_pages(obj);
  480.         if (ret)
  481.                 return ret;
  482.  
  483.         i915_gem_object_pin_pages(obj);
  484.  
  485.         offset = args->offset;
  486.  
  487.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
  488.                          offset >> PAGE_SHIFT) {
  489.                 struct page *page = sg_page_iter_page(&sg_iter);
  490.  
  491.                 if (remain <= 0)
  492.                         break;
  493.  
  494.                 /* Operation in this page
  495.                  *
  496.                  * shmem_page_offset = offset within page in shmem file
  497.                  * page_length = bytes to copy for this page
  498.                  */
  499.                 shmem_page_offset = offset_in_page(offset);
  500.                 page_length = remain;
  501.                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
  502.                         page_length = PAGE_SIZE - shmem_page_offset;
  503.  
  504.                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
  505.                         (page_to_phys(page) & (1 << 17)) != 0;
  506.  
  507.                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
  508.                                        user_data, page_do_bit17_swizzling,
  509.                                        needs_clflush);
  510.                 if (ret == 0)
  511.                         goto next_page;
  512.  
  513.                 mutex_unlock(&dev->struct_mutex);
  514.  
  515.                 if (likely(!i915_prefault_disable) && !prefaulted) {
  516.                         ret = fault_in_multipages_writeable(user_data, remain);
  517.                         /* Userspace is tricking us, but we've already clobbered
  518.                          * its pages with the prefault and promised to write the
  519.                          * data up to the first fault. Hence ignore any errors
  520.                          * and just continue. */
  521.                         (void)ret;
  522.                         prefaulted = 1;
  523.                 }
  524.  
  525.                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
  526.                                        user_data, page_do_bit17_swizzling,
  527.                                        needs_clflush);
  528.  
  529.                 mutex_lock(&dev->struct_mutex);
  530.  
  531. next_page:
  532.                 mark_page_accessed(page);
  533.  
  534.                 if (ret)
  535.                         goto out;
  536.  
  537.                 remain -= page_length;
  538.                 user_data += page_length;
  539.                 offset += page_length;
  540.         }
  541.  
  542. out:
  543.         i915_gem_object_unpin_pages(obj);
  544.  
  545.         return ret;
  546. }
  547.  
  548. /**
  549.  * Reads data from the object referenced by handle.
  550.  *
  551.  * On error, the contents of *data are undefined.
  552.  */
  553. int
  554. i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  555.                      struct drm_file *file)
  556. {
  557.         struct drm_i915_gem_pread *args = data;
  558.         struct drm_i915_gem_object *obj;
  559.         int ret = 0;
  560.  
  561.         if (args->size == 0)
  562.                 return 0;
  563.  
  564.         if (!access_ok(VERIFY_WRITE,
  565.                        to_user_ptr(args->data_ptr),
  566.                        args->size))
  567.                 return -EFAULT;
  568.  
  569.         ret = i915_mutex_lock_interruptible(dev);
  570.         if (ret)
  571.                 return ret;
  572.  
  573.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  574.         if (&obj->base == NULL) {
  575.                 ret = -ENOENT;
  576.                 goto unlock;
  577.         }
  578.  
  579.         /* Bounds check source.  */
  580.         if (args->offset > obj->base.size ||
  581.             args->size > obj->base.size - args->offset) {
  582.                 ret = -EINVAL;
  583.                 goto out;
  584.         }
  585.  
  586.         /* prime objects have no backing filp to GEM pread/pwrite
  587.          * pages from.
  588.          */
  589.         if (!obj->base.filp) {
  590.                 ret = -EINVAL;
  591.                 goto out;
  592.         }
  593.  
  594.         trace_i915_gem_object_pread(obj, args->offset, args->size);
  595.  
  596.         ret = i915_gem_shmem_pread(dev, obj, args, file);
  597.  
  598. out:
  599.         drm_gem_object_unreference(&obj->base);
  600. unlock:
  601.         mutex_unlock(&dev->struct_mutex);
  602.         return ret;
  603. }
  604.  
  605. /* This is the fast write path which cannot handle
  606.  * page faults in the source data
  607.  */
  608.  
  609. static inline int
  610. fast_user_write(struct io_mapping *mapping,
  611.                 loff_t page_base, int page_offset,
  612.                 char __user *user_data,
  613.                 int length)
  614. {
  615.         void __iomem *vaddr_atomic;
  616.         void *vaddr;
  617.         unsigned long unwritten;
  618.  
  619.         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
  620.         /* We can use the cpu mem copy function because this is X86. */
  621.         vaddr = (void __force*)vaddr_atomic + page_offset;
  622.         unwritten = __copy_from_user_inatomic_nocache(vaddr,
  623.                                                       user_data, length);
  624.         io_mapping_unmap_atomic(vaddr_atomic);
  625.         return unwritten;
  626. }
  627. #endif
  628.  
  629. #define offset_in_page(p)       ((unsigned long)(p) & ~PAGE_MASK)
  630. /**
  631.  * This is the fast pwrite path, where we copy the data directly from the
  632.  * user into the GTT, uncached.
  633.  */
  634. static int
  635. i915_gem_gtt_pwrite_fast(struct drm_device *dev,
  636.                          struct drm_i915_gem_object *obj,
  637.                          struct drm_i915_gem_pwrite *args,
  638.                          struct drm_file *file)
  639. {
  640.         drm_i915_private_t *dev_priv = dev->dev_private;
  641.         ssize_t remain;
  642.         loff_t offset, page_base;
  643.         char __user *user_data;
  644.         int page_offset, page_length, ret;
  645.     char *vaddr;
  646.  
  647.         ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
  648.         if (ret)
  649.                 goto out;
  650.  
  651.         ret = i915_gem_object_set_to_gtt_domain(obj, true);
  652.         if (ret)
  653.                 goto out_unpin;
  654.  
  655.         ret = i915_gem_object_put_fence(obj);
  656.         if (ret)
  657.                 goto out_unpin;
  658.  
  659.     vaddr = AllocKernelSpace(4096);
  660.     if(vaddr == NULL)
  661.     {
  662.         ret = -ENOSPC;
  663.         goto out_unpin;
  664.     };
  665.  
  666.         user_data = (char __user *) (uintptr_t) args->data_ptr;
  667.         remain = args->size;
  668.  
  669.         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
  670.  
  671.         while (remain > 0) {
  672.                 /* Operation in this page
  673.                  *
  674.                  * page_base = page offset within aperture
  675.                  * page_offset = offset within page
  676.                  * page_length = bytes to copy for this page
  677.                  */
  678.                 page_base = offset & PAGE_MASK;
  679.                 page_offset = offset_in_page(offset);
  680.                 page_length = remain;
  681.                 if ((page_offset + remain) > PAGE_SIZE)
  682.                         page_length = PAGE_SIZE - page_offset;
  683.  
  684.         MapPage(vaddr, page_base, PG_SW|PG_NOCACHE);
  685.  
  686.         memcpy(vaddr+page_offset, user_data, page_length);
  687.  
  688.                 remain -= page_length;
  689.                 user_data += page_length;
  690.                 offset += page_length;
  691.         }
  692.  
  693.     FreeKernelSpace(vaddr);
  694.  
  695. out_unpin:
  696.         i915_gem_object_unpin(obj);
  697. out:
  698.         return ret;
  699. }
  700.  
  701. /* Per-page copy function for the shmem pwrite fastpath.
  702.  * Flushes invalid cachelines before writing to the target if
  703.  * needs_clflush_before is set and flushes out any written cachelines after
  704.  * writing if needs_clflush is set. */
  705. static int
  706. shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
  707.                   char __user *user_data,
  708.                   bool page_do_bit17_swizzling,
  709.                   bool needs_clflush_before,
  710.                   bool needs_clflush_after)
  711. {
  712.         char *vaddr;
  713.         int ret = 0;
  714.  
  715.         if (unlikely(page_do_bit17_swizzling))
  716.                 return -EINVAL;
  717.  
  718.         vaddr = (char *)MapIoMem((addr_t)page, 4096, PG_SW);
  719.         if (needs_clflush_before)
  720.                 drm_clflush_virt_range(vaddr + shmem_page_offset,
  721.                                        page_length);
  722.         memcpy(vaddr + shmem_page_offset,
  723.                                                 user_data,
  724.                                                 page_length);
  725.         if (needs_clflush_after)
  726.                 drm_clflush_virt_range(vaddr + shmem_page_offset,
  727.                                        page_length);
  728.         FreeKernelSpace(vaddr);
  729.  
  730.         return ret ? -EFAULT : 0;
  731. }
  732. #if 0
  733.  
  734. /* Only difference to the fast-path function is that this can handle bit17
  735.  * and uses non-atomic copy and kmap functions. */
  736. static int
  737. shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
  738.                   char __user *user_data,
  739.                   bool page_do_bit17_swizzling,
  740.                   bool needs_clflush_before,
  741.                   bool needs_clflush_after)
  742. {
  743.         char *vaddr;
  744.         int ret;
  745.  
  746.         vaddr = kmap(page);
  747.         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
  748.                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
  749.                                              page_length,
  750.                                              page_do_bit17_swizzling);
  751.         if (page_do_bit17_swizzling)
  752.                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
  753.                                                 user_data,
  754.                                                 page_length);
  755.         else
  756.                 ret = __copy_from_user(vaddr + shmem_page_offset,
  757.                                        user_data,
  758.                                        page_length);
  759.         if (needs_clflush_after)
  760.                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
  761.                                              page_length,
  762.                                              page_do_bit17_swizzling);
  763.         kunmap(page);
  764.  
  765.         return ret ? -EFAULT : 0;
  766. }
  767. #endif
  768.  
  769.  
  770. static int
  771. i915_gem_shmem_pwrite(struct drm_device *dev,
  772.                       struct drm_i915_gem_object *obj,
  773.                       struct drm_i915_gem_pwrite *args,
  774.                       struct drm_file *file)
  775. {
  776.         ssize_t remain;
  777.         loff_t offset;
  778.         char __user *user_data;
  779.         int shmem_page_offset, page_length, ret = 0;
  780.         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
  781.         int hit_slowpath = 0;
  782.         int needs_clflush_after = 0;
  783.         int needs_clflush_before = 0;
  784.         struct sg_page_iter sg_iter;
  785.  
  786.         user_data = to_user_ptr(args->data_ptr);
  787.         remain = args->size;
  788.  
  789.         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
  790.  
  791.         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
  792.                 /* If we're not in the cpu write domain, set ourself into the gtt
  793.                  * write domain and manually flush cachelines (if required). This
  794.                  * optimizes for the case when the gpu will use the data
  795.                  * right away and we therefore have to clflush anyway. */
  796.                 needs_clflush_after = cpu_write_needs_clflush(obj);
  797.                 if (i915_gem_obj_bound_any(obj)) {
  798.                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
  799.                         if (ret)
  800.                                 return ret;
  801.                 }
  802.         }
  803.         /* Same trick applies to invalidate partially written cachelines read
  804.          * before writing. */
  805.         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
  806.                 needs_clflush_before =
  807.                         !cpu_cache_is_coherent(dev, obj->cache_level);
  808.  
  809.         ret = i915_gem_object_get_pages(obj);
  810.         if (ret)
  811.                 return ret;
  812.  
  813.         i915_gem_object_pin_pages(obj);
  814.  
  815.         offset = args->offset;
  816.         obj->dirty = 1;
  817.  
  818.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
  819.                          offset >> PAGE_SHIFT) {
  820.                 struct page *page = sg_page_iter_page(&sg_iter);
  821.                 int partial_cacheline_write;
  822.  
  823.                 if (remain <= 0)
  824.                         break;
  825.  
  826.                 /* Operation in this page
  827.                  *
  828.                  * shmem_page_offset = offset within page in shmem file
  829.                  * page_length = bytes to copy for this page
  830.                  */
  831.                 shmem_page_offset = offset_in_page(offset);
  832.  
  833.                 page_length = remain;
  834.                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
  835.                         page_length = PAGE_SIZE - shmem_page_offset;
  836.  
  837.                 /* If we don't overwrite a cacheline completely we need to be
  838.                  * careful to have up-to-date data by first clflushing. Don't
  839.                  * overcomplicate things and flush the entire patch. */
  840.                 partial_cacheline_write = needs_clflush_before &&
  841.                         ((shmem_page_offset | page_length)
  842.                                 & (x86_clflush_size - 1));
  843.  
  844.                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
  845.                         (page_to_phys(page) & (1 << 17)) != 0;
  846.  
  847.                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
  848.                                         user_data, page_do_bit17_swizzling,
  849.                                         partial_cacheline_write,
  850.                                         needs_clflush_after);
  851.                 if (ret == 0)
  852.                         goto next_page;
  853.  
  854.                 hit_slowpath = 1;
  855.                 mutex_unlock(&dev->struct_mutex);
  856.                 dbgprintf("%s need shmem_pwrite_slow\n",__FUNCTION__);
  857.  
  858. //              ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
  859. //                                      user_data, page_do_bit17_swizzling,
  860. //                                      partial_cacheline_write,
  861. //                                      needs_clflush_after);
  862.  
  863.                 mutex_lock(&dev->struct_mutex);
  864.  
  865. next_page:
  866.  
  867.                 if (ret)
  868.                         goto out;
  869.  
  870.                 remain -= page_length;
  871.                 user_data += page_length;
  872.                 offset += page_length;
  873.         }
  874.  
  875. out:
  876.         i915_gem_object_unpin_pages(obj);
  877.  
  878.         if (hit_slowpath) {
  879.                 /*
  880.                  * Fixup: Flush cpu caches in case we didn't flush the dirty
  881.                  * cachelines in-line while writing and the object moved
  882.                  * out of the cpu write domain while we've dropped the lock.
  883.                  */
  884.                 if (!needs_clflush_after &&
  885.                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
  886.                         if (i915_gem_clflush_object(obj, obj->pin_display))
  887.                         i915_gem_chipset_flush(dev);
  888.                 }
  889.         }
  890.  
  891.         if (needs_clflush_after)
  892.                 i915_gem_chipset_flush(dev);
  893.  
  894.         return ret;
  895. }
  896.  
  897. /**
  898.  * Writes data to the object referenced by handle.
  899.  *
  900.  * On error, the contents of the buffer that were to be modified are undefined.
  901.  */
  902. int
  903. i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  904.                       struct drm_file *file)
  905. {
  906.         struct drm_i915_gem_pwrite *args = data;
  907.         struct drm_i915_gem_object *obj;
  908.         int ret;
  909.  
  910.         if (args->size == 0)
  911.                 return 0;
  912.  
  913.      if(args->handle == -2)
  914.      {
  915.         printf("%s handle %d\n", __FUNCTION__, args->handle);
  916.         return 0;
  917.      }
  918.  
  919.         ret = i915_mutex_lock_interruptible(dev);
  920.         if (ret)
  921.                 return ret;
  922.  
  923.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  924.         if (&obj->base == NULL) {
  925.                 ret = -ENOENT;
  926.                 goto unlock;
  927.         }
  928.  
  929.         /* Bounds check destination. */
  930.         if (args->offset > obj->base.size ||
  931.             args->size > obj->base.size - args->offset) {
  932.                 ret = -EINVAL;
  933.                 goto out;
  934.         }
  935.  
  936.         /* prime objects have no backing filp to GEM pread/pwrite
  937.          * pages from.
  938.          */
  939.         if (!obj->base.filp) {
  940.                 ret = -EINVAL;
  941.                 goto out;
  942.         }
  943.  
  944.         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
  945.  
  946.         ret = -EFAULT;
  947.         /* We can only do the GTT pwrite on untiled buffers, as otherwise
  948.          * it would end up going through the fenced access, and we'll get
  949.          * different detiling behavior between reading and writing.
  950.          * pread/pwrite currently are reading and writing from the CPU
  951.          * perspective, requiring manual detiling by the client.
  952.          */
  953. //   if (obj->phys_obj) {
  954. //       ret = i915_gem_phys_pwrite(dev, obj, args, file);
  955. //       goto out;
  956. //   }
  957.  
  958.         if (obj->tiling_mode == I915_TILING_NONE &&
  959.             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
  960.             cpu_write_needs_clflush(obj)) {
  961.                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
  962.                 /* Note that the gtt paths might fail with non-page-backed user
  963.                  * pointers (e.g. gtt mappings when moving data between
  964.                  * textures). Fallback to the shmem path in that case. */
  965.         }
  966.  
  967.         if (ret == -EFAULT || ret == -ENOSPC)
  968.        ret = i915_gem_shmem_pwrite(dev, obj, args, file);
  969.  
  970. out:
  971.         drm_gem_object_unreference(&obj->base);
  972. unlock:
  973.         mutex_unlock(&dev->struct_mutex);
  974.         return ret;
  975. }
  976.  
  977. int
  978. i915_gem_check_wedge(struct i915_gpu_error *error,
  979.                      bool interruptible)
  980. {
  981.         if (i915_reset_in_progress(error)) {
  982.                 /* Non-interruptible callers can't handle -EAGAIN, hence return
  983.                  * -EIO unconditionally for these. */
  984.                 if (!interruptible)
  985.                         return -EIO;
  986.  
  987.                 /* Recovery complete, but the reset failed ... */
  988.                 if (i915_terminally_wedged(error))
  989.                         return -EIO;
  990.  
  991.                 return -EAGAIN;
  992.         }
  993.  
  994.         return 0;
  995. }
  996.  
  997. /*
  998.  * Compare seqno against outstanding lazy request. Emit a request if they are
  999.  * equal.
  1000.  */
  1001. static int
  1002. i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
  1003. {
  1004.         int ret;
  1005.  
  1006.         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
  1007.  
  1008.         ret = 0;
  1009.         if (seqno == ring->outstanding_lazy_request)
  1010.                 ret = i915_add_request(ring, NULL);
  1011.  
  1012.         return ret;
  1013. }
  1014.  
  1015. /**
  1016.  * __wait_seqno - wait until execution of seqno has finished
  1017.  * @ring: the ring expected to report seqno
  1018.  * @seqno: duh!
  1019.  * @reset_counter: reset sequence associated with the given seqno
  1020.  * @interruptible: do an interruptible wait (normally yes)
  1021.  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
  1022.  *
  1023.  * Note: It is of utmost importance that the passed in seqno and reset_counter
  1024.  * values have been read by the caller in an smp safe manner. Where read-side
  1025.  * locks are involved, it is sufficient to read the reset_counter before
  1026.  * unlocking the lock that protects the seqno. For lockless tricks, the
  1027.  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
  1028.  * inserted.
  1029.  *
  1030.  * Returns 0 if the seqno was found within the alloted time. Else returns the
  1031.  * errno with remaining time filled in timeout argument.
  1032.  */
  1033. static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
  1034.                         unsigned reset_counter,
  1035.                         bool interruptible, struct timespec *timeout)
  1036. {
  1037.         drm_i915_private_t *dev_priv = ring->dev->dev_private;
  1038.         struct timespec before, now, wait_time={1,0};
  1039.         unsigned long timeout_jiffies;
  1040.         long end;
  1041.         bool wait_forever = true;
  1042.         int ret;
  1043.  
  1044.         WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
  1045.  
  1046.         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
  1047.                 return 0;
  1048.  
  1049.         trace_i915_gem_request_wait_begin(ring, seqno);
  1050.  
  1051.         if (timeout != NULL) {
  1052.                 wait_time = *timeout;
  1053.                 wait_forever = false;
  1054.         }
  1055.  
  1056.         timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
  1057.  
  1058.         if (WARN_ON(!ring->irq_get(ring)))
  1059.                 return -ENODEV;
  1060.  
  1061.     /* Record current time in case interrupted by signal, or wedged * */
  1062.         getrawmonotonic(&before);
  1063.  
  1064. #define EXIT_COND \
  1065.         (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
  1066.          i915_reset_in_progress(&dev_priv->gpu_error) || \
  1067.          reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  1068.         do {
  1069.                 if (interruptible)
  1070.                         end = wait_event_interruptible_timeout(ring->irq_queue,
  1071.                                                                EXIT_COND,
  1072.                                                                timeout_jiffies);
  1073.                 else
  1074.                         end = wait_event_timeout(ring->irq_queue, EXIT_COND,
  1075.                                                  timeout_jiffies);
  1076.  
  1077.                 /* We need to check whether any gpu reset happened in between
  1078.                  * the caller grabbing the seqno and now ... */
  1079.                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  1080.                         end = -EAGAIN;
  1081.  
  1082.                 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
  1083.                  * gone. */
  1084.                 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
  1085.                 if (ret)
  1086.                         end = ret;
  1087.         } while (end == 0 && wait_forever);
  1088.  
  1089.         getrawmonotonic(&now);
  1090.  
  1091.         ring->irq_put(ring);
  1092.         trace_i915_gem_request_wait_end(ring, seqno);
  1093. #undef EXIT_COND
  1094.  
  1095.         if (timeout) {
  1096. //              struct timespec sleep_time = timespec_sub(now, before);
  1097. //              *timeout = timespec_sub(*timeout, sleep_time);
  1098.         }
  1099.  
  1100.         switch (end) {
  1101.         case -EIO:
  1102.         case -EAGAIN: /* Wedged */
  1103.         case -ERESTARTSYS: /* Signal */
  1104.                 return (int)end;
  1105.         case 0: /* Timeout */
  1106.                 return -ETIME;
  1107.         default: /* Completed */
  1108.                 WARN_ON(end < 0); /* We're not aware of other errors */
  1109.                 return 0;
  1110.         }
  1111. }
  1112.  
  1113. /**
  1114.  * Waits for a sequence number to be signaled, and cleans up the
  1115.  * request and object lists appropriately for that event.
  1116.  */
  1117. int
  1118. i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
  1119. {
  1120.         struct drm_device *dev = ring->dev;
  1121.         struct drm_i915_private *dev_priv = dev->dev_private;
  1122.         bool interruptible = dev_priv->mm.interruptible;
  1123.         int ret;
  1124.  
  1125.         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  1126.         BUG_ON(seqno == 0);
  1127.  
  1128.         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
  1129.         if (ret)
  1130.                 return ret;
  1131.  
  1132.         ret = i915_gem_check_olr(ring, seqno);
  1133.         if (ret)
  1134.                 return ret;
  1135.  
  1136.         return __wait_seqno(ring, seqno,
  1137.                             atomic_read(&dev_priv->gpu_error.reset_counter),
  1138.                             interruptible, NULL);
  1139. }
  1140.  
  1141. static int
  1142. i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
  1143.                                      struct intel_ring_buffer *ring)
  1144. {
  1145.         i915_gem_retire_requests_ring(ring);
  1146.  
  1147.         /* Manually manage the write flush as we may have not yet
  1148.          * retired the buffer.
  1149.          *
  1150.          * Note that the last_write_seqno is always the earlier of
  1151.          * the two (read/write) seqno, so if we haved successfully waited,
  1152.          * we know we have passed the last write.
  1153.          */
  1154.         obj->last_write_seqno = 0;
  1155.         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
  1156.  
  1157.         return 0;
  1158. }
  1159.  
  1160. /**
  1161.  * Ensures that all rendering to the object has completed and the object is
  1162.  * safe to unbind from the GTT or access from the CPU.
  1163.  */
  1164. static __must_check int
  1165. i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  1166.                                bool readonly)
  1167. {
  1168.         struct intel_ring_buffer *ring = obj->ring;
  1169.         u32 seqno;
  1170.         int ret;
  1171.  
  1172.         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
  1173.         if (seqno == 0)
  1174.                 return 0;
  1175.  
  1176.         ret = i915_wait_seqno(ring, seqno);
  1177.     if (ret)
  1178.         return ret;
  1179.  
  1180.         return i915_gem_object_wait_rendering__tail(obj, ring);
  1181. }
  1182.  
  1183. /* A nonblocking variant of the above wait. This is a highly dangerous routine
  1184.  * as the object state may change during this call.
  1185.  */
  1186. static __must_check int
  1187. i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
  1188.                                             bool readonly)
  1189. {
  1190.         struct drm_device *dev = obj->base.dev;
  1191.         struct drm_i915_private *dev_priv = dev->dev_private;
  1192.         struct intel_ring_buffer *ring = obj->ring;
  1193.         unsigned reset_counter;
  1194.         u32 seqno;
  1195.         int ret;
  1196.  
  1197.         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
  1198.         BUG_ON(!dev_priv->mm.interruptible);
  1199.  
  1200.         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
  1201.         if (seqno == 0)
  1202.                 return 0;
  1203.  
  1204.         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
  1205.         if (ret)
  1206.                 return ret;
  1207.  
  1208.         ret = i915_gem_check_olr(ring, seqno);
  1209.         if (ret)
  1210.                 return ret;
  1211.  
  1212.         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  1213.         mutex_unlock(&dev->struct_mutex);
  1214.         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
  1215.         mutex_lock(&dev->struct_mutex);
  1216.         if (ret)
  1217.                 return ret;
  1218.  
  1219.         return i915_gem_object_wait_rendering__tail(obj, ring);
  1220. }
  1221.  
  1222. /**
  1223.  * Called when user space prepares to use an object with the CPU, either
  1224.  * through the mmap ioctl's mapping or a GTT mapping.
  1225.  */
  1226. int
  1227. i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1228.                           struct drm_file *file)
  1229. {
  1230.         struct drm_i915_gem_set_domain *args = data;
  1231.         struct drm_i915_gem_object *obj;
  1232.         uint32_t read_domains = args->read_domains;
  1233.         uint32_t write_domain = args->write_domain;
  1234.         int ret;
  1235.  
  1236.  
  1237.      if(args->handle == -2)
  1238.      {
  1239.         printf("%s handle %d\n", __FUNCTION__, args->handle);
  1240.         return 0;
  1241.      }
  1242.  
  1243.         /* Only handle setting domains to types used by the CPU. */
  1244.         if (write_domain & I915_GEM_GPU_DOMAINS)
  1245.                 return -EINVAL;
  1246.  
  1247.         if (read_domains & I915_GEM_GPU_DOMAINS)
  1248.                 return -EINVAL;
  1249.  
  1250.         /* Having something in the write domain implies it's in the read
  1251.          * domain, and only that read domain.  Enforce that in the request.
  1252.          */
  1253.         if (write_domain != 0 && read_domains != write_domain)
  1254.                 return -EINVAL;
  1255.  
  1256.         ret = i915_mutex_lock_interruptible(dev);
  1257.         if (ret)
  1258.                 return ret;
  1259.  
  1260.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
  1261.         if (&obj->base == NULL) {
  1262.                 ret = -ENOENT;
  1263.                 goto unlock;
  1264.         }
  1265.  
  1266.         /* Try to flush the object off the GPU without holding the lock.
  1267.          * We will repeat the flush holding the lock in the normal manner
  1268.          * to catch cases where we are gazumped.
  1269.          */
  1270.         ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
  1271.         if (ret)
  1272.                 goto unref;
  1273.  
  1274.         if (read_domains & I915_GEM_DOMAIN_GTT) {
  1275.                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
  1276.  
  1277.                 /* Silently promote "you're not bound, there was nothing to do"
  1278.                  * to success, since the client was just asking us to
  1279.                  * make sure everything was done.
  1280.                  */
  1281.                 if (ret == -EINVAL)
  1282.                         ret = 0;
  1283.         } else {
  1284.                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
  1285.         }
  1286.  
  1287. unref:
  1288.         drm_gem_object_unreference(&obj->base);
  1289. unlock:
  1290.         mutex_unlock(&dev->struct_mutex);
  1291.         return ret;
  1292. }
  1293.  
  1294.  
  1295.  
  1296.  
  1297.  
  1298.  
  1299. /**
  1300.  * Maps the contents of an object, returning the address it is mapped
  1301.  * into.
  1302.  *
  1303.  * While the mapping holds a reference on the contents of the object, it doesn't
  1304.  * imply a ref on the object itself.
  1305.  */
  1306. int
  1307. i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1308.                     struct drm_file *file)
  1309. {
  1310.         struct drm_i915_gem_mmap *args = data;
  1311.         struct drm_gem_object *obj;
  1312.         unsigned long addr = 0;
  1313.  
  1314.      if(args->handle == -2)
  1315.      {
  1316.         printf("%s handle %d\n", __FUNCTION__, args->handle);
  1317.         return 0;
  1318.      }
  1319.  
  1320.         obj = drm_gem_object_lookup(dev, file, args->handle);
  1321.         if (obj == NULL)
  1322.                 return -ENOENT;
  1323.  
  1324.         /* prime objects have no backing filp to GEM mmap
  1325.          * pages from.
  1326.          */
  1327.         if (!obj->filp) {
  1328.                 drm_gem_object_unreference_unlocked(obj);
  1329.                 return -EINVAL;
  1330.         }
  1331.  
  1332.     addr = vm_mmap(obj->filp, 0, args->size,
  1333.               PROT_READ | PROT_WRITE, MAP_SHARED,
  1334.               args->offset);
  1335.         drm_gem_object_unreference_unlocked(obj);
  1336.     if (IS_ERR((void *)addr))
  1337.         return addr;
  1338.  
  1339.         args->addr_ptr = (uint64_t) addr;
  1340.  
  1341.     return 0;
  1342. }
  1343.  
  1344.  
  1345.  
  1346.  
  1347.  
  1348.  
  1349.  
  1350.  
  1351.  
  1352.  
  1353.  
  1354.  
  1355.  
  1356. /**
  1357.  * i915_gem_release_mmap - remove physical page mappings
  1358.  * @obj: obj in question
  1359.  *
  1360.  * Preserve the reservation of the mmapping with the DRM core code, but
  1361.  * relinquish ownership of the pages back to the system.
  1362.  *
  1363.  * It is vital that we remove the page mapping if we have mapped a tiled
  1364.  * object through the GTT and then lose the fence register due to
  1365.  * resource pressure. Similarly if the object has been moved out of the
  1366.  * aperture, than pages mapped into userspace must be revoked. Removing the
  1367.  * mapping will then trigger a page fault on the next user access, allowing
  1368.  * fixup by i915_gem_fault().
  1369.  */
  1370. void
  1371. i915_gem_release_mmap(struct drm_i915_gem_object *obj)
  1372. {
  1373.         if (!obj->fault_mappable)
  1374.                 return;
  1375.  
  1376. //      drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping);
  1377.         obj->fault_mappable = false;
  1378. }
  1379.  
  1380. uint32_t
  1381. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
  1382. {
  1383.         uint32_t gtt_size;
  1384.  
  1385.         if (INTEL_INFO(dev)->gen >= 4 ||
  1386.             tiling_mode == I915_TILING_NONE)
  1387.                 return size;
  1388.  
  1389.         /* Previous chips need a power-of-two fence region when tiling */
  1390.         if (INTEL_INFO(dev)->gen == 3)
  1391.                 gtt_size = 1024*1024;
  1392.         else
  1393.                 gtt_size = 512*1024;
  1394.  
  1395.         while (gtt_size < size)
  1396.                 gtt_size <<= 1;
  1397.  
  1398.         return gtt_size;
  1399. }
  1400.  
  1401. /**
  1402.  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
  1403.  * @obj: object to check
  1404.  *
  1405.  * Return the required GTT alignment for an object, taking into account
  1406.  * potential fence register mapping.
  1407.  */
  1408. uint32_t
  1409. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  1410.                            int tiling_mode, bool fenced)
  1411. {
  1412.         /*
  1413.          * Minimum alignment is 4k (GTT page size), but might be greater
  1414.          * if a fence register is needed for the object.
  1415.          */
  1416.         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
  1417.             tiling_mode == I915_TILING_NONE)
  1418.                 return 4096;
  1419.  
  1420.         /*
  1421.          * Previous chips need to be aligned to the size of the smallest
  1422.          * fence register that can contain the object.
  1423.          */
  1424.         return i915_gem_get_gtt_size(dev, size, tiling_mode);
  1425. }
  1426.  
  1427. /**
  1428.  * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
  1429.  *                                       unfenced object
  1430.  * @dev: the device
  1431.  * @size: size of the object
  1432.  * @tiling_mode: tiling mode of the object
  1433.  *
  1434.  * Return the required GTT alignment for an object, only taking into account
  1435.  * unfenced tiled surface requirements.
  1436.  */
  1437. uint32_t
  1438. i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
  1439.                                     uint32_t size,
  1440.                                     int tiling_mode)
  1441. {
  1442.         /*
  1443.          * Minimum alignment is 4k (GTT page size) for sane hw.
  1444.          */
  1445.         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
  1446.             tiling_mode == I915_TILING_NONE)
  1447.                 return 4096;
  1448.  
  1449.         /* Previous hardware however needs to be aligned to a power-of-two
  1450.          * tile height. The simplest method for determining this is to reuse
  1451.          * the power-of-tile object size.
  1452.          */
  1453.         return i915_gem_get_gtt_size(dev, size, tiling_mode);
  1454. }
  1455.  
  1456. int
  1457. i915_gem_mmap_gtt(struct drm_file *file,
  1458.           struct drm_device *dev,
  1459.           uint32_t handle,
  1460.           uint64_t *offset)
  1461. {
  1462.     struct drm_i915_private *dev_priv = dev->dev_private;
  1463.     struct drm_i915_gem_object *obj;
  1464.     unsigned long pfn;
  1465.     char *mem, *ptr;
  1466.     int ret;
  1467.  
  1468.     ret = i915_mutex_lock_interruptible(dev);
  1469.     if (ret)
  1470.         return ret;
  1471.  
  1472.     obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  1473.     if (&obj->base == NULL) {
  1474.         ret = -ENOENT;
  1475.         goto unlock;
  1476.     }
  1477.  
  1478.     if (obj->base.size > dev_priv->gtt.mappable_end) {
  1479.         ret = -E2BIG;
  1480.         goto out;
  1481.     }
  1482.  
  1483.     if (obj->madv != I915_MADV_WILLNEED) {
  1484.         DRM_ERROR("Attempting to mmap a purgeable buffer\n");
  1485.         ret = -EINVAL;
  1486.         goto out;
  1487.     }
  1488.     /* Now bind it into the GTT if needed */
  1489.     ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
  1490.     if (ret)
  1491.         goto out;
  1492.  
  1493.     ret = i915_gem_object_set_to_gtt_domain(obj, 1);
  1494.     if (ret)
  1495.         goto unpin;
  1496.  
  1497.     ret = i915_gem_object_get_fence(obj);
  1498.     if (ret)
  1499.         goto unpin;
  1500.  
  1501.     obj->fault_mappable = true;
  1502.  
  1503.     pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
  1504.  
  1505.     /* Finally, remap it using the new GTT offset */
  1506.  
  1507.     mem = UserAlloc(obj->base.size);
  1508.     if(unlikely(mem == NULL))
  1509.     {
  1510.         ret = -ENOMEM;
  1511.         goto unpin;
  1512.     }
  1513.  
  1514.     for(ptr = mem; ptr < mem + obj->base.size; ptr+= 4096, pfn+= 4096)
  1515.         MapPage(ptr, pfn, PG_SHARED|PG_UW);
  1516.  
  1517. unpin:
  1518.     i915_gem_object_unpin(obj);
  1519.  
  1520.  
  1521.     *offset = mem;
  1522.  
  1523. out:
  1524.     drm_gem_object_unreference(&obj->base);
  1525. unlock:
  1526.     mutex_unlock(&dev->struct_mutex);
  1527.     return ret;
  1528. }
  1529.  
  1530. /**
  1531.  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
  1532.  * @dev: DRM device
  1533.  * @data: GTT mapping ioctl data
  1534.  * @file: GEM object info
  1535.  *
  1536.  * Simply returns the fake offset to userspace so it can mmap it.
  1537.  * The mmap call will end up in drm_gem_mmap(), which will set things
  1538.  * up so we can get faults in the handler above.
  1539.  *
  1540.  * The fault handler will take care of binding the object into the GTT
  1541.  * (since it may have been evicted to make room for something), allocating
  1542.  * a fence register, and mapping the appropriate aperture address into
  1543.  * userspace.
  1544.  */
  1545. int
  1546. i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1547.             struct drm_file *file)
  1548. {
  1549.     struct drm_i915_gem_mmap_gtt *args = data;
  1550.  
  1551.     return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
  1552. }
  1553.  
  1554. /* Immediately discard the backing storage */
  1555. static void
  1556. i915_gem_object_truncate(struct drm_i915_gem_object *obj)
  1557. {
  1558. //      struct inode *inode;
  1559.  
  1560. //      i915_gem_object_free_mmap_offset(obj);
  1561.  
  1562.         if (obj->base.filp == NULL)
  1563.                 return;
  1564.  
  1565.         /* Our goal here is to return as much of the memory as
  1566.          * is possible back to the system as we are called from OOM.
  1567.          * To do this we must instruct the shmfs to drop all of its
  1568.          * backing pages, *now*.
  1569.          */
  1570. //      inode = obj->base.filp->f_path.dentry->d_inode;
  1571. //      shmem_truncate_range(inode, 0, (loff_t)-1);
  1572.  
  1573.         obj->madv = __I915_MADV_PURGED;
  1574. }
  1575.  
  1576. static inline int
  1577. i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
  1578. {
  1579.         return obj->madv == I915_MADV_DONTNEED;
  1580. }
  1581.  
  1582. static void
  1583. i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
  1584. {
  1585.         struct sg_page_iter sg_iter;
  1586.         int ret;
  1587.  
  1588.         BUG_ON(obj->madv == __I915_MADV_PURGED);
  1589.  
  1590.         ret = i915_gem_object_set_to_cpu_domain(obj, true);
  1591.         if (ret) {
  1592.                 /* In the event of a disaster, abandon all caches and
  1593.                  * hope for the best.
  1594.                  */
  1595.                 WARN_ON(ret != -EIO);
  1596.                 i915_gem_clflush_object(obj, true);
  1597.                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
  1598.         }
  1599.  
  1600.         if (obj->madv == I915_MADV_DONTNEED)
  1601.                 obj->dirty = 0;
  1602.  
  1603.         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
  1604.                 struct page *page = sg_page_iter_page(&sg_iter);
  1605.  
  1606.         page_cache_release(page);
  1607.         }
  1608.     //DRM_DEBUG_KMS("%s release %d pages\n", __FUNCTION__, page_count);
  1609.  
  1610.     obj->dirty = 0;
  1611.  
  1612.         sg_free_table(obj->pages);
  1613.         kfree(obj->pages);
  1614. }
  1615.  
  1616. int
  1617. i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
  1618. {
  1619.         const struct drm_i915_gem_object_ops *ops = obj->ops;
  1620.  
  1621.         if (obj->pages == NULL)
  1622.                 return 0;
  1623.  
  1624.         if (obj->pages_pin_count)
  1625.                 return -EBUSY;
  1626.  
  1627.         BUG_ON(i915_gem_obj_bound_any(obj));
  1628.  
  1629.         /* ->put_pages might need to allocate memory for the bit17 swizzle
  1630.          * array, hence protect them from being reaped by removing them from gtt
  1631.          * lists early. */
  1632.         list_del(&obj->global_list);
  1633.  
  1634.         ops->put_pages(obj);
  1635.         obj->pages = NULL;
  1636.  
  1637.         if (i915_gem_object_is_purgeable(obj))
  1638.                 i915_gem_object_truncate(obj);
  1639.  
  1640.         return 0;
  1641. }
  1642.  
  1643.  
  1644.  
  1645.  
  1646.  
  1647.  
  1648.  
  1649.  
  1650. static int
  1651. i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
  1652. {
  1653.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1654.     int page_count, i;
  1655.     struct sg_table *st;
  1656.         struct scatterlist *sg;
  1657.         struct sg_page_iter sg_iter;
  1658.         struct page *page;
  1659.         unsigned long last_pfn = 0;     /* suppress gcc warning */
  1660.         gfp_t gfp;
  1661.  
  1662.         /* Assert that the object is not currently in any GPU domain. As it
  1663.          * wasn't in the GTT, there shouldn't be any way it could have been in
  1664.          * a GPU cache
  1665.          */
  1666.         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
  1667.         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
  1668.  
  1669.         st = kmalloc(sizeof(*st), GFP_KERNEL);
  1670.         if (st == NULL)
  1671.                 return -ENOMEM;
  1672.  
  1673.         page_count = obj->base.size / PAGE_SIZE;
  1674.         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
  1675.                 kfree(st);
  1676.         FAIL();
  1677.                 return -ENOMEM;
  1678.         }
  1679.  
  1680.         /* Get the list of pages out of our struct file.  They'll be pinned
  1681.          * at this point until we release them.
  1682.          *
  1683.          * Fail silently without starting the shrinker
  1684.          */
  1685.         sg = st->sgl;
  1686.         st->nents = 0;
  1687.         for (i = 0; i < page_count; i++) {
  1688.         page = shmem_read_mapping_page_gfp(obj->base.filp, i, gfp);
  1689.                 if (IS_ERR(page)) {
  1690.             dbgprintf("%s invalid page %p\n", __FUNCTION__, page);
  1691.                         goto err_pages;
  1692.  
  1693.                 }
  1694.  
  1695.                 if (!i || page_to_pfn(page) != last_pfn + 1) {
  1696.                         if (i)
  1697.                                 sg = sg_next(sg);
  1698.                         st->nents++;
  1699.                 sg_set_page(sg, page, PAGE_SIZE, 0);
  1700.                 } else {
  1701.                         sg->length += PAGE_SIZE;
  1702.                 }
  1703.                 last_pfn = page_to_pfn(page);
  1704.         }
  1705.  
  1706.                 sg_mark_end(sg);
  1707.         obj->pages = st;
  1708.  
  1709.         return 0;
  1710.  
  1711. err_pages:
  1712.         sg_mark_end(sg);
  1713.         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
  1714.                 page_cache_release(sg_page_iter_page(&sg_iter));
  1715.         sg_free_table(st);
  1716.         kfree(st);
  1717.     FAIL();
  1718.         return PTR_ERR(page);
  1719. }
  1720.  
  1721. /* Ensure that the associated pages are gathered from the backing storage
  1722.  * and pinned into our object. i915_gem_object_get_pages() may be called
  1723.  * multiple times before they are released by a single call to
  1724.  * i915_gem_object_put_pages() - once the pages are no longer referenced
  1725.  * either as a result of memory pressure (reaping pages under the shrinker)
  1726.  * or as the object is itself released.
  1727.  */
  1728. int
  1729. i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
  1730. {
  1731.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1732.         const struct drm_i915_gem_object_ops *ops = obj->ops;
  1733.         int ret;
  1734.  
  1735.         if (obj->pages)
  1736.                 return 0;
  1737.  
  1738.         BUG_ON(obj->pages_pin_count);
  1739.  
  1740.         ret = ops->get_pages(obj);
  1741.         if (ret)
  1742.                 return ret;
  1743.  
  1744.         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
  1745.     return 0;
  1746. }
  1747.  
  1748. void
  1749. i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1750.                                struct intel_ring_buffer *ring)
  1751. {
  1752.         struct drm_device *dev = obj->base.dev;
  1753.         struct drm_i915_private *dev_priv = dev->dev_private;
  1754.         u32 seqno = intel_ring_get_seqno(ring);
  1755.  
  1756.         BUG_ON(ring == NULL);
  1757.         if (obj->ring != ring && obj->last_write_seqno) {
  1758.                 /* Keep the seqno relative to the current ring */
  1759.                 obj->last_write_seqno = seqno;
  1760.         }
  1761.         obj->ring = ring;
  1762.  
  1763.         /* Add a reference if we're newly entering the active list. */
  1764.         if (!obj->active) {
  1765.                 drm_gem_object_reference(&obj->base);
  1766.                 obj->active = 1;
  1767.         }
  1768.  
  1769.         list_move_tail(&obj->ring_list, &ring->active_list);
  1770.  
  1771.         obj->last_read_seqno = seqno;
  1772.  
  1773.         if (obj->fenced_gpu_access) {
  1774.                 obj->last_fenced_seqno = seqno;
  1775.  
  1776.                 /* Bump MRU to take account of the delayed flush */
  1777.                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1778.                 struct drm_i915_fence_reg *reg;
  1779.  
  1780.                 reg = &dev_priv->fence_regs[obj->fence_reg];
  1781.                         list_move_tail(&reg->lru_list,
  1782.                                        &dev_priv->mm.fence_list);
  1783.                 }
  1784.         }
  1785. }
  1786.  
  1787. static void
  1788. i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
  1789. {
  1790.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1791.         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
  1792.         struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
  1793.  
  1794.         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
  1795.         BUG_ON(!obj->active);
  1796.  
  1797.         list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
  1798.  
  1799.         list_del_init(&obj->ring_list);
  1800.         obj->ring = NULL;
  1801.  
  1802.         obj->last_read_seqno = 0;
  1803.         obj->last_write_seqno = 0;
  1804.         obj->base.write_domain = 0;
  1805.  
  1806.         obj->last_fenced_seqno = 0;
  1807.         obj->fenced_gpu_access = false;
  1808.  
  1809.         obj->active = 0;
  1810.         drm_gem_object_unreference(&obj->base);
  1811.  
  1812.         WARN_ON(i915_verify_lists(dev));
  1813. }
  1814.  
  1815. static int
  1816. i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
  1817. {
  1818.         struct drm_i915_private *dev_priv = dev->dev_private;
  1819.         struct intel_ring_buffer *ring;
  1820.         int ret, i, j;
  1821.  
  1822.         /* Carefully retire all requests without writing to the rings */
  1823.         for_each_ring(ring, dev_priv, i) {
  1824.                 ret = intel_ring_idle(ring);
  1825.         if (ret)
  1826.                 return ret;
  1827.         }
  1828.         i915_gem_retire_requests(dev);
  1829.  
  1830.         /* Finally reset hw state */
  1831.         for_each_ring(ring, dev_priv, i) {
  1832.                 intel_ring_init_seqno(ring, seqno);
  1833.  
  1834.                 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
  1835.                         ring->sync_seqno[j] = 0;
  1836.         }
  1837.  
  1838.         return 0;
  1839. }
  1840.  
  1841. int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
  1842. {
  1843.         struct drm_i915_private *dev_priv = dev->dev_private;
  1844.         int ret;
  1845.  
  1846.         if (seqno == 0)
  1847.                 return -EINVAL;
  1848.  
  1849.         /* HWS page needs to be set less than what we
  1850.          * will inject to ring
  1851.          */
  1852.         ret = i915_gem_init_seqno(dev, seqno - 1);
  1853.         if (ret)
  1854.                 return ret;
  1855.  
  1856.         /* Carefully set the last_seqno value so that wrap
  1857.          * detection still works
  1858.          */
  1859.         dev_priv->next_seqno = seqno;
  1860.         dev_priv->last_seqno = seqno - 1;
  1861.         if (dev_priv->last_seqno == 0)
  1862.                 dev_priv->last_seqno--;
  1863.  
  1864.         return 0;
  1865. }
  1866.  
  1867. int
  1868. i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
  1869. {
  1870.         struct drm_i915_private *dev_priv = dev->dev_private;
  1871.  
  1872.         /* reserve 0 for non-seqno */
  1873.         if (dev_priv->next_seqno == 0) {
  1874.                 int ret = i915_gem_init_seqno(dev, 0);
  1875.                 if (ret)
  1876.                         return ret;
  1877.  
  1878.                 dev_priv->next_seqno = 1;
  1879.         }
  1880.  
  1881.         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
  1882.         return 0;
  1883. }
  1884.  
  1885. int __i915_add_request(struct intel_ring_buffer *ring,
  1886.                  struct drm_file *file,
  1887.                        struct drm_i915_gem_object *obj,
  1888.                  u32 *out_seqno)
  1889. {
  1890.         drm_i915_private_t *dev_priv = ring->dev->dev_private;
  1891.         struct drm_i915_gem_request *request;
  1892.         u32 request_ring_position, request_start;
  1893.         int was_empty;
  1894.         int ret;
  1895.  
  1896.         request_start = intel_ring_get_tail(ring);
  1897.         /*
  1898.          * Emit any outstanding flushes - execbuf can fail to emit the flush
  1899.          * after having emitted the batchbuffer command. Hence we need to fix
  1900.          * things up similar to emitting the lazy request. The difference here
  1901.          * is that the flush _must_ happen before the next request, no matter
  1902.          * what.
  1903.          */
  1904.    ret = intel_ring_flush_all_caches(ring);
  1905.    if (ret)
  1906.        return ret;
  1907.  
  1908.         request = kmalloc(sizeof(*request), GFP_KERNEL);
  1909.         if (request == NULL)
  1910.                 return -ENOMEM;
  1911.  
  1912.  
  1913.         /* Record the position of the start of the request so that
  1914.          * should we detect the updated seqno part-way through the
  1915.     * GPU processing the request, we never over-estimate the
  1916.          * position of the head.
  1917.          */
  1918.    request_ring_position = intel_ring_get_tail(ring);
  1919.  
  1920.         ret = ring->add_request(ring);
  1921.         if (ret) {
  1922.                 kfree(request);
  1923.                 return ret;
  1924.         }
  1925.  
  1926.         request->seqno = intel_ring_get_seqno(ring);
  1927.         request->ring = ring;
  1928.         request->head = request_start;
  1929.         request->tail = request_ring_position;
  1930.         request->ctx = ring->last_context;
  1931.         request->batch_obj = obj;
  1932.  
  1933.         /* Whilst this request exists, batch_obj will be on the
  1934.          * active_list, and so will hold the active reference. Only when this
  1935.          * request is retired will the the batch_obj be moved onto the
  1936.          * inactive_list and lose its active reference. Hence we do not need
  1937.          * to explicitly hold another reference here.
  1938.          */
  1939.  
  1940.         if (request->ctx)
  1941.                 i915_gem_context_reference(request->ctx);
  1942.  
  1943.     request->emitted_jiffies = GetTimerTicks();
  1944.         was_empty = list_empty(&ring->request_list);
  1945.         list_add_tail(&request->list, &ring->request_list);
  1946.         request->file_priv = NULL;
  1947.  
  1948.         if (file) {
  1949.                 struct drm_i915_file_private *file_priv = file->driver_priv;
  1950.  
  1951.                 spin_lock(&file_priv->mm.lock);
  1952.                 request->file_priv = file_priv;
  1953.                 list_add_tail(&request->client_list,
  1954.                               &file_priv->mm.request_list);
  1955.                 spin_unlock(&file_priv->mm.lock);
  1956.         }
  1957.  
  1958.         trace_i915_gem_request_add(ring, request->seqno);
  1959.         ring->outstanding_lazy_request = 0;
  1960.  
  1961.         if (!dev_priv->ums.mm_suspended) {
  1962. //              i915_queue_hangcheck(ring->dev);
  1963.  
  1964.        if (was_empty) {
  1965.            queue_delayed_work(dev_priv->wq,
  1966.                                            &dev_priv->mm.retire_work,
  1967.                                            round_jiffies_up_relative(HZ));
  1968.            intel_mark_busy(dev_priv->dev);
  1969.        }
  1970.    }
  1971.  
  1972.         if (out_seqno)
  1973.                 *out_seqno = request->seqno;
  1974.         return 0;
  1975. }
  1976.  
  1977. static inline void
  1978. i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
  1979. {
  1980.         struct drm_i915_file_private *file_priv = request->file_priv;
  1981.  
  1982.         if (!file_priv)
  1983.                 return;
  1984.  
  1985.         spin_lock(&file_priv->mm.lock);
  1986.         if (request->file_priv) {
  1987.                 list_del(&request->client_list);
  1988.                 request->file_priv = NULL;
  1989.         }
  1990.         spin_unlock(&file_priv->mm.lock);
  1991. }
  1992.  
  1993. static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
  1994.                                     struct i915_address_space *vm)
  1995. {
  1996.         if (acthd >= i915_gem_obj_offset(obj, vm) &&
  1997.             acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
  1998.                 return true;
  1999.  
  2000.         return false;
  2001. }
  2002.  
  2003. static bool i915_head_inside_request(const u32 acthd_unmasked,
  2004.                                      const u32 request_start,
  2005.                                      const u32 request_end)
  2006. {
  2007.         const u32 acthd = acthd_unmasked & HEAD_ADDR;
  2008.  
  2009.         if (request_start < request_end) {
  2010.                 if (acthd >= request_start && acthd < request_end)
  2011.                         return true;
  2012.         } else if (request_start > request_end) {
  2013.                 if (acthd >= request_start || acthd < request_end)
  2014.                         return true;
  2015.         }
  2016.  
  2017.         return false;
  2018. }
  2019.  
  2020. static struct i915_address_space *
  2021. request_to_vm(struct drm_i915_gem_request *request)
  2022. {
  2023.         struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
  2024.         struct i915_address_space *vm;
  2025.  
  2026.         vm = &dev_priv->gtt.base;
  2027.  
  2028.         return vm;
  2029. }
  2030.  
  2031. static bool i915_request_guilty(struct drm_i915_gem_request *request,
  2032.                                 const u32 acthd, bool *inside)
  2033. {
  2034.         /* There is a possibility that unmasked head address
  2035.          * pointing inside the ring, matches the batch_obj address range.
  2036.          * However this is extremely unlikely.
  2037.          */
  2038.         if (request->batch_obj) {
  2039.                 if (i915_head_inside_object(acthd, request->batch_obj,
  2040.                                             request_to_vm(request))) {
  2041.                         *inside = true;
  2042.                         return true;
  2043.                 }
  2044.         }
  2045.  
  2046.         if (i915_head_inside_request(acthd, request->head, request->tail)) {
  2047.                 *inside = false;
  2048.                 return true;
  2049.         }
  2050.  
  2051.         return false;
  2052. }
  2053.  
  2054. static void i915_set_reset_status(struct intel_ring_buffer *ring,
  2055.                                   struct drm_i915_gem_request *request,
  2056.                                   u32 acthd)
  2057. {
  2058.         struct i915_ctx_hang_stats *hs = NULL;
  2059.         bool inside, guilty;
  2060.         unsigned long offset = 0;
  2061.  
  2062.         /* Innocent until proven guilty */
  2063.         guilty = false;
  2064.  
  2065.         if (request->batch_obj)
  2066.                 offset = i915_gem_obj_offset(request->batch_obj,
  2067.                                              request_to_vm(request));
  2068.  
  2069.         if (ring->hangcheck.action != HANGCHECK_WAIT &&
  2070.             i915_request_guilty(request, acthd, &inside)) {
  2071.                 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
  2072.                           ring->name,
  2073.                           inside ? "inside" : "flushing",
  2074.                           offset,
  2075.                           request->ctx ? request->ctx->id : 0,
  2076.                           acthd);
  2077.  
  2078.                 guilty = true;
  2079.         }
  2080.  
  2081.         /* If contexts are disabled or this is the default context, use
  2082.          * file_priv->reset_state
  2083.          */
  2084.         if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
  2085.                 hs = &request->ctx->hang_stats;
  2086.         else if (request->file_priv)
  2087.                 hs = &request->file_priv->hang_stats;
  2088.  
  2089.         if (hs) {
  2090.                 if (guilty)
  2091.                         hs->batch_active++;
  2092.                 else
  2093.                         hs->batch_pending++;
  2094.         }
  2095. }
  2096.  
  2097. static void i915_gem_free_request(struct drm_i915_gem_request *request)
  2098. {
  2099.         list_del(&request->list);
  2100.         i915_gem_request_remove_from_client(request);
  2101.  
  2102.         if (request->ctx)
  2103.                 i915_gem_context_unreference(request->ctx);
  2104.  
  2105.         kfree(request);
  2106. }
  2107.  
  2108. static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
  2109.                                       struct intel_ring_buffer *ring)
  2110. {
  2111.         u32 completed_seqno;
  2112.         u32 acthd;
  2113.  
  2114.         acthd = intel_ring_get_active_head(ring);
  2115.         completed_seqno = ring->get_seqno(ring, false);
  2116.  
  2117.         while (!list_empty(&ring->request_list)) {
  2118.                 struct drm_i915_gem_request *request;
  2119.  
  2120.                 request = list_first_entry(&ring->request_list,
  2121.                                            struct drm_i915_gem_request,
  2122.                                            list);
  2123.  
  2124.                 if (request->seqno > completed_seqno)
  2125.                         i915_set_reset_status(ring, request, acthd);
  2126.  
  2127.                 i915_gem_free_request(request);
  2128.         }
  2129.  
  2130.         while (!list_empty(&ring->active_list)) {
  2131.                 struct drm_i915_gem_object *obj;
  2132.  
  2133.                 obj = list_first_entry(&ring->active_list,
  2134.                                        struct drm_i915_gem_object,
  2135.                                        ring_list);
  2136.  
  2137.                 i915_gem_object_move_to_inactive(obj);
  2138.         }
  2139. }
  2140.  
  2141. void i915_gem_restore_fences(struct drm_device *dev)
  2142. {
  2143.         struct drm_i915_private *dev_priv = dev->dev_private;
  2144.         int i;
  2145.  
  2146.         for (i = 0; i < dev_priv->num_fence_regs; i++) {
  2147.                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
  2148.  
  2149.                 /*
  2150.                  * Commit delayed tiling changes if we have an object still
  2151.                  * attached to the fence, otherwise just clear the fence.
  2152.                  */
  2153.                 if (reg->obj) {
  2154.                         i915_gem_object_update_fence(reg->obj, reg,
  2155.                                                      reg->obj->tiling_mode);
  2156.                 } else {
  2157.                         i915_gem_write_fence(dev, i, NULL);
  2158.                 }
  2159.         }
  2160. }
  2161.  
  2162. void i915_gem_reset(struct drm_device *dev)
  2163. {
  2164.         struct drm_i915_private *dev_priv = dev->dev_private;
  2165.         struct intel_ring_buffer *ring;
  2166.         int i;
  2167.  
  2168.         for_each_ring(ring, dev_priv, i)
  2169.                 i915_gem_reset_ring_lists(dev_priv, ring);
  2170.  
  2171.         i915_gem_restore_fences(dev);
  2172. }
  2173.  
  2174. /**
  2175.  * This function clears the request list as sequence numbers are passed.
  2176.  */
  2177. void
  2178. i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
  2179. {
  2180.         uint32_t seqno;
  2181.  
  2182.         if (list_empty(&ring->request_list))
  2183.                 return;
  2184.  
  2185.         WARN_ON(i915_verify_lists(ring->dev));
  2186.  
  2187.         seqno = ring->get_seqno(ring, true);
  2188.  
  2189.         while (!list_empty(&ring->request_list)) {
  2190.                 struct drm_i915_gem_request *request;
  2191.  
  2192.                 request = list_first_entry(&ring->request_list,
  2193.                                            struct drm_i915_gem_request,
  2194.                                            list);
  2195.  
  2196.                 if (!i915_seqno_passed(seqno, request->seqno))
  2197.                         break;
  2198.  
  2199.                 trace_i915_gem_request_retire(ring, request->seqno);
  2200.                 /* We know the GPU must have read the request to have
  2201.                  * sent us the seqno + interrupt, so use the position
  2202.                  * of tail of the request to update the last known position
  2203.                  * of the GPU head.
  2204.                  */
  2205.                 ring->last_retired_head = request->tail;
  2206.  
  2207.                 i915_gem_free_request(request);
  2208.         }
  2209.  
  2210.         /* Move any buffers on the active list that are no longer referenced
  2211.          * by the ringbuffer to the flushing/inactive lists as appropriate.
  2212.          */
  2213.         while (!list_empty(&ring->active_list)) {
  2214.                 struct drm_i915_gem_object *obj;
  2215.  
  2216.                 obj = list_first_entry(&ring->active_list,
  2217.                                       struct drm_i915_gem_object,
  2218.                                       ring_list);
  2219.  
  2220.                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
  2221.                         break;
  2222.  
  2223.                         i915_gem_object_move_to_inactive(obj);
  2224.         }
  2225.  
  2226.         if (unlikely(ring->trace_irq_seqno &&
  2227.                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
  2228.                 ring->irq_put(ring);
  2229.                 ring->trace_irq_seqno = 0;
  2230.         }
  2231.  
  2232.         WARN_ON(i915_verify_lists(ring->dev));
  2233. }
  2234.  
  2235. void
  2236. i915_gem_retire_requests(struct drm_device *dev)
  2237. {
  2238.         drm_i915_private_t *dev_priv = dev->dev_private;
  2239.         struct intel_ring_buffer *ring;
  2240.         int i;
  2241.  
  2242.         for_each_ring(ring, dev_priv, i)
  2243.                 i915_gem_retire_requests_ring(ring);
  2244. }
  2245.  
  2246. static void
  2247. i915_gem_retire_work_handler(struct work_struct *work)
  2248. {
  2249.         drm_i915_private_t *dev_priv;
  2250.         struct drm_device *dev;
  2251.         struct intel_ring_buffer *ring;
  2252.         bool idle;
  2253.         int i;
  2254.  
  2255.         dev_priv = container_of(work, drm_i915_private_t,
  2256.                                 mm.retire_work.work);
  2257.         dev = dev_priv->dev;
  2258.  
  2259.         /* Come back later if the device is busy... */
  2260.         if (!mutex_trylock(&dev->struct_mutex)) {
  2261.                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
  2262.                                    round_jiffies_up_relative(HZ));
  2263.         return;
  2264.         }
  2265.  
  2266.         i915_gem_retire_requests(dev);
  2267.  
  2268.         /* Send a periodic flush down the ring so we don't hold onto GEM
  2269.          * objects indefinitely.
  2270.          */
  2271.         idle = true;
  2272.         for_each_ring(ring, dev_priv, i) {
  2273.                 if (ring->gpu_caches_dirty)
  2274.                         i915_add_request(ring, NULL);
  2275.  
  2276.                 idle &= list_empty(&ring->request_list);
  2277.         }
  2278.  
  2279.         if (!dev_priv->ums.mm_suspended && !idle)
  2280.                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
  2281.                                    round_jiffies_up_relative(HZ));
  2282.         if (idle)
  2283.                 intel_mark_idle(dev);
  2284.  
  2285.         mutex_unlock(&dev->struct_mutex);
  2286. }
  2287.  
  2288. /**
  2289.  * Ensures that an object will eventually get non-busy by flushing any required
  2290.  * write domains, emitting any outstanding lazy request and retiring and
  2291.  * completed requests.
  2292.  */
  2293. static int
  2294. i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
  2295. {
  2296.         int ret;
  2297.  
  2298.         if (obj->active) {
  2299.                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
  2300.                 if (ret)
  2301.                         return ret;
  2302.  
  2303.                 i915_gem_retire_requests_ring(obj->ring);
  2304.         }
  2305.  
  2306.         return 0;
  2307. }
  2308.  
  2309. /**
  2310.  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
  2311.  * @DRM_IOCTL_ARGS: standard ioctl arguments
  2312.  *
  2313.  * Returns 0 if successful, else an error is returned with the remaining time in
  2314.  * the timeout parameter.
  2315.  *  -ETIME: object is still busy after timeout
  2316.  *  -ERESTARTSYS: signal interrupted the wait
  2317.  *  -ENONENT: object doesn't exist
  2318.  * Also possible, but rare:
  2319.  *  -EAGAIN: GPU wedged
  2320.  *  -ENOMEM: damn
  2321.  *  -ENODEV: Internal IRQ fail
  2322.  *  -E?: The add request failed
  2323.  *
  2324.  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
  2325.  * non-zero timeout parameter the wait ioctl will wait for the given number of
  2326.  * nanoseconds on an object becoming unbusy. Since the wait itself does so
  2327.  * without holding struct_mutex the object may become re-busied before this
  2328.  * function completes. A similar but shorter * race condition exists in the busy
  2329.  * ioctl
  2330.  */
  2331. int
  2332. i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
  2333. {
  2334.         drm_i915_private_t *dev_priv = dev->dev_private;
  2335.         struct drm_i915_gem_wait *args = data;
  2336.         struct drm_i915_gem_object *obj;
  2337.         struct intel_ring_buffer *ring = NULL;
  2338.         struct timespec timeout_stack, *timeout = NULL;
  2339.         unsigned reset_counter;
  2340.         u32 seqno = 0;
  2341.         int ret = 0;
  2342.  
  2343.         if (args->timeout_ns >= 0) {
  2344.                 timeout_stack = ns_to_timespec(args->timeout_ns);
  2345.                 timeout = &timeout_stack;
  2346.         }
  2347.  
  2348.         ret = i915_mutex_lock_interruptible(dev);
  2349.         if (ret)
  2350.                 return ret;
  2351.  
  2352.     if(args->bo_handle == -2)
  2353.     {
  2354.         obj = get_fb_obj();
  2355.         drm_gem_object_reference(&obj->base);
  2356.     }
  2357.     else
  2358.         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
  2359.         if (&obj->base == NULL) {
  2360.                 mutex_unlock(&dev->struct_mutex);
  2361.                 return -ENOENT;
  2362.         }
  2363.  
  2364.         /* Need to make sure the object gets inactive eventually. */
  2365.         ret = i915_gem_object_flush_active(obj);
  2366.         if (ret)
  2367.                 goto out;
  2368.  
  2369.         if (obj->active) {
  2370.                 seqno = obj->last_read_seqno;
  2371.                 ring = obj->ring;
  2372.         }
  2373.  
  2374.         if (seqno == 0)
  2375.                  goto out;
  2376.  
  2377.         /* Do this after OLR check to make sure we make forward progress polling
  2378.          * on this IOCTL with a 0 timeout (like busy ioctl)
  2379.          */
  2380.         if (!args->timeout_ns) {
  2381.                 ret = -ETIME;
  2382.                 goto out;
  2383.         }
  2384.  
  2385.         drm_gem_object_unreference(&obj->base);
  2386.         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  2387.         mutex_unlock(&dev->struct_mutex);
  2388.  
  2389.         ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
  2390.         if (timeout)
  2391.                 args->timeout_ns = timespec_to_ns(timeout);
  2392.         return ret;
  2393.  
  2394. out:
  2395.         drm_gem_object_unreference(&obj->base);
  2396.         mutex_unlock(&dev->struct_mutex);
  2397.         return ret;
  2398. }
  2399.  
  2400. /**
  2401.  * i915_gem_object_sync - sync an object to a ring.
  2402.  *
  2403.  * @obj: object which may be in use on another ring.
  2404.  * @to: ring we wish to use the object on. May be NULL.
  2405.  *
  2406.  * This code is meant to abstract object synchronization with the GPU.
  2407.  * Calling with NULL implies synchronizing the object with the CPU
  2408.  * rather than a particular GPU ring.
  2409.  *
  2410.  * Returns 0 if successful, else propagates up the lower layer error.
  2411.  */
  2412. int
  2413. i915_gem_object_sync(struct drm_i915_gem_object *obj,
  2414.                      struct intel_ring_buffer *to)
  2415. {
  2416.         struct intel_ring_buffer *from = obj->ring;
  2417.         u32 seqno;
  2418.         int ret, idx;
  2419.  
  2420.         if (from == NULL || to == from)
  2421.                 return 0;
  2422.  
  2423.         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
  2424.                 return i915_gem_object_wait_rendering(obj, false);
  2425.  
  2426.         idx = intel_ring_sync_index(from, to);
  2427.  
  2428.         seqno = obj->last_read_seqno;
  2429.         if (seqno <= from->sync_seqno[idx])
  2430.                 return 0;
  2431.  
  2432.         ret = i915_gem_check_olr(obj->ring, seqno);
  2433.         if (ret)
  2434.                 return ret;
  2435.  
  2436.         ret = to->sync_to(to, from, seqno);
  2437.         if (!ret)
  2438.                 /* We use last_read_seqno because sync_to()
  2439.                  * might have just caused seqno wrap under
  2440.                  * the radar.
  2441.                  */
  2442.                 from->sync_seqno[idx] = obj->last_read_seqno;
  2443.  
  2444.         return ret;
  2445. }
  2446.  
  2447. static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
  2448. {
  2449.         u32 old_write_domain, old_read_domains;
  2450.  
  2451.         /* Force a pagefault for domain tracking on next user access */
  2452. //      i915_gem_release_mmap(obj);
  2453.  
  2454.         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
  2455.                 return;
  2456.  
  2457.         /* Wait for any direct GTT access to complete */
  2458.         mb();
  2459.  
  2460.         old_read_domains = obj->base.read_domains;
  2461.         old_write_domain = obj->base.write_domain;
  2462.  
  2463.         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
  2464.         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
  2465.  
  2466.         trace_i915_gem_object_change_domain(obj,
  2467.                                             old_read_domains,
  2468.                                             old_write_domain);
  2469. }
  2470.  
  2471. int i915_vma_unbind(struct i915_vma *vma)
  2472. {
  2473.         struct drm_i915_gem_object *obj = vma->obj;
  2474.         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
  2475.         int ret;
  2476.  
  2477.     if(obj == get_fb_obj())
  2478.         return 0;
  2479.  
  2480.         if (list_empty(&vma->vma_link))
  2481.                 return 0;
  2482.  
  2483.         if (!drm_mm_node_allocated(&vma->node))
  2484.                 goto destroy;
  2485.  
  2486.         if (obj->pin_count)
  2487.                 return -EBUSY;
  2488.  
  2489.         BUG_ON(obj->pages == NULL);
  2490.  
  2491.         ret = i915_gem_object_finish_gpu(obj);
  2492.         if (ret)
  2493.                 return ret;
  2494.         /* Continue on if we fail due to EIO, the GPU is hung so we
  2495.          * should be safe and we need to cleanup or else we might
  2496.          * cause memory corruption through use-after-free.
  2497.          */
  2498.  
  2499.         i915_gem_object_finish_gtt(obj);
  2500.  
  2501.         /* release the fence reg _after_ flushing */
  2502.         ret = i915_gem_object_put_fence(obj);
  2503.         if (ret)
  2504.                 return ret;
  2505.  
  2506.         trace_i915_vma_unbind(vma);
  2507.  
  2508.         if (obj->has_global_gtt_mapping)
  2509.         i915_gem_gtt_unbind_object(obj);
  2510.         if (obj->has_aliasing_ppgtt_mapping) {
  2511.                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
  2512.                 obj->has_aliasing_ppgtt_mapping = 0;
  2513.         }
  2514.         i915_gem_gtt_finish_object(obj);
  2515.         i915_gem_object_unpin_pages(obj);
  2516.  
  2517.         list_del(&vma->mm_list);
  2518.         /* Avoid an unnecessary call to unbind on rebind. */
  2519.         if (i915_is_ggtt(vma->vm))
  2520.         obj->map_and_fenceable = true;
  2521.  
  2522.         drm_mm_remove_node(&vma->node);
  2523.  
  2524. destroy:
  2525.         i915_gem_vma_destroy(vma);
  2526.  
  2527.         /* Since the unbound list is global, only move to that list if
  2528.          * no more VMAs exist.
  2529.          * NB: Until we have real VMAs there will only ever be one */
  2530.         WARN_ON(!list_empty(&obj->vma_list));
  2531.         if (list_empty(&obj->vma_list))
  2532.                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
  2533.  
  2534.         return 0;
  2535. }
  2536.  
  2537. /**
  2538.  * Unbinds an object from the global GTT aperture.
  2539.  */
  2540. int
  2541. i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
  2542. {
  2543.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2544.         struct i915_address_space *ggtt = &dev_priv->gtt.base;
  2545.  
  2546.         if (!i915_gem_obj_ggtt_bound(obj))
  2547.                 return 0;
  2548.  
  2549.         if (obj->pin_count)
  2550.                 return -EBUSY;
  2551.  
  2552.         BUG_ON(obj->pages == NULL);
  2553.  
  2554.         return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
  2555. }
  2556.  
  2557. int i915_gpu_idle(struct drm_device *dev)
  2558. {
  2559.         drm_i915_private_t *dev_priv = dev->dev_private;
  2560.         struct intel_ring_buffer *ring;
  2561.         int ret, i;
  2562.  
  2563.         /* Flush everything onto the inactive list. */
  2564.         for_each_ring(ring, dev_priv, i) {
  2565.                 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
  2566.                 if (ret)
  2567.                         return ret;
  2568.  
  2569.                 ret = intel_ring_idle(ring);
  2570.                 if (ret)
  2571.                         return ret;
  2572.         }
  2573.  
  2574.         return 0;
  2575. }
  2576.  
  2577. static void i965_write_fence_reg(struct drm_device *dev, int reg,
  2578.                                         struct drm_i915_gem_object *obj)
  2579. {
  2580.         drm_i915_private_t *dev_priv = dev->dev_private;
  2581.         int fence_reg;
  2582.         int fence_pitch_shift;
  2583.  
  2584.         if (INTEL_INFO(dev)->gen >= 6) {
  2585.                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
  2586.                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
  2587.         } else {
  2588.                 fence_reg = FENCE_REG_965_0;
  2589.                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  2590.         }
  2591.  
  2592.         fence_reg += reg * 8;
  2593.  
  2594.         /* To w/a incoherency with non-atomic 64-bit register updates,
  2595.          * we split the 64-bit update into two 32-bit writes. In order
  2596.          * for a partial fence not to be evaluated between writes, we
  2597.          * precede the update with write to turn off the fence register,
  2598.          * and only enable the fence as the last step.
  2599.          *
  2600.          * For extra levels of paranoia, we make sure each step lands
  2601.          * before applying the next step.
  2602.          */
  2603.         I915_WRITE(fence_reg, 0);
  2604.         POSTING_READ(fence_reg);
  2605.  
  2606.         if (obj) {
  2607.                 u32 size = i915_gem_obj_ggtt_size(obj);
  2608.                 uint64_t val;
  2609.  
  2610.                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
  2611.                                  0xfffff000) << 32;
  2612.                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
  2613.                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
  2614.                 if (obj->tiling_mode == I915_TILING_Y)
  2615.                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
  2616.                 val |= I965_FENCE_REG_VALID;
  2617.  
  2618.                 I915_WRITE(fence_reg + 4, val >> 32);
  2619.                 POSTING_READ(fence_reg + 4);
  2620.  
  2621.                 I915_WRITE(fence_reg + 0, val);
  2622.         POSTING_READ(fence_reg);
  2623.         } else {
  2624.                 I915_WRITE(fence_reg + 4, 0);
  2625.                 POSTING_READ(fence_reg + 4);
  2626.         }
  2627. }
  2628.  
  2629. static void i915_write_fence_reg(struct drm_device *dev, int reg,
  2630.                                  struct drm_i915_gem_object *obj)
  2631. {
  2632.         drm_i915_private_t *dev_priv = dev->dev_private;
  2633.         u32 val;
  2634.  
  2635.         if (obj) {
  2636.                 u32 size = i915_gem_obj_ggtt_size(obj);
  2637.                 int pitch_val;
  2638.                 int tile_width;
  2639.  
  2640.                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
  2641.                      (size & -size) != size ||
  2642.                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
  2643.                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
  2644.                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
  2645.  
  2646.                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
  2647.                         tile_width = 128;
  2648.                 else
  2649.                         tile_width = 512;
  2650.  
  2651.                 /* Note: pitch better be a power of two tile widths */
  2652.                 pitch_val = obj->stride / tile_width;
  2653.                 pitch_val = ffs(pitch_val) - 1;
  2654.  
  2655.                 val = i915_gem_obj_ggtt_offset(obj);
  2656.                 if (obj->tiling_mode == I915_TILING_Y)
  2657.                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
  2658.                 val |= I915_FENCE_SIZE_BITS(size);
  2659.                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
  2660.                 val |= I830_FENCE_REG_VALID;
  2661.         } else
  2662.                 val = 0;
  2663.  
  2664.         if (reg < 8)
  2665.                 reg = FENCE_REG_830_0 + reg * 4;
  2666.         else
  2667.                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
  2668.  
  2669.         I915_WRITE(reg, val);
  2670.         POSTING_READ(reg);
  2671. }
  2672.  
  2673. static void i830_write_fence_reg(struct drm_device *dev, int reg,
  2674.                                 struct drm_i915_gem_object *obj)
  2675. {
  2676.         drm_i915_private_t *dev_priv = dev->dev_private;
  2677.         uint32_t val;
  2678.  
  2679.         if (obj) {
  2680.                 u32 size = i915_gem_obj_ggtt_size(obj);
  2681.                 uint32_t pitch_val;
  2682.  
  2683.                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
  2684.                      (size & -size) != size ||
  2685.                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
  2686.                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
  2687.                      i915_gem_obj_ggtt_offset(obj), size);
  2688.  
  2689.                 pitch_val = obj->stride / 128;
  2690.                 pitch_val = ffs(pitch_val) - 1;
  2691.  
  2692.                 val = i915_gem_obj_ggtt_offset(obj);
  2693.                 if (obj->tiling_mode == I915_TILING_Y)
  2694.                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
  2695.                 val |= I830_FENCE_SIZE_BITS(size);
  2696.                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
  2697.                 val |= I830_FENCE_REG_VALID;
  2698.         } else
  2699.                 val = 0;
  2700.  
  2701.         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
  2702.         POSTING_READ(FENCE_REG_830_0 + reg * 4);
  2703. }
  2704.  
  2705. inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
  2706. {
  2707.         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
  2708. }
  2709.  
  2710. static void i915_gem_write_fence(struct drm_device *dev, int reg,
  2711.                                  struct drm_i915_gem_object *obj)
  2712. {
  2713.         struct drm_i915_private *dev_priv = dev->dev_private;
  2714.  
  2715.         /* Ensure that all CPU reads are completed before installing a fence
  2716.          * and all writes before removing the fence.
  2717.          */
  2718.         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
  2719.                 mb();
  2720.  
  2721.         WARN(obj && (!obj->stride || !obj->tiling_mode),
  2722.              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
  2723.              obj->stride, obj->tiling_mode);
  2724.  
  2725.         switch (INTEL_INFO(dev)->gen) {
  2726.         case 7:
  2727.         case 6:
  2728.         case 5:
  2729.         case 4: i965_write_fence_reg(dev, reg, obj); break;
  2730.         case 3: i915_write_fence_reg(dev, reg, obj); break;
  2731.         case 2: i830_write_fence_reg(dev, reg, obj); break;
  2732.         default: BUG();
  2733.         }
  2734.  
  2735.         /* And similarly be paranoid that no direct access to this region
  2736.          * is reordered to before the fence is installed.
  2737.          */
  2738.         if (i915_gem_object_needs_mb(obj))
  2739.                 mb();
  2740. }
  2741.  
  2742. static inline int fence_number(struct drm_i915_private *dev_priv,
  2743.                                struct drm_i915_fence_reg *fence)
  2744. {
  2745.         return fence - dev_priv->fence_regs;
  2746. }
  2747.  
  2748. static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  2749.                                          struct drm_i915_fence_reg *fence,
  2750.                                          bool enable)
  2751. {
  2752.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2753.         int reg = fence_number(dev_priv, fence);
  2754.  
  2755.         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
  2756.  
  2757.         if (enable) {
  2758.                 obj->fence_reg = reg;
  2759.                 fence->obj = obj;
  2760.                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
  2761.         } else {
  2762.                 obj->fence_reg = I915_FENCE_REG_NONE;
  2763.                 fence->obj = NULL;
  2764.                 list_del_init(&fence->lru_list);
  2765.         }
  2766.         obj->fence_dirty = false;
  2767. }
  2768.  
  2769. static int
  2770. i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
  2771. {
  2772.         if (obj->last_fenced_seqno) {
  2773.                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
  2774.                         if (ret)
  2775.                                 return ret;
  2776.  
  2777.                 obj->last_fenced_seqno = 0;
  2778.         }
  2779.  
  2780.         obj->fenced_gpu_access = false;
  2781.         return 0;
  2782. }
  2783.  
  2784. int
  2785. i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
  2786. {
  2787.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2788.         struct drm_i915_fence_reg *fence;
  2789.         int ret;
  2790.  
  2791.         ret = i915_gem_object_wait_fence(obj);
  2792.         if (ret)
  2793.                 return ret;
  2794.  
  2795.         if (obj->fence_reg == I915_FENCE_REG_NONE)
  2796.                 return 0;
  2797.  
  2798.         fence = &dev_priv->fence_regs[obj->fence_reg];
  2799.  
  2800.         i915_gem_object_fence_lost(obj);
  2801.         i915_gem_object_update_fence(obj, fence, false);
  2802.  
  2803.         return 0;
  2804. }
  2805.  
  2806. static struct drm_i915_fence_reg *
  2807. i915_find_fence_reg(struct drm_device *dev)
  2808. {
  2809.         struct drm_i915_private *dev_priv = dev->dev_private;
  2810.         struct drm_i915_fence_reg *reg, *avail;
  2811.         int i;
  2812.  
  2813.         /* First try to find a free reg */
  2814.         avail = NULL;
  2815.         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
  2816.                 reg = &dev_priv->fence_regs[i];
  2817.                 if (!reg->obj)
  2818.                         return reg;
  2819.  
  2820.                 if (!reg->pin_count)
  2821.                         avail = reg;
  2822.         }
  2823.  
  2824.         if (avail == NULL)
  2825.                 return NULL;
  2826.  
  2827.         /* None available, try to steal one or wait for a user to finish */
  2828.         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
  2829.                 if (reg->pin_count)
  2830.                         continue;
  2831.  
  2832.                 return reg;
  2833.         }
  2834.  
  2835.         return NULL;
  2836. }
  2837.  
  2838. /**
  2839.  * i915_gem_object_get_fence - set up fencing for an object
  2840.  * @obj: object to map through a fence reg
  2841.  *
  2842.  * When mapping objects through the GTT, userspace wants to be able to write
  2843.  * to them without having to worry about swizzling if the object is tiled.
  2844.  * This function walks the fence regs looking for a free one for @obj,
  2845.  * stealing one if it can't find any.
  2846.  *
  2847.  * It then sets up the reg based on the object's properties: address, pitch
  2848.  * and tiling format.
  2849.  *
  2850.  * For an untiled surface, this removes any existing fence.
  2851.  */
  2852. int
  2853. i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
  2854. {
  2855.         struct drm_device *dev = obj->base.dev;
  2856.         struct drm_i915_private *dev_priv = dev->dev_private;
  2857.         bool enable = obj->tiling_mode != I915_TILING_NONE;
  2858.         struct drm_i915_fence_reg *reg;
  2859.         int ret;
  2860.  
  2861.         /* Have we updated the tiling parameters upon the object and so
  2862.          * will need to serialise the write to the associated fence register?
  2863.          */
  2864.         if (obj->fence_dirty) {
  2865.                 ret = i915_gem_object_wait_fence(obj);
  2866.                 if (ret)
  2867.                         return ret;
  2868.         }
  2869.  
  2870.         /* Just update our place in the LRU if our fence is getting reused. */
  2871.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  2872.                 reg = &dev_priv->fence_regs[obj->fence_reg];
  2873.                 if (!obj->fence_dirty) {
  2874.                         list_move_tail(&reg->lru_list,
  2875.                                        &dev_priv->mm.fence_list);
  2876.                         return 0;
  2877.                 }
  2878.         } else if (enable) {
  2879.                 reg = i915_find_fence_reg(dev);
  2880.                 if (reg == NULL)
  2881.                         return -EDEADLK;
  2882.  
  2883.                 if (reg->obj) {
  2884.                         struct drm_i915_gem_object *old = reg->obj;
  2885.  
  2886.                         ret = i915_gem_object_wait_fence(old);
  2887.                         if (ret)
  2888.                                 return ret;
  2889.  
  2890.                         i915_gem_object_fence_lost(old);
  2891.                 }
  2892.         } else
  2893.                 return 0;
  2894.  
  2895.         i915_gem_object_update_fence(obj, reg, enable);
  2896.  
  2897.         return 0;
  2898. }
  2899.  
  2900. static bool i915_gem_valid_gtt_space(struct drm_device *dev,
  2901.                                      struct drm_mm_node *gtt_space,
  2902.                                      unsigned long cache_level)
  2903. {
  2904.         struct drm_mm_node *other;
  2905.  
  2906.         /* On non-LLC machines we have to be careful when putting differing
  2907.          * types of snoopable memory together to avoid the prefetcher
  2908.          * crossing memory domains and dying.
  2909.          */
  2910.         if (HAS_LLC(dev))
  2911.                 return true;
  2912.  
  2913.         if (!drm_mm_node_allocated(gtt_space))
  2914.                 return true;
  2915.  
  2916.         if (list_empty(&gtt_space->node_list))
  2917.                 return true;
  2918.  
  2919.         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
  2920.         if (other->allocated && !other->hole_follows && other->color != cache_level)
  2921.                 return false;
  2922.  
  2923.         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
  2924.         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
  2925.                 return false;
  2926.  
  2927.         return true;
  2928. }
  2929.  
  2930. static void i915_gem_verify_gtt(struct drm_device *dev)
  2931. {
  2932. #if WATCH_GTT
  2933.         struct drm_i915_private *dev_priv = dev->dev_private;
  2934.         struct drm_i915_gem_object *obj;
  2935.         int err = 0;
  2936.  
  2937.         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
  2938.                 if (obj->gtt_space == NULL) {
  2939.                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
  2940.                         err++;
  2941.                         continue;
  2942.                 }
  2943.  
  2944.                 if (obj->cache_level != obj->gtt_space->color) {
  2945.                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
  2946.                                i915_gem_obj_ggtt_offset(obj),
  2947.                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
  2948.                                obj->cache_level,
  2949.                                obj->gtt_space->color);
  2950.                         err++;
  2951.                         continue;
  2952.                 }
  2953.  
  2954.                 if (!i915_gem_valid_gtt_space(dev,
  2955.                                               obj->gtt_space,
  2956.                                               obj->cache_level)) {
  2957.                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
  2958.                                i915_gem_obj_ggtt_offset(obj),
  2959.                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
  2960.                                obj->cache_level);
  2961.                         err++;
  2962.                         continue;
  2963.                 }
  2964.         }
  2965.  
  2966.         WARN_ON(err);
  2967. #endif
  2968. }
  2969.  
  2970. /**
  2971.  * Finds free space in the GTT aperture and binds the object there.
  2972.  */
  2973. static int
  2974. i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
  2975.                            struct i915_address_space *vm,
  2976.                             unsigned alignment,
  2977.                             bool map_and_fenceable,
  2978.                             bool nonblocking)
  2979. {
  2980.         struct drm_device *dev = obj->base.dev;
  2981.         drm_i915_private_t *dev_priv = dev->dev_private;
  2982.         u32 size, fence_size, fence_alignment, unfenced_alignment;
  2983.         size_t gtt_max =
  2984.                 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
  2985.         struct i915_vma *vma;
  2986.         int ret;
  2987.  
  2988.         fence_size = i915_gem_get_gtt_size(dev,
  2989.                                            obj->base.size,
  2990.                                            obj->tiling_mode);
  2991.         fence_alignment = i915_gem_get_gtt_alignment(dev,
  2992.                                                      obj->base.size,
  2993.                                                      obj->tiling_mode, true);
  2994.         unfenced_alignment =
  2995.                 i915_gem_get_gtt_alignment(dev,
  2996.                                                     obj->base.size,
  2997.                                                     obj->tiling_mode, false);
  2998.  
  2999.         if (alignment == 0)
  3000.                 alignment = map_and_fenceable ? fence_alignment :
  3001.                                                 unfenced_alignment;
  3002.         if (map_and_fenceable && alignment & (fence_alignment - 1)) {
  3003.                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
  3004.                 return -EINVAL;
  3005.         }