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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include <uapi/drm/i915_drm.h>
  34. #include <uapi/drm/drm_fourcc.h>
  35.  
  36. #include "i915_reg.h"
  37. #include "intel_bios.h"
  38. #include "intel_ringbuffer.h"
  39. #include "intel_lrc.h"
  40. #include "i915_gem_gtt.h"
  41. #include "i915_gem_render_state.h"
  42. #include <linux/scatterlist.h>
  43. #include <linux/i2c.h>
  44. #include <linux/i2c-algo-bit.h>
  45. #include <drm/intel-gtt.h>
  46. #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  47. #include <drm/drm_gem.h>
  48. //#include <linux/backlight.h>
  49. #include <linux/hashtable.h>
  50. #include <linux/kref.h>
  51. #include "intel_guc.h"
  52.  
  53. #include <linux/spinlock.h>
  54. #include <linux/err.h>
  55.  
  56. #define ioread32(addr)          readl(addr)
  57. static inline u8 inb(u16 port)
  58. {
  59.         u8 v;
  60.         asm volatile("inb %1,%0" : "=a" (v) : "dN" (port));
  61.         return v;
  62. }
  63.  
  64. static inline void outb(u8 v, u16 port)
  65. {
  66.         asm volatile("outb %0,%1" : : "a" (v), "dN" (port));
  67. }
  68.  
  69.  
  70. /* General customization:
  71.  */
  72.  
  73. #define DRIVER_NAME             "i915"
  74. #define DRIVER_DESC             "Intel Graphics"
  75. #define DRIVER_DATE             "20151010"
  76.  
  77. #undef WARN_ON
  78. /* Many gcc seem to no see through this and fall over :( */
  79. #if 0
  80. #define WARN_ON(x) ({ \
  81.         bool __i915_warn_cond = (x); \
  82.         if (__builtin_constant_p(__i915_warn_cond)) \
  83.                 BUILD_BUG_ON(__i915_warn_cond); \
  84.         WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
  85. #else
  86. #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
  87. #endif
  88.  
  89. #undef WARN_ON_ONCE
  90. #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
  91.  
  92. #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
  93.                              (long) (x), __func__);
  94.  
  95. /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
  96.  * WARN_ON()) for hw state sanity checks to check for unexpected conditions
  97.  * which may not necessarily be a user visible problem.  This will either
  98.  * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
  99.  * enable distros and users to tailor their preferred amount of i915 abrt
  100.  * spam.
  101.  */
  102. #define I915_STATE_WARN(condition, format...) ({                        \
  103.         int __ret_warn_on = !!(condition);                              \
  104.         if (unlikely(__ret_warn_on)) {                                  \
  105.                 if (i915.verbose_state_checks)                          \
  106.                         WARN(1, format);                                \
  107.                 else                                                    \
  108.                         DRM_ERROR(format);                              \
  109.         }                                                               \
  110.         unlikely(__ret_warn_on);                                        \
  111. })
  112.  
  113. #define I915_STATE_WARN_ON(condition) ({                                \
  114.         int __ret_warn_on = !!(condition);                              \
  115.         if (unlikely(__ret_warn_on)) {                                  \
  116.                 if (i915.verbose_state_checks)                          \
  117.                         WARN(1, "WARN_ON(" #condition ")\n");           \
  118.                 else                                                    \
  119.                         DRM_ERROR("WARN_ON(" #condition ")\n");         \
  120.         }                                                               \
  121.         unlikely(__ret_warn_on);                                        \
  122. })
  123.  
  124. static inline const char *yesno(bool v)
  125. {
  126.         return v ? "yes" : "no";
  127. }
  128.  
  129. enum pipe {
  130.         INVALID_PIPE = -1,
  131.         PIPE_A = 0,
  132.         PIPE_B,
  133.         PIPE_C,
  134.         _PIPE_EDP,
  135.         I915_MAX_PIPES = _PIPE_EDP
  136. };
  137. #define pipe_name(p) ((p) + 'A')
  138.  
  139. enum transcoder {
  140.         TRANSCODER_A = 0,
  141.         TRANSCODER_B,
  142.         TRANSCODER_C,
  143.         TRANSCODER_EDP,
  144.         I915_MAX_TRANSCODERS
  145. };
  146. #define transcoder_name(t) ((t) + 'A')
  147.  
  148. /*
  149.  * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
  150.  * number of planes per CRTC.  Not all platforms really have this many planes,
  151.  * which means some arrays of size I915_MAX_PLANES may have unused entries
  152.  * between the topmost sprite plane and the cursor plane.
  153.  */
  154. enum plane {
  155.         PLANE_A = 0,
  156.         PLANE_B,
  157.         PLANE_C,
  158.         PLANE_CURSOR,
  159.         I915_MAX_PLANES,
  160. };
  161. #define plane_name(p) ((p) + 'A')
  162.  
  163. #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
  164.  
  165. enum port {
  166.         PORT_A = 0,
  167.         PORT_B,
  168.         PORT_C,
  169.         PORT_D,
  170.         PORT_E,
  171.         I915_MAX_PORTS
  172. };
  173. #define port_name(p) ((p) + 'A')
  174.  
  175. #define I915_NUM_PHYS_VLV 2
  176.  
  177. enum dpio_channel {
  178.         DPIO_CH0,
  179.         DPIO_CH1
  180. };
  181.  
  182. enum dpio_phy {
  183.         DPIO_PHY0,
  184.         DPIO_PHY1
  185. };
  186.  
  187. enum intel_display_power_domain {
  188.         POWER_DOMAIN_PIPE_A,
  189.         POWER_DOMAIN_PIPE_B,
  190.         POWER_DOMAIN_PIPE_C,
  191.         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  192.         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  193.         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  194.         POWER_DOMAIN_TRANSCODER_A,
  195.         POWER_DOMAIN_TRANSCODER_B,
  196.         POWER_DOMAIN_TRANSCODER_C,
  197.         POWER_DOMAIN_TRANSCODER_EDP,
  198.         POWER_DOMAIN_PORT_DDI_A_2_LANES,
  199.         POWER_DOMAIN_PORT_DDI_A_4_LANES,
  200.         POWER_DOMAIN_PORT_DDI_B_2_LANES,
  201.         POWER_DOMAIN_PORT_DDI_B_4_LANES,
  202.         POWER_DOMAIN_PORT_DDI_C_2_LANES,
  203.         POWER_DOMAIN_PORT_DDI_C_4_LANES,
  204.         POWER_DOMAIN_PORT_DDI_D_2_LANES,
  205.         POWER_DOMAIN_PORT_DDI_D_4_LANES,
  206.         POWER_DOMAIN_PORT_DDI_E_2_LANES,
  207.         POWER_DOMAIN_PORT_DSI,
  208.         POWER_DOMAIN_PORT_CRT,
  209.         POWER_DOMAIN_PORT_OTHER,
  210.         POWER_DOMAIN_VGA,
  211.         POWER_DOMAIN_AUDIO,
  212.         POWER_DOMAIN_PLLS,
  213.         POWER_DOMAIN_AUX_A,
  214.         POWER_DOMAIN_AUX_B,
  215.         POWER_DOMAIN_AUX_C,
  216.         POWER_DOMAIN_AUX_D,
  217.         POWER_DOMAIN_GMBUS,
  218.         POWER_DOMAIN_INIT,
  219.  
  220.         POWER_DOMAIN_NUM,
  221. };
  222.  
  223. #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
  224. #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
  225.                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
  226. #define POWER_DOMAIN_TRANSCODER(tran) \
  227.         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
  228.          (tran) + POWER_DOMAIN_TRANSCODER_A)
  229.  
  230. enum hpd_pin {
  231.         HPD_NONE = 0,
  232.         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
  233.         HPD_CRT,
  234.         HPD_SDVO_B,
  235.         HPD_SDVO_C,
  236.         HPD_PORT_A,
  237.         HPD_PORT_B,
  238.         HPD_PORT_C,
  239.         HPD_PORT_D,
  240.         HPD_PORT_E,
  241.         HPD_NUM_PINS
  242. };
  243.  
  244. #define for_each_hpd_pin(__pin) \
  245.         for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
  246.  
  247. struct i915_hotplug {
  248.         struct work_struct hotplug_work;
  249.  
  250.         struct {
  251.                 unsigned long last_jiffies;
  252.                 int count;
  253.                 enum {
  254.                         HPD_ENABLED = 0,
  255.                         HPD_DISABLED = 1,
  256.                         HPD_MARK_DISABLED = 2
  257.                 } state;
  258.         } stats[HPD_NUM_PINS];
  259.         u32 event_bits;
  260.         struct delayed_work reenable_work;
  261.  
  262.         struct intel_digital_port *irq_port[I915_MAX_PORTS];
  263.         u32 long_port_mask;
  264.         u32 short_port_mask;
  265.         struct work_struct dig_port_work;
  266.  
  267.         /*
  268.          * if we get a HPD irq from DP and a HPD irq from non-DP
  269.          * the non-DP HPD could block the workqueue on a mode config
  270.          * mutex getting, that userspace may have taken. However
  271.          * userspace is waiting on the DP workqueue to run which is
  272.          * blocked behind the non-DP one.
  273.          */
  274.         struct workqueue_struct *dp_wq;
  275. };
  276.  
  277. #define I915_GEM_GPU_DOMAINS \
  278.         (I915_GEM_DOMAIN_RENDER | \
  279.          I915_GEM_DOMAIN_SAMPLER | \
  280.          I915_GEM_DOMAIN_COMMAND | \
  281.          I915_GEM_DOMAIN_INSTRUCTION | \
  282.          I915_GEM_DOMAIN_VERTEX)
  283.  
  284. #define for_each_pipe(__dev_priv, __p) \
  285.         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
  286. #define for_each_plane(__dev_priv, __pipe, __p)                         \
  287.         for ((__p) = 0;                                                 \
  288.              (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
  289.              (__p)++)
  290. #define for_each_sprite(__dev_priv, __p, __s)                           \
  291.         for ((__s) = 0;                                                 \
  292.              (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];        \
  293.              (__s)++)
  294.  
  295. #define for_each_crtc(dev, crtc) \
  296.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
  297.  
  298. #define for_each_intel_plane(dev, intel_plane) \
  299.         list_for_each_entry(intel_plane,                        \
  300.                             &dev->mode_config.plane_list,       \
  301.                             base.head)
  302.  
  303. #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)      \
  304.         list_for_each_entry(intel_plane,                                \
  305.                             &(dev)->mode_config.plane_list,             \
  306.                             base.head)                                  \
  307.                 if ((intel_plane)->pipe == (intel_crtc)->pipe)
  308.  
  309. #define for_each_intel_crtc(dev, intel_crtc) \
  310.         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
  311.  
  312. #define for_each_intel_encoder(dev, intel_encoder)              \
  313.         list_for_each_entry(intel_encoder,                      \
  314.                             &(dev)->mode_config.encoder_list,   \
  315.                             base.head)
  316.  
  317. #define for_each_intel_connector(dev, intel_connector)          \
  318.         list_for_each_entry(intel_connector,                    \
  319.                             &dev->mode_config.connector_list,   \
  320.                             base.head)
  321.  
  322. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  323.         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  324.                 if ((intel_encoder)->base.crtc == (__crtc))
  325.  
  326. #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
  327.         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
  328.                 if ((intel_connector)->base.encoder == (__encoder))
  329.  
  330. #define for_each_power_domain(domain, mask)                             \
  331.         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
  332.                 if ((1 << (domain)) & (mask))
  333.  
  334. struct drm_i915_private;
  335. struct i915_mm_struct;
  336. struct i915_mmu_object;
  337.  
  338. struct drm_i915_file_private {
  339.         struct drm_i915_private *dev_priv;
  340.         struct drm_file *file;
  341.  
  342.         struct {
  343.                 spinlock_t lock;
  344.                 struct list_head request_list;
  345. /* 20ms is a fairly arbitrary limit (greater than the average frame time)
  346.  * chosen to prevent the CPU getting more than a frame ahead of the GPU
  347.  * (when using lax throttling for the frontbuffer). We also use it to
  348.  * offer free GPU waitboosts for severely congested workloads.
  349.  */
  350. #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
  351.         } mm;
  352.         struct idr context_idr;
  353.  
  354.         struct intel_rps_client {
  355.                 struct list_head link;
  356.                 unsigned boosts;
  357.         } rps;
  358.  
  359.         struct intel_engine_cs *bsd_ring;
  360. };
  361.  
  362. enum intel_dpll_id {
  363.         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
  364.         /* real shared dpll ids must be >= 0 */
  365.         DPLL_ID_PCH_PLL_A = 0,
  366.         DPLL_ID_PCH_PLL_B = 1,
  367.         /* hsw/bdw */
  368.         DPLL_ID_WRPLL1 = 0,
  369.         DPLL_ID_WRPLL2 = 1,
  370.         DPLL_ID_SPLL = 2,
  371.  
  372.         /* skl */
  373.         DPLL_ID_SKL_DPLL1 = 0,
  374.         DPLL_ID_SKL_DPLL2 = 1,
  375.         DPLL_ID_SKL_DPLL3 = 2,
  376. };
  377. #define I915_NUM_PLLS 3
  378.  
  379. struct intel_dpll_hw_state {
  380.         /* i9xx, pch plls */
  381.         uint32_t dpll;
  382.         uint32_t dpll_md;
  383.         uint32_t fp0;
  384.         uint32_t fp1;
  385.  
  386.         /* hsw, bdw */
  387.         uint32_t wrpll;
  388.         uint32_t spll;
  389.  
  390.         /* skl */
  391.         /*
  392.          * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
  393.          * lower part of ctrl1 and they get shifted into position when writing
  394.          * the register.  This allows us to easily compare the state to share
  395.          * the DPLL.
  396.          */
  397.         uint32_t ctrl1;
  398.         /* HDMI only, 0 when used for DP */
  399.         uint32_t cfgcr1, cfgcr2;
  400.  
  401.         /* bxt */
  402.         uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
  403.                  pcsdw12;
  404. };
  405.  
  406. struct intel_shared_dpll_config {
  407.         unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
  408.         struct intel_dpll_hw_state hw_state;
  409. };
  410.  
  411. struct intel_shared_dpll {
  412.         struct intel_shared_dpll_config config;
  413.  
  414.         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  415.         bool on; /* is the PLL actually active? Disabled during modeset */
  416.         const char *name;
  417.         /* should match the index in the dev_priv->shared_dplls array */
  418.         enum intel_dpll_id id;
  419.         /* The mode_set hook is optional and should be used together with the
  420.          * intel_prepare_shared_dpll function. */
  421.         void (*mode_set)(struct drm_i915_private *dev_priv,
  422.                          struct intel_shared_dpll *pll);
  423.         void (*enable)(struct drm_i915_private *dev_priv,
  424.                        struct intel_shared_dpll *pll);
  425.         void (*disable)(struct drm_i915_private *dev_priv,
  426.                         struct intel_shared_dpll *pll);
  427.         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
  428.                              struct intel_shared_dpll *pll,
  429.                              struct intel_dpll_hw_state *hw_state);
  430. };
  431.  
  432. #define SKL_DPLL0 0
  433. #define SKL_DPLL1 1
  434. #define SKL_DPLL2 2
  435. #define SKL_DPLL3 3
  436.  
  437. /* Used by dp and fdi links */
  438. struct intel_link_m_n {
  439.         uint32_t        tu;
  440.         uint32_t        gmch_m;
  441.         uint32_t        gmch_n;
  442.         uint32_t        link_m;
  443.         uint32_t        link_n;
  444. };
  445.  
  446. void intel_link_compute_m_n(int bpp, int nlanes,
  447.                             int pixel_clock, int link_clock,
  448.                             struct intel_link_m_n *m_n);
  449.  
  450. /* Interface history:
  451.  *
  452.  * 1.1: Original.
  453.  * 1.2: Add Power Management
  454.  * 1.3: Add vblank support
  455.  * 1.4: Fix cmdbuffer path, add heap destroy
  456.  * 1.5: Add vblank pipe configuration
  457.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  458.  *      - Support vertical blank on secondary display pipe
  459.  */
  460. #define DRIVER_MAJOR            1
  461. #define DRIVER_MINOR            6
  462. #define DRIVER_PATCHLEVEL       0
  463.  
  464. #define WATCH_LISTS     0
  465.  
  466. struct opregion_header;
  467. struct opregion_acpi;
  468. struct opregion_swsci;
  469. struct opregion_asle;
  470.  
  471. struct intel_opregion {
  472.         struct opregion_header *header;
  473.         struct opregion_acpi *acpi;
  474.         struct opregion_swsci *swsci;
  475.         u32 swsci_gbda_sub_functions;
  476.         u32 swsci_sbcb_sub_functions;
  477.         struct opregion_asle *asle;
  478.         void *vbt;
  479.         u32 *lid_state;
  480.         struct work_struct asle_work;
  481. };
  482. #define OPREGION_SIZE            (8*1024)
  483.  
  484. struct intel_overlay;
  485. struct intel_overlay_error_state;
  486.  
  487. #define I915_FENCE_REG_NONE -1
  488. #define I915_MAX_NUM_FENCES 32
  489. /* 32 fences + sign bit for FENCE_REG_NONE */
  490. #define I915_MAX_NUM_FENCE_BITS 6
  491.  
  492. struct drm_i915_fence_reg {
  493.         struct list_head lru_list;
  494.         struct drm_i915_gem_object *obj;
  495.         int pin_count;
  496. };
  497.  
  498. struct sdvo_device_mapping {
  499.         u8 initialized;
  500.         u8 dvo_port;
  501.         u8 slave_addr;
  502.         u8 dvo_wiring;
  503.         u8 i2c_pin;
  504.         u8 ddc_pin;
  505. };
  506.  
  507. struct intel_display_error_state;
  508.  
  509. struct drm_i915_error_state {
  510.         struct kref ref;
  511.         struct timeval time;
  512.  
  513.         char error_msg[128];
  514.         int iommu;
  515.         u32 reset_count;
  516.         u32 suspend_count;
  517.  
  518.         /* Generic register state */
  519.         u32 eir;
  520.         u32 pgtbl_er;
  521.         u32 ier;
  522.         u32 gtier[4];
  523.         u32 ccid;
  524.         u32 derrmr;
  525.         u32 forcewake;
  526.         u32 error; /* gen6+ */
  527.         u32 err_int; /* gen7 */
  528.         u32 fault_data0; /* gen8, gen9 */
  529.         u32 fault_data1; /* gen8, gen9 */
  530.         u32 done_reg;
  531.         u32 gac_eco;
  532.         u32 gam_ecochk;
  533.         u32 gab_ctl;
  534.         u32 gfx_mode;
  535.         u32 extra_instdone[I915_NUM_INSTDONE_REG];
  536.         u64 fence[I915_MAX_NUM_FENCES];
  537.         struct intel_overlay_error_state *overlay;
  538.         struct intel_display_error_state *display;
  539.         struct drm_i915_error_object *semaphore_obj;
  540.  
  541.         struct drm_i915_error_ring {
  542.                 bool valid;
  543.                 /* Software tracked state */
  544.                 bool waiting;
  545.                 int hangcheck_score;
  546.                 enum intel_ring_hangcheck_action hangcheck_action;
  547.                 int num_requests;
  548.  
  549.                 /* our own tracking of ring head and tail */
  550.                 u32 cpu_ring_head;
  551.                 u32 cpu_ring_tail;
  552.  
  553.                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
  554.  
  555.                 /* Register state */
  556.                 u32 start;
  557.                 u32 tail;
  558.                 u32 head;
  559.                 u32 ctl;
  560.                 u32 hws;
  561.                 u32 ipeir;
  562.                 u32 ipehr;
  563.                 u32 instdone;
  564.                 u32 bbstate;
  565.                 u32 instpm;
  566.                 u32 instps;
  567.                 u32 seqno;
  568.                 u64 bbaddr;
  569.                 u64 acthd;
  570.                 u32 fault_reg;
  571.                 u64 faddr;
  572.                 u32 rc_psmi; /* sleep state */
  573.                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
  574.  
  575.                 struct drm_i915_error_object {
  576.                         int page_count;
  577.                         u64 gtt_offset;
  578.                         u32 *pages[0];
  579.                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
  580.  
  581.                 struct drm_i915_error_request {
  582.                         long jiffies;
  583.                         u32 seqno;
  584.                         u32 tail;
  585.                 } *requests;
  586.  
  587.                 struct {
  588.                         u32 gfx_mode;
  589.                         union {
  590.                                 u64 pdp[4];
  591.                                 u32 pp_dir_base;
  592.                         };
  593.                 } vm_info;
  594.  
  595.                 pid_t pid;
  596.                 char comm[TASK_COMM_LEN];
  597.         } ring[I915_NUM_RINGS];
  598.  
  599.         struct drm_i915_error_buffer {
  600.                 u32 size;
  601.                 u32 name;
  602.                 u32 rseqno[I915_NUM_RINGS], wseqno;
  603.                 u64 gtt_offset;
  604.                 u32 read_domains;
  605.                 u32 write_domain;
  606.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  607.                 s32 pinned:2;
  608.                 u32 tiling:2;
  609.                 u32 dirty:1;
  610.                 u32 purgeable:1;
  611.                 u32 userptr:1;
  612.                 s32 ring:4;
  613.                 u32 cache_level:3;
  614.         } **active_bo, **pinned_bo;
  615.  
  616.         u32 *active_bo_count, *pinned_bo_count;
  617.         u32 vm_count;
  618. };
  619.  
  620. struct intel_connector;
  621. struct intel_encoder;
  622. struct intel_crtc_state;
  623. struct intel_initial_plane_config;
  624. struct intel_crtc;
  625. struct intel_limit;
  626. struct dpll;
  627.  
  628. struct drm_i915_display_funcs {
  629.         int (*get_display_clock_speed)(struct drm_device *dev);
  630.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  631.         /**
  632.          * find_dpll() - Find the best values for the PLL
  633.          * @limit: limits for the PLL
  634.          * @crtc: current CRTC
  635.          * @target: target frequency in kHz
  636.          * @refclk: reference clock frequency in kHz
  637.          * @match_clock: if provided, @best_clock P divider must
  638.          *               match the P divider from @match_clock
  639.          *               used for LVDS downclocking
  640.          * @best_clock: best PLL values found
  641.          *
  642.          * Returns true on success, false on failure.
  643.          */
  644.         bool (*find_dpll)(const struct intel_limit *limit,
  645.                           struct intel_crtc_state *crtc_state,
  646.                           int target, int refclk,
  647.                           struct dpll *match_clock,
  648.                           struct dpll *best_clock);
  649.         void (*update_wm)(struct drm_crtc *crtc);
  650.         void (*update_sprite_wm)(struct drm_plane *plane,
  651.                                  struct drm_crtc *crtc,
  652.                                  uint32_t sprite_width, uint32_t sprite_height,
  653.                                  int pixel_size, bool enable, bool scaled);
  654.         int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
  655.         void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
  656.         /* Returns the active state of the crtc, and if the crtc is active,
  657.          * fills out the pipe-config with the hw state. */
  658.         bool (*get_pipe_config)(struct intel_crtc *,
  659.                                 struct intel_crtc_state *);
  660.         void (*get_initial_plane_config)(struct intel_crtc *,
  661.                                          struct intel_initial_plane_config *);
  662.         int (*crtc_compute_clock)(struct intel_crtc *crtc,
  663.                                   struct intel_crtc_state *crtc_state);
  664.         void (*crtc_enable)(struct drm_crtc *crtc);
  665.         void (*crtc_disable)(struct drm_crtc *crtc);
  666.         void (*audio_codec_enable)(struct drm_connector *connector,
  667.                                    struct intel_encoder *encoder,
  668.                                    const struct drm_display_mode *adjusted_mode);
  669.         void (*audio_codec_disable)(struct intel_encoder *encoder);
  670.         void (*fdi_link_train)(struct drm_crtc *crtc);
  671.         void (*init_clock_gating)(struct drm_device *dev);
  672.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  673.                           struct drm_framebuffer *fb,
  674.                           struct drm_i915_gem_object *obj,
  675.                           struct drm_i915_gem_request *req,
  676.                           uint32_t flags);
  677.         void (*update_primary_plane)(struct drm_crtc *crtc,
  678.                                      struct drm_framebuffer *fb,
  679.                                      int x, int y);
  680.         void (*hpd_irq_setup)(struct drm_device *dev);
  681.         /* clock updates for mode set */
  682.         /* cursor updates */
  683.         /* render clock increase/decrease */
  684.         /* display clock increase/decrease */
  685.         /* pll clock increase/decrease */
  686. };
  687.  
  688. enum forcewake_domain_id {
  689.         FW_DOMAIN_ID_RENDER = 0,
  690.         FW_DOMAIN_ID_BLITTER,
  691.         FW_DOMAIN_ID_MEDIA,
  692.  
  693.         FW_DOMAIN_ID_COUNT
  694. };
  695.  
  696. enum forcewake_domains {
  697.         FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
  698.         FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
  699.         FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
  700.         FORCEWAKE_ALL = (FORCEWAKE_RENDER |
  701.                          FORCEWAKE_BLITTER |
  702.                          FORCEWAKE_MEDIA)
  703. };
  704.  
  705. struct intel_uncore_funcs {
  706.         void (*force_wake_get)(struct drm_i915_private *dev_priv,
  707.                                                         enum forcewake_domains domains);
  708.         void (*force_wake_put)(struct drm_i915_private *dev_priv,
  709.                                                         enum forcewake_domains domains);
  710.  
  711.         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  712.         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  713.         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  714.         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  715.  
  716.         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
  717.                                 uint8_t val, bool trace);
  718.         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
  719.                                 uint16_t val, bool trace);
  720.         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
  721.                                 uint32_t val, bool trace);
  722.         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
  723.                                 uint64_t val, bool trace);
  724. };
  725.  
  726. struct intel_uncore {
  727.         spinlock_t lock; /** lock is also taken in irq contexts. */
  728.  
  729.         struct intel_uncore_funcs funcs;
  730.  
  731.         unsigned fifo_count;
  732.         enum forcewake_domains fw_domains;
  733.  
  734.         struct intel_uncore_forcewake_domain {
  735.                 struct drm_i915_private *i915;
  736.                 enum forcewake_domain_id id;
  737.                 unsigned wake_count;
  738.                 struct timer_list timer;
  739.                 u32 reg_set;
  740.                 u32 val_set;
  741.                 u32 val_clear;
  742.                 u32 reg_ack;
  743.                 u32 reg_post;
  744.                 u32 val_reset;
  745.         } fw_domain[FW_DOMAIN_ID_COUNT];
  746. };
  747.  
  748. /* Iterate over initialised fw domains */
  749. #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
  750.         for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
  751.              (i__) < FW_DOMAIN_ID_COUNT; \
  752.              (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
  753.                 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
  754.  
  755. #define for_each_fw_domain(domain__, dev_priv__, i__) \
  756.         for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
  757.  
  758. enum csr_state {
  759.         FW_UNINITIALIZED = 0,
  760.         FW_LOADED,
  761.         FW_FAILED
  762. };
  763.  
  764. struct intel_csr {
  765.         const char *fw_path;
  766.         uint32_t *dmc_payload;
  767.         uint32_t dmc_fw_size;
  768.         uint32_t mmio_count;
  769.         uint32_t mmioaddr[8];
  770.         uint32_t mmiodata[8];
  771.         enum csr_state state;
  772. };
  773.  
  774. #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
  775.         func(is_mobile) sep \
  776.         func(is_i85x) sep \
  777.         func(is_i915g) sep \
  778.         func(is_i945gm) sep \
  779.         func(is_g33) sep \
  780.         func(need_gfx_hws) sep \
  781.         func(is_g4x) sep \
  782.         func(is_pineview) sep \
  783.         func(is_broadwater) sep \
  784.         func(is_crestline) sep \
  785.         func(is_ivybridge) sep \
  786.         func(is_valleyview) sep \
  787.         func(is_haswell) sep \
  788.         func(is_skylake) sep \
  789.         func(is_preliminary) sep \
  790.         func(has_fbc) sep \
  791.         func(has_pipe_cxsr) sep \
  792.         func(has_hotplug) sep \
  793.         func(cursor_needs_physical) sep \
  794.         func(has_overlay) sep \
  795.         func(overlay_needs_physical) sep \
  796.         func(supports_tv) sep \
  797.         func(has_llc) sep \
  798.         func(has_ddi) sep \
  799.         func(has_fpga_dbg)
  800.  
  801. #define DEFINE_FLAG(name) u8 name:1
  802. #define SEP_SEMICOLON ;
  803.  
  804. struct intel_device_info {
  805.         u32 display_mmio_offset;
  806.         u16 device_id;
  807.         u8 num_pipes:3;
  808.         u8 num_sprites[I915_MAX_PIPES];
  809.         u8 gen;
  810.         u8 ring_mask; /* Rings supported by the HW */
  811.         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
  812.         /* Register offsets for the various display pipes and transcoders */
  813.         int pipe_offsets[I915_MAX_TRANSCODERS];
  814.         int trans_offsets[I915_MAX_TRANSCODERS];
  815.         int palette_offsets[I915_MAX_PIPES];
  816.         int cursor_offsets[I915_MAX_PIPES];
  817.  
  818.         /* Slice/subslice/EU info */
  819.         u8 slice_total;
  820.         u8 subslice_total;
  821.         u8 subslice_per_slice;
  822.         u8 eu_total;
  823.         u8 eu_per_subslice;
  824.         /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
  825.         u8 subslice_7eu[3];
  826.         u8 has_slice_pg:1;
  827.         u8 has_subslice_pg:1;
  828.         u8 has_eu_pg:1;
  829. };
  830.  
  831. #undef DEFINE_FLAG
  832. #undef SEP_SEMICOLON
  833.  
  834. enum i915_cache_level {
  835.         I915_CACHE_NONE = 0,
  836.         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
  837.         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
  838.                               caches, eg sampler/render caches, and the
  839.                               large Last-Level-Cache. LLC is coherent with
  840.                               the CPU, but L3 is only visible to the GPU. */
  841.         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
  842. };
  843.  
  844. struct i915_ctx_hang_stats {
  845.         /* This context had batch pending when hang was declared */
  846.         unsigned batch_pending;
  847.  
  848.         /* This context had batch active when hang was declared */
  849.         unsigned batch_active;
  850.  
  851.         /* Time when this context was last blamed for a GPU reset */
  852.         unsigned long guilty_ts;
  853.  
  854.         /* If the contexts causes a second GPU hang within this time,
  855.          * it is permanently banned from submitting any more work.
  856.          */
  857.         unsigned long ban_period_seconds;
  858.  
  859.         /* This context is banned to submit more work */
  860.         bool banned;
  861. };
  862.  
  863. /* This must match up with the value previously used for execbuf2.rsvd1. */
  864. #define DEFAULT_CONTEXT_HANDLE 0
  865.  
  866. #define CONTEXT_NO_ZEROMAP (1<<0)
  867. /**
  868.  * struct intel_context - as the name implies, represents a context.
  869.  * @ref: reference count.
  870.  * @user_handle: userspace tracking identity for this context.
  871.  * @remap_slice: l3 row remapping information.
  872.  * @flags: context specific flags:
  873.  *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
  874.  * @file_priv: filp associated with this context (NULL for global default
  875.  *             context).
  876.  * @hang_stats: information about the role of this context in possible GPU
  877.  *              hangs.
  878.  * @ppgtt: virtual memory space used by this context.
  879.  * @legacy_hw_ctx: render context backing object and whether it is correctly
  880.  *                initialized (legacy ring submission mechanism only).
  881.  * @link: link in the global list of contexts.
  882.  *
  883.  * Contexts are memory images used by the hardware to store copies of their
  884.  * internal state.
  885.  */
  886. struct intel_context {
  887.         struct kref ref;
  888.         int user_handle;
  889.         uint8_t remap_slice;
  890.         struct drm_i915_private *i915;
  891.         int flags;
  892.         struct drm_i915_file_private *file_priv;
  893.         struct i915_ctx_hang_stats hang_stats;
  894.         struct i915_hw_ppgtt *ppgtt;
  895.  
  896.         /* Legacy ring buffer submission */
  897.         struct {
  898.                 struct drm_i915_gem_object *rcs_state;
  899.                 bool initialized;
  900.         } legacy_hw_ctx;
  901.  
  902.         /* Execlists */
  903.         struct {
  904.                 struct drm_i915_gem_object *state;
  905.                 struct intel_ringbuffer *ringbuf;
  906.                 int pin_count;
  907.         } engine[I915_NUM_RINGS];
  908.  
  909.         struct list_head link;
  910. };
  911.  
  912. enum fb_op_origin {
  913.         ORIGIN_GTT,
  914.         ORIGIN_CPU,
  915.         ORIGIN_CS,
  916.         ORIGIN_FLIP,
  917.         ORIGIN_DIRTYFB,
  918. };
  919.  
  920. struct i915_fbc {
  921.         /* This is always the inner lock when overlapping with struct_mutex and
  922.          * it's the outer lock when overlapping with stolen_lock. */
  923.         struct mutex lock;
  924.         unsigned long uncompressed_size;
  925.         unsigned threshold;
  926.         unsigned int fb_id;
  927.         unsigned int possible_framebuffer_bits;
  928.         unsigned int busy_bits;
  929.         struct intel_crtc *crtc;
  930.         int y;
  931.  
  932.         struct drm_mm_node compressed_fb;
  933.         struct drm_mm_node *compressed_llb;
  934.  
  935.         bool false_color;
  936.  
  937.         /* Tracks whether the HW is actually enabled, not whether the feature is
  938.          * possible. */
  939.         bool enabled;
  940.  
  941.         struct intel_fbc_work {
  942.                 struct delayed_work work;
  943.                 struct intel_crtc *crtc;
  944.                 struct drm_framebuffer *fb;
  945.         } *fbc_work;
  946.  
  947.         enum no_fbc_reason {
  948.                 FBC_OK, /* FBC is enabled */
  949.                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
  950.                 FBC_NO_OUTPUT, /* no outputs enabled to compress */
  951.                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
  952.                 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  953.                 FBC_MODE_TOO_LARGE, /* mode too large for compression */
  954.                 FBC_BAD_PLANE, /* fbc not supported on plane */
  955.                 FBC_NOT_TILED, /* buffer not tiled */
  956.                 FBC_MULTIPLE_PIPES, /* more than one pipe active */
  957.                 FBC_MODULE_PARAM,
  958.                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
  959.                 FBC_ROTATION, /* rotation is not supported */
  960.                 FBC_IN_DBG_MASTER, /* kernel debugger is active */
  961.                 FBC_BAD_STRIDE, /* stride is not supported */
  962.                 FBC_PIXEL_RATE, /* pixel rate is too big */
  963.                 FBC_PIXEL_FORMAT /* pixel format is invalid */
  964.         } no_fbc_reason;
  965.  
  966.         bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
  967.         void (*enable_fbc)(struct intel_crtc *crtc);
  968.         void (*disable_fbc)(struct drm_i915_private *dev_priv);
  969. };
  970.  
  971. /**
  972.  * HIGH_RR is the highest eDP panel refresh rate read from EDID
  973.  * LOW_RR is the lowest eDP panel refresh rate found from EDID
  974.  * parsing for same resolution.
  975.  */
  976. enum drrs_refresh_rate_type {
  977.         DRRS_HIGH_RR,
  978.         DRRS_LOW_RR,
  979.         DRRS_MAX_RR, /* RR count */
  980. };
  981.  
  982. enum drrs_support_type {
  983.         DRRS_NOT_SUPPORTED = 0,
  984.         STATIC_DRRS_SUPPORT = 1,
  985.         SEAMLESS_DRRS_SUPPORT = 2
  986. };
  987.  
  988. struct intel_dp;
  989. struct i915_drrs {
  990.         struct mutex mutex;
  991.         struct delayed_work work;
  992.         struct intel_dp *dp;
  993.         unsigned busy_frontbuffer_bits;
  994.         enum drrs_refresh_rate_type refresh_rate_type;
  995.         enum drrs_support_type type;
  996. };
  997.  
  998. struct i915_psr {
  999.         struct mutex lock;
  1000.         bool sink_support;
  1001.         bool source_ok;
  1002.         struct intel_dp *enabled;
  1003.         bool active;
  1004.         struct delayed_work work;
  1005.         unsigned busy_frontbuffer_bits;
  1006.         bool psr2_support;
  1007.         bool aux_frame_sync;
  1008. };
  1009.  
  1010. enum intel_pch {
  1011.         PCH_NONE = 0,   /* No PCH present */
  1012.         PCH_IBX,        /* Ibexpeak PCH */
  1013.         PCH_CPT,        /* Cougarpoint PCH */
  1014.         PCH_LPT,        /* Lynxpoint PCH */
  1015.         PCH_SPT,        /* Sunrisepoint PCH */
  1016.         PCH_NOP,
  1017. };
  1018.  
  1019. enum intel_sbi_destination {
  1020.         SBI_ICLK,
  1021.         SBI_MPHY,
  1022. };
  1023.  
  1024. #define QUIRK_PIPEA_FORCE (1<<0)
  1025. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  1026. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  1027. #define QUIRK_BACKLIGHT_PRESENT (1<<3)
  1028. #define QUIRK_PIPEB_FORCE (1<<4)
  1029. #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
  1030.  
  1031. struct intel_fbdev;
  1032. struct intel_fbc_work;
  1033.  
  1034. struct intel_gmbus {
  1035.         struct i2c_adapter adapter;
  1036.         u32 force_bit;
  1037.         u32 reg0;
  1038.         u32 gpio_reg;
  1039.         struct i2c_algo_bit_data bit_algo;
  1040.         struct drm_i915_private *dev_priv;
  1041. };
  1042.  
  1043. struct i915_suspend_saved_registers {
  1044.         u32 saveDSPARB;
  1045.         u32 saveLVDS;
  1046.         u32 savePP_ON_DELAYS;
  1047.         u32 savePP_OFF_DELAYS;
  1048.         u32 savePP_ON;
  1049.         u32 savePP_OFF;
  1050.         u32 savePP_CONTROL;
  1051.         u32 savePP_DIVISOR;
  1052.         u32 saveFBC_CONTROL;
  1053.         u32 saveCACHE_MODE_0;
  1054.         u32 saveMI_ARB_STATE;
  1055.         u32 saveSWF0[16];
  1056.         u32 saveSWF1[16];
  1057.         u32 saveSWF3[3];
  1058.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  1059.         u32 savePCH_PORT_HOTPLUG;
  1060.         u16 saveGCDGMBUS;
  1061. };
  1062.  
  1063. struct vlv_s0ix_state {
  1064.         /* GAM */
  1065.         u32 wr_watermark;
  1066.         u32 gfx_prio_ctrl;
  1067.         u32 arb_mode;
  1068.         u32 gfx_pend_tlb0;
  1069.         u32 gfx_pend_tlb1;
  1070.         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
  1071.         u32 media_max_req_count;
  1072.         u32 gfx_max_req_count;
  1073.         u32 render_hwsp;
  1074.         u32 ecochk;
  1075.         u32 bsd_hwsp;
  1076.         u32 blt_hwsp;
  1077.         u32 tlb_rd_addr;
  1078.  
  1079.         /* MBC */
  1080.         u32 g3dctl;
  1081.         u32 gsckgctl;
  1082.         u32 mbctl;
  1083.  
  1084.         /* GCP */
  1085.         u32 ucgctl1;
  1086.         u32 ucgctl3;
  1087.         u32 rcgctl1;
  1088.         u32 rcgctl2;
  1089.         u32 rstctl;
  1090.         u32 misccpctl;
  1091.  
  1092.         /* GPM */
  1093.         u32 gfxpause;
  1094.         u32 rpdeuhwtc;
  1095.         u32 rpdeuc;
  1096.         u32 ecobus;
  1097.         u32 pwrdwnupctl;
  1098.         u32 rp_down_timeout;
  1099.         u32 rp_deucsw;
  1100.         u32 rcubmabdtmr;
  1101.         u32 rcedata;
  1102.         u32 spare2gh;
  1103.  
  1104.         /* Display 1 CZ domain */
  1105.         u32 gt_imr;
  1106.         u32 gt_ier;
  1107.         u32 pm_imr;
  1108.         u32 pm_ier;
  1109.         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
  1110.  
  1111.         /* GT SA CZ domain */
  1112.         u32 tilectl;
  1113.         u32 gt_fifoctl;
  1114.         u32 gtlc_wake_ctrl;
  1115.         u32 gtlc_survive;
  1116.         u32 pmwgicz;
  1117.  
  1118.         /* Display 2 CZ domain */
  1119.         u32 gu_ctl0;
  1120.         u32 gu_ctl1;
  1121.         u32 pcbr;
  1122.         u32 clock_gate_dis2;
  1123. };
  1124.  
  1125. struct intel_rps_ei {
  1126.         u32 cz_clock;
  1127.         u32 render_c0;
  1128.         u32 media_c0;
  1129. };
  1130.  
  1131. struct intel_gen6_power_mgmt {
  1132.         /*
  1133.          * work, interrupts_enabled and pm_iir are protected by
  1134.          * dev_priv->irq_lock
  1135.          */
  1136.         struct work_struct work;
  1137.         bool interrupts_enabled;
  1138.         u32 pm_iir;
  1139.  
  1140.         /* Frequencies are stored in potentially platform dependent multiples.
  1141.          * In other words, *_freq needs to be multiplied by X to be interesting.
  1142.          * Soft limits are those which are used for the dynamic reclocking done
  1143.          * by the driver (raise frequencies under heavy loads, and lower for
  1144.          * lighter loads). Hard limits are those imposed by the hardware.
  1145.          *
  1146.          * A distinction is made for overclocking, which is never enabled by
  1147.          * default, and is considered to be above the hard limit if it's
  1148.          * possible at all.
  1149.          */
  1150.         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
  1151.         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
  1152.         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
  1153.         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
  1154.         u8 min_freq;            /* AKA RPn. Minimum frequency */
  1155.         u8 idle_freq;           /* Frequency to request when we are idle */
  1156.         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
  1157.         u8 rp1_freq;            /* "less than" RP0 power/freqency */
  1158.         u8 rp0_freq;            /* Non-overclocked max frequency. */
  1159.  
  1160.         u8 up_threshold; /* Current %busy required to uplock */
  1161.         u8 down_threshold; /* Current %busy required to downclock */
  1162.  
  1163.         int last_adj;
  1164.         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
  1165.  
  1166.         spinlock_t client_lock;
  1167.         struct list_head clients;
  1168.         bool client_boost;
  1169.  
  1170.         bool enabled;
  1171.         struct delayed_work delayed_resume_work;
  1172.         unsigned boosts;
  1173.  
  1174.         struct intel_rps_client semaphores, mmioflips;
  1175.  
  1176.         /* manual wa residency calculations */
  1177.         struct intel_rps_ei up_ei, down_ei;
  1178.  
  1179.         /*
  1180.          * Protects RPS/RC6 register access and PCU communication.
  1181.          * Must be taken after struct_mutex if nested. Note that
  1182.          * this lock may be held for long periods of time when
  1183.          * talking to hw - so only take it when talking to hw!
  1184.          */
  1185.         struct mutex hw_lock;
  1186. };
  1187.  
  1188. /* defined intel_pm.c */
  1189. extern spinlock_t mchdev_lock;
  1190.  
  1191. struct intel_ilk_power_mgmt {
  1192.         u8 cur_delay;
  1193.         u8 min_delay;
  1194.         u8 max_delay;
  1195.         u8 fmax;
  1196.         u8 fstart;
  1197.  
  1198.         u64 last_count1;
  1199.         unsigned long last_time1;
  1200.         unsigned long chipset_power;
  1201.         u64 last_count2;
  1202.         u64 last_time2;
  1203.         unsigned long gfx_power;
  1204.         u8 corr;
  1205.  
  1206.         int c_m;
  1207.         int r_t;
  1208. };
  1209.  
  1210. struct drm_i915_private;
  1211. struct i915_power_well;
  1212.  
  1213. struct i915_power_well_ops {
  1214.         /*
  1215.          * Synchronize the well's hw state to match the current sw state, for
  1216.          * example enable/disable it based on the current refcount. Called
  1217.          * during driver init and resume time, possibly after first calling
  1218.          * the enable/disable handlers.
  1219.          */
  1220.         void (*sync_hw)(struct drm_i915_private *dev_priv,
  1221.                         struct i915_power_well *power_well);
  1222.         /*
  1223.          * Enable the well and resources that depend on it (for example
  1224.          * interrupts located on the well). Called after the 0->1 refcount
  1225.          * transition.
  1226.          */
  1227.         void (*enable)(struct drm_i915_private *dev_priv,
  1228.                        struct i915_power_well *power_well);
  1229.         /*
  1230.          * Disable the well and resources that depend on it. Called after
  1231.          * the 1->0 refcount transition.
  1232.          */
  1233.         void (*disable)(struct drm_i915_private *dev_priv,
  1234.                         struct i915_power_well *power_well);
  1235.         /* Returns the hw enabled state. */
  1236.         bool (*is_enabled)(struct drm_i915_private *dev_priv,
  1237.                            struct i915_power_well *power_well);
  1238. };
  1239.  
  1240. /* Power well structure for haswell */
  1241. struct i915_power_well {
  1242.         const char *name;
  1243.         bool always_on;
  1244.         /* power well enable/disable usage count */
  1245.         int count;
  1246.         /* cached hw enabled state */
  1247.         bool hw_enabled;
  1248.         unsigned long domains;
  1249.         unsigned long data;
  1250.         const struct i915_power_well_ops *ops;
  1251. };
  1252.  
  1253. struct i915_power_domains {
  1254.         /*
  1255.          * Power wells needed for initialization at driver init and suspend
  1256.          * time are on. They are kept on until after the first modeset.
  1257.          */
  1258.         bool init_power_on;
  1259.         bool initializing;
  1260.         int power_well_count;
  1261.  
  1262.         struct mutex lock;
  1263.         int domain_use_count[POWER_DOMAIN_NUM];
  1264.         struct i915_power_well *power_wells;
  1265. };
  1266.  
  1267. #define MAX_L3_SLICES 2
  1268. struct intel_l3_parity {
  1269.         u32 *remap_info[MAX_L3_SLICES];
  1270.         struct work_struct error_work;
  1271.         int which_slice;
  1272. };
  1273.  
  1274. struct i915_gem_mm {
  1275.         /** Memory allocator for GTT stolen memory */
  1276.         struct drm_mm stolen;
  1277.         /** Protects the usage of the GTT stolen memory allocator. This is
  1278.          * always the inner lock when overlapping with struct_mutex. */
  1279.         struct mutex stolen_lock;
  1280.  
  1281.         /** List of all objects in gtt_space. Used to restore gtt
  1282.          * mappings on resume */
  1283.         struct list_head bound_list;
  1284.         /**
  1285.          * List of objects which are not bound to the GTT (thus
  1286.          * are idle and not used by the GPU) but still have
  1287.          * (presumably uncached) pages still attached.
  1288.          */
  1289.         struct list_head unbound_list;
  1290.  
  1291.         /** Usable portion of the GTT for GEM */
  1292.         unsigned long stolen_base; /* limited to low memory (32-bit) */
  1293.  
  1294.         /** PPGTT used for aliasing the PPGTT with the GTT */
  1295.         struct i915_hw_ppgtt *aliasing_ppgtt;
  1296.  
  1297.         /** LRU list of objects with fence regs on them. */
  1298.         struct list_head fence_list;
  1299.  
  1300.         /**
  1301.          * We leave the user IRQ off as much as possible,
  1302.          * but this means that requests will finish and never
  1303.          * be retired once the system goes idle. Set a timer to
  1304.          * fire periodically while the ring is running. When it
  1305.          * fires, go retire requests.
  1306.          */
  1307.         struct delayed_work retire_work;
  1308.  
  1309.         /**
  1310.          * When we detect an idle GPU, we want to turn on
  1311.          * powersaving features. So once we see that there
  1312.          * are no more requests outstanding and no more
  1313.          * arrive within a small period of time, we fire
  1314.          * off the idle_work.
  1315.          */
  1316.         struct delayed_work idle_work;
  1317.  
  1318.         /**
  1319.          * Are we in a non-interruptible section of code like
  1320.          * modesetting?
  1321.          */
  1322.         bool interruptible;
  1323.  
  1324.         /**
  1325.          * Is the GPU currently considered idle, or busy executing userspace
  1326.          * requests?  Whilst idle, we attempt to power down the hardware and
  1327.          * display clocks. In order to reduce the effect on performance, there
  1328.          * is a slight delay before we do so.
  1329.          */
  1330.         bool busy;
  1331.  
  1332.         /* the indicator for dispatch video commands on two BSD rings */
  1333.         int bsd_ring_dispatch_index;
  1334.  
  1335.         /** Bit 6 swizzling required for X tiling */
  1336.         uint32_t bit_6_swizzle_x;
  1337.         /** Bit 6 swizzling required for Y tiling */
  1338.         uint32_t bit_6_swizzle_y;
  1339.  
  1340.         /* accounting, useful for userland debugging */
  1341.         spinlock_t object_stat_lock;
  1342.         size_t object_memory;
  1343.         u32 object_count;
  1344. };
  1345.  
  1346. struct drm_i915_error_state_buf {
  1347.         struct drm_i915_private *i915;
  1348.         unsigned bytes;
  1349.         unsigned size;
  1350.         int err;
  1351.         u8 *buf;
  1352.         loff_t start;
  1353.         loff_t pos;
  1354. };
  1355.  
  1356. struct i915_error_state_file_priv {
  1357.         struct drm_device *dev;
  1358.         struct drm_i915_error_state *error;
  1359. };
  1360.  
  1361. struct i915_gpu_error {
  1362.         /* For hangcheck timer */
  1363. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  1364. #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  1365.         /* Hang gpu twice in this window and your context gets banned */
  1366. #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
  1367.  
  1368.         struct workqueue_struct *hangcheck_wq;
  1369.         struct delayed_work hangcheck_work;
  1370.  
  1371.         /* For reset and error_state handling. */
  1372.         spinlock_t lock;
  1373.         /* Protected by the above dev->gpu_error.lock. */
  1374.         struct drm_i915_error_state *first_error;
  1375.  
  1376.         unsigned long missed_irq_rings;
  1377.  
  1378.         /**
  1379.          * State variable controlling the reset flow and count
  1380.          *
  1381.          * This is a counter which gets incremented when reset is triggered,
  1382.          * and again when reset has been handled. So odd values (lowest bit set)
  1383.          * means that reset is in progress and even values that
  1384.          * (reset_counter >> 1):th reset was successfully completed.
  1385.          *
  1386.          * If reset is not completed succesfully, the I915_WEDGE bit is
  1387.          * set meaning that hardware is terminally sour and there is no
  1388.          * recovery. All waiters on the reset_queue will be woken when
  1389.          * that happens.
  1390.          *
  1391.          * This counter is used by the wait_seqno code to notice that reset
  1392.          * event happened and it needs to restart the entire ioctl (since most
  1393.          * likely the seqno it waited for won't ever signal anytime soon).
  1394.          *
  1395.          * This is important for lock-free wait paths, where no contended lock
  1396.          * naturally enforces the correct ordering between the bail-out of the
  1397.          * waiter and the gpu reset work code.
  1398.          */
  1399.         atomic_t reset_counter;
  1400.  
  1401. #define I915_RESET_IN_PROGRESS_FLAG     1
  1402. #define I915_WEDGED                     (1 << 31)
  1403.  
  1404.         /**
  1405.          * Waitqueue to signal when the reset has completed. Used by clients
  1406.          * that wait for dev_priv->mm.wedged to settle.
  1407.          */
  1408.         wait_queue_head_t reset_queue;
  1409.  
  1410.         /* Userspace knobs for gpu hang simulation;
  1411.          * combines both a ring mask, and extra flags
  1412.          */
  1413.         u32 stop_rings;
  1414. #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
  1415. #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
  1416.  
  1417.         /* For missed irq/seqno simulation. */
  1418.         unsigned int test_irq_rings;
  1419.  
  1420.         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
  1421.         bool reload_in_reset;
  1422. };
  1423.  
  1424. enum modeset_restore {
  1425.         MODESET_ON_LID_OPEN,
  1426.         MODESET_DONE,
  1427.         MODESET_SUSPENDED,
  1428. };
  1429.  
  1430. #define DP_AUX_A 0x40
  1431. #define DP_AUX_B 0x10
  1432. #define DP_AUX_C 0x20
  1433. #define DP_AUX_D 0x30
  1434.  
  1435. #define DDC_PIN_B  0x05
  1436. #define DDC_PIN_C  0x04
  1437. #define DDC_PIN_D  0x06
  1438.  
  1439. struct ddi_vbt_port_info {
  1440.         /*
  1441.          * This is an index in the HDMI/DVI DDI buffer translation table.
  1442.          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
  1443.          * populate this field.
  1444.          */
  1445. #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
  1446.         uint8_t hdmi_level_shift;
  1447.  
  1448.         uint8_t supports_dvi:1;
  1449.         uint8_t supports_hdmi:1;
  1450.         uint8_t supports_dp:1;
  1451.  
  1452.         uint8_t alternate_aux_channel;
  1453.         uint8_t alternate_ddc_pin;
  1454.  
  1455.         uint8_t dp_boost_level;
  1456.         uint8_t hdmi_boost_level;
  1457. };
  1458.  
  1459. enum psr_lines_to_wait {
  1460.         PSR_0_LINES_TO_WAIT = 0,
  1461.         PSR_1_LINE_TO_WAIT,
  1462.         PSR_4_LINES_TO_WAIT,
  1463.         PSR_8_LINES_TO_WAIT
  1464. };
  1465.  
  1466. struct intel_vbt_data {
  1467.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  1468.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  1469.  
  1470.         /* Feature bits */
  1471.         unsigned int int_tv_support:1;
  1472.         unsigned int lvds_dither:1;
  1473.         unsigned int lvds_vbt:1;
  1474.         unsigned int int_crt_support:1;
  1475.         unsigned int lvds_use_ssc:1;
  1476.         unsigned int display_clock_mode:1;
  1477.         unsigned int fdi_rx_polarity_inverted:1;
  1478.         unsigned int has_mipi:1;
  1479.         int lvds_ssc_freq;
  1480.         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  1481.  
  1482.         enum drrs_support_type drrs_type;
  1483.  
  1484.         /* eDP */
  1485.         int edp_rate;
  1486.         int edp_lanes;
  1487.         int edp_preemphasis;
  1488.         int edp_vswing;
  1489.         bool edp_initialized;
  1490.         bool edp_support;
  1491.         int edp_bpp;
  1492.         struct edp_power_seq edp_pps;
  1493.  
  1494.         struct {
  1495.                 bool full_link;
  1496.                 bool require_aux_wakeup;
  1497.                 int idle_frames;
  1498.                 enum psr_lines_to_wait lines_to_wait;
  1499.                 int tp1_wakeup_time;
  1500.                 int tp2_tp3_wakeup_time;
  1501.         } psr;
  1502.  
  1503.         struct {
  1504.                 u16 pwm_freq_hz;
  1505.                 bool present;
  1506.                 bool active_low_pwm;
  1507.                 u8 min_brightness;      /* min_brightness/255 of max */
  1508.         } backlight;
  1509.  
  1510.         /* MIPI DSI */
  1511.         struct {
  1512.                 u16 port;
  1513.                 u16 panel_id;
  1514.                 struct mipi_config *config;
  1515.                 struct mipi_pps_data *pps;
  1516.                 u8 seq_version;
  1517.                 u32 size;
  1518.                 u8 *data;
  1519.                 u8 *sequence[MIPI_SEQ_MAX];
  1520.         } dsi;
  1521.  
  1522.         int crt_ddc_pin;
  1523.  
  1524.         int child_dev_num;
  1525.         union child_device_config *child_dev;
  1526.  
  1527.         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
  1528. };
  1529.  
  1530. enum intel_ddb_partitioning {
  1531.         INTEL_DDB_PART_1_2,
  1532.         INTEL_DDB_PART_5_6, /* IVB+ */
  1533. };
  1534.  
  1535. struct intel_wm_level {
  1536.         bool enable;
  1537.         uint32_t pri_val;
  1538.         uint32_t spr_val;
  1539.         uint32_t cur_val;
  1540.         uint32_t fbc_val;
  1541. };
  1542.  
  1543. struct ilk_wm_values {
  1544.         uint32_t wm_pipe[3];
  1545.         uint32_t wm_lp[3];
  1546.         uint32_t wm_lp_spr[3];
  1547.         uint32_t wm_linetime[3];
  1548.         bool enable_fbc_wm;
  1549.         enum intel_ddb_partitioning partitioning;
  1550. };
  1551.  
  1552. struct vlv_pipe_wm {
  1553.         uint16_t primary;
  1554.         uint16_t sprite[2];
  1555.         uint8_t cursor;
  1556. };
  1557.  
  1558. struct vlv_sr_wm {
  1559.         uint16_t plane;
  1560.         uint8_t cursor;
  1561. };
  1562.  
  1563. struct vlv_wm_values {
  1564.         struct vlv_pipe_wm pipe[3];
  1565.         struct vlv_sr_wm sr;
  1566.         struct {
  1567.                 uint8_t cursor;
  1568.                 uint8_t sprite[2];
  1569.                 uint8_t primary;
  1570.         } ddl[3];
  1571.         uint8_t level;
  1572.         bool cxsr;
  1573. };
  1574.  
  1575. struct skl_ddb_entry {
  1576.         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
  1577. };
  1578.  
  1579. static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
  1580. {
  1581.         return entry->end - entry->start;
  1582. }
  1583.  
  1584. static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
  1585.                                        const struct skl_ddb_entry *e2)
  1586. {
  1587.         if (e1->start == e2->start && e1->end == e2->end)
  1588.                 return true;
  1589.  
  1590.         return false;
  1591. }
  1592.  
  1593. struct skl_ddb_allocation {
  1594.         struct skl_ddb_entry pipe[I915_MAX_PIPES];
  1595.         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
  1596.         struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
  1597. };
  1598.  
  1599. struct skl_wm_values {
  1600.         bool dirty[I915_MAX_PIPES];
  1601.         struct skl_ddb_allocation ddb;
  1602.         uint32_t wm_linetime[I915_MAX_PIPES];
  1603.         uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
  1604.         uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
  1605. };
  1606.  
  1607. struct skl_wm_level {
  1608.         bool plane_en[I915_MAX_PLANES];
  1609.         uint16_t plane_res_b[I915_MAX_PLANES];
  1610.         uint8_t plane_res_l[I915_MAX_PLANES];
  1611. };
  1612.  
  1613. /*
  1614.  * This struct helps tracking the state needed for runtime PM, which puts the
  1615.  * device in PCI D3 state. Notice that when this happens, nothing on the
  1616.  * graphics device works, even register access, so we don't get interrupts nor
  1617.  * anything else.
  1618.  *
  1619.  * Every piece of our code that needs to actually touch the hardware needs to
  1620.  * either call intel_runtime_pm_get or call intel_display_power_get with the
  1621.  * appropriate power domain.
  1622.  *
  1623.  * Our driver uses the autosuspend delay feature, which means we'll only really
  1624.  * suspend if we stay with zero refcount for a certain amount of time. The
  1625.  * default value is currently very conservative (see intel_runtime_pm_enable), but
  1626.  * it can be changed with the standard runtime PM files from sysfs.
  1627.  *
  1628.  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
  1629.  * goes back to false exactly before we reenable the IRQs. We use this variable
  1630.  * to check if someone is trying to enable/disable IRQs while they're supposed
  1631.  * to be disabled. This shouldn't happen and we'll print some error messages in
  1632.  * case it happens.
  1633.  *
  1634.  * For more, read the Documentation/power/runtime_pm.txt.
  1635.  */
  1636. struct i915_runtime_pm {
  1637.         bool suspended;
  1638.         bool irqs_enabled;
  1639. };
  1640.  
  1641. enum intel_pipe_crc_source {
  1642.         INTEL_PIPE_CRC_SOURCE_NONE,
  1643.         INTEL_PIPE_CRC_SOURCE_PLANE1,
  1644.         INTEL_PIPE_CRC_SOURCE_PLANE2,
  1645.         INTEL_PIPE_CRC_SOURCE_PF,
  1646.         INTEL_PIPE_CRC_SOURCE_PIPE,
  1647.         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
  1648.         INTEL_PIPE_CRC_SOURCE_TV,
  1649.         INTEL_PIPE_CRC_SOURCE_DP_B,
  1650.         INTEL_PIPE_CRC_SOURCE_DP_C,
  1651.         INTEL_PIPE_CRC_SOURCE_DP_D,
  1652.         INTEL_PIPE_CRC_SOURCE_AUTO,
  1653.         INTEL_PIPE_CRC_SOURCE_MAX,
  1654. };
  1655.  
  1656. struct intel_pipe_crc_entry {
  1657.         uint32_t frame;
  1658.         uint32_t crc[5];
  1659. };
  1660.  
  1661. #define INTEL_PIPE_CRC_ENTRIES_NR       128
  1662. struct intel_pipe_crc {
  1663.         spinlock_t lock;
  1664.         bool opened;            /* exclusive access to the result file */
  1665.         struct intel_pipe_crc_entry *entries;
  1666.         enum intel_pipe_crc_source source;
  1667.         int head, tail;
  1668.         wait_queue_head_t wq;
  1669. };
  1670.  
  1671. struct i915_frontbuffer_tracking {
  1672.         struct mutex lock;
  1673.  
  1674.         /*
  1675.          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
  1676.          * scheduled flips.
  1677.          */
  1678.         unsigned busy_bits;
  1679.         unsigned flip_bits;
  1680. };
  1681.  
  1682. struct i915_wa_reg {
  1683.         u32 addr;
  1684.         u32 value;
  1685.         /* bitmask representing WA bits */
  1686.         u32 mask;
  1687. };
  1688.  
  1689. #define I915_MAX_WA_REGS 16
  1690.  
  1691. struct i915_workarounds {
  1692.         struct i915_wa_reg reg[I915_MAX_WA_REGS];
  1693.         u32 count;
  1694. };
  1695.  
  1696. struct i915_virtual_gpu {
  1697.         bool active;
  1698. };
  1699.  
  1700. struct i915_execbuffer_params {
  1701.         struct drm_device               *dev;
  1702.         struct drm_file                 *file;
  1703.         uint32_t                        dispatch_flags;
  1704.         uint32_t                        args_batch_start_offset;
  1705.         uint64_t                        batch_obj_vm_offset;
  1706.         struct intel_engine_cs          *ring;
  1707.         struct drm_i915_gem_object      *batch_obj;
  1708.         struct intel_context            *ctx;
  1709.         struct drm_i915_gem_request     *request;
  1710. };
  1711.  
  1712. struct drm_i915_private {
  1713.         struct drm_device *dev;
  1714.         struct kmem_cache *objects;
  1715.         struct kmem_cache *vmas;
  1716.         struct kmem_cache *requests;
  1717.  
  1718.         const struct intel_device_info info;
  1719.  
  1720.         int relative_constants_mode;
  1721.  
  1722.         void __iomem *regs;
  1723.  
  1724.         struct intel_uncore uncore;
  1725.  
  1726.         struct i915_virtual_gpu vgpu;
  1727.  
  1728.         struct intel_guc guc;
  1729.  
  1730.         struct intel_csr csr;
  1731.  
  1732.         /* Display CSR-related protection */
  1733.         struct mutex csr_lock;
  1734.  
  1735.         struct intel_gmbus gmbus[GMBUS_NUM_PINS];
  1736.  
  1737.         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  1738.          * controller on different i2c buses. */
  1739.         struct mutex gmbus_mutex;
  1740.  
  1741.         /**
  1742.          * Base address of the gmbus and gpio block.
  1743.          */
  1744.         uint32_t gpio_mmio_base;
  1745.  
  1746.         /* MMIO base address for MIPI regs */
  1747.         uint32_t mipi_mmio_base;
  1748.  
  1749.         wait_queue_head_t gmbus_wait_queue;
  1750.  
  1751.         struct pci_dev *bridge_dev;
  1752.         struct intel_engine_cs ring[I915_NUM_RINGS];
  1753.         struct drm_i915_gem_object *semaphore_obj;
  1754.         uint32_t last_seqno, next_seqno;
  1755.  
  1756.         struct drm_dma_handle *status_page_dmah;
  1757.         struct resource mch_res;
  1758.  
  1759.         /* protects the irq masks */
  1760.         spinlock_t irq_lock;
  1761.  
  1762.         /* protects the mmio flip data */
  1763.         spinlock_t mmio_flip_lock;
  1764.  
  1765.         bool display_irqs_enabled;
  1766.  
  1767.  
  1768.         /* Sideband mailbox protection */
  1769.         struct mutex sb_lock;
  1770.  
  1771.         /** Cached value of IMR to avoid reads in updating the bitfield */
  1772.         union {
  1773.                 u32 irq_mask;
  1774.                 u32 de_irq_mask[I915_MAX_PIPES];
  1775.         };
  1776.         u32 gt_irq_mask;
  1777.         u32 pm_irq_mask;
  1778.         u32 pm_rps_events;
  1779.         u32 pipestat_irq_mask[I915_MAX_PIPES];
  1780.  
  1781.         struct i915_hotplug hotplug;
  1782.         struct i915_fbc fbc;
  1783.         struct i915_drrs drrs;
  1784.         struct intel_opregion opregion;
  1785.         struct intel_vbt_data vbt;
  1786.  
  1787.         bool preserve_bios_swizzle;
  1788.  
  1789.         /* overlay */
  1790.         struct intel_overlay *overlay;
  1791.  
  1792.         /* backlight registers and fields in struct intel_panel */
  1793.         struct mutex backlight_lock;
  1794.  
  1795.         /* LVDS info */
  1796.         bool no_aux_handshake;
  1797.  
  1798.         /* protects panel power sequencer state */
  1799.         struct mutex pps_mutex;
  1800.  
  1801.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  1802.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  1803.  
  1804.         unsigned int fsb_freq, mem_freq, is_ddr3;
  1805.         unsigned int skl_boot_cdclk;
  1806.         unsigned int cdclk_freq, max_cdclk_freq;
  1807.         unsigned int max_dotclk_freq;
  1808.         unsigned int hpll_freq;
  1809.         unsigned int czclk_freq;
  1810.  
  1811.         /**
  1812.          * wq - Driver workqueue for GEM.
  1813.          *
  1814.          * NOTE: Work items scheduled here are not allowed to grab any modeset
  1815.          * locks, for otherwise the flushing done in the pageflip code will
  1816.          * result in deadlocks.
  1817.          */
  1818.         struct workqueue_struct *wq;
  1819.  
  1820.         /* Display functions */
  1821.         struct drm_i915_display_funcs display;
  1822.  
  1823.         /* PCH chipset type */
  1824.         enum intel_pch pch_type;
  1825.         unsigned short pch_id;
  1826.  
  1827.         unsigned long quirks;
  1828.  
  1829.         enum modeset_restore modeset_restore;
  1830.         struct mutex modeset_restore_lock;
  1831.  
  1832.         struct list_head vm_list; /* Global list of all address spaces */
  1833.         struct i915_gtt gtt; /* VM representing the global address space */
  1834.  
  1835.         struct i915_gem_mm mm;
  1836.         DECLARE_HASHTABLE(mm_structs, 7);
  1837.         struct mutex mm_lock;
  1838.  
  1839.         /* Kernel Modesetting */
  1840.  
  1841.         struct sdvo_device_mapping sdvo_mappings[2];
  1842.  
  1843.         struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
  1844.         struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
  1845.         wait_queue_head_t pending_flip_queue;
  1846.  
  1847. #ifdef CONFIG_DEBUG_FS
  1848.         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
  1849. #endif
  1850.  
  1851.         int num_shared_dpll;
  1852.         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
  1853.         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
  1854.  
  1855.         struct i915_workarounds workarounds;
  1856.  
  1857.         /* Reclocking support */
  1858.         bool render_reclock_avail;
  1859.  
  1860.         struct i915_frontbuffer_tracking fb_tracking;
  1861.  
  1862.         u16 orig_clock;
  1863.  
  1864.         bool mchbar_need_disable;
  1865.  
  1866.         struct intel_l3_parity l3_parity;
  1867.  
  1868.         /* Cannot be determined by PCIID. You must always read a register. */
  1869.         size_t ellc_size;
  1870.  
  1871.         /* gen6+ rps state */
  1872.         struct intel_gen6_power_mgmt rps;
  1873.  
  1874.         /* ilk-only ips/rps state. Everything in here is protected by the global
  1875.          * mchdev_lock in intel_pm.c */
  1876.         struct intel_ilk_power_mgmt ips;
  1877.  
  1878.         struct i915_power_domains power_domains;
  1879.  
  1880.         struct i915_psr psr;
  1881.  
  1882.         struct i915_gpu_error gpu_error;
  1883.  
  1884.         struct drm_i915_gem_object *vlv_pctx;
  1885.  
  1886. #ifdef CONFIG_DRM_FBDEV_EMULATION
  1887.         /* list of fbdev register on this device */
  1888.         struct intel_fbdev *fbdev;
  1889.         struct work_struct fbdev_suspend_work;
  1890. #endif
  1891.  
  1892.         struct drm_property *broadcast_rgb_property;
  1893.         struct drm_property *force_audio_property;
  1894.  
  1895.         /* hda/i915 audio component */
  1896.         struct i915_audio_component *audio_component;
  1897.         bool audio_component_registered;
  1898.         /**
  1899.          * av_mutex - mutex for audio/video sync
  1900.          *
  1901.          */
  1902.         struct mutex av_mutex;
  1903.  
  1904.         uint32_t hw_context_size;
  1905.         struct list_head context_list;
  1906.  
  1907.         u32 fdi_rx_config;
  1908.  
  1909.         u32 chv_phy_control;
  1910.  
  1911.         u32 suspend_count;
  1912.         struct i915_suspend_saved_registers regfile;
  1913.         struct vlv_s0ix_state vlv_s0ix_state;
  1914.  
  1915.         struct {
  1916.                 /*
  1917.                  * Raw watermark latency values:
  1918.                  * in 0.1us units for WM0,
  1919.                  * in 0.5us units for WM1+.
  1920.                  */
  1921.                 /* primary */
  1922.                 uint16_t pri_latency[5];
  1923.                 /* sprite */
  1924.                 uint16_t spr_latency[5];
  1925.                 /* cursor */
  1926.                 uint16_t cur_latency[5];
  1927.                 /*
  1928.                  * Raw watermark memory latency values
  1929.                  * for SKL for all 8 levels
  1930.                  * in 1us units.
  1931.                  */
  1932.                 uint16_t skl_latency[8];
  1933.  
  1934.                 /*
  1935.                  * The skl_wm_values structure is a bit too big for stack
  1936.                  * allocation, so we keep the staging struct where we store
  1937.                  * intermediate results here instead.
  1938.                  */
  1939.                 struct skl_wm_values skl_results;
  1940.  
  1941.                 /* current hardware state */
  1942.                 union {
  1943.                         struct ilk_wm_values hw;
  1944.                         struct skl_wm_values skl_hw;
  1945.                         struct vlv_wm_values vlv;
  1946.                 };
  1947.  
  1948.                 uint8_t max_level;
  1949.         } wm;
  1950.  
  1951.         struct i915_runtime_pm pm;
  1952.  
  1953.         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
  1954.         struct {
  1955.                 int (*execbuf_submit)(struct i915_execbuffer_params *params,
  1956.                                       struct drm_i915_gem_execbuffer2 *args,
  1957.                                       struct list_head *vmas);
  1958.                 int (*init_rings)(struct drm_device *dev);
  1959.                 void (*cleanup_ring)(struct intel_engine_cs *ring);
  1960.                 void (*stop_ring)(struct intel_engine_cs *ring);
  1961.         } gt;
  1962.  
  1963.         bool edp_low_vswing;
  1964.  
  1965.         /* perform PHY state sanity checks? */
  1966.         bool chv_phy_assert[2];
  1967.  
  1968.         /*
  1969.          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
  1970.          * will be rejected. Instead look for a better place.
  1971.          */
  1972. };
  1973.  
  1974. static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
  1975. {
  1976.         return dev->dev_private;
  1977. }
  1978.  
  1979. static inline struct drm_i915_private *dev_to_i915(struct device *dev)
  1980. {
  1981.         return to_i915(dev_get_drvdata(dev));
  1982. }
  1983.  
  1984. static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
  1985. {
  1986.         return container_of(guc, struct drm_i915_private, guc);
  1987. }
  1988.  
  1989. /* Iterate over initialised rings */
  1990. #define for_each_ring(ring__, dev_priv__, i__) \
  1991.         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  1992.                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  1993.  
  1994. enum hdmi_force_audio {
  1995.         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
  1996.         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
  1997.         HDMI_AUDIO_AUTO,                /* trust EDID */
  1998.         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
  1999. };
  2000.  
  2001. #define I915_GTT_OFFSET_NONE ((u32)-1)
  2002.  
  2003. struct drm_i915_gem_object_ops {
  2004.         /* Interface between the GEM object and its backing storage.
  2005.          * get_pages() is called once prior to the use of the associated set
  2006.          * of pages before to binding them into the GTT, and put_pages() is
  2007.          * called after we no longer need them. As we expect there to be
  2008.          * associated cost with migrating pages between the backing storage
  2009.          * and making them available for the GPU (e.g. clflush), we may hold
  2010.          * onto the pages after they are no longer referenced by the GPU
  2011.          * in case they may be used again shortly (for example migrating the
  2012.          * pages to a different memory domain within the GTT). put_pages()
  2013.          * will therefore most likely be called when the object itself is
  2014.          * being released or under memory pressure (where we attempt to
  2015.          * reap pages for the shrinker).
  2016.          */
  2017.         int (*get_pages)(struct drm_i915_gem_object *);
  2018.         void (*put_pages)(struct drm_i915_gem_object *);
  2019.         int (*dmabuf_export)(struct drm_i915_gem_object *);
  2020.         void (*release)(struct drm_i915_gem_object *);
  2021. };
  2022.  
  2023. /*
  2024.  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
  2025.  * considered to be the frontbuffer for the given plane interface-wise. This
  2026.  * doesn't mean that the hw necessarily already scans it out, but that any
  2027.  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
  2028.  *
  2029.  * We have one bit per pipe and per scanout plane type.
  2030.  */
  2031. #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
  2032. #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
  2033. #define INTEL_FRONTBUFFER_BITS \
  2034.         (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
  2035. #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
  2036.         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
  2037. #define INTEL_FRONTBUFFER_CURSOR(pipe) \
  2038.         (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
  2039. #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
  2040.         (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
  2041. #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
  2042.         (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
  2043. #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
  2044.         (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
  2045.  
  2046. struct drm_i915_gem_object {
  2047.         struct drm_gem_object base;
  2048.  
  2049.         const struct drm_i915_gem_object_ops *ops;
  2050.  
  2051.         /** List of VMAs backed by this object */
  2052.         struct list_head vma_list;
  2053.  
  2054.         /** Stolen memory for this object, instead of being backed by shmem. */
  2055.         struct drm_mm_node *stolen;
  2056.         struct list_head global_list;
  2057.  
  2058.         struct list_head ring_list[I915_NUM_RINGS];
  2059.         /** Used in execbuf to temporarily hold a ref */
  2060.         struct list_head obj_exec_link;
  2061.  
  2062.         struct list_head batch_pool_link;
  2063.  
  2064.         /**
  2065.          * This is set if the object is on the active lists (has pending
  2066.          * rendering and so a non-zero seqno), and is not set if it i s on
  2067.          * inactive (ready to be unbound) list.
  2068.          */
  2069.         unsigned int active:I915_NUM_RINGS;
  2070.  
  2071.         /**
  2072.          * This is set if the object has been written to since last bound
  2073.          * to the GTT
  2074.          */
  2075.         unsigned int dirty:1;
  2076.  
  2077.         /**
  2078.          * Fence register bits (if any) for this object.  Will be set
  2079.          * as needed when mapped into the GTT.
  2080.          * Protected by dev->struct_mutex.
  2081.          */
  2082.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  2083.  
  2084.         /**
  2085.          * Advice: are the backing pages purgeable?
  2086.          */
  2087.         unsigned int madv:2;
  2088.  
  2089.         /**
  2090.          * Current tiling mode for the object.
  2091.          */
  2092.         unsigned int tiling_mode:2;
  2093.         /**
  2094.          * Whether the tiling parameters for the currently associated fence
  2095.          * register have changed. Note that for the purposes of tracking
  2096.          * tiling changes we also treat the unfenced register, the register
  2097.          * slot that the object occupies whilst it executes a fenced
  2098.          * command (such as BLT on gen2/3), as a "fence".
  2099.          */
  2100.         unsigned int fence_dirty:1;
  2101.  
  2102.         /**
  2103.          * Is the object at the current location in the gtt mappable and
  2104.          * fenceable? Used to avoid costly recalculations.
  2105.          */
  2106.         unsigned int map_and_fenceable:1;
  2107.  
  2108.         /**
  2109.          * Whether the current gtt mapping needs to be mappable (and isn't just
  2110.          * mappable by accident). Track pin and fault separate for a more
  2111.          * accurate mappable working set.
  2112.          */
  2113.         unsigned int fault_mappable:1;
  2114.  
  2115.         /*
  2116.          * Is the object to be mapped as read-only to the GPU
  2117.          * Only honoured if hardware has relevant pte bit
  2118.          */
  2119.         unsigned long gt_ro:1;
  2120.         unsigned int cache_level:3;
  2121.         unsigned int cache_dirty:1;
  2122.  
  2123.         unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
  2124.  
  2125.         unsigned int pin_display;
  2126.  
  2127.         struct sg_table *pages;
  2128.         int pages_pin_count;
  2129.         struct get_page {
  2130.                 struct scatterlist *sg;
  2131.                 int last;
  2132.         } get_page;
  2133.  
  2134.         /* prime dma-buf support */
  2135.         void *dma_buf_vmapping;
  2136.         int vmapping_count;
  2137.  
  2138.         /** Breadcrumb of last rendering to the buffer.
  2139.          * There can only be one writer, but we allow for multiple readers.
  2140.          * If there is a writer that necessarily implies that all other
  2141.          * read requests are complete - but we may only be lazily clearing
  2142.          * the read requests. A read request is naturally the most recent
  2143.          * request on a ring, so we may have two different write and read
  2144.          * requests on one ring where the write request is older than the
  2145.          * read request. This allows for the CPU to read from an active
  2146.          * buffer by only waiting for the write to complete.
  2147.          * */
  2148.         struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
  2149.         struct drm_i915_gem_request *last_write_req;
  2150.         /** Breadcrumb of last fenced GPU access to the buffer. */
  2151.         struct drm_i915_gem_request *last_fenced_req;
  2152.  
  2153.         /** Current tiling stride for the object, if it's tiled. */
  2154.         uint32_t stride;
  2155.  
  2156.         /** References from framebuffers, locks out tiling changes. */
  2157.         unsigned long framebuffer_references;
  2158.  
  2159.         /** Record of address bit 17 of each page at last unbind. */
  2160.         unsigned long *bit_17;
  2161.  
  2162.         union {
  2163.                 /** for phy allocated objects */
  2164.                 struct drm_dma_handle *phys_handle;
  2165.  
  2166.                 struct i915_gem_userptr {
  2167.                         uintptr_t ptr;
  2168.                         unsigned read_only :1;
  2169.                         unsigned workers :4;
  2170. #define I915_GEM_USERPTR_MAX_WORKERS 15
  2171.  
  2172.                         struct i915_mm_struct *mm;
  2173.                         struct i915_mmu_object *mmu_object;
  2174.                         struct work_struct *work;
  2175.                 } userptr;
  2176.         };
  2177. };
  2178. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  2179.  
  2180. void i915_gem_track_fb(struct drm_i915_gem_object *old,
  2181.                        struct drm_i915_gem_object *new,
  2182.                        unsigned frontbuffer_bits);
  2183.  
  2184. /**
  2185.  * Request queue structure.
  2186.  *
  2187.  * The request queue allows us to note sequence numbers that have been emitted
  2188.  * and may be associated with active buffers to be retired.
  2189.  *
  2190.  * By keeping this list, we can avoid having to do questionable sequence
  2191.  * number comparisons on buffer last_read|write_seqno. It also allows an
  2192.  * emission time to be associated with the request for tracking how far ahead
  2193.  * of the GPU the submission is.
  2194.  *
  2195.  * The requests are reference counted, so upon creation they should have an
  2196.  * initial reference taken using kref_init
  2197.  */
  2198. struct drm_i915_gem_request {
  2199.         struct kref ref;
  2200.  
  2201.         /** On Which ring this request was generated */
  2202.         struct drm_i915_private *i915;
  2203.         struct intel_engine_cs *ring;
  2204.  
  2205.          /** GEM sequence number associated with the previous request,
  2206.           * when the HWS breadcrumb is equal to this the GPU is processing
  2207.           * this request.
  2208.           */
  2209.         u32 previous_seqno;
  2210.  
  2211.          /** GEM sequence number associated with this request,
  2212.           * when the HWS breadcrumb is equal or greater than this the GPU
  2213.           * has finished processing this request.
  2214.           */
  2215.         u32 seqno;
  2216.  
  2217.         /** Position in the ringbuffer of the start of the request */
  2218.         u32 head;
  2219.  
  2220.         /**
  2221.          * Position in the ringbuffer of the start of the postfix.
  2222.          * This is required to calculate the maximum available ringbuffer
  2223.          * space without overwriting the postfix.
  2224.          */
  2225.          u32 postfix;
  2226.  
  2227.         /** Position in the ringbuffer of the end of the whole request */
  2228.         u32 tail;
  2229.  
  2230.         /**
  2231.          * Context and ring buffer related to this request
  2232.          * Contexts are refcounted, so when this request is associated with a
  2233.          * context, we must increment the context's refcount, to guarantee that
  2234.          * it persists while any request is linked to it. Requests themselves
  2235.          * are also refcounted, so the request will only be freed when the last
  2236.          * reference to it is dismissed, and the code in
  2237.          * i915_gem_request_free() will then decrement the refcount on the
  2238.          * context.
  2239.          */
  2240.         struct intel_context *ctx;
  2241.         struct intel_ringbuffer *ringbuf;
  2242.  
  2243.         /** Batch buffer related to this request if any (used for
  2244.             error state dump only) */
  2245.         struct drm_i915_gem_object *batch_obj;
  2246.  
  2247.         /** Time at which this request was emitted, in jiffies. */
  2248.         unsigned long emitted_jiffies;
  2249.  
  2250.         /** global list entry for this request */
  2251.         struct list_head list;
  2252.  
  2253.         struct drm_i915_file_private *file_priv;
  2254.         /** file_priv list entry for this request */
  2255.         struct list_head client_list;
  2256.  
  2257.         /** process identifier submitting this request */
  2258.         struct pid *pid;
  2259.  
  2260.         /**
  2261.          * The ELSP only accepts two elements at a time, so we queue
  2262.          * context/tail pairs on a given queue (ring->execlist_queue) until the
  2263.          * hardware is available. The queue serves a double purpose: we also use
  2264.          * it to keep track of the up to 2 contexts currently in the hardware
  2265.          * (usually one in execution and the other queued up by the GPU): We
  2266.          * only remove elements from the head of the queue when the hardware
  2267.          * informs us that an element has been completed.
  2268.          *
  2269.          * All accesses to the queue are mediated by a spinlock
  2270.          * (ring->execlist_lock).
  2271.          */
  2272.  
  2273.         /** Execlist link in the submission queue.*/
  2274.         struct list_head execlist_link;
  2275.  
  2276.         /** Execlists no. of times this request has been sent to the ELSP */
  2277.         int elsp_submitted;
  2278.  
  2279. };
  2280.  
  2281. int i915_gem_request_alloc(struct intel_engine_cs *ring,
  2282.                            struct intel_context *ctx,
  2283.                            struct drm_i915_gem_request **req_out);
  2284. void i915_gem_request_cancel(struct drm_i915_gem_request *req);
  2285. void i915_gem_request_free(struct kref *req_ref);
  2286. int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
  2287.                                    struct drm_file *file);
  2288.  
  2289. static inline uint32_t
  2290. i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
  2291. {
  2292.         return req ? req->seqno : 0;
  2293. }
  2294.  
  2295. static inline struct intel_engine_cs *
  2296. i915_gem_request_get_ring(struct drm_i915_gem_request *req)
  2297. {
  2298.         return req ? req->ring : NULL;
  2299. }
  2300.  
  2301. static inline struct drm_i915_gem_request *
  2302. i915_gem_request_reference(struct drm_i915_gem_request *req)
  2303. {
  2304.         if (req)
  2305.                 kref_get(&req->ref);
  2306.         return req;
  2307. }
  2308.  
  2309. static inline void
  2310. i915_gem_request_unreference(struct drm_i915_gem_request *req)
  2311. {
  2312.         WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
  2313.         kref_put(&req->ref, i915_gem_request_free);
  2314. }
  2315.  
  2316. static inline void
  2317. i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
  2318. {
  2319.         struct drm_device *dev;
  2320.  
  2321.         if (!req)
  2322.                 return;
  2323.  
  2324.         dev = req->ring->dev;
  2325.         if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
  2326.                 mutex_unlock(&dev->struct_mutex);
  2327. }
  2328.  
  2329. static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
  2330.                                            struct drm_i915_gem_request *src)
  2331. {
  2332.         if (src)
  2333.                 i915_gem_request_reference(src);
  2334.  
  2335.         if (*pdst)
  2336.                 i915_gem_request_unreference(*pdst);
  2337.  
  2338.         *pdst = src;
  2339. }
  2340.  
  2341. /*
  2342.  * XXX: i915_gem_request_completed should be here but currently needs the
  2343.  * definition of i915_seqno_passed() which is below. It will be moved in
  2344.  * a later patch when the call to i915_seqno_passed() is obsoleted...
  2345.  */
  2346.  
  2347. /*
  2348.  * A command that requires special handling by the command parser.
  2349.  */
  2350. struct drm_i915_cmd_descriptor {
  2351.         /*
  2352.          * Flags describing how the command parser processes the command.
  2353.          *
  2354.          * CMD_DESC_FIXED: The command has a fixed length if this is set,
  2355.          *                 a length mask if not set
  2356.          * CMD_DESC_SKIP: The command is allowed but does not follow the
  2357.          *                standard length encoding for the opcode range in
  2358.          *                which it falls
  2359.          * CMD_DESC_REJECT: The command is never allowed
  2360.          * CMD_DESC_REGISTER: The command should be checked against the
  2361.          *                    register whitelist for the appropriate ring
  2362.          * CMD_DESC_MASTER: The command is allowed if the submitting process
  2363.          *                  is the DRM master
  2364.          */
  2365.         u32 flags;
  2366. #define CMD_DESC_FIXED    (1<<0)
  2367. #define CMD_DESC_SKIP     (1<<1)
  2368. #define CMD_DESC_REJECT   (1<<2)
  2369. #define CMD_DESC_REGISTER (1<<3)
  2370. #define CMD_DESC_BITMASK  (1<<4)
  2371. #define CMD_DESC_MASTER   (1<<5)
  2372.  
  2373.         /*
  2374.          * The command's unique identification bits and the bitmask to get them.
  2375.          * This isn't strictly the opcode field as defined in the spec and may
  2376.          * also include type, subtype, and/or subop fields.
  2377.          */
  2378.         struct {
  2379.                 u32 value;
  2380.                 u32 mask;
  2381.         } cmd;
  2382.  
  2383.         /*
  2384.          * The command's length. The command is either fixed length (i.e. does
  2385.          * not include a length field) or has a length field mask. The flag
  2386.          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
  2387.          * a length mask. All command entries in a command table must include
  2388.          * length information.
  2389.          */
  2390.         union {
  2391.                 u32 fixed;
  2392.                 u32 mask;
  2393.         } length;
  2394.  
  2395.         /*
  2396.          * Describes where to find a register address in the command to check
  2397.          * against the ring's register whitelist. Only valid if flags has the
  2398.          * CMD_DESC_REGISTER bit set.
  2399.          *
  2400.          * A non-zero step value implies that the command may access multiple
  2401.          * registers in sequence (e.g. LRI), in that case step gives the
  2402.          * distance in dwords between individual offset fields.
  2403.          */
  2404.         struct {
  2405.                 u32 offset;
  2406.                 u32 mask;
  2407.                 u32 step;
  2408.         } reg;
  2409.  
  2410. #define MAX_CMD_DESC_BITMASKS 3
  2411.         /*
  2412.          * Describes command checks where a particular dword is masked and
  2413.          * compared against an expected value. If the command does not match
  2414.          * the expected value, the parser rejects it. Only valid if flags has
  2415.          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
  2416.          * are valid.
  2417.          *
  2418.          * If the check specifies a non-zero condition_mask then the parser
  2419.          * only performs the check when the bits specified by condition_mask
  2420.          * are non-zero.
  2421.          */
  2422.         struct {
  2423.                 u32 offset;
  2424.                 u32 mask;
  2425.                 u32 expected;
  2426.                 u32 condition_offset;
  2427.                 u32 condition_mask;
  2428.         } bits[MAX_CMD_DESC_BITMASKS];
  2429. };
  2430.  
  2431. /*
  2432.  * A table of commands requiring special handling by the command parser.
  2433.  *
  2434.  * Each ring has an array of tables. Each table consists of an array of command
  2435.  * descriptors, which must be sorted with command opcodes in ascending order.
  2436.  */
  2437. struct drm_i915_cmd_table {
  2438.         const struct drm_i915_cmd_descriptor *table;
  2439.         int count;
  2440. };
  2441.  
  2442. /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
  2443. #define __I915__(p) ({ \
  2444.         struct drm_i915_private *__p; \
  2445.         if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
  2446.                 __p = (struct drm_i915_private *)p; \
  2447.         else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
  2448.                 __p = to_i915((struct drm_device *)p); \
  2449.         else \
  2450.                 BUILD_BUG(); \
  2451.         __p; \
  2452. })
  2453. #define INTEL_INFO(p)   (&__I915__(p)->info)
  2454. #define INTEL_DEVID(p)  (INTEL_INFO(p)->device_id)
  2455. #define INTEL_REVID(p)  (__I915__(p)->dev->pdev->revision)
  2456.  
  2457. #define IS_I830(dev)            (INTEL_DEVID(dev) == 0x3577)
  2458. #define IS_845G(dev)            (INTEL_DEVID(dev) == 0x2562)
  2459. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  2460. #define IS_I865G(dev)           (INTEL_DEVID(dev) == 0x2572)
  2461. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  2462. #define IS_I915GM(dev)          (INTEL_DEVID(dev) == 0x2592)
  2463. #define IS_I945G(dev)           (INTEL_DEVID(dev) == 0x2772)
  2464. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  2465. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  2466. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  2467. #define IS_GM45(dev)            (INTEL_DEVID(dev) == 0x2A42)
  2468. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  2469. #define IS_PINEVIEW_G(dev)      (INTEL_DEVID(dev) == 0xa001)
  2470. #define IS_PINEVIEW_M(dev)      (INTEL_DEVID(dev) == 0xa011)
  2471. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  2472. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  2473. #define IS_IRONLAKE_M(dev)      (INTEL_DEVID(dev) == 0x0046)
  2474. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  2475. #define IS_IVB_GT1(dev)         (INTEL_DEVID(dev) == 0x0156 || \
  2476.                                  INTEL_DEVID(dev) == 0x0152 || \
  2477.                                  INTEL_DEVID(dev) == 0x015a)
  2478. #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
  2479. #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
  2480. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  2481. #define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
  2482. #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
  2483. #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
  2484. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  2485. #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
  2486.                                  (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
  2487. #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
  2488.                                  ((INTEL_DEVID(dev) & 0xf) == 0x6 ||    \
  2489.                                  (INTEL_DEVID(dev) & 0xf) == 0xb ||     \
  2490.                                  (INTEL_DEVID(dev) & 0xf) == 0xe))
  2491. /* ULX machines are also considered ULT. */
  2492. #define IS_BDW_ULX(dev)         (IS_BROADWELL(dev) && \
  2493.                                  (INTEL_DEVID(dev) & 0xf) == 0xe)
  2494. #define IS_BDW_GT3(dev)         (IS_BROADWELL(dev) && \
  2495.                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
  2496. #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
  2497.                                  (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
  2498. #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
  2499.                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
  2500. /* ULX machines are also considered ULT. */
  2501. #define IS_HSW_ULX(dev)         (INTEL_DEVID(dev) == 0x0A0E || \
  2502.                                  INTEL_DEVID(dev) == 0x0A1E)
  2503. #define IS_SKL_ULT(dev)         (INTEL_DEVID(dev) == 0x1906 || \
  2504.                                  INTEL_DEVID(dev) == 0x1913 || \
  2505.                                  INTEL_DEVID(dev) == 0x1916 || \
  2506.                                  INTEL_DEVID(dev) == 0x1921 || \
  2507.                                  INTEL_DEVID(dev) == 0x1926)
  2508. #define IS_SKL_ULX(dev)         (INTEL_DEVID(dev) == 0x190E || \
  2509.                                  INTEL_DEVID(dev) == 0x1915 || \
  2510.                                  INTEL_DEVID(dev) == 0x191E)
  2511. #define IS_SKL_GT3(dev)         (IS_SKYLAKE(dev) && \
  2512.                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
  2513. #define IS_SKL_GT4(dev)         (IS_SKYLAKE(dev) && \
  2514.                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
  2515.  
  2516. #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
  2517.  
  2518. #define SKL_REVID_A0            (0x0)
  2519. #define SKL_REVID_B0            (0x1)
  2520. #define SKL_REVID_C0            (0x2)
  2521. #define SKL_REVID_D0            (0x3)
  2522. #define SKL_REVID_E0            (0x4)
  2523. #define SKL_REVID_F0            (0x5)
  2524.  
  2525. #define BXT_REVID_A0            (0x0)
  2526. #define BXT_REVID_B0            (0x3)
  2527. #define BXT_REVID_C0            (0x9)
  2528.  
  2529. /*
  2530.  * The genX designation typically refers to the render engine, so render
  2531.  * capability related checks should use IS_GEN, while display and other checks
  2532.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  2533.  * chips, etc.).
  2534.  */
  2535. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  2536. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  2537. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  2538. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  2539. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  2540. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  2541. #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
  2542. #define IS_GEN9(dev)    (INTEL_INFO(dev)->gen == 9)
  2543.  
  2544. #define RENDER_RING             (1<<RCS)
  2545. #define BSD_RING                (1<<VCS)
  2546. #define BLT_RING                (1<<BCS)
  2547. #define VEBOX_RING              (1<<VECS)
  2548. #define BSD2_RING               (1<<VCS2)
  2549. #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
  2550. #define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
  2551. #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
  2552. #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
  2553. #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
  2554. #define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
  2555.                                  __I915__(dev)->ellc_size)
  2556. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  2557.  
  2558. #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
  2559. #define HAS_LOGICAL_RING_CONTEXTS(dev)  (INTEL_INFO(dev)->gen >= 8)
  2560. #define USES_PPGTT(dev)         (i915.enable_ppgtt)
  2561. #define USES_FULL_PPGTT(dev)    (i915.enable_ppgtt >= 2)
  2562. #define USES_FULL_48BIT_PPGTT(dev)      (i915.enable_ppgtt == 3)
  2563.  
  2564. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  2565. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  2566.  
  2567. /* Early gen2 have a totally busted CS tlb and require pinned batches. */
  2568. #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
  2569. /*
  2570.  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  2571.  * even when in MSI mode. This results in spurious interrupt warnings if the
  2572.  * legacy irq no. is shared with another device. The kernel then disables that
  2573.  * interrupt source and so prevents the other device from working properly.
  2574.  */
  2575. #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
  2576. #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
  2577.  
  2578. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  2579.  * rows, which changed the alignment requirements and fence programming.
  2580.  */
  2581. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  2582.                                                       IS_I915GM(dev)))
  2583. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  2584. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  2585.  
  2586. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  2587. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  2588. #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  2589.  
  2590. #define HAS_IPS(dev)            (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
  2591.  
  2592. #define HAS_DP_MST(dev)         (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
  2593.                                  INTEL_INFO(dev)->gen >= 9)
  2594.  
  2595. #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
  2596. #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
  2597. #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
  2598.                                  IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
  2599.                                  IS_SKYLAKE(dev))
  2600. #define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
  2601.                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
  2602.                                  IS_SKYLAKE(dev))
  2603. #define HAS_RC6(dev)            (INTEL_INFO(dev)->gen >= 6)
  2604. #define HAS_RC6p(dev)           (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
  2605.  
  2606. #define HAS_CSR(dev)    (IS_GEN9(dev))
  2607.  
  2608. #define HAS_GUC_UCODE(dev)      (IS_GEN9(dev))
  2609. #define HAS_GUC_SCHED(dev)      (IS_GEN9(dev))
  2610.  
  2611. #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
  2612.                                     INTEL_INFO(dev)->gen >= 8)
  2613.  
  2614. #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
  2615.                                  !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
  2616.  
  2617. #define INTEL_PCH_DEVICE_ID_MASK                0xff00
  2618. #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
  2619. #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
  2620. #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
  2621. #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
  2622. #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
  2623. #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
  2624. #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
  2625. #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
  2626.  
  2627. #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
  2628. #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
  2629. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  2630. #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
  2631. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  2632. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  2633. #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
  2634. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  2635.  
  2636. #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
  2637.  
  2638. /* DPF == dynamic parity feature */
  2639. #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  2640. #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
  2641.  
  2642. #define GT_FREQUENCY_MULTIPLIER 50
  2643. #define GEN9_FREQ_SCALER 3
  2644.  
  2645. #include "i915_trace.h"
  2646.  
  2647. extern const struct drm_ioctl_desc i915_ioctls[];
  2648. extern int i915_max_ioctl;
  2649.  
  2650. extern int i915_resume_switcheroo(struct drm_device *dev);
  2651.  
  2652. /* i915_params.c */
  2653. struct i915_params {
  2654.         int modeset;
  2655.         int panel_ignore_lid;
  2656.         int semaphores;
  2657.         int lvds_channel_mode;
  2658.         int panel_use_ssc;
  2659.         int vbt_sdvo_panel_type;
  2660.         int enable_rc6;
  2661.         int enable_fbc;
  2662.         int enable_ppgtt;
  2663.         int enable_execlists;
  2664.         int enable_psr;
  2665.         unsigned int preliminary_hw_support;
  2666.         int disable_power_well;
  2667.         int enable_ips;
  2668.         int invert_brightness;
  2669.         int enable_cmd_parser;
  2670.         /* leave bools at the end to not create holes */
  2671.         bool enable_hangcheck;
  2672.         bool fastboot;
  2673.         bool prefault_disable;
  2674.         bool load_detect_test;
  2675.         bool reset;
  2676.         bool disable_display;
  2677.         bool disable_vtd_wa;
  2678.         bool enable_guc_submission;
  2679.         int guc_log_level;
  2680.         int use_mmio_flip;
  2681.         int mmio_debug;
  2682.         bool verbose_state_checks;
  2683.         bool nuclear_pageflip;
  2684.         int edp_vswing;
  2685.                 /* Kolibri related */
  2686.     char *log_file;
  2687.     char *cmdline_mode;
  2688. };
  2689. extern struct i915_params i915 __read_mostly;
  2690.  
  2691.                                 /* i915_dma.c */
  2692. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  2693. extern int i915_driver_unload(struct drm_device *);
  2694. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
  2695. extern void i915_driver_lastclose(struct drm_device * dev);
  2696. extern void i915_driver_preclose(struct drm_device *dev,
  2697.                                  struct drm_file *file);
  2698. extern void i915_driver_postclose(struct drm_device *dev,
  2699.                                   struct drm_file *file);
  2700. #ifdef CONFIG_COMPAT
  2701. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  2702.                               unsigned long arg);
  2703. #endif
  2704. extern int intel_gpu_reset(struct drm_device *dev);
  2705. extern bool intel_has_gpu_reset(struct drm_device *dev);
  2706. extern int i915_reset(struct drm_device *dev);
  2707. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  2708. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  2709. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  2710. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  2711. int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
  2712. void i915_firmware_load_error_print(const char *fw_path, int err);
  2713.  
  2714. /* intel_hotplug.c */
  2715. void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
  2716. void intel_hpd_init(struct drm_i915_private *dev_priv);
  2717. void intel_hpd_init_work(struct drm_i915_private *dev_priv);
  2718. void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
  2719. bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
  2720.  
  2721. /* i915_irq.c */
  2722. void i915_queue_hangcheck(struct drm_device *dev);
  2723. __printf(3, 4)
  2724. void i915_handle_error(struct drm_device *dev, bool wedged,
  2725.                        const char *fmt, ...);
  2726.  
  2727. extern void intel_irq_init(struct drm_i915_private *dev_priv);
  2728. int intel_irq_install(struct drm_i915_private *dev_priv);
  2729. void intel_irq_uninstall(struct drm_i915_private *dev_priv);
  2730.  
  2731. extern void intel_uncore_sanitize(struct drm_device *dev);
  2732. extern void intel_uncore_early_sanitize(struct drm_device *dev,
  2733.                                         bool restore_forcewake);
  2734. extern void intel_uncore_init(struct drm_device *dev);
  2735. extern void intel_uncore_check_errors(struct drm_device *dev);
  2736. extern void intel_uncore_fini(struct drm_device *dev);
  2737. extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
  2738. const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
  2739. void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
  2740.                                 enum forcewake_domains domains);
  2741. void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
  2742.                                 enum forcewake_domains domains);
  2743. /* Like above but the caller must manage the uncore.lock itself.
  2744.  * Must be used with I915_READ_FW and friends.
  2745.  */
  2746. void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
  2747.                                         enum forcewake_domains domains);
  2748. void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
  2749.                                         enum forcewake_domains domains);
  2750. void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
  2751. static inline bool intel_vgpu_active(struct drm_device *dev)
  2752. {
  2753.         return to_i915(dev)->vgpu.active;
  2754. }
  2755.  
  2756. void
  2757. i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  2758.                      u32 status_mask);
  2759.  
  2760. void
  2761. i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
  2762.                       u32 status_mask);
  2763.  
  2764. void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
  2765. void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
  2766. void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
  2767.                                    uint32_t mask,
  2768.                                    uint32_t bits);
  2769. void
  2770. ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
  2771. void
  2772. ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
  2773. void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
  2774.                                   uint32_t interrupt_mask,
  2775.                                   uint32_t enabled_irq_mask);
  2776. #define ibx_enable_display_interrupt(dev_priv, bits) \
  2777.         ibx_display_interrupt_update((dev_priv), (bits), (bits))
  2778. #define ibx_disable_display_interrupt(dev_priv, bits) \
  2779.         ibx_display_interrupt_update((dev_priv), (bits), 0)
  2780.  
  2781. /* i915_gem.c */
  2782. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  2783.                           struct drm_file *file_priv);
  2784. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  2785.                          struct drm_file *file_priv);
  2786. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  2787.                           struct drm_file *file_priv);
  2788. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  2789.                         struct drm_file *file_priv);
  2790. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  2791.                         struct drm_file *file_priv);
  2792. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  2793.                               struct drm_file *file_priv);
  2794. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  2795.                              struct drm_file *file_priv);
  2796. void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
  2797.                                         struct drm_i915_gem_request *req);
  2798. void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
  2799. int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
  2800.                                    struct drm_i915_gem_execbuffer2 *args,
  2801.                                    struct list_head *vmas);
  2802. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  2803.                         struct drm_file *file_priv);
  2804. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  2805.                          struct drm_file *file_priv);
  2806. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  2807.                         struct drm_file *file_priv);
  2808. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  2809.                                struct drm_file *file);
  2810. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  2811.                                struct drm_file *file);
  2812. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  2813.                             struct drm_file *file_priv);
  2814. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  2815.                            struct drm_file *file_priv);
  2816. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  2817.                         struct drm_file *file_priv);
  2818. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  2819.                         struct drm_file *file_priv);
  2820. int i915_gem_init_userptr(struct drm_device *dev);
  2821. int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
  2822.                            struct drm_file *file);
  2823. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  2824.                                 struct drm_file *file_priv);
  2825. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  2826.                         struct drm_file *file_priv);
  2827. void i915_gem_load(struct drm_device *dev);
  2828. void *i915_gem_object_alloc(struct drm_device *dev);
  2829. void i915_gem_object_free(struct drm_i915_gem_object *obj);
  2830. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  2831.                          const struct drm_i915_gem_object_ops *ops);
  2832. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  2833.                                                   size_t size);
  2834. struct drm_i915_gem_object *i915_gem_object_create_from_data(
  2835.                 struct drm_device *dev, const void *data, size_t size);
  2836. void i915_gem_free_object(struct drm_gem_object *obj);
  2837. void i915_gem_vma_destroy(struct i915_vma *vma);
  2838.  
  2839. /* Flags used by pin/bind&friends. */
  2840. #define PIN_MAPPABLE    (1<<0)
  2841. #define PIN_NONBLOCK    (1<<1)
  2842. #define PIN_GLOBAL      (1<<2)
  2843. #define PIN_OFFSET_BIAS (1<<3)
  2844. #define PIN_USER        (1<<4)
  2845. #define PIN_UPDATE      (1<<5)
  2846. #define PIN_ZONE_4G     (1<<6)
  2847. #define PIN_HIGH        (1<<7)
  2848. #define PIN_OFFSET_MASK (~4095)
  2849. int __must_check
  2850. i915_gem_object_pin(struct drm_i915_gem_object *obj,
  2851.                     struct i915_address_space *vm,
  2852.                     uint32_t alignment,
  2853.                     uint64_t flags);
  2854. int __must_check
  2855. i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
  2856.                          const struct i915_ggtt_view *view,
  2857.                          uint32_t alignment,
  2858.                          uint64_t flags);
  2859.  
  2860. int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
  2861.                   u32 flags);
  2862. void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
  2863. int __must_check i915_vma_unbind(struct i915_vma *vma);
  2864. /*
  2865.  * BEWARE: Do not use the function below unless you can _absolutely_
  2866.  * _guarantee_ VMA in question is _not in use_ anywhere.
  2867.  */
  2868. int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
  2869. int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
  2870. void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
  2871. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  2872.  
  2873. int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
  2874.                                     int *needs_clflush);
  2875.  
  2876. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  2877.  
  2878. static inline int __sg_page_count(struct scatterlist *sg)
  2879. {
  2880.         return sg->length >> PAGE_SHIFT;
  2881. }
  2882.  
  2883. static inline struct page *
  2884. i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  2885. {
  2886.         if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
  2887.                 return NULL;
  2888.  
  2889.         if (n < obj->get_page.last) {
  2890.                 obj->get_page.sg = obj->pages->sgl;
  2891.                 obj->get_page.last = 0;
  2892.         }
  2893.  
  2894.         while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
  2895.                 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
  2896.                 if (unlikely(sg_is_chain(obj->get_page.sg)))
  2897.                         obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
  2898.         }
  2899.  
  2900.         return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
  2901. }
  2902.  
  2903. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  2904. {
  2905.         BUG_ON(obj->pages == NULL);
  2906.         obj->pages_pin_count++;
  2907. }
  2908. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  2909. {
  2910.         BUG_ON(obj->pages_pin_count == 0);
  2911.         obj->pages_pin_count--;
  2912. }
  2913.  
  2914. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  2915. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  2916.                          struct intel_engine_cs *to,
  2917.                          struct drm_i915_gem_request **to_req);
  2918. void i915_vma_move_to_active(struct i915_vma *vma,
  2919.                              struct drm_i915_gem_request *req);
  2920. int i915_gem_dumb_create(struct drm_file *file_priv,
  2921.                          struct drm_device *dev,
  2922.                          struct drm_mode_create_dumb *args);
  2923. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  2924.                       uint32_t handle, uint64_t *offset);
  2925. /**
  2926.  * Returns true if seq1 is later than seq2.
  2927.  */
  2928. static inline bool
  2929. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  2930. {
  2931.         return (int32_t)(seq1 - seq2) >= 0;
  2932. }
  2933.  
  2934. static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
  2935.                                            bool lazy_coherency)
  2936. {
  2937.         u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
  2938.         return i915_seqno_passed(seqno, req->previous_seqno);
  2939. }
  2940.  
  2941. static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
  2942.                                               bool lazy_coherency)
  2943. {
  2944.         u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
  2945.         return i915_seqno_passed(seqno, req->seqno);
  2946. }
  2947.  
  2948. int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
  2949. int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
  2950.  
  2951. struct drm_i915_gem_request *
  2952. i915_gem_find_active_request(struct intel_engine_cs *ring);
  2953.  
  2954. bool i915_gem_retire_requests(struct drm_device *dev);
  2955. void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
  2956. int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
  2957.                                       bool interruptible);
  2958.  
  2959. static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
  2960. {
  2961.         return unlikely(atomic_read(&error->reset_counter)
  2962.                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
  2963. }
  2964.  
  2965. static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
  2966. {
  2967.         return atomic_read(&error->reset_counter) & I915_WEDGED;
  2968. }
  2969.  
  2970. static inline u32 i915_reset_count(struct i915_gpu_error *error)
  2971. {
  2972.         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
  2973. }
  2974.  
  2975. static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
  2976. {
  2977.         return dev_priv->gpu_error.stop_rings == 0 ||
  2978.                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
  2979. }
  2980.  
  2981. static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
  2982. {
  2983.         return dev_priv->gpu_error.stop_rings == 0 ||
  2984.                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
  2985. }
  2986.  
  2987. void i915_gem_reset(struct drm_device *dev);
  2988. bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
  2989. int __must_check i915_gem_init(struct drm_device *dev);
  2990. int i915_gem_init_rings(struct drm_device *dev);
  2991. int __must_check i915_gem_init_hw(struct drm_device *dev);
  2992. int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
  2993. void i915_gem_init_swizzling(struct drm_device *dev);
  2994. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  2995. int __must_check i915_gpu_idle(struct drm_device *dev);
  2996. int __must_check i915_gem_suspend(struct drm_device *dev);
  2997. void __i915_add_request(struct drm_i915_gem_request *req,
  2998.                         struct drm_i915_gem_object *batch_obj,
  2999.                         bool flush_caches);
  3000. #define i915_add_request(req) \
  3001.         __i915_add_request(req, NULL, true)
  3002. #define i915_add_request_no_flush(req) \
  3003.         __i915_add_request(req, NULL, false)
  3004. int __i915_wait_request(struct drm_i915_gem_request *req,
  3005.                         unsigned reset_counter,
  3006.                         bool interruptible,
  3007.                         s64 *timeout,
  3008.                         struct intel_rps_client *rps);
  3009. int __must_check i915_wait_request(struct drm_i915_gem_request *req);
  3010. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  3011. int __must_check
  3012. i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  3013.                                bool readonly);
  3014. int __must_check
  3015. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  3016.                                   bool write);
  3017. int __must_check
  3018. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  3019. int __must_check
  3020. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  3021.                                      u32 alignment,
  3022.                                      struct intel_engine_cs *pipelined,
  3023.                                      struct drm_i915_gem_request **pipelined_request,
  3024.                                      const struct i915_ggtt_view *view);
  3025. void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
  3026.                                               const struct i915_ggtt_view *view);
  3027. int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
  3028.                                 int align);
  3029. int i915_gem_open(struct drm_device *dev, struct drm_file *file);
  3030. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  3031.  
  3032. uint32_t
  3033. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
  3034. uint32_t
  3035. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  3036.                             int tiling_mode, bool fenced);
  3037.  
  3038. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  3039.                                     enum i915_cache_level cache_level);
  3040.  
  3041. struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
  3042.                                 struct dma_buf *dma_buf);
  3043.  
  3044. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  3045.                                 struct drm_gem_object *gem_obj, int flags);
  3046.  
  3047. u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
  3048.                                   const struct i915_ggtt_view *view);
  3049. u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
  3050.                         struct i915_address_space *vm);
  3051. static inline u64
  3052. i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
  3053. {
  3054.         return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
  3055. }
  3056.  
  3057. bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
  3058. bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
  3059.                                   const struct i915_ggtt_view *view);
  3060. bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
  3061.                         struct i915_address_space *vm);
  3062.  
  3063. unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
  3064.                                 struct i915_address_space *vm);
  3065. struct i915_vma *
  3066. i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
  3067.                     struct i915_address_space *vm);
  3068. struct i915_vma *
  3069. i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
  3070.                           const struct i915_ggtt_view *view);
  3071.  
  3072. struct i915_vma *
  3073. i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
  3074.                                   struct i915_address_space *vm);
  3075. struct i915_vma *
  3076. i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
  3077.                                        const struct i915_ggtt_view *view);
  3078.  
  3079. static inline struct i915_vma *
  3080. i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
  3081. {
  3082.         return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
  3083. }
  3084. bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
  3085.  
  3086. /* Some GGTT VM helpers */
  3087. #define i915_obj_to_ggtt(obj) \
  3088.         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
  3089. static inline bool i915_is_ggtt(struct i915_address_space *vm)
  3090. {
  3091.         struct i915_address_space *ggtt =
  3092.                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
  3093.         return vm == ggtt;
  3094. }
  3095.  
  3096. static inline struct i915_hw_ppgtt *
  3097. i915_vm_to_ppgtt(struct i915_address_space *vm)
  3098. {
  3099.         WARN_ON(i915_is_ggtt(vm));
  3100.  
  3101.         return container_of(vm, struct i915_hw_ppgtt, base);
  3102. }
  3103.  
  3104.  
  3105. static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
  3106. {
  3107.         return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
  3108. }
  3109.  
  3110. static inline unsigned long
  3111. i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
  3112. {
  3113.         return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
  3114. }
  3115.  
  3116. static inline int __must_check
  3117. i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
  3118.                       uint32_t alignment,
  3119.                       unsigned flags)
  3120. {
  3121.         return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
  3122.                                    alignment, flags | PIN_GLOBAL);
  3123. }
  3124.  
  3125. static inline int
  3126. i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
  3127. {
  3128.         return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
  3129. }
  3130.  
  3131. void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
  3132.                                      const struct i915_ggtt_view *view);
  3133. static inline void
  3134. i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
  3135. {
  3136.         i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
  3137. }
  3138.  
  3139. /* i915_gem_fence.c */
  3140. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  3141. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  3142.  
  3143. bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
  3144. void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
  3145.  
  3146. void i915_gem_restore_fences(struct drm_device *dev);
  3147.  
  3148. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  3149. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  3150. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  3151.  
  3152. /* i915_gem_context.c */
  3153. int __must_check i915_gem_context_init(struct drm_device *dev);
  3154. void i915_gem_context_fini(struct drm_device *dev);
  3155. void i915_gem_context_reset(struct drm_device *dev);
  3156. int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
  3157. int i915_gem_context_enable(struct drm_i915_gem_request *req);
  3158. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  3159. int i915_switch_context(struct drm_i915_gem_request *req);
  3160. struct intel_context *
  3161. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
  3162. void i915_gem_context_free(struct kref *ctx_ref);
  3163. struct drm_i915_gem_object *
  3164. i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
  3165. static inline void i915_gem_context_reference(struct intel_context *ctx)
  3166. {
  3167.         kref_get(&ctx->ref);
  3168. }
  3169.  
  3170. static inline void i915_gem_context_unreference(struct intel_context *ctx)
  3171. {
  3172.         kref_put(&ctx->ref, i915_gem_context_free);
  3173. }
  3174.  
  3175. static inline bool i915_gem_context_is_default(const struct intel_context *c)
  3176. {
  3177.         return c->user_handle == DEFAULT_CONTEXT_HANDLE;
  3178. }
  3179.  
  3180. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  3181.                                   struct drm_file *file);
  3182. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  3183.                                    struct drm_file *file);
  3184. int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
  3185.                                     struct drm_file *file_priv);
  3186. int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
  3187.                                     struct drm_file *file_priv);
  3188.  
  3189. /* i915_gem_evict.c */
  3190. int __must_check i915_gem_evict_something(struct drm_device *dev,
  3191.                                           struct i915_address_space *vm,
  3192.                                           int min_size,
  3193.                                           unsigned alignment,
  3194.                                           unsigned cache_level,
  3195.                                           unsigned long start,
  3196.                                           unsigned long end,
  3197.                                           unsigned flags);
  3198. int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
  3199.  
  3200. /* belongs in i915_gem_gtt.h */
  3201. static inline void i915_gem_chipset_flush(struct drm_device *dev)
  3202. {
  3203.         if (INTEL_INFO(dev)->gen < 6)
  3204.                 intel_gtt_chipset_flush();
  3205. }
  3206.  
  3207. /* i915_gem_stolen.c */
  3208. int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
  3209.                                 struct drm_mm_node *node, u64 size,
  3210.                                 unsigned alignment);
  3211. int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
  3212.                                          struct drm_mm_node *node, u64 size,
  3213.                                          unsigned alignment, u64 start,
  3214.                                          u64 end);
  3215. void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
  3216.                                  struct drm_mm_node *node);
  3217. int i915_gem_init_stolen(struct drm_device *dev);
  3218. void i915_gem_cleanup_stolen(struct drm_device *dev);
  3219. struct drm_i915_gem_object *
  3220. i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
  3221. struct drm_i915_gem_object *
  3222. i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
  3223.                                                u32 stolen_offset,
  3224.                                                u32 gtt_offset,
  3225.                                                u32 size);
  3226.  
  3227. /* i915_gem_shrinker.c */
  3228. unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
  3229.                               unsigned long target,
  3230.                               unsigned flags);
  3231. #define I915_SHRINK_PURGEABLE 0x1
  3232. #define I915_SHRINK_UNBOUND 0x2
  3233. #define I915_SHRINK_BOUND 0x4
  3234. #define I915_SHRINK_ACTIVE 0x8
  3235. unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  3236. void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
  3237.  
  3238.  
  3239. /* i915_gem_tiling.c */
  3240. static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
  3241. {
  3242.         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  3243.  
  3244.         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
  3245.                 obj->tiling_mode != I915_TILING_NONE;
  3246. }
  3247.  
  3248. /* i915_gem_debug.c */
  3249. #if WATCH_LISTS
  3250. int i915_verify_lists(struct drm_device *dev);
  3251. #else
  3252. #define i915_verify_lists(dev) 0
  3253. #endif
  3254.  
  3255. /* i915_debugfs.c */
  3256. int i915_debugfs_init(struct drm_minor *minor);
  3257. void i915_debugfs_cleanup(struct drm_minor *minor);
  3258. #ifdef CONFIG_DEBUG_FS
  3259. int i915_debugfs_connector_add(struct drm_connector *connector);
  3260. void intel_display_crc_init(struct drm_device *dev);
  3261. #else
  3262. static inline int i915_debugfs_connector_add(struct drm_connector *connector)
  3263. { return 0; }
  3264. static inline void intel_display_crc_init(struct drm_device *dev) {}
  3265. #endif
  3266.  
  3267. /* i915_gpu_error.c */
  3268. __printf(2, 3)
  3269. void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
  3270. int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
  3271.                             const struct i915_error_state_file_priv *error);
  3272. int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
  3273.                               struct drm_i915_private *i915,
  3274.                               size_t count, loff_t pos);
  3275. static inline void i915_error_state_buf_release(
  3276.         struct drm_i915_error_state_buf *eb)
  3277. {
  3278.         kfree(eb->buf);
  3279. }
  3280. void i915_capture_error_state(struct drm_device *dev, bool wedge,
  3281.                               const char *error_msg);
  3282. void i915_error_state_get(struct drm_device *dev,
  3283.                           struct i915_error_state_file_priv *error_priv);
  3284. void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
  3285. void i915_destroy_error_state(struct drm_device *dev);
  3286.  
  3287. void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
  3288. const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
  3289.  
  3290. /* i915_cmd_parser.c */
  3291. int i915_cmd_parser_get_version(void);
  3292. int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
  3293. void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
  3294. bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
  3295. int i915_parse_cmds(struct intel_engine_cs *ring,
  3296.                     struct drm_i915_gem_object *batch_obj,
  3297.                     struct drm_i915_gem_object *shadow_batch_obj,
  3298.                     u32 batch_start_offset,
  3299.                     u32 batch_len,
  3300.                     bool is_master);
  3301.  
  3302. /* i915_suspend.c */
  3303. extern int i915_save_state(struct drm_device *dev);
  3304. extern int i915_restore_state(struct drm_device *dev);
  3305.  
  3306. /* i915_sysfs.c */
  3307. void i915_setup_sysfs(struct drm_device *dev_priv);
  3308. void i915_teardown_sysfs(struct drm_device *dev_priv);
  3309.  
  3310. /* intel_i2c.c */
  3311. extern int intel_setup_gmbus(struct drm_device *dev);
  3312. extern void intel_teardown_gmbus(struct drm_device *dev);
  3313. extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
  3314.                                      unsigned int pin);
  3315.  
  3316. extern struct i2c_adapter *
  3317. intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
  3318. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  3319. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  3320. static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  3321. {
  3322.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  3323. }
  3324. extern void intel_i2c_reset(struct drm_device *dev);
  3325.  
  3326. /* intel_opregion.c */
  3327. #ifdef CONFIG_ACPI
  3328. extern int intel_opregion_setup(struct drm_device *dev);
  3329. extern void intel_opregion_init(struct drm_device *dev);
  3330. extern void intel_opregion_fini(struct drm_device *dev);
  3331. extern void intel_opregion_asle_intr(struct drm_device *dev);
  3332. extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
  3333.                                          bool enable);
  3334. extern int intel_opregion_notify_adapter(struct drm_device *dev,
  3335.                                          pci_power_t state);
  3336. #else
  3337. static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
  3338. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  3339. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  3340. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  3341. static inline int
  3342. intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
  3343. {
  3344.         return 0;
  3345. }
  3346. static inline int
  3347. intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
  3348. {
  3349.         return 0;
  3350. }
  3351. #endif
  3352.  
  3353. /* intel_acpi.c */
  3354. #ifdef CONFIG_ACPI
  3355. extern void intel_register_dsm_handler(void);
  3356. extern void intel_unregister_dsm_handler(void);
  3357. #else
  3358. static inline void intel_register_dsm_handler(void) { return; }
  3359. static inline void intel_unregister_dsm_handler(void) { return; }
  3360. #endif /* CONFIG_ACPI */
  3361.  
  3362. /* modesetting */
  3363. extern void intel_modeset_init_hw(struct drm_device *dev);
  3364. extern void intel_modeset_init(struct drm_device *dev);
  3365. extern void intel_modeset_gem_init(struct drm_device *dev);
  3366. extern void intel_modeset_cleanup(struct drm_device *dev);
  3367. extern void intel_connector_unregister(struct intel_connector *);
  3368. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  3369. extern void intel_display_resume(struct drm_device *dev);
  3370. extern void i915_redisable_vga(struct drm_device *dev);
  3371. extern void i915_redisable_vga_power_on(struct drm_device *dev);
  3372. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  3373. extern void intel_init_pch_refclk(struct drm_device *dev);
  3374. extern void intel_set_rps(struct drm_device *dev, u8 val);
  3375. extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
  3376.                                   bool enable);
  3377. extern void intel_detect_pch(struct drm_device *dev);
  3378. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  3379. extern int intel_enable_rc6(const struct drm_device *dev);
  3380.  
  3381. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  3382. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  3383.                         struct drm_file *file);
  3384. int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
  3385.                                struct drm_file *file);
  3386.  
  3387. /* overlay */
  3388. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  3389. extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
  3390.                                             struct intel_overlay_error_state *error);
  3391.  
  3392. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  3393. extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
  3394.                                             struct drm_device *dev,
  3395.                                             struct intel_display_error_state *error);
  3396.  
  3397. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
  3398. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
  3399.  
  3400. /* intel_sideband.c */
  3401. u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
  3402. void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
  3403. u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  3404. u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
  3405. void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  3406. u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
  3407. void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  3408. u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
  3409. void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  3410. u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
  3411. void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  3412. u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
  3413. void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  3414. u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
  3415. void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
  3416. u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  3417.                    enum intel_sbi_destination destination);
  3418. void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  3419.                      enum intel_sbi_destination destination);
  3420. u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
  3421. void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  3422.  
  3423. int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
  3424. int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
  3425.  
  3426. #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
  3427. #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
  3428.  
  3429. #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
  3430. #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
  3431. #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
  3432. #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
  3433.  
  3434. #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
  3435. #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
  3436. #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
  3437. #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
  3438.  
  3439. /* Be very careful with read/write 64-bit values. On 32-bit machines, they
  3440.  * will be implemented using 2 32-bit writes in an arbitrary order with
  3441.  * an arbitrary delay between them. This can cause the hardware to
  3442.  * act upon the intermediate value, possibly leading to corruption and
  3443.  * machine death. You have been warned.
  3444.  */
  3445. #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
  3446. #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
  3447.  
  3448. #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
  3449.         u32 upper, lower, old_upper, loop = 0;                          \
  3450.         upper = I915_READ(upper_reg);                                   \
  3451.         do {                                                            \
  3452.                 old_upper = upper;                                      \
  3453.                 lower = I915_READ(lower_reg);                           \
  3454.                 upper = I915_READ(upper_reg);                           \
  3455.         } while (upper != old_upper && loop++ < 2);                     \
  3456.         (u64)upper << 32 | lower; })
  3457.  
  3458. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  3459. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  3460.  
  3461. /* These are untraced mmio-accessors that are only valid to be used inside
  3462.  * criticial sections inside IRQ handlers where forcewake is explicitly
  3463.  * controlled.
  3464.  * Think twice, and think again, before using these.
  3465.  * Note: Should only be used between intel_uncore_forcewake_irqlock() and
  3466.  * intel_uncore_forcewake_irqunlock().
  3467.  */
  3468. #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
  3469. #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
  3470. #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
  3471.  
  3472. /* "Broadcast RGB" property */
  3473. #define INTEL_BROADCAST_RGB_AUTO 0
  3474. #define INTEL_BROADCAST_RGB_FULL 1
  3475. #define INTEL_BROADCAST_RGB_LIMITED 2
  3476.  
  3477. static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
  3478. {
  3479.         if (IS_VALLEYVIEW(dev))
  3480.                 return VLV_VGACNTRL;
  3481.         else if (INTEL_INFO(dev)->gen >= 5)
  3482.                 return CPU_VGACNTRL;
  3483.         else
  3484.                 return VGACNTRL;
  3485. }
  3486.  
  3487. static inline void __user *to_user_ptr(u64 address)
  3488. {
  3489.         return (void __user *)(uintptr_t)address;
  3490. }
  3491.  
  3492. static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
  3493. {
  3494.         unsigned long j = msecs_to_jiffies(m);
  3495.  
  3496.         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  3497. }
  3498.  
  3499. static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
  3500. {
  3501.         return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
  3502. }
  3503.  
  3504. static inline unsigned long
  3505. timespec_to_jiffies_timeout(const struct timespec *value)
  3506. {
  3507.         unsigned long j = timespec_to_jiffies(value);
  3508.  
  3509.         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  3510. }
  3511.  
  3512. /*
  3513.  * If you need to wait X milliseconds between events A and B, but event B
  3514.  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
  3515.  * when event A happened, then just before event B you call this function and
  3516.  * pass the timestamp as the first argument, and X as the second argument.
  3517.  */
  3518. static inline void
  3519. wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
  3520. {
  3521.         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
  3522.  
  3523.         /*
  3524.          * Don't re-read the value of "jiffies" every time since it may change
  3525.          * behind our back and break the math.
  3526.          */
  3527.         tmp_jiffies = jiffies;
  3528.         target_jiffies = timestamp_jiffies +
  3529.                          msecs_to_jiffies_timeout(to_wait_ms);
  3530.  
  3531.         if (time_after(target_jiffies, tmp_jiffies)) {
  3532.                 remaining_jiffies = target_jiffies - tmp_jiffies;
  3533.                 delay(remaining_jiffies);
  3534.         }
  3535. }
  3536.  
  3537. static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
  3538.                                       struct drm_i915_gem_request *req)
  3539. {
  3540.         if (ring->trace_irq_req == NULL && ring->irq_get(ring))
  3541.                 i915_gem_request_assign(&ring->trace_irq_req, req);
  3542. }
  3543.  
  3544. #endif
  3545.