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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include "i915_reg.h"
  34. #include "intel_bios.h"
  35. #include "intel_ringbuffer.h"
  36. #include <linux/scatterlist.h>
  37. //#include <linux/io-mapping.h>
  38. #include <linux/i2c.h>
  39. #include <linux/i2c-algo-bit.h>
  40. #include <drm/intel-gtt.h>
  41. //#include <linux/backlight.h>
  42.  
  43. #include <linux/spinlock.h>
  44. #include <linux/err.h>
  45.  
  46.  
  47. /* General customization:
  48.  */
  49.  
  50. #define I915_TILING_NONE          0
  51.  
  52. #define VGA_RSRC_NONE          0x00
  53. #define VGA_RSRC_LEGACY_IO     0x01
  54. #define VGA_RSRC_LEGACY_MEM    0x02
  55. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  56. /* Non-legacy access */
  57. #define VGA_RSRC_NORMAL_IO     0x04
  58. #define VGA_RSRC_NORMAL_MEM    0x08
  59.  
  60. #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  61.  
  62. #define DRIVER_NAME             "i915"
  63. #define DRIVER_DESC             "Intel Graphics"
  64. #define DRIVER_DATE             "20080730"
  65.  
  66. enum pipe {
  67.         PIPE_A = 0,
  68.         PIPE_B,
  69.         PIPE_C,
  70.         I915_MAX_PIPES
  71. };
  72. #define pipe_name(p) ((p) + 'A')
  73.  
  74. enum transcoder {
  75.         TRANSCODER_A = 0,
  76.         TRANSCODER_B,
  77.         TRANSCODER_C,
  78.         TRANSCODER_EDP = 0xF,
  79. };
  80. #define transcoder_name(t) ((t) + 'A')
  81.  
  82. enum plane {
  83.         PLANE_A = 0,
  84.         PLANE_B,
  85.         PLANE_C,
  86. };
  87. #define plane_name(p) ((p) + 'A')
  88.  
  89. enum port {
  90.         PORT_A = 0,
  91.         PORT_B,
  92.         PORT_C,
  93.         PORT_D,
  94.         PORT_E,
  95.         I915_MAX_PORTS
  96. };
  97. #define port_name(p) ((p) + 'A')
  98.  
  99. #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  100.  
  101. #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  102.  
  103. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  104.         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  105.                 if ((intel_encoder)->base.crtc == (__crtc))
  106.  
  107. struct intel_pch_pll {
  108.         int refcount; /* count of number of CRTCs sharing this PLL */
  109.         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  110.         bool on; /* is the PLL actually active? Disabled during modeset */
  111.         int pll_reg;
  112.         int fp0_reg;
  113.         int fp1_reg;
  114. };
  115. #define I915_NUM_PLLS 2
  116.  
  117. struct intel_ddi_plls {
  118.         int spll_refcount;
  119.         int wrpll1_refcount;
  120.         int wrpll2_refcount;
  121. };
  122.  
  123. /* Interface history:
  124.  *
  125.  * 1.1: Original.
  126.  * 1.2: Add Power Management
  127.  * 1.3: Add vblank support
  128.  * 1.4: Fix cmdbuffer path, add heap destroy
  129.  * 1.5: Add vblank pipe configuration
  130.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  131.  *      - Support vertical blank on secondary display pipe
  132.  */
  133. #define DRIVER_MAJOR            1
  134. #define DRIVER_MINOR            6
  135. #define DRIVER_PATCHLEVEL       0
  136.  
  137. #define WATCH_COHERENCY 0
  138. #define WATCH_LISTS     0
  139. #define WATCH_GTT       0
  140.  
  141. #define I915_GEM_PHYS_CURSOR_0 1
  142. #define I915_GEM_PHYS_CURSOR_1 2
  143. #define I915_GEM_PHYS_OVERLAY_REGS 3
  144. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  145.  
  146.  
  147.  
  148. struct opregion_header;
  149. struct opregion_acpi;
  150. struct opregion_swsci;
  151. struct opregion_asle;
  152. struct drm_i915_private;
  153.  
  154. struct intel_opregion {
  155.         struct opregion_header __iomem *header;
  156.         struct opregion_acpi __iomem *acpi;
  157.         struct opregion_swsci __iomem *swsci;
  158.         struct opregion_asle __iomem *asle;
  159.         void __iomem *vbt;
  160.         u32 __iomem *lid_state;
  161. };
  162. #define OPREGION_SIZE            (8*1024)
  163.  
  164. struct intel_overlay;
  165. struct intel_overlay_error_state;
  166.  
  167. struct drm_i915_master_private {
  168.         drm_local_map_t *sarea;
  169.         struct _drm_i915_sarea *sarea_priv;
  170. };
  171. #define I915_FENCE_REG_NONE -1
  172. #define I915_MAX_NUM_FENCES 16
  173. /* 16 fences + sign bit for FENCE_REG_NONE */
  174. #define I915_MAX_NUM_FENCE_BITS 5
  175.  
  176. struct drm_i915_fence_reg {
  177.         struct list_head lru_list;
  178.         struct drm_i915_gem_object *obj;
  179.         int pin_count;
  180. };
  181.  
  182. struct sdvo_device_mapping {
  183.         u8 initialized;
  184.         u8 dvo_port;
  185.         u8 slave_addr;
  186.         u8 dvo_wiring;
  187.         u8 i2c_pin;
  188.         u8 ddc_pin;
  189. };
  190.  
  191. struct intel_display_error_state;
  192.  
  193. struct drm_i915_error_state {
  194.         struct kref ref;
  195.         u32 eir;
  196.         u32 pgtbl_er;
  197.         u32 ier;
  198.         u32 ccid;
  199.         u32 derrmr;
  200.         u32 forcewake;
  201.         bool waiting[I915_NUM_RINGS];
  202.         u32 pipestat[I915_MAX_PIPES];
  203.         u32 tail[I915_NUM_RINGS];
  204.         u32 head[I915_NUM_RINGS];
  205.         u32 ctl[I915_NUM_RINGS];
  206.         u32 ipeir[I915_NUM_RINGS];
  207.         u32 ipehr[I915_NUM_RINGS];
  208.         u32 instdone[I915_NUM_RINGS];
  209.         u32 acthd[I915_NUM_RINGS];
  210.         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  211.         u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  212.         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
  213.         /* our own tracking of ring head and tail */
  214.         u32 cpu_ring_head[I915_NUM_RINGS];
  215.         u32 cpu_ring_tail[I915_NUM_RINGS];
  216.         u32 error; /* gen6+ */
  217.         u32 err_int; /* gen7 */
  218.         u32 instpm[I915_NUM_RINGS];
  219.         u32 instps[I915_NUM_RINGS];
  220.         u32 extra_instdone[I915_NUM_INSTDONE_REG];
  221.         u32 seqno[I915_NUM_RINGS];
  222.         u64 bbaddr;
  223.         u32 fault_reg[I915_NUM_RINGS];
  224.         u32 done_reg;
  225.         u32 faddr[I915_NUM_RINGS];
  226.         u64 fence[I915_MAX_NUM_FENCES];
  227.         struct timeval time;
  228.         struct drm_i915_error_ring {
  229.         struct drm_i915_error_object {
  230.                 int page_count;
  231.                 u32 gtt_offset;
  232.                 u32 *pages[0];
  233.                 } *ringbuffer, *batchbuffer;
  234.                 struct drm_i915_error_request {
  235.                         long jiffies;
  236.                         u32 seqno;
  237.                         u32 tail;
  238.                 } *requests;
  239.                 int num_requests;
  240.         } ring[I915_NUM_RINGS];
  241.         struct drm_i915_error_buffer {
  242.                 u32 size;
  243.                 u32 name;
  244.                 u32 rseqno, wseqno;
  245.                 u32 gtt_offset;
  246.                 u32 read_domains;
  247.                 u32 write_domain;
  248.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  249.                 s32 pinned:2;
  250.                 u32 tiling:2;
  251.                 u32 dirty:1;
  252.                 u32 purgeable:1;
  253.                 s32 ring:4;
  254.                 u32 cache_level:2;
  255.         } *active_bo, *pinned_bo;
  256.         u32 active_bo_count, pinned_bo_count;
  257.         struct intel_overlay_error_state *overlay;
  258.         struct intel_display_error_state *display;
  259. };
  260.  
  261. struct drm_i915_display_funcs {
  262.         bool (*fbc_enabled)(struct drm_device *dev);
  263.         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  264.         void (*disable_fbc)(struct drm_device *dev);
  265.         int (*get_display_clock_speed)(struct drm_device *dev);
  266.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  267.         void (*update_wm)(struct drm_device *dev);
  268.         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
  269.                                  uint32_t sprite_width, int pixel_size);
  270.         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
  271.                                  struct drm_display_mode *mode);
  272.         void (*modeset_global_resources)(struct drm_device *dev);
  273.         int (*crtc_mode_set)(struct drm_crtc *crtc,
  274.                              struct drm_display_mode *mode,
  275.                              struct drm_display_mode *adjusted_mode,
  276.                              int x, int y,
  277.                              struct drm_framebuffer *old_fb);
  278.         void (*crtc_enable)(struct drm_crtc *crtc);
  279.         void (*crtc_disable)(struct drm_crtc *crtc);
  280.         void (*off)(struct drm_crtc *crtc);
  281.         void (*write_eld)(struct drm_connector *connector,
  282.                           struct drm_crtc *crtc);
  283.         void (*fdi_link_train)(struct drm_crtc *crtc);
  284.         void (*init_clock_gating)(struct drm_device *dev);
  285.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  286.                           struct drm_framebuffer *fb,
  287.                           struct drm_i915_gem_object *obj);
  288.         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  289.                             int x, int y);
  290.         /* clock updates for mode set */
  291.         /* cursor updates */
  292.         /* render clock increase/decrease */
  293.         /* display clock increase/decrease */
  294.         /* pll clock increase/decrease */
  295. };
  296.  
  297. struct drm_i915_gt_funcs {
  298.         void (*force_wake_get)(struct drm_i915_private *dev_priv);
  299.         void (*force_wake_put)(struct drm_i915_private *dev_priv);
  300. };
  301.  
  302. #define DEV_INFO_FLAGS \
  303.         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
  304.         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
  305.         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
  306.         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
  307.         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
  308.         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
  309.         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
  310.         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
  311.         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
  312.         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
  313.         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
  314.         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
  315.         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
  316.         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
  317.         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
  318.         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
  319.         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
  320.         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
  321.         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
  322.         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
  323.         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
  324.         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
  325.         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
  326.         DEV_INFO_FLAG(has_llc)
  327.  
  328. struct intel_device_info {
  329.         u8 gen;
  330.         u8 is_mobile:1;
  331.         u8 is_i85x:1;
  332.         u8 is_i915g:1;
  333.         u8 is_i945gm:1;
  334.         u8 is_g33:1;
  335.         u8 need_gfx_hws:1;
  336.         u8 is_g4x:1;
  337.         u8 is_pineview:1;
  338.         u8 is_broadwater:1;
  339.         u8 is_crestline:1;
  340.         u8 is_ivybridge:1;
  341.         u8 is_valleyview:1;
  342.         u8 has_force_wake:1;
  343.         u8 is_haswell:1;
  344.         u8 has_fbc:1;
  345.         u8 has_pipe_cxsr:1;
  346.         u8 has_hotplug:1;
  347.         u8 cursor_needs_physical:1;
  348.         u8 has_overlay:1;
  349.         u8 overlay_needs_physical:1;
  350.         u8 supports_tv:1;
  351.         u8 has_bsd_ring:1;
  352.         u8 has_blt_ring:1;
  353.         u8 has_llc:1;
  354. };
  355.  
  356. #define I915_PPGTT_PD_ENTRIES 512
  357. #define I915_PPGTT_PT_ENTRIES 1024
  358. struct i915_hw_ppgtt {
  359.         struct drm_device *dev;
  360.         unsigned num_pd_entries;
  361.         struct page **pt_pages;
  362.         uint32_t pd_offset;
  363.         dma_addr_t *pt_dma_addr;
  364.         dma_addr_t scratch_page_dma_addr;
  365. };
  366.  
  367.  
  368. /* This must match up with the value previously used for execbuf2.rsvd1. */
  369. #define DEFAULT_CONTEXT_ID 0
  370. struct i915_hw_context {
  371.         int id;
  372.         bool is_initialized;
  373.         struct drm_i915_file_private *file_priv;
  374.         struct intel_ring_buffer *ring;
  375.         struct drm_i915_gem_object *obj;
  376. };
  377.  
  378. enum no_fbc_reason {
  379.         FBC_NO_OUTPUT, /* no outputs enabled to compress */
  380.         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  381.         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  382.         FBC_MODE_TOO_LARGE, /* mode too large for compression */
  383.         FBC_BAD_PLANE, /* fbc not supported on plane */
  384.         FBC_NOT_TILED, /* buffer not tiled */
  385.         FBC_MULTIPLE_PIPES, /* more than one pipe active */
  386.         FBC_MODULE_PARAM,
  387. };
  388.  
  389. enum intel_pch {
  390.         PCH_NONE = 0,   /* No PCH present */
  391.         PCH_IBX,        /* Ibexpeak PCH */
  392.         PCH_CPT,        /* Cougarpoint PCH */
  393.         PCH_LPT,        /* Lynxpoint PCH */
  394. };
  395.  
  396. enum intel_sbi_destination {
  397.         SBI_ICLK,
  398.         SBI_MPHY,
  399. };
  400.  
  401. #define QUIRK_PIPEA_FORCE (1<<0)
  402. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  403. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  404.  
  405. struct intel_fbdev;
  406. struct intel_fbc_work;
  407.  
  408. struct intel_gmbus {
  409.         struct i2c_adapter adapter;
  410.         u32 force_bit;
  411.         u32 reg0;
  412.         u32 gpio_reg;
  413.         struct i2c_algo_bit_data bit_algo;
  414.         struct drm_i915_private *dev_priv;
  415. };
  416.  
  417. struct i915_suspend_saved_registers {
  418.         u8 saveLBB;
  419.         u32 saveDSPACNTR;
  420.         u32 saveDSPBCNTR;
  421.         u32 saveDSPARB;
  422.         u32 savePIPEACONF;
  423.         u32 savePIPEBCONF;
  424.         u32 savePIPEASRC;
  425.         u32 savePIPEBSRC;
  426.         u32 saveFPA0;
  427.         u32 saveFPA1;
  428.         u32 saveDPLL_A;
  429.         u32 saveDPLL_A_MD;
  430.         u32 saveHTOTAL_A;
  431.         u32 saveHBLANK_A;
  432.         u32 saveHSYNC_A;
  433.         u32 saveVTOTAL_A;
  434.         u32 saveVBLANK_A;
  435.         u32 saveVSYNC_A;
  436.         u32 saveBCLRPAT_A;
  437.         u32 saveTRANSACONF;
  438.         u32 saveTRANS_HTOTAL_A;
  439.         u32 saveTRANS_HBLANK_A;
  440.         u32 saveTRANS_HSYNC_A;
  441.         u32 saveTRANS_VTOTAL_A;
  442.         u32 saveTRANS_VBLANK_A;
  443.         u32 saveTRANS_VSYNC_A;
  444.         u32 savePIPEASTAT;
  445.         u32 saveDSPASTRIDE;
  446.         u32 saveDSPASIZE;
  447.         u32 saveDSPAPOS;
  448.         u32 saveDSPAADDR;
  449.         u32 saveDSPASURF;
  450.         u32 saveDSPATILEOFF;
  451.         u32 savePFIT_PGM_RATIOS;
  452.         u32 saveBLC_HIST_CTL;
  453.         u32 saveBLC_PWM_CTL;
  454.         u32 saveBLC_PWM_CTL2;
  455.         u32 saveBLC_CPU_PWM_CTL;
  456.         u32 saveBLC_CPU_PWM_CTL2;
  457.         u32 saveFPB0;
  458.         u32 saveFPB1;
  459.         u32 saveDPLL_B;
  460.         u32 saveDPLL_B_MD;
  461.         u32 saveHTOTAL_B;
  462.         u32 saveHBLANK_B;
  463.         u32 saveHSYNC_B;
  464.         u32 saveVTOTAL_B;
  465.         u32 saveVBLANK_B;
  466.         u32 saveVSYNC_B;
  467.         u32 saveBCLRPAT_B;
  468.         u32 saveTRANSBCONF;
  469.         u32 saveTRANS_HTOTAL_B;
  470.         u32 saveTRANS_HBLANK_B;
  471.         u32 saveTRANS_HSYNC_B;
  472.         u32 saveTRANS_VTOTAL_B;
  473.         u32 saveTRANS_VBLANK_B;
  474.         u32 saveTRANS_VSYNC_B;
  475.         u32 savePIPEBSTAT;
  476.         u32 saveDSPBSTRIDE;
  477.         u32 saveDSPBSIZE;
  478.         u32 saveDSPBPOS;
  479.         u32 saveDSPBADDR;
  480.         u32 saveDSPBSURF;
  481.         u32 saveDSPBTILEOFF;
  482.         u32 saveVGA0;
  483.         u32 saveVGA1;
  484.         u32 saveVGA_PD;
  485.         u32 saveVGACNTRL;
  486.         u32 saveADPA;
  487.         u32 saveLVDS;
  488.         u32 savePP_ON_DELAYS;
  489.         u32 savePP_OFF_DELAYS;
  490.         u32 saveDVOA;
  491.         u32 saveDVOB;
  492.         u32 saveDVOC;
  493.         u32 savePP_ON;
  494.         u32 savePP_OFF;
  495.         u32 savePP_CONTROL;
  496.         u32 savePP_DIVISOR;
  497.         u32 savePFIT_CONTROL;
  498.         u32 save_palette_a[256];
  499.         u32 save_palette_b[256];
  500.         u32 saveDPFC_CB_BASE;
  501.         u32 saveFBC_CFB_BASE;
  502.         u32 saveFBC_LL_BASE;
  503.         u32 saveFBC_CONTROL;
  504.         u32 saveFBC_CONTROL2;
  505.         u32 saveIER;
  506.         u32 saveIIR;
  507.         u32 saveIMR;
  508.         u32 saveDEIER;
  509.         u32 saveDEIMR;
  510.         u32 saveGTIER;
  511.         u32 saveGTIMR;
  512.         u32 saveFDI_RXA_IMR;
  513.         u32 saveFDI_RXB_IMR;
  514.         u32 saveCACHE_MODE_0;
  515.         u32 saveMI_ARB_STATE;
  516.         u32 saveSWF0[16];
  517.         u32 saveSWF1[16];
  518.         u32 saveSWF2[3];
  519.         u8 saveMSR;
  520.         u8 saveSR[8];
  521.         u8 saveGR[25];
  522.         u8 saveAR_INDEX;
  523.         u8 saveAR[21];
  524.         u8 saveDACMASK;
  525.         u8 saveCR[37];
  526.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  527.         u32 saveCURACNTR;
  528.         u32 saveCURAPOS;
  529.         u32 saveCURABASE;
  530.         u32 saveCURBCNTR;
  531.         u32 saveCURBPOS;
  532.         u32 saveCURBBASE;
  533.         u32 saveCURSIZE;
  534.         u32 saveDP_B;
  535.         u32 saveDP_C;
  536.         u32 saveDP_D;
  537.         u32 savePIPEA_GMCH_DATA_M;
  538.         u32 savePIPEB_GMCH_DATA_M;
  539.         u32 savePIPEA_GMCH_DATA_N;
  540.         u32 savePIPEB_GMCH_DATA_N;
  541.         u32 savePIPEA_DP_LINK_M;
  542.         u32 savePIPEB_DP_LINK_M;
  543.         u32 savePIPEA_DP_LINK_N;
  544.         u32 savePIPEB_DP_LINK_N;
  545.         u32 saveFDI_RXA_CTL;
  546.         u32 saveFDI_TXA_CTL;
  547.         u32 saveFDI_RXB_CTL;
  548.         u32 saveFDI_TXB_CTL;
  549.         u32 savePFA_CTL_1;
  550.         u32 savePFB_CTL_1;
  551.         u32 savePFA_WIN_SZ;
  552.         u32 savePFB_WIN_SZ;
  553.         u32 savePFA_WIN_POS;
  554.         u32 savePFB_WIN_POS;
  555.         u32 savePCH_DREF_CONTROL;
  556.         u32 saveDISP_ARB_CTL;
  557.         u32 savePIPEA_DATA_M1;
  558.         u32 savePIPEA_DATA_N1;
  559.         u32 savePIPEA_LINK_M1;
  560.         u32 savePIPEA_LINK_N1;
  561.         u32 savePIPEB_DATA_M1;
  562.         u32 savePIPEB_DATA_N1;
  563.         u32 savePIPEB_LINK_M1;
  564.         u32 savePIPEB_LINK_N1;
  565.         u32 saveMCHBAR_RENDER_STANDBY;
  566.         u32 savePCH_PORT_HOTPLUG;
  567. };
  568.  
  569. struct intel_gen6_power_mgmt {
  570.         struct work_struct work;
  571.         u32 pm_iir;
  572.         /* lock - irqsave spinlock that protectects the work_struct and
  573.          * pm_iir. */
  574.         spinlock_t lock;
  575.  
  576.         /* The below variables an all the rps hw state are protected by
  577.          * dev->struct mutext. */
  578.         u8 cur_delay;
  579.         u8 min_delay;
  580.         u8 max_delay;
  581.  
  582.         struct delayed_work delayed_resume_work;
  583.  
  584.         /*
  585.          * Protects RPS/RC6 register access and PCU communication.
  586.          * Must be taken after struct_mutex if nested.
  587.          */
  588.         struct mutex hw_lock;
  589. };
  590.  
  591. struct intel_ilk_power_mgmt {
  592.         u8 cur_delay;
  593.         u8 min_delay;
  594.         u8 max_delay;
  595.         u8 fmax;
  596.         u8 fstart;
  597.  
  598.         u64 last_count1;
  599.         unsigned long last_time1;
  600.         unsigned long chipset_power;
  601.         u64 last_count2;
  602.         struct timespec last_time2;
  603.         unsigned long gfx_power;
  604.         u8 corr;
  605.  
  606.         int c_m;
  607.         int r_t;
  608.  
  609.         struct drm_i915_gem_object *pwrctx;
  610.         struct drm_i915_gem_object *renderctx;
  611. };
  612.  
  613. struct i915_dri1_state {
  614.         unsigned allow_batchbuffer : 1;
  615.         u32 __iomem *gfx_hws_cpu_addr;
  616.  
  617.         unsigned int cpp;
  618.         int back_offset;
  619.         int front_offset;
  620.         int current_page;
  621.         int page_flipping;
  622.  
  623.         uint32_t counter;
  624. };
  625.  
  626. struct intel_l3_parity {
  627.         u32 *remap_info;
  628.         struct work_struct error_work;
  629. };
  630.  
  631. typedef struct drm_i915_private {
  632.         struct drm_device *dev;
  633.  
  634.         const struct intel_device_info *info;
  635.  
  636.         int relative_constants_mode;
  637.  
  638.         void __iomem *regs;
  639.  
  640.         struct drm_i915_gt_funcs gt;
  641.         /** gt_fifo_count and the subsequent register write are synchronized
  642.          * with dev->struct_mutex. */
  643.         unsigned gt_fifo_count;
  644.         /** forcewake_count is protected by gt_lock */
  645.         unsigned forcewake_count;
  646.         /** gt_lock is also taken in irq contexts. */
  647.         struct spinlock gt_lock;
  648.  
  649.         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  650.  
  651.         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  652.          * controller on different i2c buses. */
  653.         struct mutex gmbus_mutex;
  654.  
  655.         /**
  656.          * Base address of the gmbus and gpio block.
  657.          */
  658.         uint32_t gpio_mmio_base;
  659.  
  660.         struct pci_dev *bridge_dev;
  661.         struct intel_ring_buffer ring[I915_NUM_RINGS];
  662.         uint32_t next_seqno;
  663.  
  664.         drm_dma_handle_t *status_page_dmah;
  665.         struct resource mch_res;
  666.  
  667.         atomic_t irq_received;
  668.  
  669.         /* protects the irq masks */
  670.         spinlock_t irq_lock;
  671.  
  672.         /* DPIO indirect register protection */
  673.         spinlock_t dpio_lock;
  674.  
  675.         /** Cached value of IMR to avoid reads in updating the bitfield */
  676.         u32 pipestat[2];
  677.         u32 irq_mask;
  678.         u32 gt_irq_mask;
  679.         u32 pch_irq_mask;
  680.  
  681.         u32 hotplug_supported_mask;
  682.         struct work_struct hotplug_work;
  683.  
  684.         int num_pipe;
  685.         int num_pch_pll;
  686.  
  687.         /* For hangcheck timer */
  688. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  689. #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  690.         struct timer_list hangcheck_timer;
  691.         int hangcheck_count;
  692.         uint32_t last_acthd[I915_NUM_RINGS];
  693.         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
  694.  
  695.         unsigned int stop_rings;
  696.  
  697.         unsigned long cfb_size;
  698.         unsigned int cfb_fb;
  699.         enum plane cfb_plane;
  700.         int cfb_y;
  701.         struct intel_fbc_work *fbc_work;
  702.  
  703.         struct intel_opregion opregion;
  704.  
  705.         /* overlay */
  706.         struct intel_overlay *overlay;
  707.         bool sprite_scaling_enabled;
  708.  
  709.         /* LVDS info */
  710.         int backlight_level;  /* restore backlight to this value */
  711.         bool backlight_enabled;
  712.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  713.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  714.  
  715.         /* Feature bits from the VBIOS */
  716.         unsigned int int_tv_support:1;
  717.         unsigned int lvds_dither:1;
  718.         unsigned int lvds_vbt:1;
  719.         unsigned int int_crt_support:1;
  720.         unsigned int lvds_use_ssc:1;
  721.         unsigned int display_clock_mode:1;
  722.         int lvds_ssc_freq;
  723.         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  724.         unsigned int lvds_val; /* used for checking LVDS channel mode */
  725.         struct {
  726.                 int rate;
  727.                 int lanes;
  728.                 int preemphasis;
  729.                 int vswing;
  730.  
  731.                 bool initialized;
  732.                 bool support;
  733.                 int bpp;
  734.                 struct edp_power_seq pps;
  735.         } edp;
  736.         bool no_aux_handshake;
  737.  
  738.         int crt_ddc_pin;
  739.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  740.         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  741.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  742.  
  743.         unsigned int fsb_freq, mem_freq, is_ddr3;
  744.  
  745.         spinlock_t error_lock;
  746.         /* Protected by dev->error_lock. */
  747.         struct drm_i915_error_state *first_error;
  748.         struct work_struct error_work;
  749.         struct completion error_completion;
  750.         struct workqueue_struct *wq;
  751.  
  752.         /* Display functions */
  753.         struct drm_i915_display_funcs display;
  754.  
  755.         /* PCH chipset type */
  756.         enum intel_pch pch_type;
  757.         unsigned short pch_id;
  758.  
  759.         unsigned long quirks;
  760.  
  761.         /* Register state */
  762.         bool modeset_on_lid;
  763.  
  764.         struct {
  765.                 /** Bridge to intel-gtt-ko */
  766.                 struct intel_gtt *gtt;
  767.                 /** Memory allocator for GTT stolen memory */
  768.         struct drm_mm stolen;
  769.                 /** Memory allocator for GTT */
  770.         struct drm_mm gtt_space;
  771.                 /** List of all objects in gtt_space. Used to restore gtt
  772.                  * mappings on resume */
  773.                 struct list_head bound_list;
  774.                 /**
  775.                  * List of objects which are not bound to the GTT (thus
  776.                  * are idle and not used by the GPU) but still have
  777.                  * (presumably uncached) pages still attached.
  778.                  */
  779.                 struct list_head unbound_list;
  780.  
  781.                 /** Usable portion of the GTT for GEM */
  782.                 unsigned long gtt_start;
  783.                 unsigned long gtt_mappable_end;
  784.                 unsigned long gtt_end;
  785.  
  786. //       struct io_mapping *gtt_mapping;
  787.                 phys_addr_t gtt_base_addr;
  788.                 int gtt_mtrr;
  789.  
  790.                 /** PPGTT used for aliasing the PPGTT with the GTT */
  791.                 struct i915_hw_ppgtt *aliasing_ppgtt;
  792.  
  793. //       struct shrinker inactive_shrinker;
  794.                 bool shrinker_no_lock_stealing;
  795.  
  796.                 /**
  797.                  * List of objects currently involved in rendering.
  798.                  *
  799.                  * Includes buffers having the contents of their GPU caches
  800.                  * flushed, not necessarily primitives.  last_rendering_seqno
  801.                  * represents when the rendering involved will be completed.
  802.                  *
  803.                  * A reference is held on the buffer while on this list.
  804.                  */
  805.                 struct list_head active_list;
  806.  
  807.                 /**
  808.                  * LRU list of objects which are not in the ringbuffer and
  809.                  * are ready to unbind, but are still in the GTT.
  810.                  *
  811.                  * last_rendering_seqno is 0 while an object is in this list.
  812.                  *
  813.                  * A reference is not held on the buffer while on this list,
  814.                  * as merely being GTT-bound shouldn't prevent its being
  815.                  * freed, and we'll pull it off the list in the free path.
  816.                  */
  817.                 struct list_head inactive_list;
  818.  
  819.                 /** LRU list of objects with fence regs on them. */
  820.                 struct list_head fence_list;
  821.  
  822.                 /**
  823.                  * We leave the user IRQ off as much as possible,
  824.                  * but this means that requests will finish and never
  825.                  * be retired once the system goes idle. Set a timer to
  826.                  * fire periodically while the ring is running. When it
  827.                  * fires, go retire requests.
  828.                  */
  829.                 struct delayed_work retire_work;
  830.  
  831.                 /**
  832.                  * Are we in a non-interruptible section of code like
  833.                  * modesetting?
  834.                  */
  835.                 bool interruptible;
  836.  
  837.                 /**
  838.                  * Flag if the X Server, and thus DRM, is not currently in
  839.                  * control of the device.
  840.                  *
  841.                  * This is set between LeaveVT and EnterVT.  It needs to be
  842.                  * replaced with a semaphore.  It also needs to be
  843.                  * transitioned away from for kernel modesetting.
  844.                  */
  845.                 int suspended;
  846.  
  847.                 /**
  848.                  * Flag if the hardware appears to be wedged.
  849.                  *
  850.                  * This is set when attempts to idle the device timeout.
  851.                  * It prevents command submission from occurring and makes
  852.                  * every pending request fail
  853.                  */
  854.                 atomic_t wedged;
  855.  
  856.                 /** Bit 6 swizzling required for X tiling */
  857.                 uint32_t bit_6_swizzle_x;
  858.                 /** Bit 6 swizzling required for Y tiling */
  859.                 uint32_t bit_6_swizzle_y;
  860.  
  861.                 /* storage for physical objects */
  862. //       struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  863.  
  864.                 /* accounting, useful for userland debugging */
  865.                 size_t gtt_total;
  866.                 size_t mappable_gtt_total;
  867.                 size_t object_memory;
  868.                 u32 object_count;
  869.         } mm;
  870.  
  871.         /* Kernel Modesetting */
  872.  
  873.     struct sdvo_device_mapping sdvo_mappings[2];
  874.         /* indicate whether the LVDS_BORDER should be enabled or not */
  875.         unsigned int lvds_border_bits;
  876.         /* Panel fitter placement and size for Ironlake+ */
  877.         u32 pch_pf_pos, pch_pf_size;
  878.  
  879.     struct drm_crtc *plane_to_crtc_mapping[3];
  880.     struct drm_crtc *pipe_to_crtc_mapping[3];
  881.         wait_queue_head_t pending_flip_queue;
  882.  
  883.         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
  884.         struct intel_ddi_plls ddi_plls;
  885.  
  886.         /* Reclocking support */
  887.         bool render_reclock_avail;
  888.         bool lvds_downclock_avail;
  889.         /* indicates the reduced downclock for LVDS*/
  890.         int lvds_downclock;
  891.         u16 orig_clock;
  892.         int child_dev_num;
  893.     struct child_device_config *child_dev;
  894.  
  895.         bool mchbar_need_disable;
  896.  
  897.         struct intel_l3_parity l3_parity;
  898.  
  899.         /* gen6+ rps state */
  900.         struct intel_gen6_power_mgmt rps;
  901.  
  902.         /* ilk-only ips/rps state. Everything in here is protected by the global
  903.          * mchdev_lock in intel_pm.c */
  904.         struct intel_ilk_power_mgmt ips;
  905.  
  906.         enum no_fbc_reason no_fbc_reason;
  907.  
  908.         struct drm_mm_node *compressed_fb;
  909.         struct drm_mm_node *compressed_llb;
  910.  
  911.         unsigned long last_gpu_reset;
  912.  
  913.         /* list of fbdev register on this device */
  914.     struct intel_fbdev *fbdev;
  915.  
  916.         /*
  917.          * The console may be contended at resume, but we don't
  918.          * want it to block on it.
  919.          */
  920.         struct work_struct console_resume_work;
  921.  
  922. //   struct backlight_device *backlight;
  923.  
  924.         struct drm_property *broadcast_rgb_property;
  925.         struct drm_property *force_audio_property;
  926.  
  927.         bool hw_contexts_disabled;
  928.         uint32_t hw_context_size;
  929.  
  930.         bool fdi_rx_polarity_reversed;
  931.  
  932.         struct i915_suspend_saved_registers regfile;
  933.  
  934.         /* Old dri1 support infrastructure, beware the dragons ya fools entering
  935.          * here! */
  936.         struct i915_dri1_state dri1;
  937. } drm_i915_private_t;
  938.  
  939. /* Iterate over initialised rings */
  940. #define for_each_ring(ring__, dev_priv__, i__) \
  941.         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  942.                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  943.  
  944. enum hdmi_force_audio {
  945.         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
  946.         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
  947.         HDMI_AUDIO_AUTO,                /* trust EDID */
  948.         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
  949. };
  950.  
  951. enum i915_cache_level {
  952.         I915_CACHE_NONE = 0,
  953.         I915_CACHE_LLC,
  954.         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
  955. };
  956.  
  957. struct drm_i915_gem_object_ops {
  958.         /* Interface between the GEM object and its backing storage.
  959.          * get_pages() is called once prior to the use of the associated set
  960.          * of pages before to binding them into the GTT, and put_pages() is
  961.          * called after we no longer need them. As we expect there to be
  962.          * associated cost with migrating pages between the backing storage
  963.          * and making them available for the GPU (e.g. clflush), we may hold
  964.          * onto the pages after they are no longer referenced by the GPU
  965.          * in case they may be used again shortly (for example migrating the
  966.          * pages to a different memory domain within the GTT). put_pages()
  967.          * will therefore most likely be called when the object itself is
  968.          * being released or under memory pressure (where we attempt to
  969.          * reap pages for the shrinker).
  970.          */
  971.         int (*get_pages)(struct drm_i915_gem_object *);
  972.         void (*put_pages)(struct drm_i915_gem_object *);
  973. };
  974.  
  975. struct drm_i915_gem_object {
  976.     struct drm_gem_object base;
  977.  
  978.         const struct drm_i915_gem_object_ops *ops;
  979.  
  980. //    void  *mapped;
  981.  
  982.     /** Current space allocated to this object in the GTT, if any. */
  983.     struct drm_mm_node *gtt_space;
  984.     struct list_head gtt_list;
  985.  
  986.         /** This object's place on the active/inactive lists */
  987.     struct list_head ring_list;
  988.     struct list_head mm_list;
  989.     /** This object's place in the batchbuffer or on the eviction list */
  990.     struct list_head exec_list;
  991.  
  992.     /**
  993.          * This is set if the object is on the active lists (has pending
  994.          * rendering and so a non-zero seqno), and is not set if it i s on
  995.          * inactive (ready to be unbound) list.
  996.      */
  997.         unsigned int active:1;
  998.  
  999.     /**
  1000.      * This is set if the object has been written to since last bound
  1001.      * to the GTT
  1002.      */
  1003.         unsigned int dirty:1;
  1004.  
  1005.     /**
  1006.      * Fence register bits (if any) for this object.  Will be set
  1007.      * as needed when mapped into the GTT.
  1008.      * Protected by dev->struct_mutex.
  1009.      */
  1010.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  1011.  
  1012.     /**
  1013.      * Advice: are the backing pages purgeable?
  1014.      */
  1015.         unsigned int madv:2;
  1016.  
  1017.     /**
  1018.      * Current tiling mode for the object.
  1019.      */
  1020.         unsigned int tiling_mode:2;
  1021.         /**
  1022.          * Whether the tiling parameters for the currently associated fence
  1023.          * register have changed. Note that for the purposes of tracking
  1024.          * tiling changes we also treat the unfenced register, the register
  1025.          * slot that the object occupies whilst it executes a fenced
  1026.          * command (such as BLT on gen2/3), as a "fence".
  1027.          */
  1028.         unsigned int fence_dirty:1;
  1029.  
  1030.     /** How many users have pinned this object in GTT space. The following
  1031.      * users can each hold at most one reference: pwrite/pread, pin_ioctl
  1032.      * (via user_pin_count), execbuffer (objects are not allowed multiple
  1033.      * times for the same batchbuffer), and the framebuffer code. When
  1034.      * switching/pageflipping, the framebuffer code has at most two buffers
  1035.      * pinned per crtc.
  1036.      *
  1037.      * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  1038.      * bits with absolutely no headroom. So use 4 bits. */
  1039.         unsigned int pin_count:4;
  1040. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  1041.  
  1042.     /**
  1043.      * Is the object at the current location in the gtt mappable and
  1044.      * fenceable? Used to avoid costly recalculations.
  1045.      */
  1046.         unsigned int map_and_fenceable:1;
  1047.  
  1048.     /**
  1049.      * Whether the current gtt mapping needs to be mappable (and isn't just
  1050.      * mappable by accident). Track pin and fault separate for a more
  1051.      * accurate mappable working set.
  1052.      */
  1053.         unsigned int fault_mappable:1;
  1054.         unsigned int pin_mappable:1;
  1055.  
  1056.     /*
  1057.      * Is the GPU currently using a fence to access this buffer,
  1058.      */
  1059.     unsigned int pending_fenced_gpu_access:1;
  1060.     unsigned int fenced_gpu_access:1;
  1061.  
  1062.     unsigned int cache_level:2;
  1063.  
  1064.         unsigned int has_aliasing_ppgtt_mapping:1;
  1065.         unsigned int has_global_gtt_mapping:1;
  1066.         unsigned int has_dma_mapping:1;
  1067.  
  1068. //    dma_addr_t *allocated_pages;
  1069.         struct sg_table *pages;
  1070.         int pages_pin_count;
  1071.  
  1072.         /* prime dma-buf support */
  1073.         void *dma_buf_vmapping;
  1074.         int vmapping_count;
  1075.  
  1076.     /**
  1077.      * Used for performing relocations during execbuffer insertion.
  1078.      */
  1079.     struct hlist_node exec_node;
  1080.     unsigned long exec_handle;
  1081.     struct drm_i915_gem_exec_object2 *exec_entry;
  1082.  
  1083.     /**
  1084.      * Current offset of the object in GTT space.
  1085.      *
  1086.      * This is the same as gtt_space->start
  1087.      */
  1088.     uint32_t gtt_offset;
  1089.  
  1090.         struct intel_ring_buffer *ring;
  1091.  
  1092.     /** Breadcrumb of last rendering to the buffer. */
  1093.         uint32_t last_read_seqno;
  1094.         uint32_t last_write_seqno;
  1095.     /** Breadcrumb of last fenced GPU access to the buffer. */
  1096.     uint32_t last_fenced_seqno;
  1097.  
  1098.     /** Current tiling stride for the object, if it's tiled. */
  1099.     uint32_t stride;
  1100.  
  1101.     /** Record of address bit 17 of each page at last unbind. */
  1102.     unsigned long *bit_17;
  1103.  
  1104.     /** User space pin count and filp owning the pin */
  1105.     uint32_t user_pin_count;
  1106.     struct drm_file *pin_filp;
  1107.  
  1108.     /** for phy allocated objects */
  1109.     struct drm_i915_gem_phys_object *phys_obj;
  1110.  
  1111.     /**
  1112.      * Number of crtcs where this object is currently the fb, but
  1113.      * will be page flipped away on the next vblank.  When it
  1114.      * reaches 0, dev_priv->pending_flip_queue will be woken up.
  1115.      */
  1116.     atomic_t pending_flip;
  1117. };
  1118. #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
  1119.  
  1120. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  1121.  
  1122. /**
  1123.  * Request queue structure.
  1124.  *
  1125.  * The request queue allows us to note sequence numbers that have been emitted
  1126.  * and may be associated with active buffers to be retired.
  1127.  *
  1128.  * By keeping this list, we can avoid having to do questionable
  1129.  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  1130.  * an emission time with seqnos for tracking how far ahead of the GPU we are.
  1131.  */
  1132. struct drm_i915_gem_request {
  1133.         /** On Which ring this request was generated */
  1134.         struct intel_ring_buffer *ring;
  1135.  
  1136.         /** GEM sequence number associated with this request. */
  1137.         uint32_t seqno;
  1138.  
  1139.         /** Postion in the ringbuffer of the end of the request */
  1140.         u32 tail;
  1141.  
  1142.         /** Time at which this request was emitted, in jiffies. */
  1143.         unsigned long emitted_jiffies;
  1144.  
  1145.         /** global list entry for this request */
  1146.         struct list_head list;
  1147.  
  1148.         struct drm_i915_file_private *file_priv;
  1149.         /** file_priv list entry for this request */
  1150.         struct list_head client_list;
  1151. };
  1152.  
  1153. struct drm_i915_file_private {
  1154.         struct {
  1155.                 struct spinlock lock;
  1156.                 struct list_head request_list;
  1157.         } mm;
  1158.         struct idr context_idr;
  1159. };
  1160.  
  1161. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  1162.  
  1163. #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
  1164. #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
  1165. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  1166. #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
  1167. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  1168. #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
  1169. #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
  1170. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  1171. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  1172. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  1173. #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
  1174. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  1175. #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
  1176. #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
  1177. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  1178. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  1179. #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
  1180. #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
  1181. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  1182. #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
  1183.                                  (dev)->pci_device == 0x0152 || \
  1184.                                  (dev)->pci_device == 0x015a)
  1185. #define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
  1186.                                  (dev)->pci_device == 0x0106 || \
  1187.                                  (dev)->pci_device == 0x010A)
  1188. #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
  1189. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  1190. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  1191. #define IS_ULT(dev)             (IS_HASWELL(dev) && \
  1192.                                  ((dev)->pci_device & 0xFF00) == 0x0A00)
  1193.  
  1194. /*
  1195.  * The genX designation typically refers to the render engine, so render
  1196.  * capability related checks should use IS_GEN, while display and other checks
  1197.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  1198.  * chips, etc.).
  1199.  */
  1200. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  1201. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  1202. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  1203. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  1204. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  1205. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  1206.  
  1207. #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
  1208. #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
  1209. #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
  1210. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  1211.  
  1212. #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
  1213. #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
  1214.  
  1215. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  1216. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  1217.  
  1218. /* Early gen2 have a totally busted CS tlb and require pinned batches. */
  1219. #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
  1220.  
  1221. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1222.  * rows, which changed the alignment requirements and fence programming.
  1223.  */
  1224. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1225.                                                       IS_I915GM(dev)))
  1226. #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1227. #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
  1228. #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
  1229. #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
  1230. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  1231. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  1232. /* dsparb controlled by hw only */
  1233. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1234.  
  1235. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1236. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1237. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1238.  
  1239. #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
  1240.  
  1241. #define INTEL_PCH_DEVICE_ID_MASK                0xff00
  1242. #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
  1243. #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
  1244. #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
  1245. #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
  1246. #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
  1247.  
  1248. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1249. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  1250. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1251. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1252. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  1253.  
  1254. #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
  1255.  
  1256. #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  1257.  
  1258. #define GT_FREQUENCY_MULTIPLIER 50
  1259.  
  1260. #include "i915_trace.h"
  1261.  
  1262. /**
  1263.  * RC6 is a special power stage which allows the GPU to enter an very
  1264.  * low-voltage mode when idle, using down to 0V while at this stage.  This
  1265.  * stage is entered automatically when the GPU is idle when RC6 support is
  1266.  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  1267.  *
  1268.  * There are different RC6 modes available in Intel GPU, which differentiate
  1269.  * among each other with the latency required to enter and leave RC6 and
  1270.  * voltage consumed by the GPU in different states.
  1271.  *
  1272.  * The combination of the following flags define which states GPU is allowed
  1273.  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  1274.  * RC6pp is deepest RC6. Their support by hardware varies according to the
  1275.  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  1276.  * which brings the most power savings; deeper states save more power, but
  1277.  * require higher latency to switch to and wake up.
  1278.  */
  1279. #define INTEL_RC6_ENABLE                        (1<<0)
  1280. #define INTEL_RC6p_ENABLE                       (1<<1)
  1281. #define INTEL_RC6pp_ENABLE                      (1<<2)
  1282.  
  1283. extern unsigned int i915_fbpercrtc      __always_unused;
  1284. extern int i915_panel_ignore_lid        __read_mostly;
  1285. extern unsigned int i915_powersave      __read_mostly;
  1286. extern int i915_semaphores              __read_mostly;
  1287. extern unsigned int i915_lvds_downclock __read_mostly;
  1288. extern int i915_lvds_channel_mode       __read_mostly;
  1289. extern int i915_panel_use_ssc           __read_mostly;
  1290. extern int i915_vbt_sdvo_panel_type     __read_mostly;
  1291. extern int i915_enable_rc6              __read_mostly;
  1292. extern int i915_enable_fbc              __read_mostly;
  1293. extern bool i915_enable_hangcheck       __read_mostly;
  1294. extern int i915_enable_ppgtt            __read_mostly;
  1295. extern unsigned int i915_preliminary_hw_support __read_mostly;
  1296.  
  1297. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1298. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1299.  
  1300.                                 /* i915_dma.c */
  1301. void i915_update_dri1_breadcrumb(struct drm_device *dev);
  1302. extern void i915_kernel_lost_context(struct drm_device * dev);
  1303. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1304. extern int i915_driver_unload(struct drm_device *);
  1305. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1306. extern void i915_driver_lastclose(struct drm_device * dev);
  1307. extern void i915_driver_preclose(struct drm_device *dev,
  1308.                                  struct drm_file *file_priv);
  1309. extern void i915_driver_postclose(struct drm_device *dev,
  1310.                                   struct drm_file *file_priv);
  1311. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1312. #ifdef CONFIG_COMPAT
  1313. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1314.                               unsigned long arg);
  1315. #endif
  1316. extern int i915_emit_box(struct drm_device *dev,
  1317.                          struct drm_clip_rect *box,
  1318.                          int DR1, int DR4);
  1319. extern int intel_gpu_reset(struct drm_device *dev);
  1320. extern int i915_reset(struct drm_device *dev);
  1321. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1322. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1323. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1324. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1325.  
  1326.  
  1327. /* i915_irq.c */
  1328. void i915_hangcheck_elapsed(unsigned long data);
  1329. void i915_handle_error(struct drm_device *dev, bool wedged);
  1330.  
  1331. extern void intel_irq_init(struct drm_device *dev);
  1332. extern void intel_gt_init(struct drm_device *dev);
  1333. extern void intel_gt_reset(struct drm_device *dev);
  1334.  
  1335. void i915_error_state_free(struct kref *error_ref);
  1336.  
  1337. void
  1338. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1339.  
  1340. void
  1341. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1342.  
  1343. void intel_enable_asle(struct drm_device *dev);
  1344.  
  1345. #ifdef CONFIG_DEBUG_FS
  1346. extern void i915_destroy_error_state(struct drm_device *dev);
  1347. #else
  1348. #define i915_destroy_error_state(x)
  1349. #endif
  1350.  
  1351.  
  1352. /* i915_gem.c */
  1353. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1354.                         struct drm_file *file_priv);
  1355. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1356.                           struct drm_file *file_priv);
  1357. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1358.                          struct drm_file *file_priv);
  1359. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1360.                           struct drm_file *file_priv);
  1361. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1362.                         struct drm_file *file_priv);
  1363. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1364.                         struct drm_file *file_priv);
  1365. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1366.                               struct drm_file *file_priv);
  1367. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1368.                              struct drm_file *file_priv);
  1369. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1370.                         struct drm_file *file_priv);
  1371. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1372.                          struct drm_file *file_priv);
  1373. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1374.                        struct drm_file *file_priv);
  1375. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1376.                          struct drm_file *file_priv);
  1377. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1378.                         struct drm_file *file_priv);
  1379. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  1380.                                struct drm_file *file);
  1381. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  1382.                                struct drm_file *file);
  1383. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1384.                             struct drm_file *file_priv);
  1385. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1386.                            struct drm_file *file_priv);
  1387. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1388.                            struct drm_file *file_priv);
  1389. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1390.                            struct drm_file *file_priv);
  1391. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1392.                         struct drm_file *file_priv);
  1393. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1394.                         struct drm_file *file_priv);
  1395. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1396.                                 struct drm_file *file_priv);
  1397. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  1398.                         struct drm_file *file_priv);
  1399. void i915_gem_load(struct drm_device *dev);
  1400. int i915_gem_init_object(struct drm_gem_object *obj);
  1401. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  1402.                          const struct drm_i915_gem_object_ops *ops);
  1403. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1404.                                                   size_t size);
  1405. void i915_gem_free_object(struct drm_gem_object *obj);
  1406. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1407.                                      uint32_t alignment,
  1408.                                      bool map_and_fenceable,
  1409.                                      bool nonblocking);
  1410. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1411. int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
  1412. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1413. void i915_gem_lastclose(struct drm_device *dev);
  1414.  
  1415. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  1416. static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  1417. {
  1418.         struct scatterlist *sg = obj->pages->sgl;
  1419.         int nents = obj->pages->nents;
  1420.         while (nents > SG_MAX_SINGLE_ALLOC) {
  1421.                 if (n < SG_MAX_SINGLE_ALLOC - 1)
  1422.                         break;
  1423.  
  1424.                 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
  1425.                 n -= SG_MAX_SINGLE_ALLOC - 1;
  1426.                 nents -= SG_MAX_SINGLE_ALLOC - 1;
  1427.         }
  1428.         return sg_page(sg+n);
  1429. }
  1430. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  1431. {
  1432.         BUG_ON(obj->pages == NULL);
  1433.         obj->pages_pin_count++;
  1434. }
  1435. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  1436. {
  1437.         BUG_ON(obj->pages_pin_count == 0);
  1438.         obj->pages_pin_count--;
  1439. }
  1440.  
  1441. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1442. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  1443.                          struct intel_ring_buffer *to);
  1444. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1445.                                     struct intel_ring_buffer *ring);
  1446.  
  1447. int i915_gem_dumb_create(struct drm_file *file_priv,
  1448.                          struct drm_device *dev,
  1449.                          struct drm_mode_create_dumb *args);
  1450. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1451.                       uint32_t handle, uint64_t *offset);
  1452. int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
  1453.                           uint32_t handle);
  1454. /**
  1455.  * Returns true if seq1 is later than seq2.
  1456.  */
  1457. static inline bool
  1458. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1459. {
  1460.         return (int32_t)(seq1 - seq2) >= 0;
  1461. }
  1462.  
  1463. extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
  1464.  
  1465. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  1466. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1467.  
  1468. static inline bool
  1469. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  1470. {
  1471.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1472.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1473.                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
  1474.                 return true;
  1475.         } else
  1476.                 return false;
  1477. }
  1478.  
  1479. static inline void
  1480. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  1481. {
  1482.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1483.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1484.                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
  1485.         }
  1486. }
  1487.  
  1488. void i915_gem_retire_requests(struct drm_device *dev);
  1489. void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
  1490. int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
  1491.                                       bool interruptible);
  1492.  
  1493. void i915_gem_reset(struct drm_device *dev);
  1494. void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
  1495. int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
  1496.                                             uint32_t read_domains,
  1497.                                             uint32_t write_domain);
  1498. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1499. int __must_check i915_gem_init(struct drm_device *dev);
  1500. int __must_check i915_gem_init_hw(struct drm_device *dev);
  1501. void i915_gem_l3_remap(struct drm_device *dev);
  1502. void i915_gem_init_swizzling(struct drm_device *dev);
  1503. void i915_gem_init_ppgtt(struct drm_device *dev);
  1504. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1505. int __must_check i915_gpu_idle(struct drm_device *dev);
  1506. int __must_check i915_gem_idle(struct drm_device *dev);
  1507. int i915_add_request(struct intel_ring_buffer *ring,
  1508.                                   struct drm_file *file,
  1509.                      u32 *seqno);
  1510. int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
  1511.                                    uint32_t seqno);
  1512. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1513. int __must_check
  1514. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1515.                                   bool write);
  1516. int __must_check
  1517. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  1518. int __must_check
  1519. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1520.                                      u32 alignment,
  1521.                                      struct intel_ring_buffer *pipelined);
  1522. int i915_gem_attach_phys_object(struct drm_device *dev,
  1523.                                 struct drm_i915_gem_object *obj,
  1524.                                 int id,
  1525.                                 int align);
  1526. void i915_gem_detach_phys_object(struct drm_device *dev,
  1527.                                  struct drm_i915_gem_object *obj);
  1528. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1529. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1530.  
  1531. uint32_t
  1532. i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
  1533.                                     uint32_t size,
  1534.                                     int tiling_mode);
  1535.  
  1536. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1537.                                     enum i915_cache_level cache_level);
  1538.  
  1539.  
  1540. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  1541.                                 struct drm_gem_object *gem_obj, int flags);
  1542.  
  1543. /* i915_gem_context.c */
  1544. void i915_gem_context_init(struct drm_device *dev);
  1545. void i915_gem_context_fini(struct drm_device *dev);
  1546. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  1547. int i915_switch_context(struct intel_ring_buffer *ring,
  1548.                         struct drm_file *file, int to_id);
  1549. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  1550.                                   struct drm_file *file);
  1551. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  1552.                                    struct drm_file *file);
  1553.  
  1554. /* i915_gem_gtt.c */
  1555. int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
  1556. void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
  1557. void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
  1558.                             struct drm_i915_gem_object *obj,
  1559.                             enum i915_cache_level cache_level);
  1560. void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  1561.                               struct drm_i915_gem_object *obj);
  1562.  
  1563. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1564. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  1565. void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
  1566.                                 enum i915_cache_level cache_level);
  1567. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1568. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  1569. void i915_gem_init_global_gtt(struct drm_device *dev,
  1570.                               unsigned long start,
  1571.                               unsigned long mappable_end,
  1572.                               unsigned long end);
  1573. int i915_gem_gtt_init(struct drm_device *dev);
  1574. void i915_gem_gtt_fini(struct drm_device *dev);
  1575. static inline void i915_gem_chipset_flush(struct drm_device *dev)
  1576. {
  1577.         if (INTEL_INFO(dev)->gen < 6)
  1578.                 intel_gtt_chipset_flush();
  1579. }
  1580.  
  1581.  
  1582. /* i915_gem_evict.c */
  1583. int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
  1584.                                           unsigned alignment,
  1585.                                           unsigned cache_level,
  1586.                                           bool mappable,
  1587.                                           bool nonblock);
  1588. int i915_gem_evict_everything(struct drm_device *dev);
  1589.  
  1590. /* i915_gem_stolen.c */
  1591. int i915_gem_init_stolen(struct drm_device *dev);
  1592. void i915_gem_cleanup_stolen(struct drm_device *dev);
  1593.  
  1594. /* i915_gem_tiling.c */
  1595. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1596. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1597. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1598.  
  1599. /* i915_gem_debug.c */
  1600. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1601.                           const char *where, uint32_t mark);
  1602. #if WATCH_LISTS
  1603. int i915_verify_lists(struct drm_device *dev);
  1604. #else
  1605. #define i915_verify_lists(dev) 0
  1606. #endif
  1607. void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
  1608.                                      int handle);
  1609. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1610.                           const char *where, uint32_t mark);
  1611.  
  1612. /* i915_debugfs.c */
  1613. int i915_debugfs_init(struct drm_minor *minor);
  1614. void i915_debugfs_cleanup(struct drm_minor *minor);
  1615.  
  1616. /* i915_suspend.c */
  1617. extern int i915_save_state(struct drm_device *dev);
  1618. extern int i915_restore_state(struct drm_device *dev);
  1619.  
  1620. /* i915_suspend.c */
  1621. extern int i915_save_state(struct drm_device *dev);
  1622. extern int i915_restore_state(struct drm_device *dev);
  1623.  
  1624. /* i915_sysfs.c */
  1625. void i915_setup_sysfs(struct drm_device *dev_priv);
  1626. void i915_teardown_sysfs(struct drm_device *dev_priv);
  1627.  
  1628. /* intel_i2c.c */
  1629. extern int intel_setup_gmbus(struct drm_device *dev);
  1630. extern void intel_teardown_gmbus(struct drm_device *dev);
  1631. extern inline bool intel_gmbus_is_port_valid(unsigned port)
  1632. {
  1633.         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  1634. }
  1635.  
  1636. extern struct i2c_adapter *intel_gmbus_get_adapter(
  1637.                 struct drm_i915_private *dev_priv, unsigned port);
  1638. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1639. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1640. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1641. {
  1642.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1643. }
  1644. extern void intel_i2c_reset(struct drm_device *dev);
  1645.  
  1646. /* intel_opregion.c */
  1647. extern int intel_opregion_setup(struct drm_device *dev);
  1648. #ifdef CONFIG_ACPI
  1649. extern void intel_opregion_init(struct drm_device *dev);
  1650. extern void intel_opregion_fini(struct drm_device *dev);
  1651. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1652. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1653. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1654. #else
  1655. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1656. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1657. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1658. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1659. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1660. #endif
  1661.  
  1662. /* intel_acpi.c */
  1663. #ifdef CONFIG_ACPI
  1664. extern void intel_register_dsm_handler(void);
  1665. extern void intel_unregister_dsm_handler(void);
  1666. #else
  1667. static inline void intel_register_dsm_handler(void) { return; }
  1668. static inline void intel_unregister_dsm_handler(void) { return; }
  1669. #endif /* CONFIG_ACPI */
  1670.  
  1671. /* modesetting */
  1672. extern void intel_modeset_init_hw(struct drm_device *dev);
  1673. extern void intel_modeset_init(struct drm_device *dev);
  1674. extern void intel_modeset_gem_init(struct drm_device *dev);
  1675. extern void intel_modeset_cleanup(struct drm_device *dev);
  1676. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1677. extern void intel_modeset_setup_hw_state(struct drm_device *dev,
  1678.                                          bool force_restore);
  1679. extern bool intel_fbc_enabled(struct drm_device *dev);
  1680. extern void intel_disable_fbc(struct drm_device *dev);
  1681. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1682. extern void intel_init_pch_refclk(struct drm_device *dev);
  1683. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  1684. extern void intel_detect_pch(struct drm_device *dev);
  1685. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  1686. extern int intel_enable_rc6(const struct drm_device *dev);
  1687.  
  1688. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  1689. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  1690.                         struct drm_file *file);
  1691.  
  1692. /* overlay */
  1693. #ifdef CONFIG_DEBUG_FS
  1694. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1695. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1696.  
  1697. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  1698. extern void intel_display_print_error_state(struct seq_file *m,
  1699.                                             struct drm_device *dev,
  1700.                                             struct intel_display_error_state *error);
  1701. #endif
  1702.  
  1703. /* On SNB platform, before reading ring registers forcewake bit
  1704.  * must be set to prevent GT core from power down and stale values being
  1705.  * returned.
  1706.  */
  1707. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1708. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1709. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
  1710.  
  1711. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
  1712. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
  1713.  
  1714. #define __i915_read(x, y) \
  1715.         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
  1716.  
  1717. __i915_read(8, b)
  1718. __i915_read(16, w)
  1719. __i915_read(32, l)
  1720. __i915_read(64, q)
  1721. #undef __i915_read
  1722.  
  1723. #define __i915_write(x, y) \
  1724.         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
  1725.  
  1726. __i915_write(8, b)
  1727. __i915_write(16, w)
  1728. __i915_write(32, l)
  1729. __i915_write(64, q)
  1730. #undef __i915_write
  1731.  
  1732. #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
  1733. #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
  1734.  
  1735. #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
  1736. #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
  1737. #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
  1738. #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
  1739.  
  1740. #define I915_READ(reg)          i915_read32(dev_priv, (reg))
  1741. #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
  1742. #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
  1743. #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
  1744.  
  1745. #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
  1746. #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
  1747.  
  1748. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  1749. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  1750.  
  1751. typedef struct
  1752. {
  1753.   int width;
  1754.   int height;
  1755.   int bpp;
  1756.   int freq;
  1757. }videomode_t;
  1758.  
  1759.  
  1760. static inline int mutex_trylock(struct mutex *lock)
  1761. {
  1762.     if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1))
  1763.         return 1;
  1764.     return 0;
  1765. }
  1766.  
  1767.  
  1768. #define ioread32(addr)          readl(addr)
  1769.  
  1770.  
  1771.  
  1772.  
  1773.  
  1774. #endif
  1775.