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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include "i915_reg.h"
  34. #include "intel_bios.h"
  35. #include "intel_ringbuffer.h"
  36. //#include <linux/io-mapping.h>
  37. #include <linux/i2c.h>
  38. #include <drm/intel-gtt.h>
  39. //#include <linux/backlight.h>
  40.  
  41. #include <linux/spinlock.h>
  42.  
  43. /* General customization:
  44.  */
  45.  
  46. #define I915_TILING_NONE    0
  47.  
  48.  
  49. #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  50.  
  51. #define DRIVER_NAME             "i915"
  52. #define DRIVER_DESC             "Intel Graphics"
  53. #define DRIVER_DATE             "20080730"
  54.  
  55. enum pipe {
  56.         PIPE_A = 0,
  57.         PIPE_B,
  58.         PIPE_C,
  59.         I915_MAX_PIPES
  60. };
  61. #define pipe_name(p) ((p) + 'A')
  62.  
  63. enum plane {
  64.         PLANE_A = 0,
  65.         PLANE_B,
  66.         PLANE_C,
  67. };
  68. #define plane_name(p) ((p) + 'A')
  69.  
  70. #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  71.  
  72. #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  73.  
  74. /* Interface history:
  75.  *
  76.  * 1.1: Original.
  77.  * 1.2: Add Power Management
  78.  * 1.3: Add vblank support
  79.  * 1.4: Fix cmdbuffer path, add heap destroy
  80.  * 1.5: Add vblank pipe configuration
  81.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  82.  *      - Support vertical blank on secondary display pipe
  83.  */
  84. #define DRIVER_MAJOR            1
  85. #define DRIVER_MINOR            6
  86. #define DRIVER_PATCHLEVEL       0
  87.  
  88. #define WATCH_COHERENCY 0
  89. #define WATCH_LISTS     0
  90.  
  91. #define I915_GEM_PHYS_CURSOR_0 1
  92. #define I915_GEM_PHYS_CURSOR_1 2
  93. #define I915_GEM_PHYS_OVERLAY_REGS 3
  94. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  95.  
  96. struct mem_block {
  97.         struct mem_block *next;
  98.         struct mem_block *prev;
  99.         int start;
  100.         int size;
  101.         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  102. };
  103.  
  104. struct opregion_header;
  105. struct opregion_acpi;
  106. struct opregion_swsci;
  107. struct opregion_asle;
  108. struct drm_i915_private;
  109.  
  110. struct intel_opregion {
  111.         struct opregion_header *header;
  112.         struct opregion_acpi *acpi;
  113.         struct opregion_swsci *swsci;
  114.         struct opregion_asle *asle;
  115.         void *vbt;
  116.         u32 __iomem *lid_state;
  117. };
  118. #define OPREGION_SIZE            (8*1024)
  119.  
  120. struct intel_overlay;
  121. struct intel_overlay_error_state;
  122.  
  123. struct drm_i915_master_private {
  124.         drm_local_map_t *sarea;
  125.         struct _drm_i915_sarea *sarea_priv;
  126. };
  127. #define I915_FENCE_REG_NONE -1
  128. #define I915_MAX_NUM_FENCES 16
  129. /* 16 fences + sign bit for FENCE_REG_NONE */
  130. #define I915_MAX_NUM_FENCE_BITS 5
  131.  
  132. struct drm_i915_fence_reg {
  133.         struct list_head lru_list;
  134.         struct drm_i915_gem_object *obj;
  135.         uint32_t setup_seqno;
  136. };
  137.  
  138. struct sdvo_device_mapping {
  139.         u8 initialized;
  140.         u8 dvo_port;
  141.         u8 slave_addr;
  142.         u8 dvo_wiring;
  143.         u8 i2c_pin;
  144.         u8 ddc_pin;
  145. };
  146.  
  147. struct intel_display_error_state;
  148.  
  149. struct drm_i915_error_state {
  150.         u32 eir;
  151.         u32 pgtbl_er;
  152.         u32 pipestat[I915_MAX_PIPES];
  153.         u32 ipeir;
  154.         u32 ipehr;
  155.         u32 instdone;
  156.         u32 acthd;
  157.         u32 error; /* gen6+ */
  158.         u32 bcs_acthd; /* gen6+ blt engine */
  159.         u32 bcs_ipehr;
  160.         u32 bcs_ipeir;
  161.         u32 bcs_instdone;
  162.         u32 bcs_seqno;
  163.         u32 vcs_acthd; /* gen6+ bsd engine */
  164.         u32 vcs_ipehr;
  165.         u32 vcs_ipeir;
  166.         u32 vcs_instdone;
  167.         u32 vcs_seqno;
  168.         u32 instpm;
  169.         u32 instps;
  170.         u32 instdone1;
  171.         u32 seqno;
  172.         u64 bbaddr;
  173.         u64 fence[I915_MAX_NUM_FENCES];
  174.         struct timeval time;
  175.         struct drm_i915_error_object {
  176.                 int page_count;
  177.                 u32 gtt_offset;
  178.                 u32 *pages[0];
  179.         } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
  180.         struct drm_i915_error_buffer {
  181.                 u32 size;
  182.                 u32 name;
  183.                 u32 seqno;
  184.                 u32 gtt_offset;
  185.                 u32 read_domains;
  186.                 u32 write_domain;
  187.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  188.                 s32 pinned:2;
  189.                 u32 tiling:2;
  190.                 u32 dirty:1;
  191.                 u32 purgeable:1;
  192.                 u32 ring:4;
  193.                 u32 cache_level:2;
  194.         } *active_bo, *pinned_bo;
  195.         u32 active_bo_count, pinned_bo_count;
  196.         struct intel_overlay_error_state *overlay;
  197.         struct intel_display_error_state *display;
  198. };
  199.  
  200. struct drm_i915_display_funcs {
  201.         void (*dpms)(struct drm_crtc *crtc, int mode);
  202.         bool (*fbc_enabled)(struct drm_device *dev);
  203.         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  204.         void (*disable_fbc)(struct drm_device *dev);
  205.         int (*get_display_clock_speed)(struct drm_device *dev);
  206.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  207.         void (*update_wm)(struct drm_device *dev);
  208.         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
  209.                                  uint32_t sprite_width, int pixel_size);
  210.         int (*crtc_mode_set)(struct drm_crtc *crtc,
  211.                              struct drm_display_mode *mode,
  212.                              struct drm_display_mode *adjusted_mode,
  213.                              int x, int y,
  214.                              struct drm_framebuffer *old_fb);
  215.         void (*write_eld)(struct drm_connector *connector,
  216.                           struct drm_crtc *crtc);
  217.         void (*fdi_link_train)(struct drm_crtc *crtc);
  218.         void (*init_clock_gating)(struct drm_device *dev);
  219.         void (*init_pch_clock_gating)(struct drm_device *dev);
  220.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  221.                           struct drm_framebuffer *fb,
  222.                           struct drm_i915_gem_object *obj);
  223.         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  224.                             int x, int y);
  225.         void (*force_wake_get)(struct drm_i915_private *dev_priv);
  226.         void (*force_wake_put)(struct drm_i915_private *dev_priv);
  227.         /* clock updates for mode set */
  228.         /* cursor updates */
  229.         /* render clock increase/decrease */
  230.         /* display clock increase/decrease */
  231.         /* pll clock increase/decrease */
  232. };
  233.  
  234. struct intel_device_info {
  235.         u8 gen;
  236.         u8 is_mobile:1;
  237.         u8 is_i85x:1;
  238.         u8 is_i915g:1;
  239.         u8 is_i945gm:1;
  240.         u8 is_g33:1;
  241.         u8 need_gfx_hws:1;
  242.         u8 is_g4x:1;
  243.         u8 is_pineview:1;
  244.         u8 is_broadwater:1;
  245.         u8 is_crestline:1;
  246.         u8 is_ivybridge:1;
  247.         u8 has_fbc:1;
  248.         u8 has_pipe_cxsr:1;
  249.         u8 has_hotplug:1;
  250.         u8 cursor_needs_physical:1;
  251.         u8 has_overlay:1;
  252.         u8 overlay_needs_physical:1;
  253.         u8 supports_tv:1;
  254.         u8 has_bsd_ring:1;
  255.         u8 has_blt_ring:1;
  256. };
  257.  
  258. enum no_fbc_reason {
  259.         FBC_NO_OUTPUT, /* no outputs enabled to compress */
  260.         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  261.         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  262.         FBC_MODE_TOO_LARGE, /* mode too large for compression */
  263.         FBC_BAD_PLANE, /* fbc not supported on plane */
  264.         FBC_NOT_TILED, /* buffer not tiled */
  265.         FBC_MULTIPLE_PIPES, /* more than one pipe active */
  266.         FBC_MODULE_PARAM,
  267. };
  268.  
  269. enum intel_pch {
  270.         PCH_IBX,        /* Ibexpeak PCH */
  271.         PCH_CPT,        /* Cougarpoint PCH */
  272. };
  273.  
  274. #define QUIRK_PIPEA_FORCE (1<<0)
  275. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  276.  
  277. struct intel_fbdev;
  278. struct intel_fbc_work;
  279.  
  280. typedef struct drm_i915_private {
  281.         struct drm_device *dev;
  282.  
  283.         const struct intel_device_info *info;
  284.  
  285.         int has_gem;
  286.         int relative_constants_mode;
  287.  
  288.         void __iomem *regs;
  289.         /** gt_fifo_count and the subsequent register write are synchronized
  290.          * with dev->struct_mutex. */
  291.         unsigned gt_fifo_count;
  292.         /** forcewake_count is protected by gt_lock */
  293.         unsigned forcewake_count;
  294.         /** gt_lock is also taken in irq contexts. */
  295.     spinlock_t gt_lock;
  296.  
  297.     struct intel_gmbus {
  298.         struct i2c_adapter adapter;
  299.         struct i2c_adapter *force_bit;
  300.         u32 reg0;
  301.     } *gmbus;
  302.  
  303.         struct pci_dev *bridge_dev;
  304.     struct intel_ring_buffer ring[I915_NUM_RINGS];
  305.         uint32_t next_seqno;
  306.  
  307.     drm_dma_handle_t *status_page_dmah;
  308.         uint32_t counter;
  309.         drm_local_map_t hws_map;
  310.     struct drm_i915_gem_object *pwrctx;
  311.     struct drm_i915_gem_object *renderctx;
  312.  
  313. //   struct resource mch_res;
  314.  
  315.         unsigned int cpp;
  316.         int back_offset;
  317.         int front_offset;
  318.         int current_page;
  319.         int page_flipping;
  320.  
  321.         atomic_t irq_received;
  322.  
  323.         /* protects the irq masks */
  324.         spinlock_t irq_lock;
  325.         /** Cached value of IMR to avoid reads in updating the bitfield */
  326.         u32 pipestat[2];
  327.         u32 irq_mask;
  328.         u32 gt_irq_mask;
  329.         u32 pch_irq_mask;
  330.  
  331.         u32 hotplug_supported_mask;
  332. //   struct work_struct hotplug_work;
  333.  
  334.         int tex_lru_log_granularity;
  335.         int allow_batchbuffer;
  336.         struct mem_block *agp_heap;
  337.         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  338.         int vblank_pipe;
  339.         int num_pipe;
  340.  
  341.         /* For hangcheck timer */
  342. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  343.     struct timer_list hangcheck_timer;
  344.         int hangcheck_count;
  345.         uint32_t last_acthd;
  346.         uint32_t last_acthd_bsd;
  347.         uint32_t last_acthd_blt;
  348.         uint32_t last_instdone;
  349.         uint32_t last_instdone1;
  350.  
  351.         unsigned long cfb_size;
  352.         unsigned int cfb_fb;
  353.         enum plane cfb_plane;
  354.         int cfb_y;
  355. //   struct intel_fbc_work *fbc_work;
  356.  
  357.     struct intel_opregion opregion;
  358.  
  359.         /* overlay */
  360. //   struct intel_overlay *overlay;
  361.         bool sprite_scaling_enabled;
  362.  
  363.         /* LVDS info */
  364.         int backlight_level;  /* restore backlight to this value */
  365.         bool backlight_enabled;
  366.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  367.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  368.  
  369.         /* Feature bits from the VBIOS */
  370.         unsigned int int_tv_support:1;
  371.         unsigned int lvds_dither:1;
  372.         unsigned int lvds_vbt:1;
  373.         unsigned int int_crt_support:1;
  374.         unsigned int lvds_use_ssc:1;
  375.         unsigned int display_clock_mode:1;
  376.         int lvds_ssc_freq;
  377.         struct {
  378.                 int rate;
  379.                 int lanes;
  380.                 int preemphasis;
  381.                 int vswing;
  382.  
  383.                 bool initialized;
  384.                 bool support;
  385.                 int bpp;
  386.         struct edp_power_seq pps;
  387.         } edp;
  388.         bool no_aux_handshake;
  389.  
  390. //   struct notifier_block lid_notifier;
  391.  
  392.         int crt_ddc_pin;
  393.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  394.         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  395.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  396.  
  397.         unsigned int fsb_freq, mem_freq, is_ddr3;
  398.  
  399.         spinlock_t error_lock;
  400. //   struct drm_i915_error_state *first_error;
  401. //   struct work_struct error_work;
  402. //   struct completion error_completion;
  403. //   struct workqueue_struct *wq;
  404.  
  405.         /* Display functions */
  406.     struct drm_i915_display_funcs display;
  407.  
  408.         /* PCH chipset type */
  409.         enum intel_pch pch_type;
  410.  
  411.         unsigned long quirks;
  412.  
  413.         /* Register state */
  414.         bool modeset_on_lid;
  415.         u8 saveLBB;
  416.         u32 saveDSPACNTR;
  417.         u32 saveDSPBCNTR;
  418.         u32 saveDSPARB;
  419.         u32 saveHWS;
  420.         u32 savePIPEACONF;
  421.         u32 savePIPEBCONF;
  422.         u32 savePIPEASRC;
  423.         u32 savePIPEBSRC;
  424.         u32 saveFPA0;
  425.         u32 saveFPA1;
  426.         u32 saveDPLL_A;
  427.         u32 saveDPLL_A_MD;
  428.         u32 saveHTOTAL_A;
  429.         u32 saveHBLANK_A;
  430.         u32 saveHSYNC_A;
  431.         u32 saveVTOTAL_A;
  432.         u32 saveVBLANK_A;
  433.         u32 saveVSYNC_A;
  434.         u32 saveBCLRPAT_A;
  435.         u32 saveTRANSACONF;
  436.         u32 saveTRANS_HTOTAL_A;
  437.         u32 saveTRANS_HBLANK_A;
  438.         u32 saveTRANS_HSYNC_A;
  439.         u32 saveTRANS_VTOTAL_A;
  440.         u32 saveTRANS_VBLANK_A;
  441.         u32 saveTRANS_VSYNC_A;
  442.         u32 savePIPEASTAT;
  443.         u32 saveDSPASTRIDE;
  444.         u32 saveDSPASIZE;
  445.         u32 saveDSPAPOS;
  446.         u32 saveDSPAADDR;
  447.         u32 saveDSPASURF;
  448.         u32 saveDSPATILEOFF;
  449.         u32 savePFIT_PGM_RATIOS;
  450.         u32 saveBLC_HIST_CTL;
  451.         u32 saveBLC_PWM_CTL;
  452.         u32 saveBLC_PWM_CTL2;
  453.         u32 saveBLC_CPU_PWM_CTL;
  454.         u32 saveBLC_CPU_PWM_CTL2;
  455.         u32 saveFPB0;
  456.         u32 saveFPB1;
  457.         u32 saveDPLL_B;
  458.         u32 saveDPLL_B_MD;
  459.         u32 saveHTOTAL_B;
  460.         u32 saveHBLANK_B;
  461.         u32 saveHSYNC_B;
  462.         u32 saveVTOTAL_B;
  463.         u32 saveVBLANK_B;
  464.         u32 saveVSYNC_B;
  465.         u32 saveBCLRPAT_B;
  466.         u32 saveTRANSBCONF;
  467.         u32 saveTRANS_HTOTAL_B;
  468.         u32 saveTRANS_HBLANK_B;
  469.         u32 saveTRANS_HSYNC_B;
  470.         u32 saveTRANS_VTOTAL_B;
  471.         u32 saveTRANS_VBLANK_B;
  472.         u32 saveTRANS_VSYNC_B;
  473.         u32 savePIPEBSTAT;
  474.         u32 saveDSPBSTRIDE;
  475.         u32 saveDSPBSIZE;
  476.         u32 saveDSPBPOS;
  477.         u32 saveDSPBADDR;
  478.         u32 saveDSPBSURF;
  479.         u32 saveDSPBTILEOFF;
  480.         u32 saveVGA0;
  481.         u32 saveVGA1;
  482.         u32 saveVGA_PD;
  483.         u32 saveVGACNTRL;
  484.         u32 saveADPA;
  485.         u32 saveLVDS;
  486.         u32 savePP_ON_DELAYS;
  487.         u32 savePP_OFF_DELAYS;
  488.         u32 saveDVOA;
  489.         u32 saveDVOB;
  490.         u32 saveDVOC;
  491.         u32 savePP_ON;
  492.         u32 savePP_OFF;
  493.         u32 savePP_CONTROL;
  494.         u32 savePP_DIVISOR;
  495.         u32 savePFIT_CONTROL;
  496.         u32 save_palette_a[256];
  497.         u32 save_palette_b[256];
  498.         u32 saveDPFC_CB_BASE;
  499.         u32 saveFBC_CFB_BASE;
  500.         u32 saveFBC_LL_BASE;
  501.         u32 saveFBC_CONTROL;
  502.         u32 saveFBC_CONTROL2;
  503.         u32 saveIER;
  504.         u32 saveIIR;
  505.         u32 saveIMR;
  506.         u32 saveDEIER;
  507.         u32 saveDEIMR;
  508.         u32 saveGTIER;
  509.         u32 saveGTIMR;
  510.         u32 saveFDI_RXA_IMR;
  511.         u32 saveFDI_RXB_IMR;
  512.         u32 saveCACHE_MODE_0;
  513.         u32 saveMI_ARB_STATE;
  514.         u32 saveSWF0[16];
  515.         u32 saveSWF1[16];
  516.         u32 saveSWF2[3];
  517.         u8 saveMSR;
  518.         u8 saveSR[8];
  519.         u8 saveGR[25];
  520.         u8 saveAR_INDEX;
  521.         u8 saveAR[21];
  522.         u8 saveDACMASK;
  523.         u8 saveCR[37];
  524.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  525.         u32 saveCURACNTR;
  526.         u32 saveCURAPOS;
  527.         u32 saveCURABASE;
  528.         u32 saveCURBCNTR;
  529.         u32 saveCURBPOS;
  530.         u32 saveCURBBASE;
  531.         u32 saveCURSIZE;
  532.         u32 saveDP_B;
  533.         u32 saveDP_C;
  534.         u32 saveDP_D;
  535.         u32 savePIPEA_GMCH_DATA_M;
  536.         u32 savePIPEB_GMCH_DATA_M;
  537.         u32 savePIPEA_GMCH_DATA_N;
  538.         u32 savePIPEB_GMCH_DATA_N;
  539.         u32 savePIPEA_DP_LINK_M;
  540.         u32 savePIPEB_DP_LINK_M;
  541.         u32 savePIPEA_DP_LINK_N;
  542.         u32 savePIPEB_DP_LINK_N;
  543.         u32 saveFDI_RXA_CTL;
  544.         u32 saveFDI_TXA_CTL;
  545.         u32 saveFDI_RXB_CTL;
  546.         u32 saveFDI_TXB_CTL;
  547.         u32 savePFA_CTL_1;
  548.         u32 savePFB_CTL_1;
  549.         u32 savePFA_WIN_SZ;
  550.         u32 savePFB_WIN_SZ;
  551.         u32 savePFA_WIN_POS;
  552.         u32 savePFB_WIN_POS;
  553.         u32 savePCH_DREF_CONTROL;
  554.         u32 saveDISP_ARB_CTL;
  555.         u32 savePIPEA_DATA_M1;
  556.         u32 savePIPEA_DATA_N1;
  557.         u32 savePIPEA_LINK_M1;
  558.         u32 savePIPEA_LINK_N1;
  559.         u32 savePIPEB_DATA_M1;
  560.         u32 savePIPEB_DATA_N1;
  561.         u32 savePIPEB_LINK_M1;
  562.         u32 savePIPEB_LINK_N1;
  563.         u32 saveMCHBAR_RENDER_STANDBY;
  564.         u32 savePCH_PORT_HOTPLUG;
  565.  
  566.         struct {
  567.                 /** Bridge to intel-gtt-ko */
  568.                 const struct intel_gtt *gtt;
  569.                 /** Memory allocator for GTT stolen memory */
  570.         struct drm_mm stolen;
  571.                 /** Memory allocator for GTT */
  572.         struct drm_mm gtt_space;
  573.                 /** List of all objects in gtt_space. Used to restore gtt
  574.                  * mappings on resume */
  575.                 struct list_head gtt_list;
  576.  
  577.                 /** Usable portion of the GTT for GEM */
  578.                 unsigned long gtt_start;
  579.                 unsigned long gtt_mappable_end;
  580.                 unsigned long gtt_end;
  581.  
  582. //       struct io_mapping *gtt_mapping;
  583.                 int gtt_mtrr;
  584.  
  585. //       struct shrinker inactive_shrinker;
  586.  
  587.                 /**
  588.                  * List of objects currently involved in rendering.
  589.                  *
  590.                  * Includes buffers having the contents of their GPU caches
  591.                  * flushed, not necessarily primitives.  last_rendering_seqno
  592.                  * represents when the rendering involved will be completed.
  593.                  *
  594.                  * A reference is held on the buffer while on this list.
  595.                  */
  596.                 struct list_head active_list;
  597.  
  598.                 /**
  599.                  * List of objects which are not in the ringbuffer but which
  600.                  * still have a write_domain which needs to be flushed before
  601.                  * unbinding.
  602.                  *
  603.                  * last_rendering_seqno is 0 while an object is in this list.
  604.                  *
  605.                  * A reference is held on the buffer while on this list.
  606.                  */
  607.                 struct list_head flushing_list;
  608.  
  609.                 /**
  610.                  * LRU list of objects which are not in the ringbuffer and
  611.                  * are ready to unbind, but are still in the GTT.
  612.                  *
  613.                  * last_rendering_seqno is 0 while an object is in this list.
  614.                  *
  615.                  * A reference is not held on the buffer while on this list,
  616.                  * as merely being GTT-bound shouldn't prevent its being
  617.                  * freed, and we'll pull it off the list in the free path.
  618.                  */
  619.                 struct list_head inactive_list;
  620.  
  621.                 /**
  622.                  * LRU list of objects which are not in the ringbuffer but
  623.                  * are still pinned in the GTT.
  624.                  */
  625.                 struct list_head pinned_list;
  626.  
  627.                 /** LRU list of objects with fence regs on them. */
  628.                 struct list_head fence_list;
  629.  
  630.                 /**
  631.                  * List of objects currently pending being freed.
  632.                  *
  633.                  * These objects are no longer in use, but due to a signal
  634.                  * we were prevented from freeing them at the appointed time.
  635.                  */
  636.                 struct list_head deferred_free_list;
  637.  
  638.                 /**
  639.                  * We leave the user IRQ off as much as possible,
  640.                  * but this means that requests will finish and never
  641.                  * be retired once the system goes idle. Set a timer to
  642.                  * fire periodically while the ring is running. When it
  643.                  * fires, go retire requests.
  644.                  */
  645. //       struct delayed_work retire_work;
  646.  
  647.                 /**
  648.                  * Are we in a non-interruptible section of code like
  649.                  * modesetting?
  650.                  */
  651.                 bool interruptible;
  652.  
  653.                 /**
  654.                  * Flag if the X Server, and thus DRM, is not currently in
  655.                  * control of the device.
  656.                  *
  657.                  * This is set between LeaveVT and EnterVT.  It needs to be
  658.                  * replaced with a semaphore.  It also needs to be
  659.                  * transitioned away from for kernel modesetting.
  660.                  */
  661.                 int suspended;
  662.  
  663.                 /**
  664.                  * Flag if the hardware appears to be wedged.
  665.                  *
  666.                  * This is set when attempts to idle the device timeout.
  667.                  * It prevents command submission from occurring and makes
  668.                  * every pending request fail
  669.                  */
  670.                 atomic_t wedged;
  671.  
  672.                 /** Bit 6 swizzling required for X tiling */
  673.                 uint32_t bit_6_swizzle_x;
  674.                 /** Bit 6 swizzling required for Y tiling */
  675.                 uint32_t bit_6_swizzle_y;
  676.  
  677.                 /* storage for physical objects */
  678. //       struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  679.  
  680.                 /* accounting, useful for userland debugging */
  681.                 size_t gtt_total;
  682.                 size_t mappable_gtt_total;
  683.                 size_t object_memory;
  684.                 u32 object_count;
  685.         } mm;
  686.     struct sdvo_device_mapping sdvo_mappings[2];
  687.         /* indicate whether the LVDS_BORDER should be enabled or not */
  688.         unsigned int lvds_border_bits;
  689.         /* Panel fitter placement and size for Ironlake+ */
  690.         u32 pch_pf_pos, pch_pf_size;
  691.  
  692.     struct drm_crtc *plane_to_crtc_mapping[3];
  693.     struct drm_crtc *pipe_to_crtc_mapping[3];
  694. //   wait_queue_head_t pending_flip_queue;
  695.         bool flip_pending_is_done;
  696.  
  697.         /* Reclocking support */
  698.         bool render_reclock_avail;
  699.         bool lvds_downclock_avail;
  700.         /* indicates the reduced downclock for LVDS*/
  701.         int lvds_downclock;
  702. //   struct work_struct idle_work;
  703.     struct timer_list idle_timer;
  704.         bool busy;
  705.         u16 orig_clock;
  706.         int child_dev_num;
  707.     struct child_device_config *child_dev;
  708.     struct drm_connector *int_lvds_connector;
  709.     struct drm_connector *int_edp_connector;
  710.  
  711.         bool mchbar_need_disable;
  712.  
  713. //   struct work_struct rps_work;
  714.         spinlock_t rps_lock;
  715.         u32 pm_iir;
  716.  
  717.         u8 cur_delay;
  718.         u8 min_delay;
  719.         u8 max_delay;
  720.         u8 fmax;
  721.         u8 fstart;
  722.  
  723.         u64 last_count1;
  724.         unsigned long last_time1;
  725.         unsigned long chipset_power;
  726.         u64 last_count2;
  727.     struct timespec last_time2;
  728.         unsigned long gfx_power;
  729.         int c_m;
  730.         int r_t;
  731.         u8 corr;
  732.         spinlock_t *mchdev_lock;
  733.  
  734.         enum no_fbc_reason no_fbc_reason;
  735.  
  736. //   struct drm_mm_node *compressed_fb;
  737. //   struct drm_mm_node *compressed_llb;
  738.  
  739.         unsigned long last_gpu_reset;
  740.  
  741.         /* list of fbdev register on this device */
  742.     struct intel_fbdev *fbdev;
  743.  
  744. //   struct backlight_device *backlight;
  745.  
  746. //   struct drm_property *broadcast_rgb_property;
  747. //   struct drm_property *force_audio_property;
  748. } drm_i915_private_t;
  749.  
  750. enum i915_cache_level {
  751.         I915_CACHE_NONE,
  752.         I915_CACHE_LLC,
  753.         I915_CACHE_LLC_MLC, /* gen6+ */
  754. };
  755.  
  756. struct drm_i915_gem_object {
  757.     struct drm_gem_object base;
  758.  
  759.     /** Current space allocated to this object in the GTT, if any. */
  760.     struct drm_mm_node *gtt_space;
  761.     struct list_head gtt_list;
  762.  
  763.     /** This object's place on the active/flushing/inactive lists */
  764.     struct list_head ring_list;
  765.     struct list_head mm_list;
  766.     /** This object's place on GPU write list */
  767.     struct list_head gpu_write_list;
  768.     /** This object's place in the batchbuffer or on the eviction list */
  769.     struct list_head exec_list;
  770.  
  771.     /**
  772.      * This is set if the object is on the active or flushing lists
  773.      * (has pending rendering), and is not set if it's on inactive (ready
  774.      * to be unbound).
  775.      */
  776.         unsigned int active:1;
  777.  
  778.     /**
  779.      * This is set if the object has been written to since last bound
  780.      * to the GTT
  781.      */
  782.         unsigned int dirty:1;
  783.  
  784.     /**
  785.      * This is set if the object has been written to since the last
  786.      * GPU flush.
  787.      */
  788.         unsigned int pending_gpu_write:1;
  789.  
  790.     /**
  791.      * Fence register bits (if any) for this object.  Will be set
  792.      * as needed when mapped into the GTT.
  793.      * Protected by dev->struct_mutex.
  794.      */
  795.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  796.  
  797.     /**
  798.      * Advice: are the backing pages purgeable?
  799.      */
  800.         unsigned int madv:2;
  801.  
  802.     /**
  803.      * Current tiling mode for the object.
  804.      */
  805.         unsigned int tiling_mode:2;
  806.         unsigned int tiling_changed:1;
  807.  
  808.     /** How many users have pinned this object in GTT space. The following
  809.      * users can each hold at most one reference: pwrite/pread, pin_ioctl
  810.      * (via user_pin_count), execbuffer (objects are not allowed multiple
  811.      * times for the same batchbuffer), and the framebuffer code. When
  812.      * switching/pageflipping, the framebuffer code has at most two buffers
  813.      * pinned per crtc.
  814.      *
  815.      * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  816.      * bits with absolutely no headroom. So use 4 bits. */
  817.         unsigned int pin_count:4;
  818. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  819.  
  820.     /**
  821.      * Is the object at the current location in the gtt mappable and
  822.      * fenceable? Used to avoid costly recalculations.
  823.      */
  824.         unsigned int map_and_fenceable:1;
  825.  
  826.     /**
  827.      * Whether the current gtt mapping needs to be mappable (and isn't just
  828.      * mappable by accident). Track pin and fault separate for a more
  829.      * accurate mappable working set.
  830.      */
  831.         unsigned int fault_mappable:1;
  832.         unsigned int pin_mappable:1;
  833.  
  834.     /*
  835.      * Is the GPU currently using a fence to access this buffer,
  836.      */
  837.     unsigned int pending_fenced_gpu_access:1;
  838.     unsigned int fenced_gpu_access:1;
  839.  
  840.     unsigned int cache_level:2;
  841.  
  842.     struct page **pages;
  843.  
  844.     /**
  845.      * DMAR support
  846.      */
  847.     struct scatterlist *sg_list;
  848.     int num_sg;
  849.  
  850.     /**
  851.      * Used for performing relocations during execbuffer insertion.
  852.      */
  853.     struct hlist_node exec_node;
  854.     unsigned long exec_handle;
  855.     struct drm_i915_gem_exec_object2 *exec_entry;
  856.  
  857.     /**
  858.      * Current offset of the object in GTT space.
  859.      *
  860.      * This is the same as gtt_space->start
  861.      */
  862.     uint32_t gtt_offset;
  863.  
  864.     /** Breadcrumb of last rendering to the buffer. */
  865.     uint32_t last_rendering_seqno;
  866.     struct intel_ring_buffer *ring;
  867.  
  868.     /** Breadcrumb of last fenced GPU access to the buffer. */
  869.     uint32_t last_fenced_seqno;
  870.     struct intel_ring_buffer *last_fenced_ring;
  871.  
  872.     /** Current tiling stride for the object, if it's tiled. */
  873.     uint32_t stride;
  874.  
  875.     /** Record of address bit 17 of each page at last unbind. */
  876.     unsigned long *bit_17;
  877.  
  878.  
  879.     /**
  880.      * If present, while GEM_DOMAIN_CPU is in the read domain this array
  881.      * flags which individual pages are valid.
  882.      */
  883.     uint8_t *page_cpu_valid;
  884.  
  885.     /** User space pin count and filp owning the pin */
  886.     uint32_t user_pin_count;
  887.     struct drm_file *pin_filp;
  888.  
  889.     /** for phy allocated objects */
  890.     struct drm_i915_gem_phys_object *phys_obj;
  891.  
  892.     /**
  893.      * Number of crtcs where this object is currently the fb, but
  894.      * will be page flipped away on the next vblank.  When it
  895.      * reaches 0, dev_priv->pending_flip_queue will be woken up.
  896.      */
  897.     atomic_t pending_flip;
  898. };
  899.  
  900. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  901.  
  902. /**
  903.  * Request queue structure.
  904.  *
  905.  * The request queue allows us to note sequence numbers that have been emitted
  906.  * and may be associated with active buffers to be retired.
  907.  *
  908.  * By keeping this list, we can avoid having to do questionable
  909.  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  910.  * an emission time with seqnos for tracking how far ahead of the GPU we are.
  911.  */
  912. struct drm_i915_gem_request {
  913.         /** On Which ring this request was generated */
  914.         struct intel_ring_buffer *ring;
  915.  
  916.         /** GEM sequence number associated with this request. */
  917.         uint32_t seqno;
  918.  
  919.         /** Time at which this request was emitted, in jiffies. */
  920.         unsigned long emitted_jiffies;
  921.  
  922.         /** global list entry for this request */
  923.         struct list_head list;
  924.  
  925.         struct drm_i915_file_private *file_priv;
  926.         /** file_priv list entry for this request */
  927.         struct list_head client_list;
  928. };
  929.  
  930. struct drm_i915_file_private {
  931.         struct {
  932.         spinlock_t lock;
  933.                 struct list_head request_list;
  934.         } mm;
  935. };
  936.  
  937. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  938.  
  939. #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
  940. #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
  941. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  942. #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
  943. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  944. #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
  945. #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
  946. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  947. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  948. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  949. #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
  950. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  951. #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
  952. #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
  953. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  954. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  955. #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
  956. #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
  957. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  958. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  959.  
  960. /*
  961.  * The genX designation typically refers to the render engine, so render
  962.  * capability related checks should use IS_GEN, while display and other checks
  963.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  964.  * chips, etc.).
  965.  */
  966. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  967. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  968. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  969. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  970. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  971. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  972.  
  973. #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
  974. #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
  975. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  976.  
  977. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  978. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  979.  
  980. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  981.  * rows, which changed the alignment requirements and fence programming.
  982.  */
  983. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  984.                                                       IS_I915GM(dev)))
  985. #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  986. #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
  987. #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
  988. #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
  989. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  990. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  991. /* dsparb controlled by hw only */
  992. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  993.  
  994. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  995. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  996. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  997.  
  998. #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
  999. #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
  1000.  
  1001. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1002. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1003. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1004.  
  1005. //#include "i915_trace.h"
  1006.  
  1007. extern int i915_max_ioctl;
  1008. extern unsigned int i915_fbpercrtc;
  1009. extern int i915_panel_ignore_lid;
  1010. extern unsigned int i915_powersave;
  1011. extern unsigned int i915_semaphores;
  1012. extern unsigned int i915_lvds_downclock;
  1013. extern unsigned int i915_panel_use_ssc;
  1014. extern int i915_vbt_sdvo_panel_type;
  1015. extern unsigned int i915_enable_rc6;
  1016. extern unsigned int i915_enable_fbc;
  1017. extern bool i915_enable_hangcheck;
  1018.  
  1019. extern int i915_resume(struct drm_device *dev);
  1020. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1021. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1022.  
  1023.                                 /* i915_dma.c */
  1024. extern void i915_kernel_lost_context(struct drm_device * dev);
  1025. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1026. extern int i915_driver_unload(struct drm_device *);
  1027. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1028. extern void i915_driver_lastclose(struct drm_device * dev);
  1029. extern void i915_driver_preclose(struct drm_device *dev,
  1030.                                  struct drm_file *file_priv);
  1031. extern void i915_driver_postclose(struct drm_device *dev,
  1032.                                   struct drm_file *file_priv);
  1033. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1034. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1035.                               unsigned long arg);
  1036. extern int i915_emit_box(struct drm_device *dev,
  1037.                          struct drm_clip_rect *box,
  1038.                          int DR1, int DR4);
  1039. extern int i915_reset(struct drm_device *dev, u8 flags);
  1040. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1041. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1042. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1043. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1044.  
  1045.  
  1046. /* i915_irq.c */
  1047. void i915_hangcheck_elapsed(unsigned long data);
  1048. void i915_handle_error(struct drm_device *dev, bool wedged);
  1049. extern int i915_irq_emit(struct drm_device *dev, void *data,
  1050.                          struct drm_file *file_priv);
  1051. extern int i915_irq_wait(struct drm_device *dev, void *data,
  1052.                          struct drm_file *file_priv);
  1053.  
  1054. extern void intel_irq_init(struct drm_device *dev);
  1055.  
  1056. extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  1057.                                 struct drm_file *file_priv);
  1058. extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  1059.                                 struct drm_file *file_priv);
  1060. extern int i915_vblank_swap(struct drm_device *dev, void *data,
  1061.                             struct drm_file *file_priv);
  1062.  
  1063. void
  1064. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1065.  
  1066. void
  1067. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1068.  
  1069. void intel_enable_asle(struct drm_device *dev);
  1070.  
  1071. #ifdef CONFIG_DEBUG_FS
  1072. extern void i915_destroy_error_state(struct drm_device *dev);
  1073. #else
  1074. #define i915_destroy_error_state(x)
  1075. #endif
  1076.  
  1077.  
  1078. /* i915_mem.c */
  1079. extern int i915_mem_alloc(struct drm_device *dev, void *data,
  1080.                           struct drm_file *file_priv);
  1081. extern int i915_mem_free(struct drm_device *dev, void *data,
  1082.                          struct drm_file *file_priv);
  1083. extern int i915_mem_init_heap(struct drm_device *dev, void *data,
  1084.                               struct drm_file *file_priv);
  1085. extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
  1086.                                  struct drm_file *file_priv);
  1087. extern void i915_mem_takedown(struct mem_block **heap);
  1088. extern void i915_mem_release(struct drm_device * dev,
  1089.                              struct drm_file *file_priv, struct mem_block *heap);
  1090. /* i915_gem.c */
  1091. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1092.                         struct drm_file *file_priv);
  1093. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1094.                           struct drm_file *file_priv);
  1095. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1096.                          struct drm_file *file_priv);
  1097. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1098.                           struct drm_file *file_priv);
  1099. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1100.                         struct drm_file *file_priv);
  1101. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1102.                         struct drm_file *file_priv);
  1103. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1104.                               struct drm_file *file_priv);
  1105. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1106.                              struct drm_file *file_priv);
  1107. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1108.                         struct drm_file *file_priv);
  1109. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1110.                          struct drm_file *file_priv);
  1111. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1112.                        struct drm_file *file_priv);
  1113. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1114.                          struct drm_file *file_priv);
  1115. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1116.                         struct drm_file *file_priv);
  1117. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1118.                             struct drm_file *file_priv);
  1119. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1120.                            struct drm_file *file_priv);
  1121. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1122.                            struct drm_file *file_priv);
  1123. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1124.                            struct drm_file *file_priv);
  1125. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1126.                         struct drm_file *file_priv);
  1127. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1128.                         struct drm_file *file_priv);
  1129. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1130.                                 struct drm_file *file_priv);
  1131. void i915_gem_load(struct drm_device *dev);
  1132. int i915_gem_init_object(struct drm_gem_object *obj);
  1133. int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
  1134.                                      uint32_t invalidate_domains,
  1135.                                      uint32_t flush_domains);
  1136. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1137.                                                   size_t size);
  1138. void i915_gem_free_object(struct drm_gem_object *obj);
  1139. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1140.                                      uint32_t alignment,
  1141.                                      bool map_and_fenceable);
  1142. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1143. int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
  1144. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1145. void i915_gem_lastclose(struct drm_device *dev);
  1146.  
  1147. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1148. int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
  1149. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1150.                                     struct intel_ring_buffer *ring,
  1151.                                     u32 seqno);
  1152.  
  1153. int i915_gem_dumb_create(struct drm_file *file_priv,
  1154.                          struct drm_device *dev,
  1155.                          struct drm_mode_create_dumb *args);
  1156. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1157.                       uint32_t handle, uint64_t *offset);
  1158. int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
  1159.                           uint32_t handle);
  1160. /**
  1161.  * Returns true if seq1 is later than seq2.
  1162.  */
  1163. static inline bool
  1164. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1165. {
  1166.         return (int32_t)(seq1 - seq2) >= 0;
  1167. }
  1168.  
  1169. static inline u32
  1170. i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
  1171. {
  1172.    drm_i915_private_t *dev_priv = ring->dev->dev_private;
  1173.    return ring->outstanding_lazy_request = dev_priv->next_seqno;
  1174. }
  1175.  
  1176. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
  1177.                                            struct intel_ring_buffer *pipelined);
  1178. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1179.  
  1180. void i915_gem_retire_requests(struct drm_device *dev);
  1181. void i915_gem_reset(struct drm_device *dev);
  1182. void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
  1183. int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
  1184.                                             uint32_t read_domains,
  1185.                                             uint32_t write_domain);
  1186. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1187. int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
  1188. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1189. void i915_gem_do_init(struct drm_device *dev,
  1190.                       unsigned long start,
  1191.                       unsigned long mappable_end,
  1192.                       unsigned long end);
  1193. int __must_check i915_gpu_idle(struct drm_device *dev);
  1194. int __must_check i915_gem_idle(struct drm_device *dev);
  1195. int __must_check i915_add_request(struct intel_ring_buffer *ring,
  1196.                                   struct drm_file *file,
  1197.                                   struct drm_i915_gem_request *request);
  1198. int __must_check i915_wait_request(struct intel_ring_buffer *ring,
  1199.                                    uint32_t seqno);
  1200. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1201. int __must_check
  1202. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1203.                                   bool write);
  1204. int __must_check
  1205. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1206.                                      u32 alignment,
  1207.                                      struct intel_ring_buffer *pipelined);
  1208. int i915_gem_attach_phys_object(struct drm_device *dev,
  1209.                                 struct drm_i915_gem_object *obj,
  1210.                                 int id,
  1211.                                 int align);
  1212. void i915_gem_detach_phys_object(struct drm_device *dev,
  1213.                                  struct drm_i915_gem_object *obj);
  1214. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1215. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1216.  
  1217. uint32_t
  1218. i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
  1219.                                     uint32_t size,
  1220.                                     int tiling_mode);
  1221.  
  1222. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1223.                                     enum i915_cache_level cache_level);
  1224.  
  1225. /* i915_gem_gtt.c */
  1226. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1227. int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
  1228. void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
  1229.                                 enum i915_cache_level cache_level);
  1230. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1231.  
  1232. /* i915_gem_evict.c */
  1233. int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
  1234.                                           unsigned alignment, bool mappable);
  1235. int __must_check i915_gem_evict_everything(struct drm_device *dev,
  1236.                                            bool purgeable_only);
  1237. int __must_check i915_gem_evict_inactive(struct drm_device *dev,
  1238.                                          bool purgeable_only);
  1239.  
  1240. /* i915_gem_tiling.c */
  1241. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1242. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1243. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1244.  
  1245. /* i915_gem_debug.c */
  1246. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1247.                           const char *where, uint32_t mark);
  1248. #if WATCH_LISTS
  1249. int i915_verify_lists(struct drm_device *dev);
  1250. #else
  1251. #define i915_verify_lists(dev) 0
  1252. #endif
  1253. void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
  1254.                                      int handle);
  1255. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1256.                           const char *where, uint32_t mark);
  1257.  
  1258. /* i915_debugfs.c */
  1259. int i915_debugfs_init(struct drm_minor *minor);
  1260. void i915_debugfs_cleanup(struct drm_minor *minor);
  1261.  
  1262. /* i915_suspend.c */
  1263. extern int i915_save_state(struct drm_device *dev);
  1264. extern int i915_restore_state(struct drm_device *dev);
  1265.  
  1266. /* i915_suspend.c */
  1267. extern int i915_save_state(struct drm_device *dev);
  1268. extern int i915_restore_state(struct drm_device *dev);
  1269.  
  1270. /* intel_i2c.c */
  1271. extern int intel_setup_gmbus(struct drm_device *dev);
  1272. extern void intel_teardown_gmbus(struct drm_device *dev);
  1273. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1274. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1275. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1276. {
  1277.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1278. }
  1279. extern void intel_i2c_reset(struct drm_device *dev);
  1280.  
  1281. /* intel_opregion.c */
  1282. extern int intel_opregion_setup(struct drm_device *dev);
  1283. #ifdef CONFIG_ACPI
  1284. extern void intel_opregion_init(struct drm_device *dev);
  1285. extern void intel_opregion_fini(struct drm_device *dev);
  1286. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1287. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1288. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1289. #else
  1290. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1291. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1292. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1293. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1294. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1295. #endif
  1296.  
  1297. /* intel_acpi.c */
  1298. #ifdef CONFIG_ACPI
  1299. extern void intel_register_dsm_handler(void);
  1300. extern void intel_unregister_dsm_handler(void);
  1301. #else
  1302. static inline void intel_register_dsm_handler(void) { return; }
  1303. static inline void intel_unregister_dsm_handler(void) { return; }
  1304. #endif /* CONFIG_ACPI */
  1305.  
  1306. /* modesetting */
  1307. extern void intel_modeset_init(struct drm_device *dev);
  1308. extern void intel_modeset_gem_init(struct drm_device *dev);
  1309. extern void intel_modeset_cleanup(struct drm_device *dev);
  1310. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1311. extern bool intel_fbc_enabled(struct drm_device *dev);
  1312. extern void intel_disable_fbc(struct drm_device *dev);
  1313. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1314. extern void ironlake_init_pch_refclk(struct drm_device *dev);
  1315. extern void ironlake_enable_rc6(struct drm_device *dev);
  1316. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  1317. extern void intel_detect_pch(struct drm_device *dev);
  1318. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  1319.  
  1320. extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1321. extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
  1322. extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1323. extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
  1324.  
  1325. /* overlay */
  1326. #ifdef CONFIG_DEBUG_FS
  1327. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1328. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1329.  
  1330. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  1331. extern void intel_display_print_error_state(struct seq_file *m,
  1332.                                             struct drm_device *dev,
  1333.                                             struct intel_display_error_state *error);
  1334. #endif
  1335.  
  1336. #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  1337.  
  1338. #define BEGIN_LP_RING(n) \
  1339.         intel_ring_begin(LP_RING(dev_priv), (n))
  1340.  
  1341. #define OUT_RING(x) \
  1342.         intel_ring_emit(LP_RING(dev_priv), x)
  1343.  
  1344. #define ADVANCE_LP_RING() \
  1345.         intel_ring_advance(LP_RING(dev_priv))
  1346.  
  1347. /**
  1348.  * Lock test for when it's just for synchronization of ring access.
  1349.  *
  1350.  * In that case, we don't need to do it when GEM is initialized as nobody else
  1351.  * has access to the ring.
  1352.  */
  1353. #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  1354.         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  1355.                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  1356. } while (0)
  1357.  
  1358. /* On SNB platform, before reading ring registers forcewake bit
  1359.  * must be set to prevent GT core from power down and stale values being
  1360.  * returned.
  1361.  */
  1362. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1363. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1364. void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
  1365.  
  1366. /* We give fast paths for the really cool registers */
  1367. #define NEEDS_FORCE_WAKE(dev_priv, reg) \
  1368.         (((dev_priv)->info->gen >= 6) && \
  1369.         ((reg) < 0x40000) && \
  1370.         ((reg) != FORCEWAKE))
  1371.  
  1372. #define __i915_read(x, y) \
  1373.         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
  1374.  
  1375. __i915_read(8, b)
  1376. __i915_read(16, w)
  1377. __i915_read(32, l)
  1378. __i915_read(64, q)
  1379. #undef __i915_read
  1380.  
  1381. #define __i915_write(x, y) \
  1382.         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
  1383.  
  1384. __i915_write(8, b)
  1385. __i915_write(16, w)
  1386. __i915_write(32, l)
  1387. __i915_write(64, q)
  1388. #undef __i915_write
  1389.  
  1390. #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
  1391. #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
  1392.  
  1393. #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
  1394. #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
  1395. #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
  1396. #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
  1397.  
  1398. #define I915_READ(reg)          i915_read32(dev_priv, (reg))
  1399. #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
  1400. #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
  1401. #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
  1402.  
  1403. #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
  1404. #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
  1405.  
  1406. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  1407. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  1408.  
  1409. typedef struct
  1410. {
  1411.   int width;
  1412.   int height;
  1413.   int bpp;
  1414.   int freq;
  1415. }videomode_t;
  1416.  
  1417. #endif
  1418.