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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include "i915_reg.h"
  34. #include "intel_bios.h"
  35. #include "intel_ringbuffer.h"
  36. //#include <linux/io-mapping.h>
  37. #include <linux/i2c.h>
  38. #include <linux/i2c-algo-bit.h>
  39. #include <drm/intel-gtt.h>
  40. //#include <linux/backlight.h>
  41.  
  42. #include <linux/spinlock.h>
  43.  
  44.  
  45. /* General customization:
  46.  */
  47.  
  48. #define I915_TILING_NONE          0
  49.  
  50. #define VGA_RSRC_NONE          0x00
  51. #define VGA_RSRC_LEGACY_IO     0x01
  52. #define VGA_RSRC_LEGACY_MEM    0x02
  53. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  54. /* Non-legacy access */
  55. #define VGA_RSRC_NORMAL_IO     0x04
  56. #define VGA_RSRC_NORMAL_MEM    0x08
  57.  
  58. #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  59.  
  60. #define DRIVER_NAME             "i915"
  61. #define DRIVER_DESC             "Intel Graphics"
  62. #define DRIVER_DATE             "20080730"
  63.  
  64. enum pipe {
  65.         PIPE_A = 0,
  66.         PIPE_B,
  67.         PIPE_C,
  68.         I915_MAX_PIPES
  69. };
  70. #define pipe_name(p) ((p) + 'A')
  71.  
  72. enum plane {
  73.         PLANE_A = 0,
  74.         PLANE_B,
  75.         PLANE_C,
  76. };
  77. #define plane_name(p) ((p) + 'A')
  78.  
  79. enum port {
  80.         PORT_A = 0,
  81.         PORT_B,
  82.         PORT_C,
  83.         PORT_D,
  84.         PORT_E,
  85.         I915_MAX_PORTS
  86. };
  87. #define port_name(p) ((p) + 'A')
  88.  
  89. #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  90.  
  91. #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  92.  
  93. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  94.         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  95.                 if ((intel_encoder)->base.crtc == (__crtc))
  96.  
  97. struct intel_pch_pll {
  98.         int refcount; /* count of number of CRTCs sharing this PLL */
  99.         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  100.         bool on; /* is the PLL actually active? Disabled during modeset */
  101.         int pll_reg;
  102.         int fp0_reg;
  103.         int fp1_reg;
  104. };
  105. #define I915_NUM_PLLS 2
  106.  
  107. /* Interface history:
  108.  *
  109.  * 1.1: Original.
  110.  * 1.2: Add Power Management
  111.  * 1.3: Add vblank support
  112.  * 1.4: Fix cmdbuffer path, add heap destroy
  113.  * 1.5: Add vblank pipe configuration
  114.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  115.  *      - Support vertical blank on secondary display pipe
  116.  */
  117. #define DRIVER_MAJOR            1
  118. #define DRIVER_MINOR            6
  119. #define DRIVER_PATCHLEVEL       0
  120.  
  121. #define WATCH_COHERENCY 0
  122. #define WATCH_LISTS     0
  123. #define WATCH_GTT       0
  124.  
  125. #define I915_GEM_PHYS_CURSOR_0 1
  126. #define I915_GEM_PHYS_CURSOR_1 2
  127. #define I915_GEM_PHYS_OVERLAY_REGS 3
  128. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  129.  
  130. struct mem_block {
  131.         struct mem_block *next;
  132.         struct mem_block *prev;
  133.         int start;
  134.         int size;
  135.         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  136. };
  137.  
  138. struct opregion_header;
  139. struct opregion_acpi;
  140. struct opregion_swsci;
  141. struct opregion_asle;
  142. struct drm_i915_private;
  143.  
  144. struct intel_opregion {
  145.         struct opregion_header __iomem *header;
  146.         struct opregion_acpi __iomem *acpi;
  147.         struct opregion_swsci __iomem *swsci;
  148.         struct opregion_asle __iomem *asle;
  149.         void __iomem *vbt;
  150.         u32 __iomem *lid_state;
  151. };
  152. #define OPREGION_SIZE            (8*1024)
  153.  
  154. struct intel_overlay;
  155. struct intel_overlay_error_state;
  156.  
  157. struct drm_i915_master_private {
  158.         drm_local_map_t *sarea;
  159.         struct _drm_i915_sarea *sarea_priv;
  160. };
  161. #define I915_FENCE_REG_NONE -1
  162. #define I915_MAX_NUM_FENCES 16
  163. /* 16 fences + sign bit for FENCE_REG_NONE */
  164. #define I915_MAX_NUM_FENCE_BITS 5
  165.  
  166. struct drm_i915_fence_reg {
  167.         struct list_head lru_list;
  168.         struct drm_i915_gem_object *obj;
  169.         int pin_count;
  170. };
  171.  
  172. struct sdvo_device_mapping {
  173.         u8 initialized;
  174.         u8 dvo_port;
  175.         u8 slave_addr;
  176.         u8 dvo_wiring;
  177.         u8 i2c_pin;
  178.         u8 ddc_pin;
  179. };
  180.  
  181. struct intel_display_error_state;
  182.  
  183. struct drm_i915_error_state {
  184.         u32 eir;
  185.         u32 pgtbl_er;
  186.         u32 ier;
  187.         u32 ccid;
  188.         bool waiting[I915_NUM_RINGS];
  189.         u32 pipestat[I915_MAX_PIPES];
  190.         u32 tail[I915_NUM_RINGS];
  191.         u32 head[I915_NUM_RINGS];
  192.         u32 ipeir[I915_NUM_RINGS];
  193.         u32 ipehr[I915_NUM_RINGS];
  194.         u32 instdone[I915_NUM_RINGS];
  195.         u32 acthd[I915_NUM_RINGS];
  196.         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  197.         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
  198.         /* our own tracking of ring head and tail */
  199.         u32 cpu_ring_head[I915_NUM_RINGS];
  200.         u32 cpu_ring_tail[I915_NUM_RINGS];
  201.         u32 error; /* gen6+ */
  202.         u32 err_int; /* gen7 */
  203.         u32 instpm[I915_NUM_RINGS];
  204.         u32 instps[I915_NUM_RINGS];
  205.         u32 extra_instdone[I915_NUM_INSTDONE_REG];
  206.         u32 seqno[I915_NUM_RINGS];
  207.         u64 bbaddr;
  208.         u32 fault_reg[I915_NUM_RINGS];
  209.         u32 done_reg;
  210.         u32 faddr[I915_NUM_RINGS];
  211.         u64 fence[I915_MAX_NUM_FENCES];
  212.         struct timeval time;
  213.         struct drm_i915_error_ring {
  214.         struct drm_i915_error_object {
  215.                 int page_count;
  216.                 u32 gtt_offset;
  217.                 u32 *pages[0];
  218.                 } *ringbuffer, *batchbuffer;
  219.                 struct drm_i915_error_request {
  220.                         long jiffies;
  221.                         u32 seqno;
  222.                         u32 tail;
  223.                 } *requests;
  224.                 int num_requests;
  225.         } ring[I915_NUM_RINGS];
  226.         struct drm_i915_error_buffer {
  227.                 u32 size;
  228.                 u32 name;
  229.                 u32 rseqno, wseqno;
  230.                 u32 gtt_offset;
  231.                 u32 read_domains;
  232.                 u32 write_domain;
  233.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  234.                 s32 pinned:2;
  235.                 u32 tiling:2;
  236.                 u32 dirty:1;
  237.                 u32 purgeable:1;
  238.                 s32 ring:4;
  239.                 u32 cache_level:2;
  240.         } *active_bo, *pinned_bo;
  241.         u32 active_bo_count, pinned_bo_count;
  242.         struct intel_overlay_error_state *overlay;
  243.         struct intel_display_error_state *display;
  244. };
  245.  
  246. struct drm_i915_display_funcs {
  247.         bool (*fbc_enabled)(struct drm_device *dev);
  248.         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  249.         void (*disable_fbc)(struct drm_device *dev);
  250.         int (*get_display_clock_speed)(struct drm_device *dev);
  251.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  252.         void (*update_wm)(struct drm_device *dev);
  253.         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
  254.                                  uint32_t sprite_width, int pixel_size);
  255.         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
  256.                                  struct drm_display_mode *mode);
  257.         int (*crtc_mode_set)(struct drm_crtc *crtc,
  258.                              struct drm_display_mode *mode,
  259.                              struct drm_display_mode *adjusted_mode,
  260.                              int x, int y,
  261.                              struct drm_framebuffer *old_fb);
  262.         void (*crtc_enable)(struct drm_crtc *crtc);
  263.         void (*crtc_disable)(struct drm_crtc *crtc);
  264.         void (*off)(struct drm_crtc *crtc);
  265.         void (*write_eld)(struct drm_connector *connector,
  266.                           struct drm_crtc *crtc);
  267.         void (*fdi_link_train)(struct drm_crtc *crtc);
  268.         void (*init_clock_gating)(struct drm_device *dev);
  269.         void (*init_pch_clock_gating)(struct drm_device *dev);
  270.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  271.                           struct drm_framebuffer *fb,
  272.                           struct drm_i915_gem_object *obj);
  273.         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  274.                             int x, int y);
  275.         /* clock updates for mode set */
  276.         /* cursor updates */
  277.         /* render clock increase/decrease */
  278.         /* display clock increase/decrease */
  279.         /* pll clock increase/decrease */
  280. };
  281.  
  282. struct drm_i915_gt_funcs {
  283.         void (*force_wake_get)(struct drm_i915_private *dev_priv);
  284.         void (*force_wake_put)(struct drm_i915_private *dev_priv);
  285. };
  286.  
  287. #define DEV_INFO_FLAGS \
  288.         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
  289.         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
  290.         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
  291.         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
  292.         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
  293.         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
  294.         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
  295.         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
  296.         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
  297.         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
  298.         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
  299.         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
  300.         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
  301.         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
  302.         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
  303.         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
  304.         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
  305.         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
  306.         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
  307.         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
  308.         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
  309.         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
  310.         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
  311.         DEV_INFO_FLAG(has_llc)
  312.  
  313. struct intel_device_info {
  314.         u8 gen;
  315.         u8 is_mobile:1;
  316.         u8 is_i85x:1;
  317.         u8 is_i915g:1;
  318.         u8 is_i945gm:1;
  319.         u8 is_g33:1;
  320.         u8 need_gfx_hws:1;
  321.         u8 is_g4x:1;
  322.         u8 is_pineview:1;
  323.         u8 is_broadwater:1;
  324.         u8 is_crestline:1;
  325.         u8 is_ivybridge:1;
  326.         u8 is_valleyview:1;
  327.         u8 has_force_wake:1;
  328.         u8 is_haswell:1;
  329.         u8 has_fbc:1;
  330.         u8 has_pipe_cxsr:1;
  331.         u8 has_hotplug:1;
  332.         u8 cursor_needs_physical:1;
  333.         u8 has_overlay:1;
  334.         u8 overlay_needs_physical:1;
  335.         u8 supports_tv:1;
  336.         u8 has_bsd_ring:1;
  337.         u8 has_blt_ring:1;
  338.         u8 has_llc:1;
  339. };
  340.  
  341. #define I915_PPGTT_PD_ENTRIES 512
  342. #define I915_PPGTT_PT_ENTRIES 1024
  343. struct i915_hw_ppgtt {
  344.         unsigned num_pd_entries;
  345.     dma_addr_t *pt_pages;
  346.         uint32_t pd_offset;
  347.         dma_addr_t *pt_dma_addr;
  348.         dma_addr_t scratch_page_dma_addr;
  349. };
  350.  
  351.  
  352. /* This must match up with the value previously used for execbuf2.rsvd1. */
  353. #define DEFAULT_CONTEXT_ID 0
  354. struct i915_hw_context {
  355.         int id;
  356.         bool is_initialized;
  357.         struct drm_i915_file_private *file_priv;
  358.         struct intel_ring_buffer *ring;
  359.         struct drm_i915_gem_object *obj;
  360. };
  361.  
  362. enum no_fbc_reason {
  363.         FBC_NO_OUTPUT, /* no outputs enabled to compress */
  364.         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  365.         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  366.         FBC_MODE_TOO_LARGE, /* mode too large for compression */
  367.         FBC_BAD_PLANE, /* fbc not supported on plane */
  368.         FBC_NOT_TILED, /* buffer not tiled */
  369.         FBC_MULTIPLE_PIPES, /* more than one pipe active */
  370.         FBC_MODULE_PARAM,
  371. };
  372.  
  373. enum intel_pch {
  374.         PCH_NONE = 0,   /* No PCH present */
  375.         PCH_IBX,        /* Ibexpeak PCH */
  376.         PCH_CPT,        /* Cougarpoint PCH */
  377.         PCH_LPT,        /* Lynxpoint PCH */
  378. };
  379.  
  380. #define QUIRK_PIPEA_FORCE (1<<0)
  381. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  382. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  383.  
  384. struct intel_fbdev;
  385. struct intel_fbc_work;
  386.  
  387. struct intel_gmbus {
  388.         struct i2c_adapter adapter;
  389.         bool force_bit;
  390.         u32 reg0;
  391.         u32 gpio_reg;
  392.         struct i2c_algo_bit_data bit_algo;
  393.         struct drm_i915_private *dev_priv;
  394. };
  395.  
  396. typedef struct drm_i915_private {
  397.         struct drm_device *dev;
  398.  
  399.         const struct intel_device_info *info;
  400.  
  401.         int relative_constants_mode;
  402.  
  403.         void __iomem *regs;
  404.  
  405.         struct drm_i915_gt_funcs gt;
  406.         /** gt_fifo_count and the subsequent register write are synchronized
  407.          * with dev->struct_mutex. */
  408.         unsigned gt_fifo_count;
  409.         /** forcewake_count is protected by gt_lock */
  410.         unsigned forcewake_count;
  411.         /** gt_lock is also taken in irq contexts. */
  412.     spinlock_t gt_lock;
  413.  
  414.         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  415.  
  416.         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  417.          * controller on different i2c buses. */
  418.         struct mutex gmbus_mutex;
  419.  
  420.         /**
  421.          * Base address of the gmbus and gpio block.
  422.          */
  423.         uint32_t gpio_mmio_base;
  424.  
  425.         struct pci_dev *bridge_dev;
  426.     struct intel_ring_buffer ring[I915_NUM_RINGS];
  427.         uint32_t next_seqno;
  428.  
  429.     drm_dma_handle_t *status_page_dmah;
  430.         uint32_t counter;
  431.     struct drm_i915_gem_object *pwrctx;
  432.     struct drm_i915_gem_object *renderctx;
  433.  
  434. //   struct resource mch_res;
  435.  
  436.         atomic_t irq_received;
  437.  
  438.         /* protects the irq masks */
  439.         spinlock_t irq_lock;
  440.  
  441.         /* DPIO indirect register protection */
  442.         spinlock_t dpio_lock;
  443.  
  444.         /** Cached value of IMR to avoid reads in updating the bitfield */
  445.         u32 pipestat[2];
  446.         u32 irq_mask;
  447.         u32 gt_irq_mask;
  448.         u32 pch_irq_mask;
  449.  
  450.         u32 hotplug_supported_mask;
  451.         struct work_struct hotplug_work;
  452.  
  453.         int num_pipe;
  454.         int num_pch_pll;
  455.  
  456.         /* For hangcheck timer */
  457. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  458.     struct timer_list hangcheck_timer;
  459.         int hangcheck_count;
  460.         uint32_t last_acthd[I915_NUM_RINGS];
  461.         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
  462.  
  463.         unsigned int stop_rings;
  464.  
  465.         unsigned long cfb_size;
  466.         unsigned int cfb_fb;
  467.         enum plane cfb_plane;
  468.         int cfb_y;
  469. //   struct intel_fbc_work *fbc_work;
  470.  
  471.     struct intel_opregion opregion;
  472.  
  473.         /* overlay */
  474. //   struct intel_overlay *overlay;
  475.         bool sprite_scaling_enabled;
  476.  
  477.         /* LVDS info */
  478.         int backlight_level;  /* restore backlight to this value */
  479.         bool backlight_enabled;
  480.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  481.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  482.  
  483.         /* Feature bits from the VBIOS */
  484.         unsigned int int_tv_support:1;
  485.         unsigned int lvds_dither:1;
  486.         unsigned int lvds_vbt:1;
  487.         unsigned int int_crt_support:1;
  488.         unsigned int lvds_use_ssc:1;
  489.         unsigned int display_clock_mode:1;
  490.         int lvds_ssc_freq;
  491.         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  492.         unsigned int lvds_val; /* used for checking LVDS channel mode */
  493.         struct {
  494.                 int rate;
  495.                 int lanes;
  496.                 int preemphasis;
  497.                 int vswing;
  498.  
  499.                 bool initialized;
  500.                 bool support;
  501.                 int bpp;
  502.         struct edp_power_seq pps;
  503.         } edp;
  504.         bool no_aux_handshake;
  505.  
  506. //   struct notifier_block lid_notifier;
  507.  
  508.         int crt_ddc_pin;
  509.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  510.         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  511.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  512.  
  513.         unsigned int fsb_freq, mem_freq, is_ddr3;
  514.  
  515.         spinlock_t error_lock;
  516.         /* Protected by dev->error_lock. */
  517.         struct drm_i915_error_state *first_error;
  518.         struct work_struct error_work;
  519.         struct completion error_completion;
  520.     struct workqueue_struct *wq;
  521.  
  522.         /* Display functions */
  523.     struct drm_i915_display_funcs display;
  524.  
  525.         /* PCH chipset type */
  526.         enum intel_pch pch_type;
  527.  
  528.         unsigned long quirks;
  529.  
  530.         /* Register state */
  531.         bool modeset_on_lid;
  532.         u8 saveLBB;
  533.         u32 saveDSPACNTR;
  534.         u32 saveDSPBCNTR;
  535.         u32 saveDSPARB;
  536.         u32 saveHWS;
  537.         u32 savePIPEACONF;
  538.         u32 savePIPEBCONF;
  539.         u32 savePIPEASRC;
  540.         u32 savePIPEBSRC;
  541.         u32 saveFPA0;
  542.         u32 saveFPA1;
  543.         u32 saveDPLL_A;
  544.         u32 saveDPLL_A_MD;
  545.         u32 saveHTOTAL_A;
  546.         u32 saveHBLANK_A;
  547.         u32 saveHSYNC_A;
  548.         u32 saveVTOTAL_A;
  549.         u32 saveVBLANK_A;
  550.         u32 saveVSYNC_A;
  551.         u32 saveBCLRPAT_A;
  552.         u32 saveTRANSACONF;
  553.         u32 saveTRANS_HTOTAL_A;
  554.         u32 saveTRANS_HBLANK_A;
  555.         u32 saveTRANS_HSYNC_A;
  556.         u32 saveTRANS_VTOTAL_A;
  557.         u32 saveTRANS_VBLANK_A;
  558.         u32 saveTRANS_VSYNC_A;
  559.         u32 savePIPEASTAT;
  560.         u32 saveDSPASTRIDE;
  561.         u32 saveDSPASIZE;
  562.         u32 saveDSPAPOS;
  563.         u32 saveDSPAADDR;
  564.         u32 saveDSPASURF;
  565.         u32 saveDSPATILEOFF;
  566.         u32 savePFIT_PGM_RATIOS;
  567.         u32 saveBLC_HIST_CTL;
  568.         u32 saveBLC_PWM_CTL;
  569.         u32 saveBLC_PWM_CTL2;
  570.         u32 saveBLC_CPU_PWM_CTL;
  571.         u32 saveBLC_CPU_PWM_CTL2;
  572.         u32 saveFPB0;
  573.         u32 saveFPB1;
  574.         u32 saveDPLL_B;
  575.         u32 saveDPLL_B_MD;
  576.         u32 saveHTOTAL_B;
  577.         u32 saveHBLANK_B;
  578.         u32 saveHSYNC_B;
  579.         u32 saveVTOTAL_B;
  580.         u32 saveVBLANK_B;
  581.         u32 saveVSYNC_B;
  582.         u32 saveBCLRPAT_B;
  583.         u32 saveTRANSBCONF;
  584.         u32 saveTRANS_HTOTAL_B;
  585.         u32 saveTRANS_HBLANK_B;
  586.         u32 saveTRANS_HSYNC_B;
  587.         u32 saveTRANS_VTOTAL_B;
  588.         u32 saveTRANS_VBLANK_B;
  589.         u32 saveTRANS_VSYNC_B;
  590.         u32 savePIPEBSTAT;
  591.         u32 saveDSPBSTRIDE;
  592.         u32 saveDSPBSIZE;
  593.         u32 saveDSPBPOS;
  594.         u32 saveDSPBADDR;
  595.         u32 saveDSPBSURF;
  596.         u32 saveDSPBTILEOFF;
  597.         u32 saveVGA0;
  598.         u32 saveVGA1;
  599.         u32 saveVGA_PD;
  600.         u32 saveVGACNTRL;
  601.         u32 saveADPA;
  602.         u32 saveLVDS;
  603.         u32 savePP_ON_DELAYS;
  604.         u32 savePP_OFF_DELAYS;
  605.         u32 saveDVOA;
  606.         u32 saveDVOB;
  607.         u32 saveDVOC;
  608.         u32 savePP_ON;
  609.         u32 savePP_OFF;
  610.         u32 savePP_CONTROL;
  611.         u32 savePP_DIVISOR;
  612.         u32 savePFIT_CONTROL;
  613.         u32 save_palette_a[256];
  614.         u32 save_palette_b[256];
  615.         u32 saveDPFC_CB_BASE;
  616.         u32 saveFBC_CFB_BASE;
  617.         u32 saveFBC_LL_BASE;
  618.         u32 saveFBC_CONTROL;
  619.         u32 saveFBC_CONTROL2;
  620.         u32 saveIER;
  621.         u32 saveIIR;
  622.         u32 saveIMR;
  623.         u32 saveDEIER;
  624.         u32 saveDEIMR;
  625.         u32 saveGTIER;
  626.         u32 saveGTIMR;
  627.         u32 saveFDI_RXA_IMR;
  628.         u32 saveFDI_RXB_IMR;
  629.         u32 saveCACHE_MODE_0;
  630.         u32 saveMI_ARB_STATE;
  631.         u32 saveSWF0[16];
  632.         u32 saveSWF1[16];
  633.         u32 saveSWF2[3];
  634.         u8 saveMSR;
  635.         u8 saveSR[8];
  636.         u8 saveGR[25];
  637.         u8 saveAR_INDEX;
  638.         u8 saveAR[21];
  639.         u8 saveDACMASK;
  640.         u8 saveCR[37];
  641.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  642.         u32 saveCURACNTR;
  643.         u32 saveCURAPOS;
  644.         u32 saveCURABASE;
  645.         u32 saveCURBCNTR;
  646.         u32 saveCURBPOS;
  647.         u32 saveCURBBASE;
  648.         u32 saveCURSIZE;
  649.         u32 saveDP_B;
  650.         u32 saveDP_C;
  651.         u32 saveDP_D;
  652.         u32 savePIPEA_GMCH_DATA_M;
  653.         u32 savePIPEB_GMCH_DATA_M;
  654.         u32 savePIPEA_GMCH_DATA_N;
  655.         u32 savePIPEB_GMCH_DATA_N;
  656.         u32 savePIPEA_DP_LINK_M;
  657.         u32 savePIPEB_DP_LINK_M;
  658.         u32 savePIPEA_DP_LINK_N;
  659.         u32 savePIPEB_DP_LINK_N;
  660.         u32 saveFDI_RXA_CTL;
  661.         u32 saveFDI_TXA_CTL;
  662.         u32 saveFDI_RXB_CTL;
  663.         u32 saveFDI_TXB_CTL;
  664.         u32 savePFA_CTL_1;
  665.         u32 savePFB_CTL_1;
  666.         u32 savePFA_WIN_SZ;
  667.         u32 savePFB_WIN_SZ;
  668.         u32 savePFA_WIN_POS;
  669.         u32 savePFB_WIN_POS;
  670.         u32 savePCH_DREF_CONTROL;
  671.         u32 saveDISP_ARB_CTL;
  672.         u32 savePIPEA_DATA_M1;
  673.         u32 savePIPEA_DATA_N1;
  674.         u32 savePIPEA_LINK_M1;
  675.         u32 savePIPEA_LINK_N1;
  676.         u32 savePIPEB_DATA_M1;
  677.         u32 savePIPEB_DATA_N1;
  678.         u32 savePIPEB_LINK_M1;
  679.         u32 savePIPEB_LINK_N1;
  680.         u32 saveMCHBAR_RENDER_STANDBY;
  681.         u32 savePCH_PORT_HOTPLUG;
  682.  
  683.         struct {
  684.                 /** Bridge to intel-gtt-ko */
  685.                 const struct intel_gtt *gtt;
  686.                 /** Memory allocator for GTT stolen memory */
  687.         struct drm_mm stolen;
  688.                 /** Memory allocator for GTT */
  689.         struct drm_mm gtt_space;
  690.                 /** List of all objects in gtt_space. Used to restore gtt
  691.                  * mappings on resume */
  692.                 struct list_head bound_list;
  693.                 /**
  694.                  * List of objects which are not bound to the GTT (thus
  695.                  * are idle and not used by the GPU) but still have
  696.                  * (presumably uncached) pages still attached.
  697.                  */
  698.                 struct list_head unbound_list;
  699.  
  700.                 /** Usable portion of the GTT for GEM */
  701.                 unsigned long gtt_start;
  702.                 unsigned long gtt_mappable_end;
  703.                 unsigned long gtt_end;
  704.  
  705. //       struct io_mapping *gtt_mapping;
  706.                 phys_addr_t gtt_base_addr;
  707.                 int gtt_mtrr;
  708.  
  709.                 /** PPGTT used for aliasing the PPGTT with the GTT */
  710.                 struct i915_hw_ppgtt *aliasing_ppgtt;
  711.  
  712.                 u32 *l3_remap_info;
  713.  
  714. //       struct shrinker inactive_shrinker;
  715.  
  716.                 /**
  717.                  * List of objects currently involved in rendering.
  718.                  *
  719.                  * Includes buffers having the contents of their GPU caches
  720.                  * flushed, not necessarily primitives.  last_rendering_seqno
  721.                  * represents when the rendering involved will be completed.
  722.                  *
  723.                  * A reference is held on the buffer while on this list.
  724.                  */
  725.                 struct list_head active_list;
  726.  
  727.                 /**
  728.                  * LRU list of objects which are not in the ringbuffer and
  729.                  * are ready to unbind, but are still in the GTT.
  730.                  *
  731.                  * last_rendering_seqno is 0 while an object is in this list.
  732.                  *
  733.                  * A reference is not held on the buffer while on this list,
  734.                  * as merely being GTT-bound shouldn't prevent its being
  735.                  * freed, and we'll pull it off the list in the free path.
  736.                  */
  737.                 struct list_head inactive_list;
  738.  
  739.                 /** LRU list of objects with fence regs on them. */
  740.                 struct list_head fence_list;
  741.  
  742.                 /**
  743.                  * We leave the user IRQ off as much as possible,
  744.                  * but this means that requests will finish and never
  745.                  * be retired once the system goes idle. Set a timer to
  746.                  * fire periodically while the ring is running. When it
  747.                  * fires, go retire requests.
  748.                  */
  749.                 struct delayed_work retire_work;
  750.  
  751.                 /**
  752.                  * Are we in a non-interruptible section of code like
  753.                  * modesetting?
  754.                  */
  755.                 bool interruptible;
  756.  
  757.                 /**
  758.                  * Flag if the X Server, and thus DRM, is not currently in
  759.                  * control of the device.
  760.                  *
  761.                  * This is set between LeaveVT and EnterVT.  It needs to be
  762.                  * replaced with a semaphore.  It also needs to be
  763.                  * transitioned away from for kernel modesetting.
  764.                  */
  765.                 int suspended;
  766.  
  767.                 /**
  768.                  * Flag if the hardware appears to be wedged.
  769.                  *
  770.                  * This is set when attempts to idle the device timeout.
  771.                  * It prevents command submission from occurring and makes
  772.                  * every pending request fail
  773.                  */
  774.                 atomic_t wedged;
  775.  
  776.                 /** Bit 6 swizzling required for X tiling */
  777.                 uint32_t bit_6_swizzle_x;
  778.                 /** Bit 6 swizzling required for Y tiling */
  779.                 uint32_t bit_6_swizzle_y;
  780.  
  781.                 /* storage for physical objects */
  782. //       struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  783.  
  784.                 /* accounting, useful for userland debugging */
  785.                 size_t gtt_total;
  786.                 size_t mappable_gtt_total;
  787.                 size_t object_memory;
  788.                 u32 object_count;
  789.         } mm;
  790.  
  791.         /* Old dri1 support infrastructure, beware the dragons ya fools entering
  792.          * here! */
  793.         struct {
  794.                 unsigned allow_batchbuffer : 1;
  795.                 u32 __iomem *gfx_hws_cpu_addr;
  796.  
  797.                 unsigned int cpp;
  798.                 int back_offset;
  799.                 int front_offset;
  800.                 int current_page;
  801.                 int page_flipping;
  802.         } dri1;
  803.  
  804.         /* Kernel Modesetting */
  805.  
  806.     struct sdvo_device_mapping sdvo_mappings[2];
  807.         /* indicate whether the LVDS_BORDER should be enabled or not */
  808.         unsigned int lvds_border_bits;
  809.         /* Panel fitter placement and size for Ironlake+ */
  810.         u32 pch_pf_pos, pch_pf_size;
  811.  
  812.     struct drm_crtc *plane_to_crtc_mapping[3];
  813.     struct drm_crtc *pipe_to_crtc_mapping[3];
  814.         wait_queue_head_t pending_flip_queue;
  815.  
  816.         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
  817.  
  818.         /* Reclocking support */
  819.         bool render_reclock_avail;
  820.         bool lvds_downclock_avail;
  821.         /* indicates the reduced downclock for LVDS*/
  822.         int lvds_downclock;
  823.         u16 orig_clock;
  824.         int child_dev_num;
  825.     struct child_device_config *child_dev;
  826.     struct drm_connector *int_lvds_connector;
  827.     struct drm_connector *int_edp_connector;
  828.  
  829.         bool mchbar_need_disable;
  830.  
  831.         /* gen6+ rps state */
  832.         struct {
  833.                 struct work_struct work;
  834.         u32 pm_iir;
  835.                 /* lock - irqsave spinlock that protectects the work_struct and
  836.                  * pm_iir. */
  837.                 spinlock_t lock;
  838.  
  839.                 /* The below variables an all the rps hw state are protected by
  840.                  * dev->struct mutext. */
  841.                 u8 cur_delay;
  842.                 u8 min_delay;
  843.                 u8 max_delay;
  844.         } rps;
  845.  
  846.         /* ilk-only ips/rps state. Everything in here is protected by the global
  847.          * mchdev_lock in intel_pm.c */
  848.         struct {
  849.         u8 cur_delay;
  850.         u8 min_delay;
  851.         u8 max_delay;
  852.         u8 fmax;
  853.         u8 fstart;
  854.  
  855.         u64 last_count1;
  856.         unsigned long last_time1;
  857.         unsigned long chipset_power;
  858.         u64 last_count2;
  859.     struct timespec last_time2;
  860.         unsigned long gfx_power;
  861.                 u8 corr;
  862.  
  863.         int c_m;
  864.         int r_t;
  865.         } ips;
  866.  
  867.         enum no_fbc_reason no_fbc_reason;
  868.  
  869.         struct drm_mm_node *compressed_fb;
  870.         struct drm_mm_node *compressed_llb;
  871.  
  872.         unsigned long last_gpu_reset;
  873.  
  874.         /* list of fbdev register on this device */
  875.     struct intel_fbdev *fbdev;
  876.  
  877. //   struct backlight_device *backlight;
  878.  
  879.         struct drm_property *broadcast_rgb_property;
  880.         struct drm_property *force_audio_property;
  881.  
  882.         bool hw_contexts_disabled;
  883.         uint32_t hw_context_size;
  884. } drm_i915_private_t;
  885.  
  886. /* Iterate over initialised rings */
  887. #define for_each_ring(ring__, dev_priv__, i__) \
  888.         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  889.                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  890.  
  891. enum hdmi_force_audio {
  892.         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
  893.         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
  894.         HDMI_AUDIO_AUTO,                /* trust EDID */
  895.         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
  896. };
  897.  
  898. enum i915_cache_level {
  899.         I915_CACHE_NONE = 0,
  900.         I915_CACHE_LLC,
  901.         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
  902. };
  903.  
  904. struct drm_i915_gem_object_ops {
  905.         /* Interface between the GEM object and its backing storage.
  906.          * get_pages() is called once prior to the use of the associated set
  907.          * of pages before to binding them into the GTT, and put_pages() is
  908.          * called after we no longer need them. As we expect there to be
  909.          * associated cost with migrating pages between the backing storage
  910.          * and making them available for the GPU (e.g. clflush), we may hold
  911.          * onto the pages after they are no longer referenced by the GPU
  912.          * in case they may be used again shortly (for example migrating the
  913.          * pages to a different memory domain within the GTT). put_pages()
  914.          * will therefore most likely be called when the object itself is
  915.          * being released or under memory pressure (where we attempt to
  916.          * reap pages for the shrinker).
  917.          */
  918.         int (*get_pages)(struct drm_i915_gem_object *);
  919.         void (*put_pages)(struct drm_i915_gem_object *);
  920. };
  921.  
  922. struct drm_i915_gem_object {
  923.     struct drm_gem_object base;
  924.  
  925.         const struct drm_i915_gem_object_ops *ops;
  926.  
  927.     void  *mapped;
  928.  
  929.     /** Current space allocated to this object in the GTT, if any. */
  930.     struct drm_mm_node *gtt_space;
  931.     struct list_head gtt_list;
  932.  
  933.         /** This object's place on the active/inactive lists */
  934.     struct list_head ring_list;
  935.     struct list_head mm_list;
  936.     /** This object's place in the batchbuffer or on the eviction list */
  937.     struct list_head exec_list;
  938.  
  939.     /**
  940.          * This is set if the object is on the active lists (has pending
  941.          * rendering and so a non-zero seqno), and is not set if it i s on
  942.          * inactive (ready to be unbound) list.
  943.      */
  944.         unsigned int active:1;
  945.  
  946.     /**
  947.      * This is set if the object has been written to since last bound
  948.      * to the GTT
  949.      */
  950.         unsigned int dirty:1;
  951.  
  952.     /**
  953.      * Fence register bits (if any) for this object.  Will be set
  954.      * as needed when mapped into the GTT.
  955.      * Protected by dev->struct_mutex.
  956.      */
  957.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  958.  
  959.     /**
  960.      * Advice: are the backing pages purgeable?
  961.      */
  962.         unsigned int madv:2;
  963.  
  964.     /**
  965.      * Current tiling mode for the object.
  966.      */
  967.         unsigned int tiling_mode:2;
  968.         /**
  969.          * Whether the tiling parameters for the currently associated fence
  970.          * register have changed. Note that for the purposes of tracking
  971.          * tiling changes we also treat the unfenced register, the register
  972.          * slot that the object occupies whilst it executes a fenced
  973.          * command (such as BLT on gen2/3), as a "fence".
  974.          */
  975.         unsigned int fence_dirty:1;
  976.  
  977.     /** How many users have pinned this object in GTT space. The following
  978.      * users can each hold at most one reference: pwrite/pread, pin_ioctl
  979.      * (via user_pin_count), execbuffer (objects are not allowed multiple
  980.      * times for the same batchbuffer), and the framebuffer code. When
  981.      * switching/pageflipping, the framebuffer code has at most two buffers
  982.      * pinned per crtc.
  983.      *
  984.      * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  985.      * bits with absolutely no headroom. So use 4 bits. */
  986.         unsigned int pin_count:4;
  987. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  988.  
  989.     /**
  990.      * Is the object at the current location in the gtt mappable and
  991.      * fenceable? Used to avoid costly recalculations.
  992.      */
  993.         unsigned int map_and_fenceable:1;
  994.  
  995.     /**
  996.      * Whether the current gtt mapping needs to be mappable (and isn't just
  997.      * mappable by accident). Track pin and fault separate for a more
  998.      * accurate mappable working set.
  999.      */
  1000.         unsigned int fault_mappable:1;
  1001.         unsigned int pin_mappable:1;
  1002.  
  1003.     /*
  1004.      * Is the GPU currently using a fence to access this buffer,
  1005.      */
  1006.     unsigned int pending_fenced_gpu_access:1;
  1007.     unsigned int fenced_gpu_access:1;
  1008.  
  1009.     unsigned int cache_level:2;
  1010.  
  1011.         unsigned int has_aliasing_ppgtt_mapping:1;
  1012.         unsigned int has_global_gtt_mapping:1;
  1013.         unsigned int has_dma_mapping:1;
  1014.  
  1015.     dma_addr_t *allocated_pages;
  1016.     struct pagelist pages;
  1017.         int pages_pin_count;
  1018.  
  1019.         /* prime dma-buf support */
  1020.         void *dma_buf_vmapping;
  1021.         int vmapping_count;
  1022.  
  1023.     /**
  1024.      * Used for performing relocations during execbuffer insertion.
  1025.      */
  1026.     struct hlist_node exec_node;
  1027.     unsigned long exec_handle;
  1028.     struct drm_i915_gem_exec_object2 *exec_entry;
  1029.  
  1030.     /**
  1031.      * Current offset of the object in GTT space.
  1032.      *
  1033.      * This is the same as gtt_space->start
  1034.      */
  1035.     uint32_t gtt_offset;
  1036.  
  1037.         struct intel_ring_buffer *ring;
  1038.  
  1039.     /** Breadcrumb of last rendering to the buffer. */
  1040.         uint32_t last_read_seqno;
  1041.         uint32_t last_write_seqno;
  1042.     /** Breadcrumb of last fenced GPU access to the buffer. */
  1043.     uint32_t last_fenced_seqno;
  1044.  
  1045.     /** Current tiling stride for the object, if it's tiled. */
  1046.     uint32_t stride;
  1047.  
  1048.     /** Record of address bit 17 of each page at last unbind. */
  1049.     unsigned long *bit_17;
  1050.  
  1051.     /** User space pin count and filp owning the pin */
  1052.     uint32_t user_pin_count;
  1053.     struct drm_file *pin_filp;
  1054.  
  1055.     /** for phy allocated objects */
  1056.     struct drm_i915_gem_phys_object *phys_obj;
  1057.  
  1058.     /**
  1059.      * Number of crtcs where this object is currently the fb, but
  1060.      * will be page flipped away on the next vblank.  When it
  1061.      * reaches 0, dev_priv->pending_flip_queue will be woken up.
  1062.      */
  1063.     atomic_t pending_flip;
  1064. };
  1065.  
  1066. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  1067.  
  1068. /**
  1069.  * Request queue structure.
  1070.  *
  1071.  * The request queue allows us to note sequence numbers that have been emitted
  1072.  * and may be associated with active buffers to be retired.
  1073.  *
  1074.  * By keeping this list, we can avoid having to do questionable
  1075.  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  1076.  * an emission time with seqnos for tracking how far ahead of the GPU we are.
  1077.  */
  1078. struct drm_i915_gem_request {
  1079.         /** On Which ring this request was generated */
  1080.         struct intel_ring_buffer *ring;
  1081.  
  1082.         /** GEM sequence number associated with this request. */
  1083.         uint32_t seqno;
  1084.  
  1085.         /** Postion in the ringbuffer of the end of the request */
  1086.         u32 tail;
  1087.  
  1088.         /** Time at which this request was emitted, in jiffies. */
  1089.         unsigned long emitted_jiffies;
  1090.  
  1091.         /** global list entry for this request */
  1092.         struct list_head list;
  1093.  
  1094.         struct drm_i915_file_private *file_priv;
  1095.         /** file_priv list entry for this request */
  1096.         struct list_head client_list;
  1097. };
  1098.  
  1099. struct drm_i915_file_private {
  1100.         struct {
  1101.         spinlock_t lock;
  1102.                 struct list_head request_list;
  1103.         } mm;
  1104.         struct idr context_idr;
  1105. };
  1106.  
  1107. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  1108.  
  1109. #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
  1110. #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
  1111. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  1112. #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
  1113. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  1114. #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
  1115. #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
  1116. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  1117. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  1118. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  1119. #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
  1120. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  1121. #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
  1122. #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
  1123. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  1124. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  1125. #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
  1126. #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
  1127. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  1128. #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
  1129. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  1130. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  1131.  
  1132. /*
  1133.  * The genX designation typically refers to the render engine, so render
  1134.  * capability related checks should use IS_GEN, while display and other checks
  1135.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  1136.  * chips, etc.).
  1137.  */
  1138. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  1139. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  1140. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  1141. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  1142. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  1143. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  1144.  
  1145. #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
  1146. #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
  1147. #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
  1148. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  1149.  
  1150. #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
  1151. #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
  1152.  
  1153. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  1154. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  1155.  
  1156. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1157.  * rows, which changed the alignment requirements and fence programming.
  1158.  */
  1159. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1160.                                                       IS_I915GM(dev)))
  1161. #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1162. #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
  1163. #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
  1164. #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
  1165. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  1166. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  1167. /* dsparb controlled by hw only */
  1168. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1169.  
  1170. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1171. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1172. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1173.  
  1174. #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
  1175.  
  1176. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1177. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  1178. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1179. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1180. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  1181.  
  1182. #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
  1183.  
  1184. #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  1185.  
  1186. #define GT_FREQUENCY_MULTIPLIER 50
  1187.  
  1188. #include "i915_trace.h"
  1189.  
  1190. /**
  1191.  * RC6 is a special power stage which allows the GPU to enter an very
  1192.  * low-voltage mode when idle, using down to 0V while at this stage.  This
  1193.  * stage is entered automatically when the GPU is idle when RC6 support is
  1194.  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  1195.  *
  1196.  * There are different RC6 modes available in Intel GPU, which differentiate
  1197.  * among each other with the latency required to enter and leave RC6 and
  1198.  * voltage consumed by the GPU in different states.
  1199.  *
  1200.  * The combination of the following flags define which states GPU is allowed
  1201.  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  1202.  * RC6pp is deepest RC6. Their support by hardware varies according to the
  1203.  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  1204.  * which brings the most power savings; deeper states save more power, but
  1205.  * require higher latency to switch to and wake up.
  1206.  */
  1207. #define INTEL_RC6_ENABLE                        (1<<0)
  1208. #define INTEL_RC6p_ENABLE                       (1<<1)
  1209. #define INTEL_RC6pp_ENABLE                      (1<<2)
  1210.  
  1211. extern unsigned int i915_fbpercrtc      __always_unused;
  1212. extern int i915_panel_ignore_lid        __read_mostly;
  1213. extern unsigned int i915_powersave      __read_mostly;
  1214. extern int i915_semaphores              __read_mostly;
  1215. extern unsigned int i915_lvds_downclock __read_mostly;
  1216. extern int i915_lvds_channel_mode       __read_mostly;
  1217. extern int i915_panel_use_ssc           __read_mostly;
  1218. extern int i915_vbt_sdvo_panel_type     __read_mostly;
  1219. extern int i915_enable_rc6              __read_mostly;
  1220. extern int i915_enable_fbc              __read_mostly;
  1221. extern bool i915_enable_hangcheck       __read_mostly;
  1222. extern int i915_enable_ppgtt            __read_mostly;
  1223. extern unsigned int i915_preliminary_hw_support __read_mostly;
  1224.  
  1225. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1226. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1227.  
  1228.                                 /* i915_dma.c */
  1229. void i915_update_dri1_breadcrumb(struct drm_device *dev);
  1230. extern void i915_kernel_lost_context(struct drm_device * dev);
  1231. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1232. extern int i915_driver_unload(struct drm_device *);
  1233. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1234. extern void i915_driver_lastclose(struct drm_device * dev);
  1235. extern void i915_driver_preclose(struct drm_device *dev,
  1236.                                  struct drm_file *file_priv);
  1237. extern void i915_driver_postclose(struct drm_device *dev,
  1238.                                   struct drm_file *file_priv);
  1239. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1240. #ifdef CONFIG_COMPAT
  1241. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1242.                               unsigned long arg);
  1243. #endif
  1244. extern int i915_emit_box(struct drm_device *dev,
  1245.                          struct drm_clip_rect *box,
  1246.                          int DR1, int DR4);
  1247. extern int intel_gpu_reset(struct drm_device *dev);
  1248. extern int i915_reset(struct drm_device *dev);
  1249. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1250. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1251. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1252. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1253.  
  1254.  
  1255. /* i915_irq.c */
  1256. void i915_hangcheck_elapsed(unsigned long data);
  1257. void i915_handle_error(struct drm_device *dev, bool wedged);
  1258.  
  1259. extern void intel_irq_init(struct drm_device *dev);
  1260. extern void intel_gt_init(struct drm_device *dev);
  1261.  
  1262. void i915_error_state_free(struct kref *error_ref);
  1263.  
  1264. void
  1265. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1266.  
  1267. void
  1268. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1269.  
  1270. void intel_enable_asle(struct drm_device *dev);
  1271.  
  1272. #ifdef CONFIG_DEBUG_FS
  1273. extern void i915_destroy_error_state(struct drm_device *dev);
  1274. #else
  1275. #define i915_destroy_error_state(x)
  1276. #endif
  1277.  
  1278.  
  1279. /* i915_gem.c */
  1280. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1281.                         struct drm_file *file_priv);
  1282. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1283.                           struct drm_file *file_priv);
  1284. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1285.                          struct drm_file *file_priv);
  1286. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1287.                           struct drm_file *file_priv);
  1288. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1289.                         struct drm_file *file_priv);
  1290. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1291.                         struct drm_file *file_priv);
  1292. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1293.                               struct drm_file *file_priv);
  1294. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1295.                              struct drm_file *file_priv);
  1296. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1297.                         struct drm_file *file_priv);
  1298. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1299.                          struct drm_file *file_priv);
  1300. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1301.                        struct drm_file *file_priv);
  1302. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1303.                          struct drm_file *file_priv);
  1304. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1305.                         struct drm_file *file_priv);
  1306. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  1307.                                struct drm_file *file);
  1308. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  1309.                                struct drm_file *file);
  1310. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1311.                             struct drm_file *file_priv);
  1312. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1313.                            struct drm_file *file_priv);
  1314. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1315.                            struct drm_file *file_priv);
  1316. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1317.                            struct drm_file *file_priv);
  1318. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1319.                         struct drm_file *file_priv);
  1320. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1321.                         struct drm_file *file_priv);
  1322. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1323.                                 struct drm_file *file_priv);
  1324. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  1325.                         struct drm_file *file_priv);
  1326. void i915_gem_load(struct drm_device *dev);
  1327. int i915_gem_init_object(struct drm_gem_object *obj);
  1328. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  1329.                          const struct drm_i915_gem_object_ops *ops);
  1330. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1331.                                                   size_t size);
  1332. void i915_gem_free_object(struct drm_gem_object *obj);
  1333. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1334.                                      uint32_t alignment,
  1335.                                      bool map_and_fenceable,
  1336.                                      bool nonblocking);
  1337. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1338. int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
  1339. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1340. void i915_gem_lastclose(struct drm_device *dev);
  1341.  
  1342. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  1343.  
  1344. static inline dma_addr_t i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  1345. {
  1346.     return obj->pages.page[n];
  1347. };
  1348.  
  1349. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  1350. {
  1351.     BUG_ON(obj->pages.page == NULL);
  1352.         obj->pages_pin_count++;
  1353. }
  1354. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  1355. {
  1356.         BUG_ON(obj->pages_pin_count == 0);
  1357.         obj->pages_pin_count--;
  1358. }
  1359.  
  1360. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1361. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  1362.                          struct intel_ring_buffer *to);
  1363. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1364.                                     struct intel_ring_buffer *ring,
  1365.                                     u32 seqno);
  1366.  
  1367. int i915_gem_dumb_create(struct drm_file *file_priv,
  1368.                          struct drm_device *dev,
  1369.                          struct drm_mode_create_dumb *args);
  1370. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1371.                       uint32_t handle, uint64_t *offset);
  1372. int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
  1373.                           uint32_t handle);
  1374. /**
  1375.  * Returns true if seq1 is later than seq2.
  1376.  */
  1377. static inline bool
  1378. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1379. {
  1380.         return (int32_t)(seq1 - seq2) >= 0;
  1381. }
  1382.  
  1383. u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
  1384.  
  1385. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  1386. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1387.  
  1388. static inline bool
  1389. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  1390. {
  1391.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1392.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1393.                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
  1394.                 return true;
  1395.         } else
  1396.                 return false;
  1397. }
  1398.  
  1399. static inline void
  1400. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  1401. {
  1402.         if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1403.                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1404.                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
  1405.         }
  1406. }
  1407.  
  1408. void i915_gem_retire_requests(struct drm_device *dev);
  1409. void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
  1410. int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
  1411.                                       bool interruptible);
  1412.  
  1413. void i915_gem_reset(struct drm_device *dev);
  1414. void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
  1415. int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
  1416.                                             uint32_t read_domains,
  1417.                                             uint32_t write_domain);
  1418. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1419. int __must_check i915_gem_init(struct drm_device *dev);
  1420. int __must_check i915_gem_init_hw(struct drm_device *dev);
  1421. void i915_gem_l3_remap(struct drm_device *dev);
  1422. void i915_gem_init_swizzling(struct drm_device *dev);
  1423. void i915_gem_init_ppgtt(struct drm_device *dev);
  1424. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1425. int __must_check i915_gpu_idle(struct drm_device *dev);
  1426. int __must_check i915_gem_idle(struct drm_device *dev);
  1427. int i915_add_request(struct intel_ring_buffer *ring,
  1428.                                   struct drm_file *file,
  1429.                      u32 *seqno);
  1430. int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
  1431.                                    uint32_t seqno);
  1432. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1433. int __must_check
  1434. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1435.                                   bool write);
  1436. int __must_check
  1437. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  1438. int __must_check
  1439. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1440.                                      u32 alignment,
  1441.                                      struct intel_ring_buffer *pipelined);
  1442. int i915_gem_attach_phys_object(struct drm_device *dev,
  1443.                                 struct drm_i915_gem_object *obj,
  1444.                                 int id,
  1445.                                 int align);
  1446. void i915_gem_detach_phys_object(struct drm_device *dev,
  1447.                                  struct drm_i915_gem_object *obj);
  1448. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1449. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1450.  
  1451. uint32_t
  1452. i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
  1453.                                     uint32_t size,
  1454.                                     int tiling_mode);
  1455.  
  1456. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1457.                                     enum i915_cache_level cache_level);
  1458.  
  1459.  
  1460. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  1461.                                 struct drm_gem_object *gem_obj, int flags);
  1462.  
  1463. /* i915_gem_context.c */
  1464. void i915_gem_context_init(struct drm_device *dev);
  1465. void i915_gem_context_fini(struct drm_device *dev);
  1466. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  1467. int i915_switch_context(struct intel_ring_buffer *ring,
  1468.                         struct drm_file *file, int to_id);
  1469. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  1470.                                   struct drm_file *file);
  1471. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  1472.                                    struct drm_file *file);
  1473.  
  1474. /* i915_gem_gtt.c */
  1475. int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
  1476. void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
  1477. void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
  1478.                             struct drm_i915_gem_object *obj,
  1479.                             enum i915_cache_level cache_level);
  1480. void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  1481.                               struct drm_i915_gem_object *obj);
  1482.  
  1483. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1484. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  1485. void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
  1486.                                 enum i915_cache_level cache_level);
  1487. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1488. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  1489. void i915_gem_init_global_gtt(struct drm_device *dev,
  1490.                               unsigned long start,
  1491.                               unsigned long mappable_end,
  1492.                               unsigned long end);
  1493.  
  1494. /* i915_gem_evict.c */
  1495. int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
  1496.                                           unsigned alignment,
  1497.                                           unsigned cache_level,
  1498.                                           bool mappable,
  1499.                                           bool nonblock);
  1500. int i915_gem_evict_everything(struct drm_device *dev);
  1501.  
  1502. /* i915_gem_stolen.c */
  1503. int i915_gem_init_stolen(struct drm_device *dev);
  1504. void i915_gem_cleanup_stolen(struct drm_device *dev);
  1505.  
  1506. /* i915_gem_tiling.c */
  1507. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1508. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1509. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1510.  
  1511. /* i915_gem_debug.c */
  1512. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1513.                           const char *where, uint32_t mark);
  1514. #if WATCH_LISTS
  1515. int i915_verify_lists(struct drm_device *dev);
  1516. #else
  1517. #define i915_verify_lists(dev) 0
  1518. #endif
  1519. void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
  1520.                                      int handle);
  1521. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1522.                           const char *where, uint32_t mark);
  1523.  
  1524. /* i915_debugfs.c */
  1525. int i915_debugfs_init(struct drm_minor *minor);
  1526. void i915_debugfs_cleanup(struct drm_minor *minor);
  1527.  
  1528. /* i915_suspend.c */
  1529. extern int i915_save_state(struct drm_device *dev);
  1530. extern int i915_restore_state(struct drm_device *dev);
  1531.  
  1532. /* i915_suspend.c */
  1533. extern int i915_save_state(struct drm_device *dev);
  1534. extern int i915_restore_state(struct drm_device *dev);
  1535.  
  1536. /* i915_sysfs.c */
  1537. void i915_setup_sysfs(struct drm_device *dev_priv);
  1538. void i915_teardown_sysfs(struct drm_device *dev_priv);
  1539.  
  1540. /* intel_i2c.c */
  1541. extern int intel_setup_gmbus(struct drm_device *dev);
  1542. extern void intel_teardown_gmbus(struct drm_device *dev);
  1543. extern inline bool intel_gmbus_is_port_valid(unsigned port)
  1544. {
  1545.         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  1546. }
  1547.  
  1548. extern struct i2c_adapter *intel_gmbus_get_adapter(
  1549.                 struct drm_i915_private *dev_priv, unsigned port);
  1550. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1551. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1552. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1553. {
  1554.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1555. }
  1556. extern void intel_i2c_reset(struct drm_device *dev);
  1557.  
  1558. /* intel_opregion.c */
  1559. extern int intel_opregion_setup(struct drm_device *dev);
  1560. #ifdef CONFIG_ACPI
  1561. extern void intel_opregion_init(struct drm_device *dev);
  1562. extern void intel_opregion_fini(struct drm_device *dev);
  1563. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1564. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1565. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1566. #else
  1567. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1568. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1569. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1570. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1571. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1572. #endif
  1573.  
  1574. /* intel_acpi.c */
  1575. #ifdef CONFIG_ACPI
  1576. extern void intel_register_dsm_handler(void);
  1577. extern void intel_unregister_dsm_handler(void);
  1578. #else
  1579. static inline void intel_register_dsm_handler(void) { return; }
  1580. static inline void intel_unregister_dsm_handler(void) { return; }
  1581. #endif /* CONFIG_ACPI */
  1582.  
  1583. /* modesetting */
  1584. extern void intel_modeset_init_hw(struct drm_device *dev);
  1585. extern void intel_modeset_init(struct drm_device *dev);
  1586. extern void intel_modeset_gem_init(struct drm_device *dev);
  1587. extern void intel_modeset_cleanup(struct drm_device *dev);
  1588. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1589. extern void intel_modeset_setup_hw_state(struct drm_device *dev);
  1590. extern bool intel_fbc_enabled(struct drm_device *dev);
  1591. extern void intel_disable_fbc(struct drm_device *dev);
  1592. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1593. extern void ironlake_init_pch_refclk(struct drm_device *dev);
  1594. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  1595. extern void intel_detect_pch(struct drm_device *dev);
  1596. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  1597. extern int intel_enable_rc6(const struct drm_device *dev);
  1598.  
  1599. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  1600. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  1601.                         struct drm_file *file);
  1602.  
  1603. /* overlay */
  1604. #ifdef CONFIG_DEBUG_FS
  1605. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1606. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1607.  
  1608. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  1609. extern void intel_display_print_error_state(struct seq_file *m,
  1610.                                             struct drm_device *dev,
  1611.                                             struct intel_display_error_state *error);
  1612. #endif
  1613.  
  1614. /* On SNB platform, before reading ring registers forcewake bit
  1615.  * must be set to prevent GT core from power down and stale values being
  1616.  * returned.
  1617.  */
  1618. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1619. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1620. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
  1621.  
  1622. #define __i915_read(x, y) \
  1623.         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
  1624.  
  1625. __i915_read(8, b)
  1626. __i915_read(16, w)
  1627. __i915_read(32, l)
  1628. __i915_read(64, q)
  1629. #undef __i915_read
  1630.  
  1631. #define __i915_write(x, y) \
  1632.         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
  1633.  
  1634. __i915_write(8, b)
  1635. __i915_write(16, w)
  1636. __i915_write(32, l)
  1637. __i915_write(64, q)
  1638. #undef __i915_write
  1639.  
  1640. #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
  1641. #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
  1642.  
  1643. #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
  1644. #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
  1645. #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
  1646. #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
  1647.  
  1648. #define I915_READ(reg)          i915_read32(dev_priv, (reg))
  1649. #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
  1650. #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
  1651. #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
  1652.  
  1653. #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
  1654. #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
  1655.  
  1656. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  1657. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  1658.  
  1659. typedef struct
  1660. {
  1661.   int width;
  1662.   int height;
  1663.   int bpp;
  1664.   int freq;
  1665. }videomode_t;
  1666.  
  1667.  
  1668. static inline int mutex_trylock(struct mutex *lock)
  1669. {
  1670.     if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1))
  1671.         return 1;
  1672.     return 0;
  1673. }
  1674.  
  1675.  
  1676. #define ioread32(addr)          readl(addr)
  1677.  
  1678.  
  1679.  
  1680.  
  1681.  
  1682. #endif
  1683.