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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. #ifndef _I915_DRV_H_
  31. #define _I915_DRV_H_
  32.  
  33. #include "i915_reg.h"
  34. #include "intel_bios.h"
  35. #include "intel_ringbuffer.h"
  36. //#include <linux/io-mapping.h>
  37. #include <linux/i2c.h>
  38. #include <drm/intel-gtt.h>
  39. //#include <linux/backlight.h>
  40.  
  41. #include <linux/spinlock.h>
  42.  
  43.  
  44. /* General customization:
  45.  */
  46.  
  47. #define I915_TILING_NONE    0
  48.  
  49.  
  50. #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  51.  
  52. #define DRIVER_NAME             "i915"
  53. #define DRIVER_DESC             "Intel Graphics"
  54. #define DRIVER_DATE             "20080730"
  55.  
  56. enum pipe {
  57.         PIPE_A = 0,
  58.         PIPE_B,
  59.         PIPE_C,
  60.         I915_MAX_PIPES
  61. };
  62. #define pipe_name(p) ((p) + 'A')
  63.  
  64. enum plane {
  65.         PLANE_A = 0,
  66.         PLANE_B,
  67.         PLANE_C,
  68. };
  69. #define plane_name(p) ((p) + 'A')
  70.  
  71. #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  72.  
  73. #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  74.  
  75. /* Interface history:
  76.  *
  77.  * 1.1: Original.
  78.  * 1.2: Add Power Management
  79.  * 1.3: Add vblank support
  80.  * 1.4: Fix cmdbuffer path, add heap destroy
  81.  * 1.5: Add vblank pipe configuration
  82.  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  83.  *      - Support vertical blank on secondary display pipe
  84.  */
  85. #define DRIVER_MAJOR            1
  86. #define DRIVER_MINOR            6
  87. #define DRIVER_PATCHLEVEL       0
  88.  
  89. #define WATCH_COHERENCY 0
  90. #define WATCH_LISTS     0
  91.  
  92. #define I915_GEM_PHYS_CURSOR_0 1
  93. #define I915_GEM_PHYS_CURSOR_1 2
  94. #define I915_GEM_PHYS_OVERLAY_REGS 3
  95. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  96.  
  97. struct mem_block {
  98.         struct mem_block *next;
  99.         struct mem_block *prev;
  100.         int start;
  101.         int size;
  102.         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  103. };
  104.  
  105. struct opregion_header;
  106. struct opregion_acpi;
  107. struct opregion_swsci;
  108. struct opregion_asle;
  109. struct drm_i915_private;
  110.  
  111. struct intel_opregion {
  112.         struct opregion_header *header;
  113.         struct opregion_acpi *acpi;
  114.         struct opregion_swsci *swsci;
  115.         struct opregion_asle *asle;
  116.         void *vbt;
  117.         u32 __iomem *lid_state;
  118. };
  119. #define OPREGION_SIZE            (8*1024)
  120.  
  121. struct intel_overlay;
  122. struct intel_overlay_error_state;
  123.  
  124. struct drm_i915_master_private {
  125.         drm_local_map_t *sarea;
  126.         struct _drm_i915_sarea *sarea_priv;
  127. };
  128. #define I915_FENCE_REG_NONE -1
  129. #define I915_MAX_NUM_FENCES 16
  130. /* 16 fences + sign bit for FENCE_REG_NONE */
  131. #define I915_MAX_NUM_FENCE_BITS 5
  132.  
  133. struct drm_i915_fence_reg {
  134.         struct list_head lru_list;
  135.         struct drm_i915_gem_object *obj;
  136.         uint32_t setup_seqno;
  137. };
  138.  
  139. struct sdvo_device_mapping {
  140.         u8 initialized;
  141.         u8 dvo_port;
  142.         u8 slave_addr;
  143.         u8 dvo_wiring;
  144.         u8 i2c_pin;
  145.         u8 ddc_pin;
  146. };
  147.  
  148. struct intel_display_error_state;
  149.  
  150. struct drm_i915_error_state {
  151.         u32 eir;
  152.         u32 pgtbl_er;
  153.         u32 pipestat[I915_MAX_PIPES];
  154.         u32 ipeir;
  155.         u32 ipehr;
  156.         u32 instdone;
  157.         u32 acthd;
  158.         u32 error; /* gen6+ */
  159.         u32 bcs_acthd; /* gen6+ blt engine */
  160.         u32 bcs_ipehr;
  161.         u32 bcs_ipeir;
  162.         u32 bcs_instdone;
  163.         u32 bcs_seqno;
  164.         u32 vcs_acthd; /* gen6+ bsd engine */
  165.         u32 vcs_ipehr;
  166.         u32 vcs_ipeir;
  167.         u32 vcs_instdone;
  168.         u32 vcs_seqno;
  169.         u32 instpm;
  170.         u32 instps;
  171.         u32 instdone1;
  172.         u32 seqno;
  173.         u64 bbaddr;
  174.         u64 fence[I915_MAX_NUM_FENCES];
  175.         struct timeval time;
  176.         struct drm_i915_error_object {
  177.                 int page_count;
  178.                 u32 gtt_offset;
  179.                 u32 *pages[0];
  180.         } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
  181.         struct drm_i915_error_buffer {
  182.                 u32 size;
  183.                 u32 name;
  184.                 u32 seqno;
  185.                 u32 gtt_offset;
  186.                 u32 read_domains;
  187.                 u32 write_domain;
  188.                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  189.                 s32 pinned:2;
  190.                 u32 tiling:2;
  191.                 u32 dirty:1;
  192.                 u32 purgeable:1;
  193.                 u32 ring:4;
  194.                 u32 cache_level:2;
  195.         } *active_bo, *pinned_bo;
  196.         u32 active_bo_count, pinned_bo_count;
  197.         struct intel_overlay_error_state *overlay;
  198.         struct intel_display_error_state *display;
  199. };
  200.  
  201. struct drm_i915_display_funcs {
  202.         void (*dpms)(struct drm_crtc *crtc, int mode);
  203.         bool (*fbc_enabled)(struct drm_device *dev);
  204.         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  205.         void (*disable_fbc)(struct drm_device *dev);
  206.         int (*get_display_clock_speed)(struct drm_device *dev);
  207.         int (*get_fifo_size)(struct drm_device *dev, int plane);
  208.         void (*update_wm)(struct drm_device *dev);
  209.         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
  210.                                  uint32_t sprite_width, int pixel_size);
  211.         int (*crtc_mode_set)(struct drm_crtc *crtc,
  212.                              struct drm_display_mode *mode,
  213.                              struct drm_display_mode *adjusted_mode,
  214.                              int x, int y,
  215.                              struct drm_framebuffer *old_fb);
  216.         void (*write_eld)(struct drm_connector *connector,
  217.                           struct drm_crtc *crtc);
  218.         void (*fdi_link_train)(struct drm_crtc *crtc);
  219.         void (*init_clock_gating)(struct drm_device *dev);
  220.         void (*init_pch_clock_gating)(struct drm_device *dev);
  221.         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  222.                           struct drm_framebuffer *fb,
  223.                           struct drm_i915_gem_object *obj);
  224.         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  225.                             int x, int y);
  226.         void (*force_wake_get)(struct drm_i915_private *dev_priv);
  227.         void (*force_wake_put)(struct drm_i915_private *dev_priv);
  228.         /* clock updates for mode set */
  229.         /* cursor updates */
  230.         /* render clock increase/decrease */
  231.         /* display clock increase/decrease */
  232.         /* pll clock increase/decrease */
  233. };
  234.  
  235. struct intel_device_info {
  236.         u8 gen;
  237.         u8 is_mobile:1;
  238.         u8 is_i85x:1;
  239.         u8 is_i915g:1;
  240.         u8 is_i945gm:1;
  241.         u8 is_g33:1;
  242.         u8 need_gfx_hws:1;
  243.         u8 is_g4x:1;
  244.         u8 is_pineview:1;
  245.         u8 is_broadwater:1;
  246.         u8 is_crestline:1;
  247.         u8 is_ivybridge:1;
  248.         u8 has_fbc:1;
  249.         u8 has_pipe_cxsr:1;
  250.         u8 has_hotplug:1;
  251.         u8 cursor_needs_physical:1;
  252.         u8 has_overlay:1;
  253.         u8 overlay_needs_physical:1;
  254.         u8 supports_tv:1;
  255.         u8 has_bsd_ring:1;
  256.         u8 has_blt_ring:1;
  257. };
  258.  
  259. enum no_fbc_reason {
  260.         FBC_NO_OUTPUT, /* no outputs enabled to compress */
  261.         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  262.         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  263.         FBC_MODE_TOO_LARGE, /* mode too large for compression */
  264.         FBC_BAD_PLANE, /* fbc not supported on plane */
  265.         FBC_NOT_TILED, /* buffer not tiled */
  266.         FBC_MULTIPLE_PIPES, /* more than one pipe active */
  267.         FBC_MODULE_PARAM,
  268. };
  269.  
  270. enum intel_pch {
  271.         PCH_IBX,        /* Ibexpeak PCH */
  272.         PCH_CPT,        /* Cougarpoint PCH */
  273. };
  274.  
  275. #define QUIRK_PIPEA_FORCE (1<<0)
  276. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  277.  
  278. struct intel_fbdev;
  279. struct intel_fbc_work;
  280.  
  281. typedef struct drm_i915_private {
  282.         struct drm_device *dev;
  283.  
  284.         const struct intel_device_info *info;
  285.  
  286.         int has_gem;
  287.         int relative_constants_mode;
  288.  
  289.         void __iomem *regs;
  290.         /** gt_fifo_count and the subsequent register write are synchronized
  291.          * with dev->struct_mutex. */
  292.         unsigned gt_fifo_count;
  293.         /** forcewake_count is protected by gt_lock */
  294.         unsigned forcewake_count;
  295.         /** gt_lock is also taken in irq contexts. */
  296.     spinlock_t gt_lock;
  297.  
  298.     struct intel_gmbus {
  299.         struct i2c_adapter adapter;
  300.         struct i2c_adapter *force_bit;
  301.         u32 reg0;
  302.     } *gmbus;
  303.  
  304.         struct pci_dev *bridge_dev;
  305.     struct intel_ring_buffer ring[I915_NUM_RINGS];
  306.         uint32_t next_seqno;
  307.  
  308.     drm_dma_handle_t *status_page_dmah;
  309.         uint32_t counter;
  310.         drm_local_map_t hws_map;
  311.     struct drm_i915_gem_object *pwrctx;
  312.     struct drm_i915_gem_object *renderctx;
  313.  
  314. //   struct resource mch_res;
  315.  
  316.         unsigned int cpp;
  317.         int back_offset;
  318.         int front_offset;
  319.         int current_page;
  320.         int page_flipping;
  321.  
  322.         atomic_t irq_received;
  323.  
  324.         /* protects the irq masks */
  325.         spinlock_t irq_lock;
  326.         /** Cached value of IMR to avoid reads in updating the bitfield */
  327.         u32 pipestat[2];
  328.         u32 irq_mask;
  329.         u32 gt_irq_mask;
  330.         u32 pch_irq_mask;
  331.  
  332.         u32 hotplug_supported_mask;
  333.         struct work_struct hotplug_work;
  334.  
  335.         int tex_lru_log_granularity;
  336.         int allow_batchbuffer;
  337.         struct mem_block *agp_heap;
  338.         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  339.         int vblank_pipe;
  340.         int num_pipe;
  341.  
  342.         /* For hangcheck timer */
  343. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  344.     struct timer_list hangcheck_timer;
  345.         int hangcheck_count;
  346.         uint32_t last_acthd;
  347.         uint32_t last_acthd_bsd;
  348.         uint32_t last_acthd_blt;
  349.         uint32_t last_instdone;
  350.         uint32_t last_instdone1;
  351.  
  352.         unsigned long cfb_size;
  353.         unsigned int cfb_fb;
  354.         enum plane cfb_plane;
  355.         int cfb_y;
  356. //   struct intel_fbc_work *fbc_work;
  357.  
  358.     struct intel_opregion opregion;
  359.  
  360.         /* overlay */
  361. //   struct intel_overlay *overlay;
  362.         bool sprite_scaling_enabled;
  363.  
  364.         /* LVDS info */
  365.         int backlight_level;  /* restore backlight to this value */
  366.         bool backlight_enabled;
  367.         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  368.         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  369.  
  370.         /* Feature bits from the VBIOS */
  371.         unsigned int int_tv_support:1;
  372.         unsigned int lvds_dither:1;
  373.         unsigned int lvds_vbt:1;
  374.         unsigned int int_crt_support:1;
  375.         unsigned int lvds_use_ssc:1;
  376.         unsigned int display_clock_mode:1;
  377.         int lvds_ssc_freq;
  378.         struct {
  379.                 int rate;
  380.                 int lanes;
  381.                 int preemphasis;
  382.                 int vswing;
  383.  
  384.                 bool initialized;
  385.                 bool support;
  386.                 int bpp;
  387.         struct edp_power_seq pps;
  388.         } edp;
  389.         bool no_aux_handshake;
  390.  
  391. //   struct notifier_block lid_notifier;
  392.  
  393.         int crt_ddc_pin;
  394.         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  395.         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  396.         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  397.  
  398.         unsigned int fsb_freq, mem_freq, is_ddr3;
  399.  
  400.         spinlock_t error_lock;
  401. //      struct drm_i915_error_state *first_error;
  402.         struct work_struct error_work;
  403. //      struct completion error_completion;
  404.     struct workqueue_struct *wq;
  405.  
  406.         /* Display functions */
  407.     struct drm_i915_display_funcs display;
  408.  
  409.         /* PCH chipset type */
  410.         enum intel_pch pch_type;
  411.  
  412.         unsigned long quirks;
  413.  
  414.         /* Register state */
  415.         bool modeset_on_lid;
  416.         u8 saveLBB;
  417.         u32 saveDSPACNTR;
  418.         u32 saveDSPBCNTR;
  419.         u32 saveDSPARB;
  420.         u32 saveHWS;
  421.         u32 savePIPEACONF;
  422.         u32 savePIPEBCONF;
  423.         u32 savePIPEASRC;
  424.         u32 savePIPEBSRC;
  425.         u32 saveFPA0;
  426.         u32 saveFPA1;
  427.         u32 saveDPLL_A;
  428.         u32 saveDPLL_A_MD;
  429.         u32 saveHTOTAL_A;
  430.         u32 saveHBLANK_A;
  431.         u32 saveHSYNC_A;
  432.         u32 saveVTOTAL_A;
  433.         u32 saveVBLANK_A;
  434.         u32 saveVSYNC_A;
  435.         u32 saveBCLRPAT_A;
  436.         u32 saveTRANSACONF;
  437.         u32 saveTRANS_HTOTAL_A;
  438.         u32 saveTRANS_HBLANK_A;
  439.         u32 saveTRANS_HSYNC_A;
  440.         u32 saveTRANS_VTOTAL_A;
  441.         u32 saveTRANS_VBLANK_A;
  442.         u32 saveTRANS_VSYNC_A;
  443.         u32 savePIPEASTAT;
  444.         u32 saveDSPASTRIDE;
  445.         u32 saveDSPASIZE;
  446.         u32 saveDSPAPOS;
  447.         u32 saveDSPAADDR;
  448.         u32 saveDSPASURF;
  449.         u32 saveDSPATILEOFF;
  450.         u32 savePFIT_PGM_RATIOS;
  451.         u32 saveBLC_HIST_CTL;
  452.         u32 saveBLC_PWM_CTL;
  453.         u32 saveBLC_PWM_CTL2;
  454.         u32 saveBLC_CPU_PWM_CTL;
  455.         u32 saveBLC_CPU_PWM_CTL2;
  456.         u32 saveFPB0;
  457.         u32 saveFPB1;
  458.         u32 saveDPLL_B;
  459.         u32 saveDPLL_B_MD;
  460.         u32 saveHTOTAL_B;
  461.         u32 saveHBLANK_B;
  462.         u32 saveHSYNC_B;
  463.         u32 saveVTOTAL_B;
  464.         u32 saveVBLANK_B;
  465.         u32 saveVSYNC_B;
  466.         u32 saveBCLRPAT_B;
  467.         u32 saveTRANSBCONF;
  468.         u32 saveTRANS_HTOTAL_B;
  469.         u32 saveTRANS_HBLANK_B;
  470.         u32 saveTRANS_HSYNC_B;
  471.         u32 saveTRANS_VTOTAL_B;
  472.         u32 saveTRANS_VBLANK_B;
  473.         u32 saveTRANS_VSYNC_B;
  474.         u32 savePIPEBSTAT;
  475.         u32 saveDSPBSTRIDE;
  476.         u32 saveDSPBSIZE;
  477.         u32 saveDSPBPOS;
  478.         u32 saveDSPBADDR;
  479.         u32 saveDSPBSURF;
  480.         u32 saveDSPBTILEOFF;
  481.         u32 saveVGA0;
  482.         u32 saveVGA1;
  483.         u32 saveVGA_PD;
  484.         u32 saveVGACNTRL;
  485.         u32 saveADPA;
  486.         u32 saveLVDS;
  487.         u32 savePP_ON_DELAYS;
  488.         u32 savePP_OFF_DELAYS;
  489.         u32 saveDVOA;
  490.         u32 saveDVOB;
  491.         u32 saveDVOC;
  492.         u32 savePP_ON;
  493.         u32 savePP_OFF;
  494.         u32 savePP_CONTROL;
  495.         u32 savePP_DIVISOR;
  496.         u32 savePFIT_CONTROL;
  497.         u32 save_palette_a[256];
  498.         u32 save_palette_b[256];
  499.         u32 saveDPFC_CB_BASE;
  500.         u32 saveFBC_CFB_BASE;
  501.         u32 saveFBC_LL_BASE;
  502.         u32 saveFBC_CONTROL;
  503.         u32 saveFBC_CONTROL2;
  504.         u32 saveIER;
  505.         u32 saveIIR;
  506.         u32 saveIMR;
  507.         u32 saveDEIER;
  508.         u32 saveDEIMR;
  509.         u32 saveGTIER;
  510.         u32 saveGTIMR;
  511.         u32 saveFDI_RXA_IMR;
  512.         u32 saveFDI_RXB_IMR;
  513.         u32 saveCACHE_MODE_0;
  514.         u32 saveMI_ARB_STATE;
  515.         u32 saveSWF0[16];
  516.         u32 saveSWF1[16];
  517.         u32 saveSWF2[3];
  518.         u8 saveMSR;
  519.         u8 saveSR[8];
  520.         u8 saveGR[25];
  521.         u8 saveAR_INDEX;
  522.         u8 saveAR[21];
  523.         u8 saveDACMASK;
  524.         u8 saveCR[37];
  525.         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  526.         u32 saveCURACNTR;
  527.         u32 saveCURAPOS;
  528.         u32 saveCURABASE;
  529.         u32 saveCURBCNTR;
  530.         u32 saveCURBPOS;
  531.         u32 saveCURBBASE;
  532.         u32 saveCURSIZE;
  533.         u32 saveDP_B;
  534.         u32 saveDP_C;
  535.         u32 saveDP_D;
  536.         u32 savePIPEA_GMCH_DATA_M;
  537.         u32 savePIPEB_GMCH_DATA_M;
  538.         u32 savePIPEA_GMCH_DATA_N;
  539.         u32 savePIPEB_GMCH_DATA_N;
  540.         u32 savePIPEA_DP_LINK_M;
  541.         u32 savePIPEB_DP_LINK_M;
  542.         u32 savePIPEA_DP_LINK_N;
  543.         u32 savePIPEB_DP_LINK_N;
  544.         u32 saveFDI_RXA_CTL;
  545.         u32 saveFDI_TXA_CTL;
  546.         u32 saveFDI_RXB_CTL;
  547.         u32 saveFDI_TXB_CTL;
  548.         u32 savePFA_CTL_1;
  549.         u32 savePFB_CTL_1;
  550.         u32 savePFA_WIN_SZ;
  551.         u32 savePFB_WIN_SZ;
  552.         u32 savePFA_WIN_POS;
  553.         u32 savePFB_WIN_POS;
  554.         u32 savePCH_DREF_CONTROL;
  555.         u32 saveDISP_ARB_CTL;
  556.         u32 savePIPEA_DATA_M1;
  557.         u32 savePIPEA_DATA_N1;
  558.         u32 savePIPEA_LINK_M1;
  559.         u32 savePIPEA_LINK_N1;
  560.         u32 savePIPEB_DATA_M1;
  561.         u32 savePIPEB_DATA_N1;
  562.         u32 savePIPEB_LINK_M1;
  563.         u32 savePIPEB_LINK_N1;
  564.         u32 saveMCHBAR_RENDER_STANDBY;
  565.         u32 savePCH_PORT_HOTPLUG;
  566.  
  567.         struct {
  568.                 /** Bridge to intel-gtt-ko */
  569.                 const struct intel_gtt *gtt;
  570.                 /** Memory allocator for GTT stolen memory */
  571.         struct drm_mm stolen;
  572.                 /** Memory allocator for GTT */
  573.         struct drm_mm gtt_space;
  574.                 /** List of all objects in gtt_space. Used to restore gtt
  575.                  * mappings on resume */
  576.                 struct list_head gtt_list;
  577.  
  578.                 /** Usable portion of the GTT for GEM */
  579.                 unsigned long gtt_start;
  580.                 unsigned long gtt_mappable_end;
  581.                 unsigned long gtt_end;
  582.  
  583. //       struct io_mapping *gtt_mapping;
  584.                 int gtt_mtrr;
  585.  
  586. //       struct shrinker inactive_shrinker;
  587.  
  588.                 /**
  589.                  * List of objects currently involved in rendering.
  590.                  *
  591.                  * Includes buffers having the contents of their GPU caches
  592.                  * flushed, not necessarily primitives.  last_rendering_seqno
  593.                  * represents when the rendering involved will be completed.
  594.                  *
  595.                  * A reference is held on the buffer while on this list.
  596.                  */
  597.                 struct list_head active_list;
  598.  
  599.                 /**
  600.                  * List of objects which are not in the ringbuffer but which
  601.                  * still have a write_domain which needs to be flushed before
  602.                  * unbinding.
  603.                  *
  604.                  * last_rendering_seqno is 0 while an object is in this list.
  605.                  *
  606.                  * A reference is held on the buffer while on this list.
  607.                  */
  608.                 struct list_head flushing_list;
  609.  
  610.                 /**
  611.                  * LRU list of objects which are not in the ringbuffer and
  612.                  * are ready to unbind, but are still in the GTT.
  613.                  *
  614.                  * last_rendering_seqno is 0 while an object is in this list.
  615.                  *
  616.                  * A reference is not held on the buffer while on this list,
  617.                  * as merely being GTT-bound shouldn't prevent its being
  618.                  * freed, and we'll pull it off the list in the free path.
  619.                  */
  620.                 struct list_head inactive_list;
  621.  
  622.                 /**
  623.                  * LRU list of objects which are not in the ringbuffer but
  624.                  * are still pinned in the GTT.
  625.                  */
  626.                 struct list_head pinned_list;
  627.  
  628.                 /** LRU list of objects with fence regs on them. */
  629.                 struct list_head fence_list;
  630.  
  631.                 /**
  632.                  * List of objects currently pending being freed.
  633.                  *
  634.                  * These objects are no longer in use, but due to a signal
  635.                  * we were prevented from freeing them at the appointed time.
  636.                  */
  637.                 struct list_head deferred_free_list;
  638.  
  639.                 /**
  640.                  * We leave the user IRQ off as much as possible,
  641.                  * but this means that requests will finish and never
  642.                  * be retired once the system goes idle. Set a timer to
  643.                  * fire periodically while the ring is running. When it
  644.                  * fires, go retire requests.
  645.                  */
  646.                 struct delayed_work retire_work;
  647.  
  648.                 /**
  649.                  * Are we in a non-interruptible section of code like
  650.                  * modesetting?
  651.                  */
  652.                 bool interruptible;
  653.  
  654.                 /**
  655.                  * Flag if the X Server, and thus DRM, is not currently in
  656.                  * control of the device.
  657.                  *
  658.                  * This is set between LeaveVT and EnterVT.  It needs to be
  659.                  * replaced with a semaphore.  It also needs to be
  660.                  * transitioned away from for kernel modesetting.
  661.                  */
  662.                 int suspended;
  663.  
  664.                 /**
  665.                  * Flag if the hardware appears to be wedged.
  666.                  *
  667.                  * This is set when attempts to idle the device timeout.
  668.                  * It prevents command submission from occurring and makes
  669.                  * every pending request fail
  670.                  */
  671.                 atomic_t wedged;
  672.  
  673.                 /** Bit 6 swizzling required for X tiling */
  674.                 uint32_t bit_6_swizzle_x;
  675.                 /** Bit 6 swizzling required for Y tiling */
  676.                 uint32_t bit_6_swizzle_y;
  677.  
  678.                 /* storage for physical objects */
  679. //       struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  680.  
  681.                 /* accounting, useful for userland debugging */
  682.                 size_t gtt_total;
  683.                 size_t mappable_gtt_total;
  684.                 size_t object_memory;
  685.                 u32 object_count;
  686.         } mm;
  687.     struct sdvo_device_mapping sdvo_mappings[2];
  688.         /* indicate whether the LVDS_BORDER should be enabled or not */
  689.         unsigned int lvds_border_bits;
  690.         /* Panel fitter placement and size for Ironlake+ */
  691.         u32 pch_pf_pos, pch_pf_size;
  692.  
  693.     struct drm_crtc *plane_to_crtc_mapping[3];
  694.     struct drm_crtc *pipe_to_crtc_mapping[3];
  695.         wait_queue_head_t pending_flip_queue;
  696.         bool flip_pending_is_done;
  697.  
  698.         /* Reclocking support */
  699.         bool render_reclock_avail;
  700.         bool lvds_downclock_avail;
  701.         /* indicates the reduced downclock for LVDS*/
  702.         int lvds_downclock;
  703.         struct work_struct idle_work;
  704.     struct timer_list idle_timer;
  705.         bool busy;
  706.         u16 orig_clock;
  707.         int child_dev_num;
  708.     struct child_device_config *child_dev;
  709.     struct drm_connector *int_lvds_connector;
  710.     struct drm_connector *int_edp_connector;
  711.  
  712.         bool mchbar_need_disable;
  713.  
  714.         struct work_struct rps_work;
  715.         spinlock_t rps_lock;
  716.         u32 pm_iir;
  717.  
  718.         u8 cur_delay;
  719.         u8 min_delay;
  720.         u8 max_delay;
  721.         u8 fmax;
  722.         u8 fstart;
  723.  
  724.         u64 last_count1;
  725.         unsigned long last_time1;
  726.         unsigned long chipset_power;
  727.         u64 last_count2;
  728.     struct timespec last_time2;
  729.         unsigned long gfx_power;
  730.         int c_m;
  731.         int r_t;
  732.         u8 corr;
  733.         spinlock_t *mchdev_lock;
  734.  
  735.         enum no_fbc_reason no_fbc_reason;
  736.  
  737. //   struct drm_mm_node *compressed_fb;
  738. //   struct drm_mm_node *compressed_llb;
  739.  
  740.         unsigned long last_gpu_reset;
  741.  
  742.         /* list of fbdev register on this device */
  743.     struct intel_fbdev *fbdev;
  744.  
  745. //   struct backlight_device *backlight;
  746.  
  747. //   struct drm_property *broadcast_rgb_property;
  748. //   struct drm_property *force_audio_property;
  749. } drm_i915_private_t;
  750.  
  751. enum i915_cache_level {
  752.         I915_CACHE_NONE,
  753.         I915_CACHE_LLC,
  754.         I915_CACHE_LLC_MLC, /* gen6+ */
  755. };
  756.  
  757. struct drm_i915_gem_object {
  758.     struct drm_gem_object base;
  759.  
  760.     void  *mapped;
  761.  
  762.     /** Current space allocated to this object in the GTT, if any. */
  763.     struct drm_mm_node *gtt_space;
  764.     struct list_head gtt_list;
  765.  
  766.     /** This object's place on the active/flushing/inactive lists */
  767.     struct list_head ring_list;
  768.     struct list_head mm_list;
  769.     /** This object's place on GPU write list */
  770.     struct list_head gpu_write_list;
  771.     /** This object's place in the batchbuffer or on the eviction list */
  772.     struct list_head exec_list;
  773.  
  774.     /**
  775.      * This is set if the object is on the active or flushing lists
  776.      * (has pending rendering), and is not set if it's on inactive (ready
  777.      * to be unbound).
  778.      */
  779.         unsigned int active:1;
  780.  
  781.     /**
  782.      * This is set if the object has been written to since last bound
  783.      * to the GTT
  784.      */
  785.         unsigned int dirty:1;
  786.  
  787.     /**
  788.      * This is set if the object has been written to since the last
  789.      * GPU flush.
  790.      */
  791.         unsigned int pending_gpu_write:1;
  792.  
  793.     /**
  794.      * Fence register bits (if any) for this object.  Will be set
  795.      * as needed when mapped into the GTT.
  796.      * Protected by dev->struct_mutex.
  797.      */
  798.         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  799.  
  800.     /**
  801.      * Advice: are the backing pages purgeable?
  802.      */
  803.         unsigned int madv:2;
  804.  
  805.     /**
  806.      * Current tiling mode for the object.
  807.      */
  808.         unsigned int tiling_mode:2;
  809.         unsigned int tiling_changed:1;
  810.  
  811.     /** How many users have pinned this object in GTT space. The following
  812.      * users can each hold at most one reference: pwrite/pread, pin_ioctl
  813.      * (via user_pin_count), execbuffer (objects are not allowed multiple
  814.      * times for the same batchbuffer), and the framebuffer code. When
  815.      * switching/pageflipping, the framebuffer code has at most two buffers
  816.      * pinned per crtc.
  817.      *
  818.      * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  819.      * bits with absolutely no headroom. So use 4 bits. */
  820.         unsigned int pin_count:4;
  821. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  822.  
  823.     /**
  824.      * Is the object at the current location in the gtt mappable and
  825.      * fenceable? Used to avoid costly recalculations.
  826.      */
  827.         unsigned int map_and_fenceable:1;
  828.  
  829.     /**
  830.      * Whether the current gtt mapping needs to be mappable (and isn't just
  831.      * mappable by accident). Track pin and fault separate for a more
  832.      * accurate mappable working set.
  833.      */
  834.         unsigned int fault_mappable:1;
  835.         unsigned int pin_mappable:1;
  836.  
  837.     /*
  838.      * Is the GPU currently using a fence to access this buffer,
  839.      */
  840.     unsigned int pending_fenced_gpu_access:1;
  841.     unsigned int fenced_gpu_access:1;
  842.  
  843.     unsigned int cache_level:2;
  844.  
  845.     struct page **pages;
  846.  
  847.     /**
  848.      * DMAR support
  849.      */
  850.     struct scatterlist *sg_list;
  851.     int num_sg;
  852.  
  853.     /**
  854.      * Used for performing relocations during execbuffer insertion.
  855.      */
  856.     struct hlist_node exec_node;
  857.     unsigned long exec_handle;
  858.     struct drm_i915_gem_exec_object2 *exec_entry;
  859.  
  860.     /**
  861.      * Current offset of the object in GTT space.
  862.      *
  863.      * This is the same as gtt_space->start
  864.      */
  865.     uint32_t gtt_offset;
  866.  
  867.     /** Breadcrumb of last rendering to the buffer. */
  868.     uint32_t last_rendering_seqno;
  869.     struct intel_ring_buffer *ring;
  870.  
  871.     /** Breadcrumb of last fenced GPU access to the buffer. */
  872.     uint32_t last_fenced_seqno;
  873.     struct intel_ring_buffer *last_fenced_ring;
  874.  
  875.     /** Current tiling stride for the object, if it's tiled. */
  876.     uint32_t stride;
  877.  
  878.     /** Record of address bit 17 of each page at last unbind. */
  879.     unsigned long *bit_17;
  880.  
  881.  
  882.     /**
  883.      * If present, while GEM_DOMAIN_CPU is in the read domain this array
  884.      * flags which individual pages are valid.
  885.      */
  886.     uint8_t *page_cpu_valid;
  887.  
  888.     /** User space pin count and filp owning the pin */
  889.     uint32_t user_pin_count;
  890.     struct drm_file *pin_filp;
  891.  
  892.     /** for phy allocated objects */
  893.     struct drm_i915_gem_phys_object *phys_obj;
  894.  
  895.     /**
  896.      * Number of crtcs where this object is currently the fb, but
  897.      * will be page flipped away on the next vblank.  When it
  898.      * reaches 0, dev_priv->pending_flip_queue will be woken up.
  899.      */
  900.     atomic_t pending_flip;
  901. };
  902.  
  903. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  904.  
  905. /**
  906.  * Request queue structure.
  907.  *
  908.  * The request queue allows us to note sequence numbers that have been emitted
  909.  * and may be associated with active buffers to be retired.
  910.  *
  911.  * By keeping this list, we can avoid having to do questionable
  912.  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  913.  * an emission time with seqnos for tracking how far ahead of the GPU we are.
  914.  */
  915. struct drm_i915_gem_request {
  916.         /** On Which ring this request was generated */
  917.         struct intel_ring_buffer *ring;
  918.  
  919.         /** GEM sequence number associated with this request. */
  920.         uint32_t seqno;
  921.  
  922.         /** Time at which this request was emitted, in jiffies. */
  923.         unsigned long emitted_jiffies;
  924.  
  925.         /** global list entry for this request */
  926.         struct list_head list;
  927.  
  928.         struct drm_i915_file_private *file_priv;
  929.         /** file_priv list entry for this request */
  930.         struct list_head client_list;
  931. };
  932.  
  933. struct drm_i915_file_private {
  934.         struct {
  935.         spinlock_t lock;
  936.                 struct list_head request_list;
  937.         } mm;
  938. };
  939.  
  940. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  941.  
  942. #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
  943. #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
  944. #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
  945. #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
  946. #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
  947. #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
  948. #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
  949. #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
  950. #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
  951. #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
  952. #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
  953. #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
  954. #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
  955. #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
  956. #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
  957. #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
  958. #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
  959. #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
  960. #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
  961. #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
  962.  
  963. /*
  964.  * The genX designation typically refers to the render engine, so render
  965.  * capability related checks should use IS_GEN, while display and other checks
  966.  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  967.  * chips, etc.).
  968.  */
  969. #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
  970. #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
  971. #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
  972. #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
  973. #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
  974. #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
  975.  
  976. #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
  977. #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
  978. #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
  979.  
  980. #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
  981. #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
  982.  
  983. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  984.  * rows, which changed the alignment requirements and fence programming.
  985.  */
  986. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  987.                                                       IS_I915GM(dev)))
  988. #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  989. #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
  990. #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
  991. #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
  992. #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
  993. #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
  994. /* dsparb controlled by hw only */
  995. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  996.  
  997. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  998. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  999. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1000.  
  1001. #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
  1002. #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
  1003.  
  1004. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1005. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1006. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1007.  
  1008. //#include "i915_trace.h"
  1009.  
  1010. extern int i915_max_ioctl;
  1011. extern unsigned int i915_fbpercrtc;
  1012. extern int i915_panel_ignore_lid;
  1013. extern unsigned int i915_powersave;
  1014. extern unsigned int i915_semaphores;
  1015. extern unsigned int i915_lvds_downclock;
  1016. extern unsigned int i915_panel_use_ssc;
  1017. extern int i915_vbt_sdvo_panel_type;
  1018. extern unsigned int i915_enable_rc6;
  1019. extern unsigned int i915_enable_fbc;
  1020. extern bool i915_enable_hangcheck;
  1021.  
  1022. extern int i915_resume(struct drm_device *dev);
  1023. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1024. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1025.  
  1026.                                 /* i915_dma.c */
  1027. extern void i915_kernel_lost_context(struct drm_device * dev);
  1028. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1029. extern int i915_driver_unload(struct drm_device *);
  1030. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1031. extern void i915_driver_lastclose(struct drm_device * dev);
  1032. extern void i915_driver_preclose(struct drm_device *dev,
  1033.                                  struct drm_file *file_priv);
  1034. extern void i915_driver_postclose(struct drm_device *dev,
  1035.                                   struct drm_file *file_priv);
  1036. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1037. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1038.                               unsigned long arg);
  1039. extern int i915_emit_box(struct drm_device *dev,
  1040.                          struct drm_clip_rect *box,
  1041.                          int DR1, int DR4);
  1042. extern int i915_reset(struct drm_device *dev, u8 flags);
  1043. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1044. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1045. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1046. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1047.  
  1048.  
  1049. /* i915_irq.c */
  1050. void i915_hangcheck_elapsed(unsigned long data);
  1051. void i915_handle_error(struct drm_device *dev, bool wedged);
  1052. extern int i915_irq_emit(struct drm_device *dev, void *data,
  1053.                          struct drm_file *file_priv);
  1054. extern int i915_irq_wait(struct drm_device *dev, void *data,
  1055.                          struct drm_file *file_priv);
  1056.  
  1057. extern void intel_irq_init(struct drm_device *dev);
  1058.  
  1059. extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  1060.                                 struct drm_file *file_priv);
  1061. extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  1062.                                 struct drm_file *file_priv);
  1063. extern int i915_vblank_swap(struct drm_device *dev, void *data,
  1064.                             struct drm_file *file_priv);
  1065.  
  1066. void
  1067. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1068.  
  1069. void
  1070. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1071.  
  1072. void intel_enable_asle(struct drm_device *dev);
  1073.  
  1074. #ifdef CONFIG_DEBUG_FS
  1075. extern void i915_destroy_error_state(struct drm_device *dev);
  1076. #else
  1077. #define i915_destroy_error_state(x)
  1078. #endif
  1079.  
  1080.  
  1081. /* i915_mem.c */
  1082. extern int i915_mem_alloc(struct drm_device *dev, void *data,
  1083.                           struct drm_file *file_priv);
  1084. extern int i915_mem_free(struct drm_device *dev, void *data,
  1085.                          struct drm_file *file_priv);
  1086. extern int i915_mem_init_heap(struct drm_device *dev, void *data,
  1087.                               struct drm_file *file_priv);
  1088. extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
  1089.                                  struct drm_file *file_priv);
  1090. extern void i915_mem_takedown(struct mem_block **heap);
  1091. extern void i915_mem_release(struct drm_device * dev,
  1092.                              struct drm_file *file_priv, struct mem_block *heap);
  1093. /* i915_gem.c */
  1094. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1095.                         struct drm_file *file_priv);
  1096. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1097.                           struct drm_file *file_priv);
  1098. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1099.                          struct drm_file *file_priv);
  1100. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1101.                           struct drm_file *file_priv);
  1102. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1103.                         struct drm_file *file_priv);
  1104. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1105.                         struct drm_file *file_priv);
  1106. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1107.                               struct drm_file *file_priv);
  1108. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1109.                              struct drm_file *file_priv);
  1110. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1111.                         struct drm_file *file_priv);
  1112. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1113.                          struct drm_file *file_priv);
  1114. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1115.                        struct drm_file *file_priv);
  1116. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1117.                          struct drm_file *file_priv);
  1118. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1119.                         struct drm_file *file_priv);
  1120. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1121.                             struct drm_file *file_priv);
  1122. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1123.                            struct drm_file *file_priv);
  1124. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1125.                            struct drm_file *file_priv);
  1126. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1127.                            struct drm_file *file_priv);
  1128. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1129.                         struct drm_file *file_priv);
  1130. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1131.                         struct drm_file *file_priv);
  1132. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1133.                                 struct drm_file *file_priv);
  1134. void i915_gem_load(struct drm_device *dev);
  1135. int i915_gem_init_object(struct drm_gem_object *obj);
  1136. int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
  1137.                                      uint32_t invalidate_domains,
  1138.                                      uint32_t flush_domains);
  1139. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1140.                                                   size_t size);
  1141. void i915_gem_free_object(struct drm_gem_object *obj);
  1142. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1143.                                      uint32_t alignment,
  1144.                                      bool map_and_fenceable);
  1145. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1146. int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
  1147. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1148. void i915_gem_lastclose(struct drm_device *dev);
  1149.  
  1150. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1151. int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
  1152. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1153.                                     struct intel_ring_buffer *ring,
  1154.                                     u32 seqno);
  1155.  
  1156. int i915_gem_dumb_create(struct drm_file *file_priv,
  1157.                          struct drm_device *dev,
  1158.                          struct drm_mode_create_dumb *args);
  1159. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1160.                       uint32_t handle, uint64_t *offset);
  1161. int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
  1162.                           uint32_t handle);
  1163. /**
  1164.  * Returns true if seq1 is later than seq2.
  1165.  */
  1166. static inline bool
  1167. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1168. {
  1169.         return (int32_t)(seq1 - seq2) >= 0;
  1170. }
  1171.  
  1172. static inline u32
  1173. i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
  1174. {
  1175.    drm_i915_private_t *dev_priv = ring->dev->dev_private;
  1176.    return ring->outstanding_lazy_request = dev_priv->next_seqno;
  1177. }
  1178.  
  1179. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
  1180.                                            struct intel_ring_buffer *pipelined);
  1181. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1182.  
  1183. void i915_gem_retire_requests(struct drm_device *dev);
  1184. void i915_gem_reset(struct drm_device *dev);
  1185. void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
  1186. int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
  1187.                                             uint32_t read_domains,
  1188.                                             uint32_t write_domain);
  1189. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1190. int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
  1191. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1192. void i915_gem_do_init(struct drm_device *dev,
  1193.                       unsigned long start,
  1194.                       unsigned long mappable_end,
  1195.                       unsigned long end);
  1196. int __must_check i915_gpu_idle(struct drm_device *dev);
  1197. int __must_check i915_gem_idle(struct drm_device *dev);
  1198. int __must_check i915_add_request(struct intel_ring_buffer *ring,
  1199.                                   struct drm_file *file,
  1200.                                   struct drm_i915_gem_request *request);
  1201. int __must_check i915_wait_request(struct intel_ring_buffer *ring,
  1202.                                    uint32_t seqno);
  1203. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1204. int __must_check
  1205. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1206.                                   bool write);
  1207. int __must_check
  1208. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1209.                                      u32 alignment,
  1210.                                      struct intel_ring_buffer *pipelined);
  1211. int i915_gem_attach_phys_object(struct drm_device *dev,
  1212.                                 struct drm_i915_gem_object *obj,
  1213.                                 int id,
  1214.                                 int align);
  1215. void i915_gem_detach_phys_object(struct drm_device *dev,
  1216.                                  struct drm_i915_gem_object *obj);
  1217. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1218. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1219.  
  1220. uint32_t
  1221. i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
  1222.                                     uint32_t size,
  1223.                                     int tiling_mode);
  1224.  
  1225. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1226.                                     enum i915_cache_level cache_level);
  1227.  
  1228. /* i915_gem_gtt.c */
  1229. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1230. int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
  1231. void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
  1232.                                 enum i915_cache_level cache_level);
  1233. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1234.  
  1235. /* i915_gem_evict.c */
  1236. int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
  1237.                                           unsigned alignment, bool mappable);
  1238. int __must_check i915_gem_evict_everything(struct drm_device *dev,
  1239.                                            bool purgeable_only);
  1240. int __must_check i915_gem_evict_inactive(struct drm_device *dev,
  1241.                                          bool purgeable_only);
  1242.  
  1243. /* i915_gem_tiling.c */
  1244. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1245. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1246. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1247.  
  1248. /* i915_gem_debug.c */
  1249. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1250.                           const char *where, uint32_t mark);
  1251. #if WATCH_LISTS
  1252. int i915_verify_lists(struct drm_device *dev);
  1253. #else
  1254. #define i915_verify_lists(dev) 0
  1255. #endif
  1256. void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
  1257.                                      int handle);
  1258. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1259.                           const char *where, uint32_t mark);
  1260.  
  1261. /* i915_debugfs.c */
  1262. int i915_debugfs_init(struct drm_minor *minor);
  1263. void i915_debugfs_cleanup(struct drm_minor *minor);
  1264.  
  1265. /* i915_suspend.c */
  1266. extern int i915_save_state(struct drm_device *dev);
  1267. extern int i915_restore_state(struct drm_device *dev);
  1268.  
  1269. /* i915_suspend.c */
  1270. extern int i915_save_state(struct drm_device *dev);
  1271. extern int i915_restore_state(struct drm_device *dev);
  1272.  
  1273. /* intel_i2c.c */
  1274. extern int intel_setup_gmbus(struct drm_device *dev);
  1275. extern void intel_teardown_gmbus(struct drm_device *dev);
  1276. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1277. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1278. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1279. {
  1280.         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1281. }
  1282. extern void intel_i2c_reset(struct drm_device *dev);
  1283.  
  1284. /* intel_opregion.c */
  1285. extern int intel_opregion_setup(struct drm_device *dev);
  1286. #ifdef CONFIG_ACPI
  1287. extern void intel_opregion_init(struct drm_device *dev);
  1288. extern void intel_opregion_fini(struct drm_device *dev);
  1289. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1290. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1291. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1292. #else
  1293. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1294. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1295. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1296. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1297. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1298. #endif
  1299.  
  1300. /* intel_acpi.c */
  1301. #ifdef CONFIG_ACPI
  1302. extern void intel_register_dsm_handler(void);
  1303. extern void intel_unregister_dsm_handler(void);
  1304. #else
  1305. static inline void intel_register_dsm_handler(void) { return; }
  1306. static inline void intel_unregister_dsm_handler(void) { return; }
  1307. #endif /* CONFIG_ACPI */
  1308.  
  1309. /* modesetting */
  1310. extern void intel_modeset_init(struct drm_device *dev);
  1311. extern void intel_modeset_gem_init(struct drm_device *dev);
  1312. extern void intel_modeset_cleanup(struct drm_device *dev);
  1313. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1314. extern bool intel_fbc_enabled(struct drm_device *dev);
  1315. extern void intel_disable_fbc(struct drm_device *dev);
  1316. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1317. extern void ironlake_init_pch_refclk(struct drm_device *dev);
  1318. extern void ironlake_enable_rc6(struct drm_device *dev);
  1319. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  1320. extern void intel_detect_pch(struct drm_device *dev);
  1321. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  1322.  
  1323. extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1324. extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
  1325. extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1326. extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
  1327.  
  1328. /* overlay */
  1329. #ifdef CONFIG_DEBUG_FS
  1330. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1331. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1332.  
  1333. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  1334. extern void intel_display_print_error_state(struct seq_file *m,
  1335.                                             struct drm_device *dev,
  1336.                                             struct intel_display_error_state *error);
  1337. #endif
  1338.  
  1339. #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  1340.  
  1341. #define BEGIN_LP_RING(n) \
  1342.         intel_ring_begin(LP_RING(dev_priv), (n))
  1343.  
  1344. #define OUT_RING(x) \
  1345.         intel_ring_emit(LP_RING(dev_priv), x)
  1346.  
  1347. #define ADVANCE_LP_RING() \
  1348.         intel_ring_advance(LP_RING(dev_priv))
  1349.  
  1350. /**
  1351.  * Lock test for when it's just for synchronization of ring access.
  1352.  *
  1353.  * In that case, we don't need to do it when GEM is initialized as nobody else
  1354.  * has access to the ring.
  1355.  */
  1356. #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  1357.         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  1358.                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  1359. } while (0)
  1360.  
  1361. /* On SNB platform, before reading ring registers forcewake bit
  1362.  * must be set to prevent GT core from power down and stale values being
  1363.  * returned.
  1364.  */
  1365. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1366. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1367. void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
  1368.  
  1369. /* We give fast paths for the really cool registers */
  1370. #define NEEDS_FORCE_WAKE(dev_priv, reg) \
  1371.         (((dev_priv)->info->gen >= 6) && \
  1372.         ((reg) < 0x40000) && \
  1373.         ((reg) != FORCEWAKE))
  1374.  
  1375. #define __i915_read(x, y) \
  1376.         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
  1377.  
  1378. __i915_read(8, b)
  1379. __i915_read(16, w)
  1380. __i915_read(32, l)
  1381. __i915_read(64, q)
  1382. #undef __i915_read
  1383.  
  1384. #define __i915_write(x, y) \
  1385.         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
  1386.  
  1387. __i915_write(8, b)
  1388. __i915_write(16, w)
  1389. __i915_write(32, l)
  1390. __i915_write(64, q)
  1391. #undef __i915_write
  1392.  
  1393. #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
  1394. #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
  1395.  
  1396. #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
  1397. #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
  1398. #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
  1399. #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
  1400.  
  1401. #define I915_READ(reg)          i915_read32(dev_priv, (reg))
  1402. #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
  1403. #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
  1404. #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
  1405.  
  1406. #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
  1407. #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
  1408.  
  1409. #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
  1410. #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
  1411.  
  1412. typedef struct
  1413. {
  1414.   int width;
  1415.   int height;
  1416.   int bpp;
  1417.   int freq;
  1418. }videomode_t;
  1419.  
  1420.  
  1421. static inline int mutex_trylock(struct mutex *lock)
  1422. {
  1423.     if (likely(atomic_cmpxchg(&lock->count, 1, 0) == 1))
  1424.         return 1;
  1425.     return 0;
  1426. }
  1427.  
  1428.  
  1429.  
  1430.  
  1431.  
  1432.  
  1433.  
  1434. #endif
  1435.