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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. //#include <linux/device.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "intel_drv.h"
  35.  
  36. #include <linux/kernel.h>
  37. #include <linux/module.h>
  38. #include <linux/mod_devicetable.h>
  39. #include <errno-base.h>
  40. #include <linux/pci.h>
  41.  
  42. #include <drm/drm_crtc_helper.h>
  43.  
  44. #include <syscall.h>
  45.  
  46. #define __read_mostly
  47.  
  48. int init_display_kms(struct drm_device *dev);
  49.  
  50. struct drm_device *main_device;
  51.  
  52. struct drm_file *drm_file_handlers[256];
  53.  
  54. static int i915_modeset __read_mostly = 1;
  55. MODULE_PARM_DESC(modeset,
  56.                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  57.                 "1=on, -1=force vga console preference [default])");
  58.  
  59.  
  60. int i915_panel_ignore_lid __read_mostly         =  0;
  61. MODULE_PARM_DESC(panel_ignore_lid,
  62.                 "Override lid status (0=autodetect [default], 1=lid open, "
  63.                 "-1=lid closed)");
  64.  
  65. unsigned int i915_powersave  __read_mostly      =  0;
  66. MODULE_PARM_DESC(powersave,
  67.                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  68.  
  69. int i915_semaphores __read_mostly = -1;
  70.  
  71. MODULE_PARM_DESC(semaphores,
  72.                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  73.  
  74. int i915_enable_rc6 __read_mostly      = 0;
  75. MODULE_PARM_DESC(i915_enable_rc6,
  76.                 "Enable power-saving render C-state 6. "
  77.                 "Different stages can be selected via bitmask values "
  78.                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  79.                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  80.                 "default: -1 (use per-chip default)");
  81.  
  82. int i915_enable_fbc __read_mostly      =  0;
  83. MODULE_PARM_DESC(i915_enable_fbc,
  84.                 "Enable frame buffer compression for power savings "
  85.                 "(default: -1 (use per-chip default))");
  86.  
  87. unsigned int i915_lvds_downclock  __read_mostly =  0;
  88. MODULE_PARM_DESC(lvds_downclock,
  89.                 "Use panel (LVDS/eDP) downclocking for power savings "
  90.                 "(default: false)");
  91.  
  92. int i915_lvds_channel_mode __read_mostly;
  93. MODULE_PARM_DESC(lvds_channel_mode,
  94.                  "Specify LVDS channel mode "
  95.                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  96.  
  97. int i915_panel_use_ssc __read_mostly = -1;
  98. MODULE_PARM_DESC(lvds_use_ssc,
  99.                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  100.                 "(default: auto from VBT)");
  101.  
  102. int i915_vbt_sdvo_panel_type __read_mostly      = -1;
  103. MODULE_PARM_DESC(vbt_sdvo_panel_type,
  104.                 "Override/Ignore selection of SDVO panel mode in the VBT "
  105.                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
  106.  
  107. static bool i915_try_reset __read_mostly = true;
  108. MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  109.  
  110. bool i915_enable_hangcheck __read_mostly = false;
  111. MODULE_PARM_DESC(enable_hangcheck,
  112.                 "Periodically check GPU activity for detecting hangs. "
  113.                 "WARNING: Disabling this can cause system wide hangs. "
  114.                 "(default: true)");
  115.  
  116. int i915_enable_ppgtt __read_mostly = false;
  117. MODULE_PARM_DESC(i915_enable_ppgtt,
  118.                 "Enable PPGTT (default: true)");
  119.  
  120. unsigned int i915_preliminary_hw_support __read_mostly = true;
  121. MODULE_PARM_DESC(preliminary_hw_support,
  122.                 "Enable preliminary hardware support. "
  123.                 "Enable Haswell and ValleyView Support. "
  124.                 "(default: false)");
  125.  
  126.  
  127. #define PCI_VENDOR_ID_INTEL        0x8086
  128.  
  129. #define INTEL_VGA_DEVICE(id, info) {        \
  130.         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
  131.     .class_mask = 0xff0000,                 \
  132.     .vendor = 0x8086,                       \
  133.     .device = id,                           \
  134.     .subvendor = PCI_ANY_ID,                \
  135.     .subdevice = PCI_ANY_ID,                \
  136.     .driver_data = (unsigned long) info }
  137.  
  138.  
  139. static const struct intel_device_info intel_i915g_info = {
  140.         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  141.         .has_overlay = 1, .overlay_needs_physical = 1,
  142. };
  143. static const struct intel_device_info intel_i915gm_info = {
  144.         .gen = 3, .is_mobile = 1,
  145.         .cursor_needs_physical = 1,
  146.         .has_overlay = 1, .overlay_needs_physical = 1,
  147.         .supports_tv = 1,
  148. };
  149. static const struct intel_device_info intel_i945g_info = {
  150.         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  151.         .has_overlay = 1, .overlay_needs_physical = 1,
  152. };
  153. static const struct intel_device_info intel_i945gm_info = {
  154.         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  155.         .has_hotplug = 1, .cursor_needs_physical = 1,
  156.         .has_overlay = 1, .overlay_needs_physical = 1,
  157.         .supports_tv = 1,
  158. };
  159.  
  160. static const struct intel_device_info intel_i965g_info = {
  161.         .gen = 4, .is_broadwater = 1,
  162.         .has_hotplug = 1,
  163.         .has_overlay = 1,
  164. };
  165.  
  166. static const struct intel_device_info intel_i965gm_info = {
  167.         .gen = 4, .is_crestline = 1,
  168.         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  169.         .has_overlay = 1,
  170.         .supports_tv = 1,
  171. };
  172.  
  173. static const struct intel_device_info intel_g33_info = {
  174.         .gen = 3, .is_g33 = 1,
  175.         .need_gfx_hws = 1, .has_hotplug = 1,
  176.         .has_overlay = 1,
  177. };
  178.  
  179. static const struct intel_device_info intel_g45_info = {
  180.         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
  181.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  182.         .has_bsd_ring = 1,
  183. };
  184.  
  185. static const struct intel_device_info intel_gm45_info = {
  186.         .gen = 4, .is_g4x = 1,
  187.         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
  188.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  189.         .supports_tv = 1,
  190.         .has_bsd_ring = 1,
  191. };
  192.  
  193. static const struct intel_device_info intel_pineview_info = {
  194.         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
  195.         .need_gfx_hws = 1, .has_hotplug = 1,
  196.         .has_overlay = 1,
  197. };
  198.  
  199. static const struct intel_device_info intel_ironlake_d_info = {
  200.         .gen = 5,
  201.         .need_gfx_hws = 1, .has_hotplug = 1,
  202.         .has_bsd_ring = 1,
  203. };
  204.  
  205. static const struct intel_device_info intel_ironlake_m_info = {
  206.         .gen = 5, .is_mobile = 1,
  207.         .need_gfx_hws = 1, .has_hotplug = 1,
  208.         .has_fbc = 1,
  209.         .has_bsd_ring = 1,
  210. };
  211.  
  212. static const struct intel_device_info intel_sandybridge_d_info = {
  213.     .gen = 6,
  214.         .need_gfx_hws = 1, .has_hotplug = 1,
  215.     .has_bsd_ring = 1,
  216.     .has_blt_ring = 1,
  217.         .has_llc = 1,
  218.         .has_force_wake = 1,
  219. };
  220.  
  221. static const struct intel_device_info intel_sandybridge_m_info = {
  222.         .gen = 6, .is_mobile = 1,
  223.         .need_gfx_hws = 1, .has_hotplug = 1,
  224.     .has_fbc      = 1,
  225.     .has_bsd_ring = 1,
  226.     .has_blt_ring = 1,
  227.         .has_llc = 1,
  228.         .has_force_wake = 1,
  229. };
  230.  
  231. static const struct intel_device_info intel_ivybridge_d_info = {
  232.         .is_ivybridge = 1, .gen = 7,
  233.         .need_gfx_hws = 1, .has_hotplug = 1,
  234.         .has_bsd_ring = 1,
  235.         .has_blt_ring = 1,
  236.         .has_llc = 1,
  237.         .has_force_wake = 1,
  238. };
  239.  
  240. static const struct intel_device_info intel_ivybridge_m_info = {
  241.         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
  242.         .need_gfx_hws = 1, .has_hotplug = 1,
  243.         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
  244.         .has_bsd_ring = 1,
  245.         .has_blt_ring = 1,
  246.         .has_llc = 1,
  247.         .has_force_wake = 1,
  248. };
  249.  
  250. static const struct intel_device_info intel_valleyview_m_info = {
  251.         .gen = 7, .is_mobile = 1,
  252.         .need_gfx_hws = 1, .has_hotplug = 1,
  253.         .has_fbc = 0,
  254.         .has_bsd_ring = 1,
  255.         .has_blt_ring = 1,
  256.         .is_valleyview = 1,
  257. };
  258.  
  259. static const struct intel_device_info intel_valleyview_d_info = {
  260.         .gen = 7,
  261.         .need_gfx_hws = 1, .has_hotplug = 1,
  262.         .has_fbc = 0,
  263.         .has_bsd_ring = 1,
  264.         .has_blt_ring = 1,
  265.         .is_valleyview = 1,
  266. };
  267.  
  268. static const struct intel_device_info intel_haswell_d_info = {
  269.         .is_haswell = 1, .gen = 7,
  270.         .need_gfx_hws = 1, .has_hotplug = 1,
  271.         .has_bsd_ring = 1,
  272.         .has_blt_ring = 1,
  273.         .has_llc = 1,
  274.         .has_force_wake = 1,
  275. };
  276.  
  277. static const struct intel_device_info intel_haswell_m_info = {
  278.         .is_haswell = 1, .gen = 7, .is_mobile = 1,
  279.         .need_gfx_hws = 1, .has_hotplug = 1,
  280.         .has_bsd_ring = 1,
  281.         .has_blt_ring = 1,
  282.         .has_llc = 1,
  283.         .has_force_wake = 1,
  284. };
  285.  
  286. static const struct pci_device_id pciidlist[] = {       /* aka */
  287.         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
  288.         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
  289.         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
  290.         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
  291.         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
  292.         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
  293.         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
  294.         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
  295.         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
  296.         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
  297.         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
  298.         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
  299.         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
  300.         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
  301.         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
  302.         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
  303.         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
  304.         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
  305.         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
  306.         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
  307.         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
  308.         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
  309.         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  310.         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  311.         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  312.         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  313.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  314.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  315.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  316.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  317.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  318.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  319.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  320.         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
  321.         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
  322.         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
  323.         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
  324.         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
  325.         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
  326.         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
  327.         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
  328.         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
  329.         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
  330.         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
  331.         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
  332.         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
  333.         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
  334.         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
  335.         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
  336.         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
  337.         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
  338.         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
  339.         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
  340.         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
  341.         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
  342.         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
  343.         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
  344.         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
  345.         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
  346.         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
  347.         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
  348.         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
  349.         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
  350.         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
  351.         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
  352.         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
  353.         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
  354.         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
  355.         INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
  356.         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
  357.         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
  358.         INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
  359.         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
  360.         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
  361.         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
  362.         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
  363.         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
  364.         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
  365.     {0, 0, 0}
  366. };
  367.  
  368. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  369. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  370. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  371. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  372. #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
  373.  
  374. void intel_detect_pch(struct drm_device *dev)
  375. {
  376.     struct drm_i915_private *dev_priv = dev->dev_private;
  377.     struct pci_dev *pch;
  378.  
  379.     /*
  380.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  381.      * make graphics device passthrough work easy for VMM, that only
  382.      * need to expose ISA bridge to let driver know the real hardware
  383.      * underneath. This is a requirement from virtualization team.
  384.      */
  385.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  386.     if (pch) {
  387.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  388.                         unsigned short id;
  389.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  390.                         dev_priv->pch_id = id;
  391.  
  392.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  393.                 dev_priv->pch_type = PCH_IBX;
  394.                                 dev_priv->num_pch_pll = 2;
  395.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  396.                                 WARN_ON(!IS_GEN5(dev));
  397.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  398.                 dev_priv->pch_type = PCH_CPT;
  399.                                 dev_priv->num_pch_pll = 2;
  400.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  401.                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  402.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  403.                 /* PantherPoint is CPT compatible */
  404.                 dev_priv->pch_type = PCH_CPT;
  405.                                 dev_priv->num_pch_pll = 2;
  406.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  407.                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  408.                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  409.                                 dev_priv->pch_type = PCH_LPT;
  410.                                 dev_priv->num_pch_pll = 0;
  411.                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
  412.                                 WARN_ON(!IS_HASWELL(dev));
  413.                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  414.                                 dev_priv->pch_type = PCH_LPT;
  415.                                 dev_priv->num_pch_pll = 0;
  416.                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
  417.                                 WARN_ON(!IS_HASWELL(dev));
  418.             }
  419.                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
  420.         }
  421.     }
  422. }
  423.  
  424. bool i915_semaphore_is_enabled(struct drm_device *dev)
  425. {
  426.         if (INTEL_INFO(dev)->gen < 6)
  427.                 return 0;
  428.  
  429.         if (i915_semaphores >= 0)
  430.                 return i915_semaphores;
  431.  
  432. #ifdef CONFIG_INTEL_IOMMU
  433.         /* Enable semaphores on SNB when IO remapping is off */
  434.         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
  435.                 return false;
  436. #endif
  437.  
  438.         return 1;
  439. }
  440.  
  441.  
  442.  
  443.  
  444.  
  445. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  446.  
  447. int i915_init(void)
  448. {
  449.     static pci_dev_t device;
  450.     const struct pci_device_id  *ent;
  451.     int  err;
  452.  
  453.     ent = find_pci_device(&device, pciidlist);
  454.     if( unlikely(ent == NULL) )
  455.     {
  456.         dbgprintf("device not found\n");
  457.         return 0;
  458.     };
  459.  
  460.     struct intel_device_info *intel_info =
  461.         (struct intel_device_info *) ent->driver_data;
  462.  
  463.         if (intel_info->is_valleyview)
  464.         if(!i915_preliminary_hw_support) {
  465.             DRM_ERROR("Preliminary hardware support disabled\n");
  466.             return -ENODEV;
  467.         }
  468.  
  469.     DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
  470.                                 device.pci_dev.device);
  471.  
  472.     if (intel_info->gen != 3) {
  473.  
  474.     } else if (init_agp() != 0) {
  475.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  476.         return -ENODEV;
  477.     }
  478.  
  479.     err = drm_get_dev(&device.pci_dev, ent);
  480.  
  481.     return err;
  482. }
  483.  
  484.  
  485.  
  486. static struct drm_driver driver = {
  487.     /* Don't use MTRRs here; the Xserver or userspace app should
  488.      * deal with them for Intel hardware.
  489.      */
  490. //    .driver_features =
  491. //        DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  492. //        DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
  493. //    .load = i915_driver_load,
  494. //    .unload = i915_driver_unload,
  495.       .open = i915_driver_open,
  496. //    .lastclose = i915_driver_lastclose,
  497. //    .preclose = i915_driver_preclose,
  498. //    .postclose = i915_driver_postclose,
  499.  
  500.     /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  501. //    .suspend = i915_suspend,
  502. //    .resume = i915_resume,
  503.  
  504. //    .device_is_agp = i915_driver_device_is_agp,
  505. //    .master_create = i915_master_create,
  506. //    .master_destroy = i915_master_destroy,
  507.     .gem_init_object = i915_gem_init_object,
  508.     .gem_free_object = i915_gem_free_object,
  509. //    .gem_vm_ops = &i915_gem_vm_ops,
  510.  
  511. //    .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  512. //    .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  513. //    .gem_prime_export = i915_gem_prime_export,
  514. //    .gem_prime_import = i915_gem_prime_import,
  515.  
  516. //    .dumb_create = i915_gem_dumb_create,
  517. //    .dumb_map_offset = i915_gem_mmap_gtt,
  518. //    .dumb_destroy = i915_gem_dumb_destroy,
  519. //    .ioctls = i915_ioctls,
  520. //    .fops = &i915_driver_fops,
  521. //    .name = DRIVER_NAME,
  522. //    .desc = DRIVER_DESC,
  523. //    .date = DRIVER_DATE,
  524. //    .major = DRIVER_MAJOR,
  525. //    .minor = DRIVER_MINOR,
  526. //    .patchlevel = DRIVER_PATCHLEVEL,
  527. };
  528.  
  529.  
  530. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  531. {
  532.     static struct drm_device drm_dev;
  533.     static struct drm_file   drm_file;
  534.  
  535.     struct drm_device *dev;
  536.     struct drm_file   *priv;
  537.  
  538.     int ret;
  539.  
  540.     dev  = &drm_dev;
  541.     priv = &drm_file;
  542.  
  543.     drm_file_handlers[0] = priv;
  544.  
  545.  //   ret = pci_enable_device(pdev);
  546.  //   if (ret)
  547.  //       goto err_g1;
  548.  
  549.     pci_set_master(pdev);
  550.  
  551.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  552.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  553.  //       goto err_g2;
  554.  //   }
  555.  
  556.     dev->pdev = pdev;
  557.     dev->pci_device = pdev->device;
  558.     dev->pci_vendor = pdev->vendor;
  559.  
  560.     INIT_LIST_HEAD(&dev->filelist);
  561.     INIT_LIST_HEAD(&dev->ctxlist);
  562.     INIT_LIST_HEAD(&dev->vmalist);
  563.     INIT_LIST_HEAD(&dev->maplist);
  564.  
  565.     spin_lock_init(&dev->count_lock);
  566.     mutex_init(&dev->struct_mutex);
  567.     mutex_init(&dev->ctxlist_mutex);
  568.  
  569.     INIT_LIST_HEAD(&priv->lhead);
  570.     INIT_LIST_HEAD(&priv->fbs);
  571.     INIT_LIST_HEAD(&priv->event_list);
  572.     init_waitqueue_head(&priv->event_wait);
  573.     priv->event_space = 4096; /* set aside 4k for event buffer */
  574.  
  575.     idr_init(&priv->object_idr);
  576.     spin_lock_init(&priv->table_lock);
  577.  
  578.     dev->driver = &driver;
  579.  
  580.     if (dev->driver->open) {
  581.         ret = dev->driver->open(dev, priv);
  582.         if (ret < 0)
  583.             goto err_g4;
  584.     }
  585.  
  586.     ret = i915_driver_load(dev, ent->driver_data );
  587.  
  588.     if (ret)
  589.         goto err_g4;
  590.  
  591.     ret = init_display_kms(dev);
  592.  
  593.     if (ret)
  594.         goto err_g4;
  595.  
  596.     return 0;
  597.  
  598. err_g4:
  599. //err_g3:
  600. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  601. //        drm_put_minor(&dev->control);
  602. //err_g2:
  603. //    pci_disable_device(pdev);
  604. //err_g1:
  605.  
  606.     return ret;
  607. }
  608.  
  609. /* We give fast paths for the really cool registers */
  610. #define NEEDS_FORCE_WAKE(dev_priv, reg) \
  611.         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
  612.          ((reg) < 0x40000) &&            \
  613.          ((reg) != FORCEWAKE))
  614.  
  615. static bool IS_DISPLAYREG(u32 reg)
  616. {
  617.         /*
  618.          * This should make it easier to transition modules over to the
  619.          * new register block scheme, since we can do it incrementally.
  620.          */
  621.         if (reg >= VLV_DISPLAY_BASE)
  622.                 return false;
  623.  
  624.         if (reg >= RENDER_RING_BASE &&
  625.             reg < RENDER_RING_BASE + 0xff)
  626.                 return false;
  627.         if (reg >= GEN6_BSD_RING_BASE &&
  628.             reg < GEN6_BSD_RING_BASE + 0xff)
  629.                 return false;
  630.         if (reg >= BLT_RING_BASE &&
  631.             reg < BLT_RING_BASE + 0xff)
  632.                 return false;
  633.  
  634.         if (reg == PGTBL_ER)
  635.                 return false;
  636.  
  637.         if (reg >= IPEIR_I965 &&
  638.             reg < HWSTAM)
  639.                 return false;
  640.  
  641.         if (reg == MI_MODE)
  642.                 return false;
  643.  
  644.         if (reg == GFX_MODE_GEN7)
  645.                 return false;
  646.  
  647.         if (reg == RENDER_HWS_PGA_GEN7 ||
  648.             reg == BSD_HWS_PGA_GEN7 ||
  649.             reg == BLT_HWS_PGA_GEN7)
  650.                 return false;
  651.  
  652.         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
  653.             reg == GEN6_BSD_RNCID)
  654.                 return false;
  655.  
  656.         if (reg == GEN6_BLITTER_ECOSKPD)
  657.                 return false;
  658.  
  659.         if (reg >= 0x4000c &&
  660.             reg <= 0x4002c)
  661.                 return false;
  662.  
  663.         if (reg >= 0x4f000 &&
  664.             reg <= 0x4f08f)
  665.                 return false;
  666.  
  667.         if (reg >= 0x4f100 &&
  668.             reg <= 0x4f11f)
  669.                 return false;
  670.  
  671.         if (reg >= VLV_MASTER_IER &&
  672.             reg <= GEN6_PMIER)
  673.                 return false;
  674.  
  675.         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
  676.             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
  677.                 return false;
  678.  
  679.         if (reg >= VLV_IIR_RW &&
  680.             reg <= VLV_ISR)
  681.                 return false;
  682.  
  683.         if (reg == FORCEWAKE_VLV ||
  684.             reg == FORCEWAKE_ACK_VLV)
  685.                 return false;
  686.  
  687.         if (reg == GEN6_GDRST)
  688.                 return false;
  689.  
  690.         switch (reg) {
  691.         case _3D_CHICKEN3:
  692.         case IVB_CHICKEN3:
  693.         case GEN7_COMMON_SLICE_CHICKEN1:
  694.         case GEN7_L3CNTLREG1:
  695.         case GEN7_L3_CHICKEN_MODE_REGISTER:
  696.         case GEN7_ROW_CHICKEN2:
  697.         case GEN7_L3SQCREG4:
  698.         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
  699.         case GEN7_HALF_SLICE_CHICKEN1:
  700.         case GEN6_MBCTL:
  701.         case GEN6_UCGCTL2:
  702.                 return false;
  703.         default:
  704.                 break;
  705.         }
  706.  
  707.         return true;
  708. }
  709.  
  710. static void
  711. ilk_dummy_write(struct drm_i915_private *dev_priv)
  712. {
  713.         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
  714.          * chip from rc6 before touching it for real. MI_MODE is masked, hence
  715.          * harmless to write 0 into. */
  716.         I915_WRITE_NOTRACE(MI_MODE, 0);
  717. }
  718.  
  719. #define __i915_read(x, y) \
  720. u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
  721.         u##x val = 0; \
  722.         if (IS_GEN5(dev_priv->dev)) \
  723.                 ilk_dummy_write(dev_priv); \
  724.         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  725.                 unsigned long irqflags; \
  726.                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
  727.                 if (dev_priv->forcewake_count == 0) \
  728.                         dev_priv->gt.force_wake_get(dev_priv); \
  729.                 val = read##y(dev_priv->regs + reg); \
  730.                 if (dev_priv->forcewake_count == 0) \
  731.                         dev_priv->gt.force_wake_put(dev_priv); \
  732.                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
  733.         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
  734.                 val = read##y(dev_priv->regs + reg + 0x180000);         \
  735.         } else { \
  736.                 val = read##y(dev_priv->regs + reg); \
  737.         } \
  738.         return val; \
  739. }
  740.  
  741. __i915_read(8, b)
  742. __i915_read(16, w)
  743. __i915_read(32, l)
  744. __i915_read(64, q)
  745. #undef __i915_read
  746.  
  747. #define __i915_write(x, y) \
  748. void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
  749.         u32 __fifo_ret = 0; \
  750.         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
  751.         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  752.                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
  753.         } \
  754.         if (IS_GEN5(dev_priv->dev)) \
  755.                 ilk_dummy_write(dev_priv); \
  756.         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  757.                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
  758.                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
  759.         } \
  760.         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
  761.                 write##y(val, dev_priv->regs + reg + 0x180000);         \
  762.         } else {                                                        \
  763.         write##y(val, dev_priv->regs + reg); \
  764.         }                                                               \
  765.         if (unlikely(__fifo_ret)) { \
  766.                 gen6_gt_check_fifodbg(dev_priv); \
  767.         } \
  768.         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  769.                 DRM_ERROR("Unclaimed write to %x\n", reg); \
  770.                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
  771.         } \
  772. }
  773. __i915_write(8, b)
  774. __i915_write(16, w)
  775. __i915_write(32, l)
  776. __i915_write(64, q)
  777. #undef __i915_write
  778.