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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. //#include <linux/device.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "intel_drv.h"
  35.  
  36.  
  37. #include <linux/kernel.h>
  38. #include <linux/module.h>
  39. #include <linux/mod_devicetable.h>
  40. #include <errno-base.h>
  41. #include <linux/pci.h>
  42.  
  43. #include <drm/drm_crtc_helper.h>
  44.  
  45. #include <syscall.h>
  46.  
  47. #define __read_mostly
  48.  
  49. int init_display_kms(struct drm_device *dev);
  50.  
  51. struct drm_device *main_device;
  52.  
  53. static int i915_modeset __read_mostly = 1;
  54. MODULE_PARM_DESC(modeset,
  55.                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  56.                 "1=on, -1=force vga console preference [default])");
  57.  
  58.  
  59. int i915_panel_ignore_lid __read_mostly         =  0;
  60. MODULE_PARM_DESC(panel_ignore_lid,
  61.                 "Override lid status (0=autodetect [default], 1=lid open, "
  62.                 "-1=lid closed)");
  63.  
  64. unsigned int i915_powersave  __read_mostly      =  0;
  65. MODULE_PARM_DESC(powersave,
  66.                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  67.  
  68. int i915_semaphores __read_mostly = -1;
  69.  
  70. MODULE_PARM_DESC(semaphores,
  71.                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  72.  
  73. int i915_enable_rc6 __read_mostly      = 0;
  74. MODULE_PARM_DESC(i915_enable_rc6,
  75.                 "Enable power-saving render C-state 6. "
  76.                 "Different stages can be selected via bitmask values "
  77.                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  78.                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  79.                 "default: -1 (use per-chip default)");
  80.  
  81. int i915_enable_fbc __read_mostly      =  0;
  82. MODULE_PARM_DESC(i915_enable_fbc,
  83.                 "Enable frame buffer compression for power savings "
  84.                 "(default: -1 (use per-chip default))");
  85.  
  86. unsigned int i915_lvds_downclock  __read_mostly =  0;
  87. MODULE_PARM_DESC(lvds_downclock,
  88.                 "Use panel (LVDS/eDP) downclocking for power savings "
  89.                 "(default: false)");
  90.  
  91. int i915_lvds_channel_mode __read_mostly;
  92. MODULE_PARM_DESC(lvds_channel_mode,
  93.                  "Specify LVDS channel mode "
  94.                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  95.  
  96. int i915_panel_use_ssc __read_mostly = -1;
  97. MODULE_PARM_DESC(lvds_use_ssc,
  98.                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  99.                 "(default: auto from VBT)");
  100.  
  101. int i915_vbt_sdvo_panel_type __read_mostly      = -1;
  102. MODULE_PARM_DESC(vbt_sdvo_panel_type,
  103.                 "Override/Ignore selection of SDVO panel mode in the VBT "
  104.                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
  105.  
  106. static bool i915_try_reset __read_mostly = true;
  107. MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  108.  
  109. bool i915_enable_hangcheck __read_mostly = false;
  110. MODULE_PARM_DESC(enable_hangcheck,
  111.                 "Periodically check GPU activity for detecting hangs. "
  112.                 "WARNING: Disabling this can cause system wide hangs. "
  113.                 "(default: true)");
  114.  
  115. int i915_enable_ppgtt __read_mostly = false;
  116. MODULE_PARM_DESC(i915_enable_ppgtt,
  117.                 "Enable PPGTT (default: true)");
  118.  
  119. unsigned int i915_preliminary_hw_support __read_mostly = true;
  120. MODULE_PARM_DESC(preliminary_hw_support,
  121.                 "Enable preliminary hardware support. "
  122.                 "Enable Haswell and ValleyView Support. "
  123.                 "(default: false)");
  124.  
  125.  
  126. #define PCI_VENDOR_ID_INTEL        0x8086
  127.  
  128. #define INTEL_VGA_DEVICE(id, info) {        \
  129.         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
  130.     .class_mask = 0xff0000,                 \
  131.     .vendor = 0x8086,                       \
  132.     .device = id,                           \
  133.     .subvendor = PCI_ANY_ID,                \
  134.     .subdevice = PCI_ANY_ID,                \
  135.     .driver_data = (unsigned long) info }
  136.  
  137.  
  138. static const struct intel_device_info intel_i915g_info = {
  139.         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  140.         .has_overlay = 1, .overlay_needs_physical = 1,
  141. };
  142. static const struct intel_device_info intel_i915gm_info = {
  143.         .gen = 3, .is_mobile = 1,
  144.         .cursor_needs_physical = 1,
  145.         .has_overlay = 1, .overlay_needs_physical = 1,
  146.         .supports_tv = 1,
  147. };
  148. static const struct intel_device_info intel_i945g_info = {
  149.         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  150.         .has_overlay = 1, .overlay_needs_physical = 1,
  151. };
  152. static const struct intel_device_info intel_i945gm_info = {
  153.         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  154.         .has_hotplug = 1, .cursor_needs_physical = 1,
  155.         .has_overlay = 1, .overlay_needs_physical = 1,
  156.         .supports_tv = 1,
  157. };
  158.  
  159. static const struct intel_device_info intel_i965g_info = {
  160.         .gen = 4, .is_broadwater = 1,
  161.         .has_hotplug = 1,
  162.         .has_overlay = 1,
  163. };
  164.  
  165. static const struct intel_device_info intel_i965gm_info = {
  166.         .gen = 4, .is_crestline = 1,
  167.         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  168.         .has_overlay = 1,
  169.         .supports_tv = 1,
  170. };
  171.  
  172. static const struct intel_device_info intel_g33_info = {
  173.         .gen = 3, .is_g33 = 1,
  174.         .need_gfx_hws = 1, .has_hotplug = 1,
  175.         .has_overlay = 1,
  176. };
  177.  
  178. static const struct intel_device_info intel_g45_info = {
  179.         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
  180.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  181.         .has_bsd_ring = 1,
  182. };
  183.  
  184. static const struct intel_device_info intel_gm45_info = {
  185.         .gen = 4, .is_g4x = 1,
  186.         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
  187.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  188.         .supports_tv = 1,
  189.         .has_bsd_ring = 1,
  190. };
  191.  
  192. static const struct intel_device_info intel_pineview_info = {
  193.         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
  194.         .need_gfx_hws = 1, .has_hotplug = 1,
  195.         .has_overlay = 1,
  196. };
  197.  
  198. static const struct intel_device_info intel_ironlake_d_info = {
  199.         .gen = 5,
  200.         .need_gfx_hws = 1, .has_hotplug = 1,
  201.         .has_bsd_ring = 1,
  202. };
  203.  
  204. static const struct intel_device_info intel_ironlake_m_info = {
  205.         .gen = 5, .is_mobile = 1,
  206.         .need_gfx_hws = 1, .has_hotplug = 1,
  207.         .has_fbc = 1,
  208.         .has_bsd_ring = 1,
  209. };
  210.  
  211. static const struct intel_device_info intel_sandybridge_d_info = {
  212.     .gen = 6,
  213.         .need_gfx_hws = 1, .has_hotplug = 1,
  214.     .has_bsd_ring = 1,
  215.     .has_blt_ring = 1,
  216.         .has_llc = 1,
  217.         .has_force_wake = 1,
  218. };
  219.  
  220. static const struct intel_device_info intel_sandybridge_m_info = {
  221.         .gen = 6, .is_mobile = 1,
  222.         .need_gfx_hws = 1, .has_hotplug = 1,
  223.     .has_fbc      = 1,
  224.     .has_bsd_ring = 1,
  225.     .has_blt_ring = 1,
  226.         .has_llc = 1,
  227.         .has_force_wake = 1,
  228. };
  229.  
  230. static const struct intel_device_info intel_ivybridge_d_info = {
  231.         .is_ivybridge = 1, .gen = 7,
  232.         .need_gfx_hws = 1, .has_hotplug = 1,
  233.         .has_bsd_ring = 1,
  234.         .has_blt_ring = 1,
  235.         .has_llc = 1,
  236.         .has_force_wake = 1,
  237. };
  238.  
  239. static const struct intel_device_info intel_ivybridge_m_info = {
  240.         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
  241.         .need_gfx_hws = 1, .has_hotplug = 1,
  242.         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
  243.         .has_bsd_ring = 1,
  244.         .has_blt_ring = 1,
  245.         .has_llc = 1,
  246.         .has_force_wake = 1,
  247. };
  248.  
  249. static const struct intel_device_info intel_valleyview_m_info = {
  250.         .gen = 7, .is_mobile = 1,
  251.         .need_gfx_hws = 1, .has_hotplug = 1,
  252.         .has_fbc = 0,
  253.         .has_bsd_ring = 1,
  254.         .has_blt_ring = 1,
  255.         .is_valleyview = 1,
  256. };
  257.  
  258. static const struct intel_device_info intel_valleyview_d_info = {
  259.         .gen = 7,
  260.         .need_gfx_hws = 1, .has_hotplug = 1,
  261.         .has_fbc = 0,
  262.         .has_bsd_ring = 1,
  263.         .has_blt_ring = 1,
  264.         .is_valleyview = 1,
  265. };
  266.  
  267. static const struct intel_device_info intel_haswell_d_info = {
  268.         .is_haswell = 1, .gen = 7,
  269.         .need_gfx_hws = 1, .has_hotplug = 1,
  270.         .has_bsd_ring = 1,
  271.         .has_blt_ring = 1,
  272.         .has_llc = 1,
  273.         .has_force_wake = 1,
  274. };
  275.  
  276. static const struct intel_device_info intel_haswell_m_info = {
  277.         .is_haswell = 1, .gen = 7, .is_mobile = 1,
  278.         .need_gfx_hws = 1, .has_hotplug = 1,
  279.         .has_bsd_ring = 1,
  280.         .has_blt_ring = 1,
  281.         .has_llc = 1,
  282.         .has_force_wake = 1,
  283. };
  284.  
  285. static const struct pci_device_id pciidlist[] = {       /* aka */
  286.         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
  287.         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
  288.         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
  289.         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
  290.         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
  291.         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
  292.         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
  293.         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
  294.         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
  295.         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
  296.         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
  297.         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
  298.         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
  299.         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
  300.         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
  301.         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
  302.         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
  303.         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
  304.         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
  305.         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
  306.         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
  307.         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
  308.         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  309.         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  310.         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  311.         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  312.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  313.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  314.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  315.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  316.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  317.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  318.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  319.         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
  320.         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
  321.         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
  322.         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
  323.         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
  324.         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
  325.         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
  326.         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
  327.         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
  328.         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
  329.         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
  330.         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
  331.         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
  332.         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
  333.         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
  334.         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
  335.         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
  336.         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
  337.         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
  338.         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
  339.         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
  340.         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
  341.         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
  342.         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
  343.         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
  344.         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
  345.         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
  346.         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
  347.         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
  348.         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
  349.         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
  350.         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
  351.         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
  352.         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
  353.         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
  354.         INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
  355.         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
  356.         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
  357.         INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
  358.         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
  359.         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
  360.         INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
  361.         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
  362.         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
  363.         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
  364.     {0, 0, 0}
  365. };
  366.  
  367. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  368. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  369. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  370. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  371. #define INTEL_PCH_LPT_DEVICE_ID_TYPE    0x8c00
  372.  
  373. void intel_detect_pch(struct drm_device *dev)
  374. {
  375.     struct drm_i915_private *dev_priv = dev->dev_private;
  376.     struct pci_dev *pch;
  377.  
  378.     /*
  379.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  380.      * make graphics device passthrough work easy for VMM, that only
  381.      * need to expose ISA bridge to let driver know the real hardware
  382.      * underneath. This is a requirement from virtualization team.
  383.      */
  384.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  385.     if (pch) {
  386.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  387.             int id;
  388.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  389.  
  390.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  391.                 dev_priv->pch_type = PCH_IBX;
  392.                                 dev_priv->num_pch_pll = 2;
  393.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  394.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  395.                 dev_priv->pch_type = PCH_CPT;
  396.                                 dev_priv->num_pch_pll = 2;
  397.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  398.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  399.                 /* PantherPoint is CPT compatible */
  400.                 dev_priv->pch_type = PCH_CPT;
  401.                                 dev_priv->num_pch_pll = 2;
  402.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  403.                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  404.                                 dev_priv->pch_type = PCH_LPT;
  405.                                 dev_priv->num_pch_pll = 0;
  406.                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
  407.             }
  408.                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
  409.         }
  410.     }
  411. }
  412.  
  413. bool i915_semaphore_is_enabled(struct drm_device *dev)
  414. {
  415.         if (INTEL_INFO(dev)->gen < 6)
  416.                 return 0;
  417.  
  418.         if (i915_semaphores >= 0)
  419.                 return i915_semaphores;
  420.  
  421. #ifdef CONFIG_INTEL_IOMMU
  422.         /* Enable semaphores on SNB when IO remapping is off */
  423.         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
  424.                 return false;
  425. #endif
  426.  
  427.         return 1;
  428. }
  429.  
  430.  
  431.  
  432.  
  433.  
  434. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  435.  
  436. int i915_init(void)
  437. {
  438.     static pci_dev_t device;
  439.     const struct pci_device_id  *ent;
  440.     int  err;
  441.  
  442.     ent = find_pci_device(&device, pciidlist);
  443.     if( unlikely(ent == NULL) )
  444.     {
  445.         dbgprintf("device not found\n");
  446.         return 0;
  447.     };
  448.  
  449.     struct intel_device_info *intel_info =
  450.         (struct intel_device_info *) ent->driver_data;
  451.  
  452.     if (intel_info->is_haswell || intel_info->is_valleyview)
  453.         if(!i915_preliminary_hw_support) {
  454.             DRM_ERROR("Preliminary hardware support disabled\n");
  455.             return -ENODEV;
  456.         }
  457.  
  458.     DRM_INFO("device %x:%x\n", device.pci_dev.vendor,
  459.                                 device.pci_dev.device);
  460.  
  461.     if (intel_info->gen != 3) {
  462.  
  463.     } else if (init_agp() != 0) {
  464.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  465.         return -ENODEV;
  466.     }
  467.  
  468.     err = drm_get_dev(&device.pci_dev, ent);
  469.  
  470.     return err;
  471. }
  472.  
  473. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  474. {
  475.     struct drm_device *dev;
  476.     int ret;
  477.  
  478.     dev = kzalloc(sizeof(*dev), 0);
  479.     if (!dev)
  480.         return -ENOMEM;
  481.  
  482.  //   ret = pci_enable_device(pdev);
  483.  //   if (ret)
  484.  //       goto err_g1;
  485.  
  486.     pci_set_master(pdev);
  487.  
  488.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  489.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  490.  //       goto err_g2;
  491.  //   }
  492.  
  493.     dev->pdev = pdev;
  494.     dev->pci_device = pdev->device;
  495.     dev->pci_vendor = pdev->vendor;
  496.  
  497.     INIT_LIST_HEAD(&dev->filelist);
  498.     INIT_LIST_HEAD(&dev->ctxlist);
  499.     INIT_LIST_HEAD(&dev->vmalist);
  500.     INIT_LIST_HEAD(&dev->maplist);
  501.  
  502.     spin_lock_init(&dev->count_lock);
  503.     mutex_init(&dev->struct_mutex);
  504.     mutex_init(&dev->ctxlist_mutex);
  505.  
  506.     ret = i915_driver_load(dev, ent->driver_data );
  507.  
  508.     if (ret)
  509.         goto err_g4;
  510.  
  511.     ret = init_display_kms(dev);
  512.  
  513.     if (ret)
  514.         goto err_g4;
  515.  
  516.     return 0;
  517.  
  518. err_g4:
  519. //    drm_put_minor(&dev->primary);
  520. //err_g3:
  521. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  522. //        drm_put_minor(&dev->control);
  523. //err_g2:
  524. //    pci_disable_device(pdev);
  525. //err_g1:
  526.     free(dev);
  527.  
  528.     return ret;
  529. }
  530.  
  531. /* We give fast paths for the really cool registers */
  532. #define NEEDS_FORCE_WAKE(dev_priv, reg) \
  533.         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
  534.          ((reg) < 0x40000) &&            \
  535.          ((reg) != FORCEWAKE))
  536.  
  537. static bool IS_DISPLAYREG(u32 reg)
  538. {
  539.         /*
  540.          * This should make it easier to transition modules over to the
  541.          * new register block scheme, since we can do it incrementally.
  542.          */
  543.         if (reg >= VLV_DISPLAY_BASE)
  544.                 return false;
  545.  
  546.         if (reg >= RENDER_RING_BASE &&
  547.             reg < RENDER_RING_BASE + 0xff)
  548.                 return false;
  549.         if (reg >= GEN6_BSD_RING_BASE &&
  550.             reg < GEN6_BSD_RING_BASE + 0xff)
  551.                 return false;
  552.         if (reg >= BLT_RING_BASE &&
  553.             reg < BLT_RING_BASE + 0xff)
  554.                 return false;
  555.  
  556.         if (reg == PGTBL_ER)
  557.                 return false;
  558.  
  559.         if (reg >= IPEIR_I965 &&
  560.             reg < HWSTAM)
  561.                 return false;
  562.  
  563.         if (reg == MI_MODE)
  564.                 return false;
  565.  
  566.         if (reg == GFX_MODE_GEN7)
  567.                 return false;
  568.  
  569.         if (reg == RENDER_HWS_PGA_GEN7 ||
  570.             reg == BSD_HWS_PGA_GEN7 ||
  571.             reg == BLT_HWS_PGA_GEN7)
  572.                 return false;
  573.  
  574.         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
  575.             reg == GEN6_BSD_RNCID)
  576.                 return false;
  577.  
  578.         if (reg == GEN6_BLITTER_ECOSKPD)
  579.                 return false;
  580.  
  581.         if (reg >= 0x4000c &&
  582.             reg <= 0x4002c)
  583.                 return false;
  584.  
  585.         if (reg >= 0x4f000 &&
  586.             reg <= 0x4f08f)
  587.                 return false;
  588.  
  589.         if (reg >= 0x4f100 &&
  590.             reg <= 0x4f11f)
  591.                 return false;
  592.  
  593.         if (reg >= VLV_MASTER_IER &&
  594.             reg <= GEN6_PMIER)
  595.                 return false;
  596.  
  597.         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
  598.             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
  599.                 return false;
  600.  
  601.         if (reg >= VLV_IIR_RW &&
  602.             reg <= VLV_ISR)
  603.                 return false;
  604.  
  605.         if (reg == FORCEWAKE_VLV ||
  606.             reg == FORCEWAKE_ACK_VLV)
  607.                 return false;
  608.  
  609.         if (reg == GEN6_GDRST)
  610.                 return false;
  611.  
  612.         return true;
  613. }
  614.  
  615. #define __i915_read(x, y) \
  616. u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
  617.         u##x val = 0; \
  618.         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  619.                 unsigned long irqflags; \
  620.                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
  621.                 if (dev_priv->forcewake_count == 0) \
  622.                         dev_priv->gt.force_wake_get(dev_priv); \
  623.                 val = read##y(dev_priv->regs + reg); \
  624.                 if (dev_priv->forcewake_count == 0) \
  625.                         dev_priv->gt.force_wake_put(dev_priv); \
  626.                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
  627.         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
  628.                 val = read##y(dev_priv->regs + reg + 0x180000);         \
  629.         } else { \
  630.                 val = read##y(dev_priv->regs + reg); \
  631.         } \
  632.         return val; \
  633. }
  634.  
  635. __i915_read(8, b)
  636. __i915_read(16, w)
  637. __i915_read(32, l)
  638. __i915_read(64, q)
  639. #undef __i915_read
  640.  
  641. #define __i915_write(x, y) \
  642. void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
  643.         u32 __fifo_ret = 0; \
  644.         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
  645.         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  646.                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
  647.         } \
  648.         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
  649.                 write##y(val, dev_priv->regs + reg + 0x180000);         \
  650.         } else {                                                        \
  651.         write##y(val, dev_priv->regs + reg); \
  652.         }                                                               \
  653.         if (unlikely(__fifo_ret)) { \
  654.                 gen6_gt_check_fifodbg(dev_priv); \
  655.         } \
  656.         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  657.                 DRM_ERROR("Unclaimed write to %x\n", reg); \
  658.                 writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT);  \
  659.         } \
  660. }
  661. __i915_write(8, b)
  662. __i915_write(16, w)
  663. __i915_write(32, l)
  664. __i915_write(64, q)
  665. #undef __i915_write
  666.