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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2.  */
  3. /*
  4.  *
  5.  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6.  * All Rights Reserved.
  7.  *
  8.  * Permission is hereby granted, free of charge, to any person obtaining a
  9.  * copy of this software and associated documentation files (the
  10.  * "Software"), to deal in the Software without restriction, including
  11.  * without limitation the rights to use, copy, modify, merge, publish,
  12.  * distribute, sub license, and/or sell copies of the Software, and to
  13.  * permit persons to whom the Software is furnished to do so, subject to
  14.  * the following conditions:
  15.  *
  16.  * The above copyright notice and this permission notice (including the
  17.  * next paragraph) shall be included in all copies or substantial portions
  18.  * of the Software.
  19.  *
  20.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23.  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27.  *
  28.  */
  29.  
  30. //#include <linux/device.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "intel_drv.h"
  36.  
  37.  
  38. #include <linux/kernel.h>
  39. #include <linux/module.h>
  40. #include <linux/mod_devicetable.h>
  41. #include <errno-base.h>
  42. #include <linux/pci.h>
  43.  
  44. #include <syscall.h>
  45.  
  46. #define __read_mostly
  47.  
  48. int init_display_kms(struct drm_device *dev);
  49.  
  50.  
  51. int i915_panel_ignore_lid __read_mostly         =  0;
  52.  
  53. unsigned int i915_powersave  __read_mostly      =  0;
  54.  
  55. unsigned int i915_enable_rc6 __read_mostly      =  0;
  56.  
  57. unsigned int i915_enable_fbc __read_mostly      =  0;
  58.  
  59. unsigned int i915_lvds_downclock  __read_mostly =  0;
  60.  
  61. unsigned int i915_panel_use_ssc __read_mostly   =  1;
  62.  
  63. int i915_vbt_sdvo_panel_type __read_mostly      = -1;
  64.  
  65. #define PCI_VENDOR_ID_INTEL        0x8086
  66.  
  67. #define INTEL_VGA_DEVICE(id, info) {        \
  68.     .class = PCI_CLASS_DISPLAY_VGA << 8,    \
  69.     .class_mask = 0xff0000,                 \
  70.     .vendor = 0x8086,                       \
  71.     .device = id,                           \
  72.     .subvendor = PCI_ANY_ID,                \
  73.     .subdevice = PCI_ANY_ID,                \
  74.     .driver_data = (unsigned long) info }
  75.  
  76. static const struct intel_device_info intel_i830_info = {
  77.         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  78.         .has_overlay = 1, .overlay_needs_physical = 1,
  79. };
  80.  
  81. static const struct intel_device_info intel_845g_info = {
  82.         .gen = 2,
  83.         .has_overlay = 1, .overlay_needs_physical = 1,
  84. };
  85.  
  86. static const struct intel_device_info intel_i85x_info = {
  87.         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  88.         .cursor_needs_physical = 1,
  89.         .has_overlay = 1, .overlay_needs_physical = 1,
  90. };
  91.  
  92. static const struct intel_device_info intel_i865g_info = {
  93.         .gen = 2,
  94.         .has_overlay = 1, .overlay_needs_physical = 1,
  95. };
  96.  
  97. static const struct intel_device_info intel_i915g_info = {
  98.         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  99.         .has_overlay = 1, .overlay_needs_physical = 1,
  100. };
  101. static const struct intel_device_info intel_i915gm_info = {
  102.         .gen = 3, .is_mobile = 1,
  103.         .cursor_needs_physical = 1,
  104.         .has_overlay = 1, .overlay_needs_physical = 1,
  105.         .supports_tv = 1,
  106. };
  107. static const struct intel_device_info intel_i945g_info = {
  108.         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  109.         .has_overlay = 1, .overlay_needs_physical = 1,
  110. };
  111. static const struct intel_device_info intel_i945gm_info = {
  112.         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  113.         .has_hotplug = 1, .cursor_needs_physical = 1,
  114.         .has_overlay = 1, .overlay_needs_physical = 1,
  115.         .supports_tv = 1,
  116. };
  117.  
  118. static const struct intel_device_info intel_i965g_info = {
  119.         .gen = 4, .is_broadwater = 1,
  120.         .has_hotplug = 1,
  121.         .has_overlay = 1,
  122. };
  123.  
  124. static const struct intel_device_info intel_i965gm_info = {
  125.         .gen = 4, .is_crestline = 1,
  126.         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  127.         .has_overlay = 1,
  128.         .supports_tv = 1,
  129. };
  130.  
  131. static const struct intel_device_info intel_g33_info = {
  132.         .gen = 3, .is_g33 = 1,
  133.         .need_gfx_hws = 1, .has_hotplug = 1,
  134.         .has_overlay = 1,
  135. };
  136.  
  137. static const struct intel_device_info intel_g45_info = {
  138.         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
  139.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  140.         .has_bsd_ring = 1,
  141. };
  142.  
  143. static const struct intel_device_info intel_gm45_info = {
  144.         .gen = 4, .is_g4x = 1,
  145.         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
  146.         .has_pipe_cxsr = 1, .has_hotplug = 1,
  147.         .supports_tv = 1,
  148.         .has_bsd_ring = 1,
  149. };
  150.  
  151. static const struct intel_device_info intel_pineview_info = {
  152.         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
  153.         .need_gfx_hws = 1, .has_hotplug = 1,
  154.         .has_overlay = 1,
  155. };
  156.  
  157. static const struct intel_device_info intel_ironlake_d_info = {
  158.         .gen = 5,
  159.         .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
  160.         .has_bsd_ring = 1,
  161. };
  162.  
  163. static const struct intel_device_info intel_ironlake_m_info = {
  164.         .gen = 5, .is_mobile = 1,
  165.         .need_gfx_hws = 1, .has_hotplug = 1,
  166.         .has_fbc = 1,
  167.         .has_bsd_ring = 1,
  168. };
  169.  
  170. static const struct intel_device_info intel_sandybridge_d_info = {
  171.     .gen = 6,
  172.         .need_gfx_hws = 1, .has_hotplug = 1,
  173.     .has_bsd_ring = 1,
  174.     .has_blt_ring = 1,
  175. };
  176.  
  177. static const struct intel_device_info intel_sandybridge_m_info = {
  178.         .gen = 6, .is_mobile = 1,
  179.         .need_gfx_hws = 1, .has_hotplug = 1,
  180.     .has_fbc      = 1,
  181.     .has_bsd_ring = 1,
  182.     .has_blt_ring = 1,
  183. };
  184.  
  185. static const struct intel_device_info intel_ivybridge_d_info = {
  186.         .is_ivybridge = 1, .gen = 7,
  187.         .need_gfx_hws = 1, .has_hotplug = 1,
  188.         .has_bsd_ring = 1,
  189.         .has_blt_ring = 1,
  190. };
  191.  
  192. static const struct intel_device_info intel_ivybridge_m_info = {
  193.         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
  194.         .need_gfx_hws = 1, .has_hotplug = 1,
  195.         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
  196.         .has_bsd_ring = 1,
  197.         .has_blt_ring = 1,
  198. };
  199.  
  200. static const struct pci_device_id pciidlist[] = {       /* aka */
  201.         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
  202.         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
  203.         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
  204.         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
  205.         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
  206.         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
  207.         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
  208.         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
  209.         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
  210.         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
  211.         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
  212.         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
  213.         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
  214.         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
  215.         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
  216.         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
  217.         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
  218.         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
  219.         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
  220.         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
  221.         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
  222.         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
  223.         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  224.         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  225.         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  226.         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  227.     INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  228.     INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  229.     INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  230.     INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  231.     INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  232.     INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  233.     INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  234.         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
  235.         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
  236.         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
  237.         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
  238.         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
  239.     {0, 0, 0}
  240. };
  241.  
  242. #define INTEL_PCH_DEVICE_ID_MASK        0xff00
  243. #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
  244. #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
  245. #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
  246.  
  247. void intel_detect_pch (struct drm_device *dev)
  248. {
  249.     struct drm_i915_private *dev_priv = dev->dev_private;
  250.     struct pci_dev *pch;
  251.  
  252.     /*
  253.      * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  254.      * make graphics device passthrough work easy for VMM, that only
  255.      * need to expose ISA bridge to let driver know the real hardware
  256.      * underneath. This is a requirement from virtualization team.
  257.      */
  258.     pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  259.     if (pch) {
  260.         if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  261.             int id;
  262.             id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  263.  
  264.             if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  265.                 dev_priv->pch_type = PCH_IBX;
  266.                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  267.             } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  268.                 dev_priv->pch_type = PCH_CPT;
  269.                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  270.             } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  271.                 /* PantherPoint is CPT compatible */
  272.                 dev_priv->pch_type = PCH_CPT;
  273.                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  274.             }
  275.         }
  276.     }
  277. }
  278.  
  279. static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  280. {
  281.     int count;
  282.  
  283.     count = 0;
  284.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
  285.         udelay(10);
  286.  
  287.     I915_WRITE_NOTRACE(FORCEWAKE, 1);
  288.     POSTING_READ(FORCEWAKE);
  289.  
  290.     count = 0;
  291.     while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
  292.         udelay(10);
  293. }
  294.  
  295. /*
  296.  * Generally this is called implicitly by the register read function. However,
  297.  * if some sequence requires the GT to not power down then this function should
  298.  * be called at the beginning of the sequence followed by a call to
  299.  * gen6_gt_force_wake_put() at the end of the sequence.
  300.  */
  301. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
  302. {
  303. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  304.  
  305.     /* Forcewake is atomic in case we get in here without the lock */
  306.     if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
  307.         __gen6_gt_force_wake_get(dev_priv);
  308. }
  309.  
  310. static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  311. {
  312.     I915_WRITE_NOTRACE(FORCEWAKE, 0);
  313.     POSTING_READ(FORCEWAKE);
  314. }
  315.  
  316. /*
  317.  * see gen6_gt_force_wake_get()
  318.  */
  319. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
  320. {
  321. //    WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  322.  
  323.     if (atomic_dec_and_test(&dev_priv->forcewake_count))
  324.         __gen6_gt_force_wake_put(dev_priv);
  325. }
  326.  
  327. void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
  328. {
  329.     if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES ) {
  330.         int loop = 500;
  331.         u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  332.         while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
  333.             udelay(10);
  334.             fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  335.         }
  336. //        WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES);
  337.         dev_priv->gt_fifo_count = fifo;
  338.     }
  339.     dev_priv->gt_fifo_count--;
  340. }
  341.  
  342.  
  343.  
  344.  
  345.  
  346. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent);
  347.  
  348. int i915_init(void)
  349. {
  350.     static pci_dev_t device;
  351.     const struct pci_device_id  *ent;
  352.     int  err;
  353.  
  354.     if( init_agp() != 0)
  355.     {
  356.         DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  357.         return 0;
  358.     };
  359.  
  360.     ent = find_pci_device(&device, pciidlist);
  361.  
  362.     if( unlikely(ent == NULL) )
  363.     {
  364.         dbgprintf("device not found\n");
  365.         return 0;
  366.     };
  367.  
  368.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  369.                                 device.pci_dev.device);
  370.  
  371.     err = drm_get_dev(&device.pci_dev, ent);
  372.  
  373.     return err;
  374. }
  375.  
  376. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  377. {
  378.     static struct drm_device *dev;
  379.     int ret;
  380.  
  381.     ENTER();
  382.  
  383.     dev = kzalloc(sizeof(*dev), 0);
  384.     if (!dev)
  385.         return -ENOMEM;
  386.  
  387.  //   ret = pci_enable_device(pdev);
  388.  //   if (ret)
  389.  //       goto err_g1;
  390.  
  391.  //   pci_set_master(pdev);
  392.  
  393.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  394.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  395.  //       goto err_g2;
  396.  //   }
  397.  
  398.     dev->pdev = pdev;
  399.     dev->pci_device = pdev->device;
  400.     dev->pci_vendor = pdev->vendor;
  401.  
  402.     INIT_LIST_HEAD(&dev->filelist);
  403.     INIT_LIST_HEAD(&dev->ctxlist);
  404.     INIT_LIST_HEAD(&dev->vmalist);
  405.     INIT_LIST_HEAD(&dev->maplist);
  406.  
  407.     spin_lock_init(&dev->count_lock);
  408.     mutex_init(&dev->struct_mutex);
  409.     mutex_init(&dev->ctxlist_mutex);
  410.  
  411.     ret = i915_driver_load(dev, ent->driver_data );
  412.  
  413.     if (ret)
  414.         goto err_g4;
  415.  
  416.     ret = init_display_kms(dev);
  417.  
  418.     if (ret)
  419.         goto err_g4;
  420.  
  421.  
  422. //    if( radeon_modeset )
  423. //        init_display_kms(dev->dev_private, &usermode);
  424. //    else
  425. //        init_display(dev->dev_private, &usermode);
  426.  
  427.     LEAVE();
  428.  
  429.     return 0;
  430.  
  431. err_g4:
  432. //    drm_put_minor(&dev->primary);
  433. //err_g3:
  434. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  435. //        drm_put_minor(&dev->control);
  436. //err_g2:
  437. //    pci_disable_device(pdev);
  438. //err_g1:
  439.     free(dev);
  440.  
  441.     LEAVE();
  442.  
  443.     return ret;
  444. }
  445.  
  446.  
  447.