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  1. /*
  2.  * (C) Copyright IBM Corporation 2006
  3.  * Copyright 2009 Red Hat, Inc.
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * on the rights to use, copy, modify, merge, publish, distribute, sub
  10.  * license, and/or sell copies of the Software, and to permit persons to whom
  11.  * the Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the next
  14.  * paragraph) shall be included in all copies or substantial portions of the
  15.  * Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
  20.  * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23.  * DEALINGS IN THE SOFTWARE.
  24.  */
  25. /*
  26.  * Copyright (c) 2007 Paulo R. Zanoni, Tiago Vignatti
  27.  *
  28.  * Permission is hereby granted, free of charge, to any person
  29.  * obtaining a copy of this software and associated documentation
  30.  * files (the "Software"), to deal in the Software without
  31.  * restriction, including without limitation the rights to use,
  32.  * copy, modify, merge, publish, distribute, sublicense, and/or sell
  33.  * copies of the Software, and to permit persons to whom the
  34.  * Software is furnished to do so, subject to the following
  35.  * conditions:
  36.  *
  37.  * The above copyright notice and this permission notice shall be
  38.  * included in all copies or substantial portions of the Software.
  39.  *
  40.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41.  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42.  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43.  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44.  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45.  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46.  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47.  * OTHER DEALINGS IN THE SOFTWARE.
  48.  *
  49.  */
  50.  
  51. /**
  52.  * \file pciaccess.h
  53.  *
  54.  * \author Ian Romanick <idr@us.ibm.com>
  55.  */
  56.  
  57. #ifndef PCIACCESS_H
  58. #define PCIACCESS_H
  59.  
  60. #include <inttypes.h>
  61.  
  62. #if __GNUC__ >= 3
  63. #define __deprecated __attribute__((deprecated))
  64. #else
  65. #define __deprecated
  66. #endif
  67.  
  68. typedef uint64_t pciaddr_t;
  69.  
  70. struct pci_device;
  71. struct pci_device_iterator;
  72. struct pci_id_match;
  73. struct pci_slot_match;
  74.  
  75. #ifdef __cplusplus
  76. extern "C" {
  77. #endif
  78.  
  79. int pci_device_has_kernel_driver(struct pci_device *dev);
  80.  
  81. int pci_device_is_boot_vga(struct pci_device *dev);
  82.  
  83. int pci_device_read_rom(struct pci_device *dev, void *buffer);
  84.  
  85. int  __deprecated pci_device_map_region(struct pci_device *dev,
  86.     unsigned region, int write_enable);
  87.  
  88. int __deprecated pci_device_unmap_region(struct pci_device *dev,
  89.     unsigned region);
  90.  
  91. int pci_device_map_range(struct pci_device *dev, pciaddr_t base,
  92.     pciaddr_t size, unsigned map_flags, void **addr);
  93.  
  94. int pci_device_unmap_range(struct pci_device *dev, void *memory,
  95.     pciaddr_t size);
  96.  
  97. int __deprecated pci_device_map_memory_range(struct pci_device *dev,
  98.     pciaddr_t base, pciaddr_t size, int write_enable, void **addr);
  99.  
  100. int __deprecated pci_device_unmap_memory_range(struct pci_device *dev,
  101.     void *memory, pciaddr_t size);
  102.  
  103. int pci_device_probe(struct pci_device *dev);
  104.  
  105. const struct pci_agp_info *pci_device_get_agp_info(struct pci_device *dev);
  106.  
  107. const struct pci_bridge_info *pci_device_get_bridge_info(
  108.     struct pci_device *dev);
  109.  
  110. const struct pci_pcmcia_bridge_info *pci_device_get_pcmcia_bridge_info(
  111.     struct pci_device *dev);
  112.  
  113. int pci_device_get_bridge_buses(struct pci_device *dev, int *primary_bus,
  114.     int *secondary_bus, int *subordinate_bus);
  115.  
  116. int pci_system_init(void);
  117.  
  118. void pci_system_init_dev_mem(int fd);
  119.  
  120. void pci_system_cleanup(void);
  121.  
  122. struct pci_device_iterator *pci_slot_match_iterator_create(
  123.     const struct pci_slot_match *match);
  124.  
  125. struct pci_device_iterator *pci_id_match_iterator_create(
  126.     const struct pci_id_match *match);
  127.  
  128. void pci_iterator_destroy(struct pci_device_iterator *iter);
  129.  
  130. struct pci_device *pci_device_next(struct pci_device_iterator *iter);
  131.  
  132. struct pci_device *pci_device_find_by_slot(uint32_t domain, uint32_t bus,
  133.     uint32_t dev, uint32_t func);
  134.  
  135. struct pci_device *pci_device_get_parent_bridge(struct pci_device *dev);
  136.  
  137. void pci_get_strings(const struct pci_id_match *m,
  138.     const char **device_name, const char **vendor_name,
  139.     const char **subdevice_name, const char **subvendor_name);
  140. const char *pci_device_get_device_name(const struct pci_device *dev);
  141. const char *pci_device_get_subdevice_name(const struct pci_device *dev);
  142. const char *pci_device_get_vendor_name(const struct pci_device *dev);
  143. const char *pci_device_get_subvendor_name(const struct pci_device *dev);
  144.  
  145. void pci_device_enable(struct pci_device *dev);
  146.  
  147. int pci_device_cfg_read    (struct pci_device *dev, void *data,
  148.     pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read);
  149. int pci_device_cfg_read_u8 (struct pci_device *dev, uint8_t  *data,
  150.     pciaddr_t offset);
  151. int pci_device_cfg_read_u16(struct pci_device *dev, uint16_t *data,
  152.     pciaddr_t offset);
  153. int pci_device_cfg_read_u32(struct pci_device *dev, uint32_t *data,
  154.     pciaddr_t offset);
  155.  
  156. int pci_device_cfg_write    (struct pci_device *dev, const void *data,
  157.     pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written);
  158. int pci_device_cfg_write_u8 (struct pci_device *dev, uint8_t  data,
  159.     pciaddr_t offset);
  160. int pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data,
  161.     pciaddr_t offset);
  162. int pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data,
  163.     pciaddr_t offset);
  164. int pci_device_cfg_write_bits(struct pci_device *dev, uint32_t mask,
  165.     uint32_t data, pciaddr_t offset);
  166.  
  167. #ifdef __cplusplus
  168. }
  169. #endif
  170.  
  171. /**
  172.  * \name Mapping flags passed to \c pci_device_map_range
  173.  */
  174. /*@{*/
  175. #define PCI_DEV_MAP_FLAG_WRITABLE       (1U<<0)
  176. #define PCI_DEV_MAP_FLAG_WRITE_COMBINE  (1U<<1)
  177. #define PCI_DEV_MAP_FLAG_CACHABLE       (1U<<2)
  178. /*@}*/
  179.  
  180.  
  181. #define PCI_MATCH_ANY  (~0)
  182.  
  183. /**
  184.  * Compare two PCI ID values (either vendor or device).  This is used
  185.  * internally to compare the fields of \c pci_id_match to the fields of
  186.  * \c pci_device.
  187.  */
  188. #define PCI_ID_COMPARE(a, b) \
  189.     (((a) == PCI_MATCH_ANY) || ((a) == (b)))
  190.  
  191. /**
  192.  */
  193. struct pci_id_match {
  194.     /**
  195.      * \name Device / vendor matching controls
  196.      *
  197.      * Control the search based on the device, vendor, subdevice, or subvendor
  198.      * IDs.  Setting any of these fields to \c PCI_MATCH_ANY will cause the
  199.      * field to not be used in the comparison.
  200.      */
  201.     /*@{*/
  202.     uint32_t    vendor_id;
  203.     uint32_t    device_id;
  204.     uint32_t    subvendor_id;
  205.     uint32_t    subdevice_id;
  206.     /*@}*/
  207.  
  208.  
  209.     /**
  210.      * \name Device class matching controls
  211.      *
  212.      */
  213.     /*@{*/
  214.     uint32_t    device_class;
  215.     uint32_t    device_class_mask;
  216.     /*@}*/
  217.  
  218.     intptr_t    match_data;
  219. };
  220.  
  221.  
  222. /**
  223.  */
  224. struct pci_slot_match {
  225.     /**
  226.      * \name Device slot matching controls
  227.      *
  228.      * Control the search based on the domain, bus, slot, and function of
  229.      * the device.  Setting any of these fields to \c PCI_MATCH_ANY will cause
  230.      * the field to not be used in the comparison.
  231.      */
  232.     /*@{*/
  233.     uint32_t    domain;
  234.     uint32_t    bus;
  235.     uint32_t    dev;
  236.     uint32_t    func;
  237.     /*@}*/
  238.  
  239.     intptr_t    match_data;
  240. };
  241.  
  242. /**
  243.  * BAR descriptor for a PCI device.
  244.  */
  245. struct pci_mem_region {
  246.     /**
  247.      * When the region is mapped, this is the pointer to the memory.
  248.      *
  249.      * This field is \b only set when the deprecated \c pci_device_map_region
  250.      * interface is used.  Use \c pci_device_map_range instead.
  251.      *
  252.      * \deprecated
  253.      */
  254.     void *memory;
  255.  
  256.  
  257.     /**
  258.      * Base physical address of the region within its bus / domain.
  259.      *
  260.      * \warning
  261.      * This address is really only useful to other devices in the same
  262.      * domain.  It's probably \b not the address applications will ever
  263.      * use.
  264.      *
  265.      * \warning
  266.      * Most (all?) platform back-ends leave this field unset.
  267.      */
  268.     pciaddr_t bus_addr;
  269.  
  270.  
  271.     /**
  272.      * Base physical address of the region from the CPU's point of view.
  273.      *
  274.      * This address is typically passed to \c pci_device_map_range to create
  275.      * a mapping of the region to the CPU's virtual address space.
  276.      */
  277.     pciaddr_t base_addr;
  278.  
  279.  
  280.     /**
  281.      * Size, in bytes, of the region.
  282.      */
  283.     pciaddr_t size;
  284.  
  285.  
  286.     /**
  287.      * Is the region I/O ports or memory?
  288.      */
  289.     unsigned is_IO:1;
  290.  
  291.     /**
  292.      * Is the memory region prefetchable?
  293.      *
  294.      * \note
  295.      * This can only be set if \c is_IO is not set.
  296.      */
  297.     unsigned is_prefetchable:1;
  298.  
  299.  
  300.     /**
  301.      * Is the memory at a 64-bit address?
  302.      *
  303.      * \note
  304.      * This can only be set if \c is_IO is not set.
  305.      */
  306.     unsigned is_64:1;
  307. };
  308.  
  309.  
  310. /**
  311.  * PCI device.
  312.  *
  313.  * Contains all of the information about a particular PCI device.
  314.  */
  315. struct pci_device {
  316.     /**
  317.      * \name Device bus identification.
  318.      *
  319.      * Complete bus identification, including domain, of the device.  On
  320.      * platforms that do not support PCI domains (e.g., 32-bit x86 hardware),
  321.      * the domain will always be zero.
  322.      */
  323.     /*@{*/
  324.     uint16_t    domain;
  325.     uint8_t     bus;
  326.     uint8_t     dev;
  327.     uint8_t     func;
  328.     /*@}*/
  329.  
  330.  
  331.     /**
  332.      * \name Vendor / device ID
  333.      *
  334.      * The vendor ID, device ID, and sub-IDs for the device.
  335.      */
  336.     /*@{*/
  337.     uint16_t    vendor_id;
  338.     uint16_t    device_id;
  339.     uint16_t    subvendor_id;
  340.     uint16_t    subdevice_id;
  341.     /*@}*/
  342.  
  343.     /**
  344.      * Device's class, subclass, and programming interface packed into a
  345.      * single 32-bit value.  The class is at bits [23:16], subclass is at
  346.      * bits [15:8], and programming interface is at [7:0].
  347.      */
  348.     uint32_t    device_class;
  349.  
  350.  
  351.     /**
  352.      * Device revision number, as read from the configuration header.
  353.      */
  354.     uint8_t     revision;
  355.  
  356.  
  357.     /**
  358.      * BAR descriptors for the device.
  359.      */
  360.     struct pci_mem_region regions[6];
  361.  
  362.  
  363.     /**
  364.      * Size, in bytes, of the device's expansion ROM.
  365.      */
  366.     pciaddr_t   rom_size;
  367.  
  368.  
  369.     /**
  370.      * IRQ associated with the device.  If there is no IRQ, this value will
  371.      * be -1.
  372.      */
  373.     int irq;
  374.  
  375.  
  376.     /**
  377.      * Storage for user data.  Users of the library can store arbitrary
  378.      * data in this pointer.  The library will not use it for any purpose.
  379.      * It is the user's responsability to free this memory before destroying
  380.      * the \c pci_device structure.
  381.      */
  382.     intptr_t user_data;
  383.  
  384.     /**
  385.       * Used by the VGA arbiter. Type of resource decoded by the device and
  386.       * the file descriptor (/dev/vga_arbiter). */
  387.     int vgaarb_rsrc;
  388. };
  389.  
  390.  
  391. /**
  392.  * Description of the AGP capability of the device.
  393.  *
  394.  * \sa pci_device_get_agp_info
  395.  */
  396. struct pci_agp_info {
  397.     /**
  398.      * Offset of the AGP registers in the devices configuration register
  399.      * space.  This is generally used so that the offset of the AGP command
  400.      * register can be determined.
  401.      */
  402.     unsigned    config_offset;
  403.  
  404.  
  405.     /**
  406.      * \name AGP major / minor version.
  407.      */
  408.     /*@{*/
  409.     uint8_t     major_version;
  410.     uint8_t     minor_version;
  411.     /*@}*/
  412.  
  413.     /**
  414.      * Logical OR of the supported AGP rates.  For example, a value of 0x07
  415.      * means that the device can support 1x, 2x, and 4x.  A value of 0x0c
  416.      * means that the device can support 8x and 4x.
  417.      */
  418.     uint8_t    rates;
  419.  
  420.     unsigned int    fast_writes:1;  /**< Are fast-writes supported? */
  421.     unsigned int    addr64:1;
  422.     unsigned int    htrans:1;
  423.     unsigned int    gart64:1;
  424.     unsigned int    coherent:1;
  425.     unsigned int    sideband:1;     /**< Is side-band addressing supported? */
  426.     unsigned int    isochronus:1;
  427.  
  428.     uint8_t    async_req_size;
  429.     uint8_t    calibration_cycle_timing;
  430.     uint8_t    max_requests;
  431. };
  432.  
  433. /**
  434.  * Description of a PCI-to-PCI bridge device.
  435.  *
  436.  * \sa pci_device_get_bridge_info
  437.  */
  438. struct pci_bridge_info {
  439.     uint8_t    primary_bus;
  440.     uint8_t    secondary_bus;
  441.     uint8_t    subordinate_bus;
  442.     uint8_t    secondary_latency_timer;
  443.  
  444.     uint8_t     io_type;
  445.     uint8_t     mem_type;
  446.     uint8_t     prefetch_mem_type;
  447.  
  448.     uint16_t    secondary_status;
  449.     uint16_t    bridge_control;
  450.  
  451.     uint32_t    io_base;
  452.     uint32_t    io_limit;
  453.  
  454.     uint32_t    mem_base;
  455.     uint32_t    mem_limit;
  456.  
  457.     uint64_t    prefetch_mem_base;
  458.     uint64_t    prefetch_mem_limit;
  459. };
  460.  
  461. /**
  462.  * Description of a PCI-to-PCMCIA bridge device.
  463.  *
  464.  * \sa pci_device_get_pcmcia_bridge_info
  465.  */
  466. struct pci_pcmcia_bridge_info {
  467.     uint8_t    primary_bus;
  468.     uint8_t    card_bus;
  469.     uint8_t    subordinate_bus;
  470.     uint8_t    cardbus_latency_timer;
  471.  
  472.     uint16_t    secondary_status;
  473.     uint16_t    bridge_control;
  474.  
  475.     struct {
  476.         uint32_t    base;
  477.         uint32_t    limit;
  478.     } io[2];
  479.  
  480.     struct {
  481.         uint32_t    base;
  482.         uint32_t    limit;
  483.     } mem[2];
  484.  
  485. };
  486.  
  487.  
  488. /**
  489.  * VGA Arbiter definitions, functions and related.
  490.  */
  491.  
  492. /* Legacy VGA regions */
  493. #define VGA_ARB_RSRC_NONE       0x00
  494. #define VGA_ARB_RSRC_LEGACY_IO  0x01
  495. #define VGA_ARB_RSRC_LEGACY_MEM 0x02
  496. /* Non-legacy access */
  497. #define VGA_ARB_RSRC_NORMAL_IO  0x04
  498. #define VGA_ARB_RSRC_NORMAL_MEM 0x08
  499.  
  500. int  pci_device_vgaarb_init         (void);
  501. void pci_device_vgaarb_fini         (void);
  502. int  pci_device_vgaarb_set_target   (struct pci_device *dev);
  503. /* use the targetted device */
  504. int  pci_device_vgaarb_decodes      (int new_vga_rsrc);
  505. int  pci_device_vgaarb_lock         (void);
  506. int  pci_device_vgaarb_trylock      (void);
  507. int  pci_device_vgaarb_unlock       (void);
  508. /* return the current device count + resource decodes for the device */
  509. int pci_device_vgaarb_get_info      (struct pci_device *dev, int *vga_count, int *rsrc_decodes);
  510.  
  511. /*
  512.  * I/O space access.
  513.  */
  514.  
  515. struct pci_io_handle;
  516.  
  517. struct pci_io_handle *pci_device_open_io(struct pci_device *dev, pciaddr_t base,
  518.                                          pciaddr_t size);
  519. struct pci_io_handle *pci_legacy_open_io(struct pci_device *dev, pciaddr_t base,
  520.                                          pciaddr_t size);
  521. void pci_device_close_io(struct pci_device *dev, struct pci_io_handle *handle);
  522. uint32_t pci_io_read32(struct pci_io_handle *handle, uint32_t reg);
  523. uint16_t pci_io_read16(struct pci_io_handle *handle, uint32_t reg);
  524. uint8_t pci_io_read8(struct pci_io_handle *handle, uint32_t reg);
  525. void pci_io_write32(struct pci_io_handle *handle, uint32_t reg, uint32_t data);
  526. void pci_io_write16(struct pci_io_handle *handle, uint32_t reg, uint16_t data);
  527. void pci_io_write8(struct pci_io_handle *handle, uint32_t reg, uint8_t data);
  528.  
  529. /*
  530.  * Legacy memory access
  531.  */
  532.  
  533. int pci_device_map_legacy(struct pci_device *dev, pciaddr_t base,
  534.                           pciaddr_t size, unsigned map_flags, void **addr);
  535. int pci_device_unmap_legacy(struct pci_device *dev, void *addr, pciaddr_t size);
  536.  
  537. #endif /* PCIACCESS_H */
  538.