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  1.  
  2.  
  3. static Bool rhdMapMMIO(RHDPtr rhdPtr)
  4. {
  5.      rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
  6.      rhdPtr->MMIOBase = MapIoMem(rhdPtr->memBase[RHD_MMIO_BAR],
  7.                                  rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
  8.      if( rhdPtr->MMIOBase==0)
  9.         return 0;
  10.  
  11.      DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize));
  12.      return 1;
  13. }
  14.  
  15. /* Read MC register */
  16. unsigned INMC(RHDPtr info, int addr)
  17. {
  18.     u32_t       data;
  19.  
  20.     if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  21.        (info->ChipFamily == CHIP_FAMILY_RS740)) {
  22.         OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  23.         data = INREG(RS690_MC_DATA);
  24.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  25.         OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
  26.         data = INREG(RS600_MC_DATA);
  27.     } else if (IS_AVIVO_VARIANT) {
  28.         OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
  29.         (void)INREG(AVIVO_MC_INDEX);
  30.         data = INREG(AVIVO_MC_DATA);
  31.  
  32.         OUTREG(AVIVO_MC_INDEX, 0);
  33.         (void)INREG(AVIVO_MC_INDEX);
  34.     } else {
  35.         OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
  36.         (void)INREG(R300_MC_IND_INDEX);
  37.         data = INREG(R300_MC_IND_DATA);
  38.  
  39.         OUTREG(R300_MC_IND_INDEX, 0);
  40.         (void)INREG(R300_MC_IND_INDEX);
  41.     }
  42.  
  43.     return data;
  44. }
  45.  
  46.      /* Write MC information */
  47. void OUTMC(RHDPtr info, int addr, u32_t data)
  48. {
  49.     if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  50.         (info->ChipFamily == CHIP_FAMILY_RS740)) {
  51.         OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN));
  52.          OUTREG(RS690_MC_DATA, data);
  53.         OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
  54.     }
  55.     else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  56.         OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN));
  57.         OUTREG(RS600_MC_DATA, data);
  58.         OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK);
  59.     }
  60.     else if (IS_AVIVO_VARIANT) {
  61.         OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
  62.         (void)INREG(AVIVO_MC_INDEX);
  63.         OUTREG(AVIVO_MC_DATA, data);
  64.         OUTREG(AVIVO_MC_INDEX, 0);
  65.         (void)INREG(AVIVO_MC_INDEX);
  66.     }
  67.     else {
  68.         OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN));
  69.         (void)INREG(R300_MC_IND_INDEX);
  70.         OUTREG(R300_MC_IND_DATA, data);
  71.         OUTREG(R300_MC_IND_INDEX, 0);
  72.         (void)INREG(R300_MC_IND_INDEX);
  73.     }
  74. }
  75.  
  76. static Bool avivo_get_mc_idle(RHDPtr info)
  77. {
  78.  
  79.     if (info->ChipFamily >= CHIP_FAMILY_R600) {
  80.         /* no idea where this is on r600 yet */
  81.         return TRUE;
  82.     }
  83.     else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  84.         if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
  85.             return TRUE;
  86.         else
  87.             return FALSE;
  88.     }
  89.     else if (info->ChipFamily == CHIP_FAMILY_RS600)
  90.     {
  91.         if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
  92.             return TRUE;
  93.         else
  94.             return FALSE;
  95.     }
  96.     else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  97.           (info->ChipFamily == CHIP_FAMILY_RS740)) {
  98.         if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
  99.             return TRUE;
  100.         else
  101.             return FALSE;
  102.     }
  103.     else {
  104.         if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
  105.             return TRUE;
  106.         else
  107.             return FALSE;
  108.     }
  109. }
  110.  
  111. #define LOC_FB    0x1
  112. #define LOC_AGP   0x2
  113.  
  114. static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
  115.                                 u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
  116. {
  117.  
  118.     if (info->ChipFamily >= CHIP_FAMILY_RV770)
  119.     {
  120.         if (mask & LOC_FB)
  121.             *fb_loc = INREG(R700_MC_VM_FB_LOCATION);
  122.         if (mask & LOC_AGP) {
  123.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  124.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  125.         }
  126.     }
  127.     else if (info->ChipFamily >= CHIP_FAMILY_R600)
  128.     {
  129.         if (mask & LOC_FB)
  130.             *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
  131.         if (mask & LOC_AGP) {
  132.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  133.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  134.         }
  135.     }
  136.     else if (info->ChipFamily == CHIP_FAMILY_RV515)
  137.     {
  138.         if (mask & LOC_FB)
  139.             *fb_loc = INMC(info, RV515_MC_FB_LOCATION);
  140.         if (mask & LOC_AGP) {
  141.             *agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
  142.             *agp_loc_hi = 0;
  143.         }
  144.     }
  145.     else if (info->ChipFamily == CHIP_FAMILY_RS600)
  146.     {
  147.         if (mask & LOC_FB)
  148.             *fb_loc = INMC(info, RS600_MC_FB_LOCATION);
  149.         if (mask & LOC_AGP) {
  150.             *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
  151.             *agp_loc_hi = 0;
  152.         }
  153.     }
  154.     else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  155.              (info->ChipFamily == CHIP_FAMILY_RS740))
  156.     {
  157.         if (mask & LOC_FB)
  158.             *fb_loc = INMC(info, RS690_MC_FB_LOCATION);
  159.         if (mask & LOC_AGP) {
  160.             *agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
  161.             *agp_loc_hi = 0;
  162.         }
  163.     }
  164.     else if (info->ChipFamily >= CHIP_FAMILY_R520)
  165.     {
  166.         if (mask & LOC_FB)
  167.             *fb_loc = INMC(info, R520_MC_FB_LOCATION);
  168.         if (mask & LOC_AGP) {
  169.             *agp_loc = INMC(info, R520_MC_AGP_LOCATION);
  170.             *agp_loc_hi = 0;
  171.         }
  172.     }
  173.     else
  174.     {
  175.         if (mask & LOC_FB)
  176.             *fb_loc = INREG(RADEON_MC_FB_LOCATION);
  177.         if (mask & LOC_AGP)
  178.             *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
  179.     }
  180. }
  181.  
  182. static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc,
  183.                       u32_t agp_loc, u32_t agp_loc_hi)
  184. {
  185.  
  186.      if (info->ChipFamily >= CHIP_FAMILY_RV770) {
  187.         if (mask & LOC_FB)
  188.            OUTREG(R700_MC_VM_FB_LOCATION, fb_loc);
  189.         if (mask & LOC_AGP) {
  190.            OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
  191.            OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
  192.         }
  193.      }
  194.      else if (info->ChipFamily >= CHIP_FAMILY_R600)
  195.      {
  196.         if (mask & LOC_FB)
  197.            OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
  198.         if (mask & LOC_AGP) {
  199.            OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
  200.            OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
  201.         }
  202.      }
  203.      else if (info->ChipFamily == CHIP_FAMILY_RV515)
  204.      {
  205.         if (mask & LOC_FB)
  206.            OUTMC(info, RV515_MC_FB_LOCATION, fb_loc);
  207.         if (mask & LOC_AGP)
  208.            OUTMC(info, RV515_MC_AGP_LOCATION, agp_loc);
  209.            (void)INMC(info, RV515_MC_AGP_LOCATION);
  210.      }
  211.      else if (info->ChipFamily == CHIP_FAMILY_RS600)
  212.      {
  213.      if (mask & LOC_FB)
  214.         OUTMC(info, RS600_MC_FB_LOCATION, fb_loc);
  215.         /*      if (mask & LOC_AGP)
  216.                 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/
  217.      }
  218.      else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  219.               (info->ChipFamily == CHIP_FAMILY_RS740))
  220.      {
  221.         if (mask & LOC_FB)
  222.            OUTMC(info, RS690_MC_FB_LOCATION, fb_loc);
  223.         if (mask & LOC_AGP)
  224.            OUTMC(info, RS690_MC_AGP_LOCATION, agp_loc);
  225.      }
  226.      else if (info->ChipFamily >= CHIP_FAMILY_R520)
  227.      {
  228.         if (mask & LOC_FB)
  229.            OUTMC(info, R520_MC_FB_LOCATION, fb_loc);
  230.         if (mask & LOC_AGP)
  231.            OUTMC(info, R520_MC_AGP_LOCATION, agp_loc);
  232.            (void)INMC(info, R520_MC_FB_LOCATION);
  233.      }
  234.      else {
  235.         if (mask & LOC_FB)
  236.            OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
  237.         if (mask & LOC_AGP)
  238.            OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
  239.     }
  240. }
  241.  
  242.  
  243. static void RADEONUpdateMemMapRegisters(RHDPtr info)
  244. {
  245.      u32_t timeout;
  246.  
  247.      u32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
  248.  
  249.      radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &mc_fb_loc,
  250.                                    &mc_agp_loc, &mc_agp_loc_hi);
  251.  
  252.      if (IS_AVIVO_VARIANT)
  253.      {
  254.  
  255.         if (mc_fb_loc  != info->mc_fb_location  ||
  256.             mc_agp_loc != info->mc_agp_location)
  257.         {
  258.            u32_t d1crtc, d2crtc;
  259.            u32_t tmp;
  260. //           RADEONWaitForIdleMMIO(pScrn);
  261.  
  262.            OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
  263.            OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
  264.  
  265.            /* Stop display & memory access */
  266.            d1crtc = INREG(AVIVO_D1CRTC_CONTROL);
  267.            OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc & ~AVIVO_CRTC_EN);
  268.  
  269.            d2crtc = INREG(AVIVO_D2CRTC_CONTROL);
  270.            OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc & ~AVIVO_CRTC_EN);
  271.  
  272.            tmp = INREG(AVIVO_D2CRTC_CONTROL);
  273.  
  274.            usleep(1000);
  275.            timeout = 0;
  276.            while (!(avivo_get_mc_idle(info)))
  277.            {
  278.               if (++timeout > 1000000)
  279.               {
  280.                  dbgprintf("Timeout trying to update memory controller settings !\n");
  281.                  dbgprintf("You will probably crash now ... \n");
  282.                /* Nothing we can do except maybe try to kill the server,
  283.                 * let's wait 2 seconds to leave the above message a chance
  284.                 * to maybe hit the disk and continue trying to setup despite
  285.                 * the MC being non-idle
  286.                 */
  287.                  usleep(20000);
  288.               }
  289.               usleep(10);
  290.            }
  291.  
  292.            radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP,
  293.                            info->mc_fb_location,
  294.                            info->mc_agp_location,
  295.                            info->mc_agp_location_hi);
  296.  
  297.            if (info->ChipFamily < CHIP_FAMILY_R600) {
  298.               OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  299.            }
  300.            else {
  301.               OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  302.            }
  303.  
  304.            OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc );
  305.  
  306.            OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc );
  307.  
  308.            tmp = INREG(AVIVO_D2CRTC_CONTROL);
  309.  
  310.            /* Reset the engine and HDP */
  311. //           RADEONEngineReset(pScrn);
  312.        }
  313.      }
  314.      else
  315.      {
  316.  
  317.         /* Write memory mapping registers only if their value change
  318.          * since we must ensure no access is done while they are
  319.          * reprogrammed
  320.          */
  321.         if ( mc_fb_loc != info->mc_fb_location   ||
  322.              mc_agp_loc != info->mc_agp_location)
  323.         {
  324.            u32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
  325.            u32_t old_mc_status, status_idle;
  326.  
  327.            dbgprintf("  Map Changed ! Applying ...\n");
  328.  
  329.             /* Make sure engine is idle. We assume the CCE is stopped
  330.              * at this point
  331.              */
  332.    //        RADEONWaitForIdleMMIO(info);
  333.  
  334.            if (info->IsIGP)
  335.               goto igp_no_mcfb;
  336.  
  337.             /* Capture MC_STATUS in case things go wrong ... */
  338.            old_mc_status = INREG(RADEON_MC_STATUS);
  339.  
  340.             /* Stop display & memory access */
  341.            ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
  342.            OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
  343.            crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
  344.            OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
  345.            crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
  346. //           RADEONWaitForVerticalSync(pScrn);
  347.            OUTREG(RADEON_CRTC_GEN_CNTL,
  348.                  (crtc_gen_cntl  & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN))
  349.                  | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
  350.  
  351.            if (info->HasCRTC2)
  352.            {
  353.               crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
  354. //              RADEONWaitForVerticalSync2(pScrn);
  355.               OUTREG(RADEON_CRTC2_GEN_CNTL, (crtc2_gen_cntl
  356.                      & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN))
  357.                     | RADEON_CRTC2_DISP_REQ_EN_B);
  358.            }
  359.  
  360.             /* Make sure the chip settles down (paranoid !) */
  361.            usleep(1000);
  362.  
  363.             /* Wait for MC idle */
  364.            if (IS_R300_VARIANT)
  365.               status_idle = R300_MC_IDLE;
  366.            else
  367.               status_idle = RADEON_MC_IDLE;
  368.  
  369.            timeout = 0;
  370.            while (!(INREG(RADEON_MC_STATUS) & status_idle))
  371.            {
  372.               if (++timeout > 1000000)
  373.               {
  374.                  dbgprintf("Timeout trying to update memory controller settings !\n");
  375.                  dbgprintf("MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
  376.                            INREG(RADEON_MC_STATUS), old_mc_status);
  377.                  dbgprintf("You will probably crash now ... \n");
  378.                     /* Nothing we can do except maybe try to kill the server,
  379.                      * let's wait 2 seconds to leave the above message a chance
  380.                      * to maybe hit the disk and continue trying to setup despite
  381.                      * the MC being non-idle
  382.                      */
  383.                  usleep(20000);
  384.               }
  385.               usleep(10);
  386.            }
  387.  
  388.             /* Update maps, first clearing out AGP to make sure we don't get
  389.              * a temporary overlap
  390.              */
  391.            OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
  392.            OUTREG(RADEON_MC_FB_LOCATION, info->mc_fb_location);
  393.            radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, info->mc_fb_location,
  394.                            0xfffffffc, 0);
  395.  
  396.            OUTREG(RADEON_CRTC_GEN_CNTL,crtc_gen_cntl );
  397.            OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  398.            OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl );
  399.  
  400.  
  401. igp_no_mcfb:
  402.            radeon_write_mc_fb_agp_location(info, LOC_AGP, 0,
  403.                         info->mc_agp_location, 0);
  404.             /* Make sure map fully reached the chip */
  405.            (void)INREG(RADEON_MC_FB_LOCATION);
  406.  
  407.            dbgprintf("  Map applied, resetting engine ...\n");
  408.  
  409.             /* Reset the engine and HDP */
  410. //        RADEONEngineReset(pScrn);
  411.  
  412.             /* Make sure we have sane offsets before re-enabling the CRTCs, disable
  413.              * stereo, clear offsets, and wait for offsets to catch up with hw
  414.              */
  415.  
  416.            OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
  417.            OUTREG(RADEON_CRTC_OFFSET, 0);
  418.            OUTREG(RADEON_CUR_OFFSET, 0);
  419.            timeout = 0;
  420.            while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
  421.            {
  422.               if (timeout++ > 1000000) {
  423.                  dbgprintf("Timeout waiting for CRTC offset to update !\n");
  424.                  break;
  425.               }
  426.               usleep(1000);
  427.            }
  428.            if (info->HasCRTC2)
  429.            {
  430.               OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
  431.               OUTREG(RADEON_CRTC2_OFFSET, 0);
  432.               OUTREG(RADEON_CUR2_OFFSET, 0);
  433.               timeout = 0;
  434.               while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET)
  435.               {
  436.                  if (timeout++ > 1000000) {
  437.                     dbgprintf("Timeout waiting for CRTC2 offset to update !\n");
  438.                     break;
  439.                  }
  440.                  usleep(1000);
  441.               }
  442.            }
  443.         }
  444.  
  445.         dbgprintf("Updating display base addresses...\n");
  446.  
  447.         OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation);
  448.         if (info->HasCRTC2)
  449.            OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation);
  450.         OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation);
  451.         (void)INREG(RADEON_OV0_BASE_ADDR);
  452.  
  453.         /* More paranoia delays, wait 100ms */
  454.         usleep(1000);
  455.  
  456.         dbgprintf("Memory map updated.\n");
  457.      };
  458. };
  459.  
  460.  
  461. static void RADEONInitMemoryMap(RHDPtr info)
  462. {
  463.     u32_t       mem_size;
  464.     u32_t       aper_size;
  465.  
  466.     radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location,
  467.                    &info->mc_agp_location, &info->mc_agp_location_hi);
  468.  
  469.     dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  470.     dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  471.  
  472.  
  473.     /* We shouldn't use info->videoRam here which might have been clipped
  474.      * but the real video RAM instead
  475.      */
  476.     if (info->ChipFamily >= CHIP_FAMILY_R600){
  477.         mem_size = INREG(R600_CONFIG_MEMSIZE);
  478.         aper_size = INREG(R600_CONFIG_APER_SIZE);
  479.     }
  480.     else {
  481.         mem_size = INREG(RADEON_CONFIG_MEMSIZE);
  482.         aper_size = INREG(RADEON_CONFIG_APER_SIZE);
  483.     }
  484.  
  485.     if (mem_size == 0)
  486.         mem_size = 0x800000;
  487.  
  488.     /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  489.        Novell bug 204882 + along with lots of ubuntu ones */
  490.     if (aper_size > mem_size)
  491.         mem_size = aper_size;
  492.  
  493.  
  494.     if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
  495.          (info->ChipFamily != CHIP_FAMILY_RS690) &&
  496.          (info->ChipFamily != CHIP_FAMILY_RS740))
  497.     {
  498.         if (info->IsIGP)
  499.           info->mc_fb_location = INREG(RADEON_NB_TOM);
  500.         else
  501.         {
  502.             u32_t aper0_base;
  503.  
  504.             if (info->ChipFamily >= CHIP_FAMILY_R600) {
  505.                 aper0_base = INREG(R600_CONFIG_F0_BASE);
  506.             }
  507.             else {
  508.                 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
  509.             }
  510.             dbgprintf("aper0 base %x\n", aper0_base );
  511.  
  512.         /* Recent chips have an "issue" with the memory controller, the
  513.          * location must be aligned to the size. We just align it down,
  514.          * too bad if we walk over the top of system memory, we don't
  515.          * use DMA without a remapped anyway.
  516.          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  517.          */
  518.             if ( info->ChipFamily == CHIP_FAMILY_RV280 ||
  519.                  info->ChipFamily == CHIP_FAMILY_R300 ||
  520.                  info->ChipFamily == CHIP_FAMILY_R350 ||
  521.                  info->ChipFamily == CHIP_FAMILY_RV350 ||
  522.                  info->ChipFamily == CHIP_FAMILY_RV380 ||
  523.                  info->ChipFamily == CHIP_FAMILY_R420 ||
  524.                  info->ChipFamily == CHIP_FAMILY_RV410)
  525.                 aper0_base &= ~(mem_size - 1);
  526.  
  527.             if ( info->ChipFamily >= CHIP_FAMILY_R600) {
  528.                  info->mc_fb_location = (aper0_base >> 24) |
  529.                  (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
  530.                 dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  531.             }
  532.             else {
  533.                 info->mc_fb_location = (aper0_base >> 16) |
  534.                 ((aper0_base + mem_size - 1) & 0xffff0000U);
  535.                 dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  536.             }
  537.         }
  538.     }
  539.     if (info->ChipFamily >= CHIP_FAMILY_R600) {
  540.         info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
  541.     }
  542.     else {
  543.         info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
  544.     }
  545.     /* Just disable the damn AGP apertures for now, it may be
  546.      * re-enabled later by the DRM
  547.      */
  548.  
  549.     if (IS_AVIVO_VARIANT) {
  550.        if (info->ChipFamily >= CHIP_FAMILY_R600) {
  551.           OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  552.        }
  553.        else {
  554.           OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  555.        }
  556.        info->mc_agp_location =  0x003f0000;
  557.     }
  558.     else
  559.         info->mc_agp_location = 0xffffffc0;
  560.  
  561.     dbgprintf("RADEONInitMemoryMap() : \n");
  562.     dbgprintf("  mem_size         : 0x%08x\n", (u32_t)mem_size);
  563.     dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  564.     dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  565.     dbgprintf("  FB_LOCATION   : 0x%08x\n", (unsigned)info->fbLocation);
  566.  
  567.  
  568.     RADEONUpdateMemMapRegisters(info);
  569.  
  570.  
  571. }
  572.  
  573. static void RADEONGetVRamType(RHDPtr info)
  574. {
  575.      u32_t tmp;
  576.  
  577.      if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
  578.         info->IsDDR = TRUE;
  579.      else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  580.         info->IsDDR = TRUE;
  581.      else
  582.         info->IsDDR = FALSE;
  583.  
  584.      if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
  585.           (info->ChipFamily <= CHIP_FAMILY_RV635))
  586.      {
  587.         int chansize;
  588.         /* r6xx */
  589.         tmp = INREG(R600_RAMCFG);
  590.         if (tmp & R600_CHANSIZE_OVERRIDE)
  591.             chansize = 16;
  592.         else if (tmp & R600_CHANSIZE)
  593.             chansize = 64;
  594.         else
  595.             chansize = 32;
  596.         if (info->ChipFamily == CHIP_FAMILY_R600)
  597.             info->RamWidth = 8 * chansize;
  598.         else if (info->ChipFamily == CHIP_FAMILY_RV670)
  599.             info->RamWidth = 4 * chansize;
  600.         else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
  601.              (info->ChipFamily == CHIP_FAMILY_RV620))
  602.             info->RamWidth = chansize;
  603.         else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
  604.              (info->ChipFamily == CHIP_FAMILY_RV635))
  605.             info->RamWidth = 2 * chansize;
  606.      }
  607.      else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  608.      /* rv515/rv550 */
  609.         tmp = INMC(info, RV515_MC_CNTL);
  610.         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
  611.         switch (tmp) {
  612.            case 0: info->RamWidth = 64; break;
  613.            case 1: info->RamWidth = 128; break;
  614.            default: info->RamWidth = 128; break;
  615.         }
  616.      }
  617.      else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
  618.               (info->ChipFamily <= CHIP_FAMILY_RV570)){
  619.      /* r520/rv530/rv560/rv570/r580 */
  620.         tmp = INMC(info, R520_MC_CNTL0);
  621.         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
  622.            case 0: info->RamWidth = 32; break;
  623.            case 1: info->RamWidth = 64; break;
  624.            case 2: info->RamWidth = 128; break;
  625.            case 3: info->RamWidth = 256; break;
  626.            default: info->RamWidth = 64; break;
  627.         }
  628.         if (tmp & R520_MC_CHANNEL_SIZE) {
  629.            info->RamWidth *= 2;
  630.         }
  631.      }
  632.      else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
  633.               (info->ChipFamily <= CHIP_FAMILY_RV410)) {
  634.      /* r3xx, r4xx */
  635.         tmp = INREG(RADEON_MEM_CNTL);
  636.         tmp &= R300_MEM_NUM_CHANNELS_MASK;
  637.         switch (tmp) {
  638.            case 0: info->RamWidth = 64; break;
  639.            case 1: info->RamWidth = 128; break;
  640.            case 2: info->RamWidth = 256; break;
  641.            default: info->RamWidth = 128; break;
  642.         }
  643.      }
  644.      else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
  645.               (info->ChipFamily == CHIP_FAMILY_RS100) ||
  646.               (info->ChipFamily == CHIP_FAMILY_RS200)){
  647.      tmp = INREG(RADEON_MEM_CNTL);
  648.      if (tmp & RV100_HALF_MODE)
  649.         info->RamWidth = 32;
  650.      else
  651.         info->RamWidth = 64;
  652.  
  653.      if (!info->HasCRTC2) {
  654.           info->RamWidth /= 4;
  655.           info->IsDDR = TRUE;
  656.      }
  657.      }
  658.      else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
  659.         tmp = INREG(RADEON_MEM_CNTL);
  660.      if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
  661.         info->RamWidth = 128;
  662.      else
  663.         info->RamWidth = 64;
  664.      } else {
  665.      /* newer IGPs */
  666.         info->RamWidth = 128;
  667.      }
  668.  
  669.      /* This may not be correct, as some cards can have half of channel disabled
  670.       * ToDo: identify these cases
  671.       */
  672. }
  673.  
  674. /*
  675.  * Depending on card genertation, chipset bugs, etc... the amount of vram
  676.  * accessible to the CPU can vary. This function is our best shot at figuring
  677.  * it out. Returns a value in KB.
  678.  */
  679. static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
  680. {
  681.     u32_t       aper_size;
  682.     unsigned char  byte;
  683.  
  684.     if (info->ChipFamily >= CHIP_FAMILY_R600)
  685.        aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
  686.     else
  687.        aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
  688.  
  689.  
  690.     /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  691.      * that is has the 2nd generation multifunction PCI interface
  692.      */
  693.     if (info->ChipFamily == CHIP_FAMILY_RV280 ||
  694.         info->ChipFamily == CHIP_FAMILY_RV350 ||
  695.         info->ChipFamily == CHIP_FAMILY_RV380 ||
  696.         info->ChipFamily == CHIP_FAMILY_R420  ||
  697.         info->ChipFamily == CHIP_FAMILY_RV410 ||
  698.         IS_AVIVO_VARIANT) {
  699.         MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  700.                      ~RADEON_HDP_APER_CNTL);
  701.         dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
  702.             return aper_size * 2;
  703.     }
  704.  
  705.     /* Older cards have all sorts of funny issues to deal with. First
  706.      * check if it's a multifunction card by reading the PCI config
  707.      * header type... Limit those to one aperture size
  708.      */
  709.     byte = pciReadByte(info->PciTag, 0xe);
  710.     if (byte & 0x80) {
  711.        dbgprintf("Generation 1 PCI interface in multifunction mode, "
  712.                  "accessible memory limited to one aperture\n");
  713.        return aper_size;
  714.     }
  715.  
  716.     /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  717.      * have set it up. We don't write this as it's broken on some ASICs but
  718.      * we expect the BIOS to have done the right thing (might be too optimistic...)
  719.      */
  720.     if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  721.        return aper_size * 2;
  722.  
  723.     return aper_size;
  724. }
  725.  
  726. int RADEONDRIGetPciAperTableSize(RHDPtr info)
  727. {
  728.     int ret_size;
  729.     int num_pages;
  730.  
  731.     num_pages = (info->pciAperSize * 1024 * 1024) / 4096;
  732.  
  733.     ret_size = num_pages * sizeof(unsigned int);
  734.  
  735.     return ret_size;
  736. }
  737.  
  738. static Bool RADEONPreInitVRAM(RHDPtr info)
  739. {
  740.      u32_t accessible, bar_size;
  741.  
  742.      if ((!IS_AVIVO_VARIANT) && info->IsIGP)
  743.      {
  744.         u32_t tom = INREG(RADEON_NB_TOM);
  745.  
  746.         info->videoRam = (((tom >> 16) -
  747.                  (tom & 0xffff) + 1) << 6);
  748.  
  749.         OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
  750.      }
  751.      else
  752.      {
  753.         if (info->ChipFamily >= CHIP_FAMILY_R600)
  754.            info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
  755.         else
  756.         {
  757.          /* Read VRAM size from card */
  758.            info->videoRam      = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
  759.  
  760.          /* Some production boards of m6 will return 0 if it's 8 MB */
  761.            if (info->videoRam == 0)
  762.            {
  763.               info->videoRam = 8192;
  764.               OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
  765.            }
  766.         }
  767.      }
  768.  
  769.      RADEONGetVRamType(info);
  770.  
  771.      /* Get accessible memory */
  772.      accessible = RADEONGetAccessibleVRAM(info);
  773.  
  774.      /* Crop it to the size of the PCI BAR */
  775. //     bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
  776.  
  777.      bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
  778.  
  779.      if (bar_size == 0)
  780.         bar_size = 0x20000;
  781.      if (accessible > bar_size)
  782.         accessible = bar_size;
  783.  
  784.      dbgprintf("Detected total video RAM=%dK width=%dbit,"
  785.                 "accessible=%uK (PCI BAR=%uK)\n",
  786.                 info->videoRam, info->RamWidth,
  787.                 (unsigned)accessible, (unsigned)bar_size);
  788.  
  789.      if (info->videoRam > accessible)
  790.         info->videoRam = accessible;
  791.  
  792.      if (!IS_AVIVO_VARIANT)
  793.         info->MemCntl            = INREG(RADEON_SDRAM_MODE_REG);
  794.         info->BusCntl            = INREG(RADEON_BUS_CNTL);
  795.  
  796.      info->videoRam  &= ~1023;
  797.      info->FbMapSize  = info->videoRam * 1024;
  798.  
  799.     // info->gartSize      = RADEON_DEFAULT_GART_SIZE;
  800.      info->ringSize      = RADEON_DEFAULT_RING_SIZE;
  801.      info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
  802.  
  803.    //  info->gartTexSize   = info->gartSize - (info->ringSize + info->bufSize);
  804.  
  805.      info->pciAperSize   = RADEON_DEFAULT_PCI_APER_SIZE;
  806.      info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
  807.  
  808.  
  809.  
  810.      /* if the card is PCI Express reserve the last 32k for the gart table */
  811.  
  812.  //    if (info->cardType == CARD_PCIE )
  813.  //     /* work out the size of pcie aperture */
  814.  //       info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
  815.  //    else
  816.  //       info->FbSecureSize = 0;
  817.  
  818.      return TRUE;
  819. }
  820.  
  821.  
  822. static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
  823. {
  824.     u32_t cmd_stat;
  825.  
  826.     rhdPtr->ChipErrata = 0;
  827.  
  828.     if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
  829.          ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
  830.           == RADEON_CFG_ATI_REV_A11))
  831.         rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG;
  832.  
  833.     if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) ||
  834.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  835.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
  836.  
  837.     if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) ||
  838.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  839.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  840.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
  841.  
  842.     rhdPtr->cardType = CARD_PCI;
  843.  
  844.  
  845.     cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
  846.  
  847.     if (cmd_stat & RADEON_CAP_LIST)
  848.     {
  849.         u32_t cap_ptr, cap_id;
  850.  
  851.         cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
  852.         cap_ptr &= RADEON_CAP_PTR_MASK;
  853.  
  854.         while(cap_ptr != RADEON_CAP_ID_NULL)
  855.         {
  856.             cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
  857.             if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
  858.                  rhdPtr->cardType = CARD_AGP;
  859.                 break;
  860.             }
  861.             if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
  862.                 rhdPtr->cardType = CARD_PCIE;
  863.                 break;
  864.             }
  865.             cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
  866.         }
  867.     }
  868.  
  869.     dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
  870.               (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP");
  871.  
  872.     /* treat PCIE IGP cards as PCI  */
  873.     if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP)
  874.         rhdPtr->cardType = CARD_PCI;
  875.  
  876.     if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  877.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ||
  878.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) ||
  879.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) ||
  880.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) ||
  881.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) ||
  882.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) ||
  883.          (rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
  884.         rhdPtr->has_tcl = FALSE;
  885.     else {
  886.         rhdPtr->has_tcl = TRUE;
  887.     }
  888.  
  889.   //  rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
  890.  
  891.     return TRUE;
  892. }
  893.  
  894. #if 0
  895. static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
  896. {
  897.     unsigned char *RADEONMMIO = info->MMIO;
  898. //    unsigned long mode   = drmAgpGetMode(info->dri->drmFD); /* Default mode */
  899. //    unsigned int  vendor = drmAgpVendorId(info->dri->drmFD);
  900. //    unsigned int  device = drmAgpDeviceId(info->dri->drmFD);
  901.     /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
  902.        pcie-agp rialto bridge chip - use the one from bridge which must match */
  903.     uint32_t agp_status = (INREG(RADEON_AGP_STATUS) ); // & RADEON_AGP_MODE_MASK;
  904.     Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
  905.     unsigned int defaultMode;
  906.  
  907.     if (is_v3) {
  908.        defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
  909.     } else {
  910.         if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
  911.         else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
  912.         else defaultMode = 1;
  913.     }
  914.  
  915.    // agpMode = defaultMode;
  916.  
  917.     dbgprintf(pScreen->myNum, from, "Using AGP %dx\n", dbgprintf);
  918.  
  919.     mode &= ~RADEON_AGP_MODE_MASK;
  920.     if (is_v3) {
  921.         /* only set one mode bit for AGPv3 */
  922.     switch (defaultMode) {
  923.         case 8:          mode |= RADEON_AGPv3_8X_MODE; break;
  924.         case 4: default: mode |= RADEON_AGPv3_4X_MODE;
  925.         }
  926.         /*TODO: need to take care of other bits valid for v3 mode
  927.          *      currently these bits are not used in all tested cards.
  928.          */
  929.     } else {
  930.     switch (defaultMode) {
  931.         case 4:          mode |= RADEON_AGP_4X_MODE;
  932.         case 2:          mode |= RADEON_AGP_2X_MODE;
  933.         case 1: default: mode |= RADEON_AGP_1X_MODE;
  934.         }
  935.     }
  936.  
  937.     /* AGP Fast Writes.
  938.      * TODO: take into account that certain agp modes don't support fast
  939.      * writes at all */
  940.     mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
  941.  
  942.     dbgprintf("AGP Mode 0x%08lx\n", mode);
  943.  
  944.     if (drmAgpEnable(info->dri->drmFD, mode) < 0) {
  945.         xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
  946.         drmAgpRelease(info->dri->drmFD);
  947.         return FALSE;
  948.     }
  949.  
  950.     /* Workaround for some hardware bugs */
  951.     if (info->ChipFamily < CHIP_FAMILY_R200)
  952.         OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
  953.  
  954.                                 /* Modify the mode if the default mode
  955.                                  * is not appropriate for this
  956.                                  * particular combination of graphics
  957.                                  * card and AGP chipset.
  958.                                  */
  959.  
  960.     return TRUE;
  961. }
  962. #endif
  963.  
  964. Bool RHDPreInit()
  965. {
  966.     RHDPtr info;
  967.  
  968.     /* We need access to IO space already */
  969.     if ( !rhdMapMMIO(&rhd) ) {
  970.         dbgprintf("Failed to map MMIO.\n");
  971.         return FALSE;
  972.     };
  973.  
  974.     if( !RADEONPreInitChipType(&rhd))
  975.        return FALSE;
  976.  
  977.     if (!RADEONPreInitVRAM(&rhd))
  978.        return FALSE;
  979.  
  980.     RADEONInitMemoryMap(&rhd);
  981.  
  982.     if (!rhd.videoRam)
  983.     {
  984.        dbgprintf("No Video RAM detected.\n");
  985.        goto error1;
  986.     }
  987.     dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
  988.  
  989.  /* setup the raster pipes */
  990.     init_pipes(&rhd);
  991.  
  992.     init_gart(&rhd);
  993.  
  994.     rhd.FbFreeSize = rhd.videoRam << 10;
  995.  
  996.     rhd.FbFreeStart    = 10*1024*1024;
  997.     rhd.FbFreeSize     = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize;
  998.  
  999.     rhdInitHeap(&rhd);
  1000.  
  1001.     info = &rhd;
  1002.  
  1003.     return TRUE;
  1004.  
  1005. error1:
  1006.  
  1007.     return FALSE;
  1008. };
  1009.  
  1010. static void RADEONPllErrataAfterIndex()
  1011. {
  1012.     if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
  1013.        return;
  1014.  
  1015.     /* This workaround is necessary on rv200 and RS200 or PLL
  1016.      * reads may return garbage (among others...)
  1017.      */
  1018.     (void)INREG(RADEON_CLOCK_CNTL_DATA);
  1019.     (void)INREG(RADEON_CRTC_GEN_CNTL);
  1020. }
  1021.  
  1022.  
  1023. static void RADEONPllErrataAfterData()
  1024. {
  1025.  
  1026.     /* This function is required to workaround a hardware bug in some (all?)
  1027.      * revisions of the R300.  This workaround should be called after every
  1028.      * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
  1029.      * may not be correct.
  1030.      */
  1031.     if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
  1032.     {
  1033.         u32_t save, tmp;
  1034.  
  1035.         save = INREG(RADEON_CLOCK_CNTL_INDEX);
  1036.         tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
  1037.         OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
  1038.         tmp = INREG(RADEON_CLOCK_CNTL_DATA);
  1039.         OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
  1040.     }
  1041. }
  1042.  
  1043.  
  1044. /* Read PLL register */
  1045. static u32_t RADEONINPLL(int addr)
  1046. {
  1047.     u32_t       data;
  1048.  
  1049.     OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
  1050.     RADEONPllErrataAfterIndex();
  1051.     data = INREG(RADEON_CLOCK_CNTL_DATA);
  1052.     RADEONPllErrataAfterData();
  1053.  
  1054.     return data;
  1055. };
  1056.  
  1057. /* Write PLL information */
  1058. static void RADEONOUTPLL(int addr, u32_t data)
  1059. {
  1060.     OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
  1061.                                       RADEON_PLL_WR_EN));
  1062.     RADEONPllErrataAfterIndex();
  1063.     OUTREG(RADEON_CLOCK_CNTL_DATA, data);
  1064.     RADEONPllErrataAfterData();
  1065. }
  1066.  
  1067. static void init_pipes(RHDPtr info)
  1068. {
  1069.     u32_t gb_tile_config = 0;
  1070.  
  1071.     if ( (info->ChipFamily == CHIP_FAMILY_RV410) ||
  1072.          (info->ChipFamily == CHIP_FAMILY_R420)  ||
  1073.          (info->ChipFamily == CHIP_FAMILY_RS600) ||
  1074.          (info->ChipFamily == CHIP_FAMILY_RS690) ||
  1075.          (info->ChipFamily == CHIP_FAMILY_RS740) ||
  1076.          (info->ChipFamily == CHIP_FAMILY_RS400) ||
  1077.          (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D)
  1078.     {
  1079.         u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
  1080.  
  1081.         info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
  1082.         if (IS_R500_3D)
  1083.             OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
  1084.     }
  1085.     else
  1086.     {
  1087.         if ((info->ChipFamily == CHIP_FAMILY_R300) ||
  1088.            (info->ChipFamily == CHIP_FAMILY_R350))
  1089.         {
  1090.         /* R3xx chips */
  1091.             info->num_gb_pipes = 2;
  1092.         }
  1093.         else {
  1094.         /* RV3xx chips */
  1095.             info->num_gb_pipes = 1;
  1096.         }
  1097.     }
  1098.  
  1099.     if (IS_R300_3D || IS_R500_3D)
  1100.     {
  1101.  
  1102.         dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes);
  1103.  
  1104.         switch(info->num_gb_pipes) {
  1105.             case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
  1106.             case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
  1107.             case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
  1108.             default:
  1109.                 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
  1110.         }
  1111.  
  1112.         OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
  1113.         OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
  1114.         OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
  1115.         OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
  1116.                                        R300_DC_AUTOFLUSH_ENABLE |
  1117.                                        R300_DC_DC_DISABLE_IGNORE_PE));
  1118.     }
  1119.     else
  1120.         OUTREG(RADEON_RB3D_CNTL, 0);
  1121. };
  1122.  
  1123. #define RADEON_AIC_PT_BASE      0x01d8
  1124. #define RADEON_AIC_LO_ADDR              0x01dc
  1125. #define RADEON_AIC_HI_ADDR              0x01e0
  1126. #define RADEON_AIC_TLB_ADDR             0x01e4
  1127. #define RADEON_AIC_TLB_DATA             0x01e8
  1128.  
  1129. #define RADEON_PCIE_INDEX               0x0030
  1130. #define RADEON_PCIE_DATA                0x0034
  1131. #define RADEON_PCIE_TX_GART_CNTL        0x10
  1132. #       define RADEON_PCIE_TX_GART_EN           (1 << 0)
  1133. #       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
  1134. #       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1 << 1)
  1135. #       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3 << 1)
  1136. #       define RADEON_PCIE_TX_GART_MODE_32_128_CACHE    (0 << 3)
  1137. #       define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE   (1 << 3)
  1138. #       define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1 << 5)
  1139. #       define RADEON_PCIE_TX_GART_INVALIDATE_TLB       (1 << 8)
  1140. #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
  1141. #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
  1142. #define RADEON_PCIE_TX_GART_BASE          0x13
  1143. #define RADEON_PCIE_TX_GART_START_LO      0x14
  1144. #define RADEON_PCIE_TX_GART_START_HI      0x15
  1145. #define RADEON_PCIE_TX_GART_END_LO        0x16
  1146. #define RADEON_PCIE_TX_GART_END_HI        0x17
  1147.  
  1148.  
  1149. #define RADEON_WRITE8(offset, val)       \
  1150.     *(volatile u8_t*)((addr_t)rhd.MMIOBase + (offset)) = val
  1151.  
  1152. #define RADEON_WRITE_PCIE( addr, val )        \
  1153. do {                                          \
  1154.     RADEON_WRITE8( RADEON_PCIE_INDEX,         \
  1155.             ((addr) & 0xff));                 \
  1156.     OUTREG( RADEON_PCIE_DATA, (val) );        \
  1157. } while (0)
  1158.  
  1159. static u32_t RADEON_READ_PCIE(int addr)
  1160. {
  1161.         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
  1162.     return INREG(RADEON_PCIE_DATA);
  1163. }
  1164.  
  1165. static void radeon_set_pciegart(RHDPtr info, int on)
  1166. {
  1167.     u32_t tmp = RADEON_READ_PCIE(RADEON_PCIE_TX_GART_CNTL);
  1168.     if (on)
  1169.     {
  1170.                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
  1171.                   info->gart_vm_start);
  1172.                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
  1173.                   info->gart_table_dma);
  1174.                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
  1175.                   info->gart_vm_start);
  1176.                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
  1177.                   info->gart_vm_start + info->gart_size - 1);
  1178.  
  1179. //        radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
  1180.         OUTREG(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
  1181.  
  1182.                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
  1183.                                   RADEON_PCIE_TX_GART_EN);
  1184.         } else {
  1185.                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
  1186.                                   tmp & ~RADEON_PCIE_TX_GART_EN);
  1187.         }
  1188. }
  1189.  
  1190.  
  1191. static void radeon_set_pcigart(RHDPtr info, int on)
  1192. {
  1193.     u32_t tmp;
  1194.  
  1195.     tmp = INREG(RADEON_AIC_CNTL);
  1196.  
  1197.     if( on )
  1198.     {
  1199.         OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN);
  1200.  
  1201.                 /* set PCI GART page-table base address
  1202.                  */
  1203.         OUTREG(RADEON_AIC_PT_BASE, info->gart_table_dma);
  1204.  
  1205.                 /* set address range for PCI address translate
  1206.                  */
  1207.         OUTREG(RADEON_AIC_LO_ADDR, info->gart_vm_start);
  1208.         OUTREG(RADEON_AIC_HI_ADDR, info->gart_vm_start
  1209.                + info->gart_size - 1);
  1210.  
  1211.                 /* Turn off AGP aperture -- is this required for PCI GART?
  1212.                  */
  1213. //        radeon_write_agp_location(dev_priv, 0xffffffc0);
  1214.         OUTREG(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
  1215.     }
  1216.     else  OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
  1217.  
  1218. }
  1219.  
  1220.  
  1221. void init_gart(RHDPtr info)
  1222. {
  1223.     u32_t   *pci_gart;
  1224.     count_t  pages;
  1225.  
  1226.     info->gart_size  = 16*1024*1024;
  1227.  
  1228.     info->gart_vm_start = info->fbLocation + (info->videoRam << 10);
  1229.  
  1230.  
  1231.     if( info->gart_type == RADEON_IS_PCIE)
  1232.         info->gart_table_dma = info->gart_vm_start
  1233.                                - RADEON_PCIGART_TABLE_SIZE;
  1234.     else
  1235.         info->gart_table_dma = AllocPages(RADEON_PCIGART_TABLE_SIZE >> 12);
  1236.  
  1237.     if ( ! info->gart_table_dma) {
  1238.         dbgprintf("cannot allocate PCI GART page!\n");
  1239.         return;
  1240.     }
  1241.  
  1242.     info->gart_table = (u32_t*)MapIoMem(info->gart_table_dma,
  1243.                                         RADEON_PCIGART_TABLE_SIZE,
  1244.                                         PG_SW | PG_NOCACHE);
  1245.  
  1246.     if ( ! info->gart_table) {
  1247.         dbgprintf("cannot map PCI GART page!\n");
  1248.         return;
  1249.     }
  1250.  
  1251.     pci_gart = info->gart_table;
  1252.  
  1253.     memset(pci_gart, 0, RADEON_PCIGART_TABLE_SIZE);
  1254.  
  1255.     __asm__ __volatile(
  1256.     "wbinvd"
  1257.     :::"memory");
  1258.  
  1259.     if( info->gart_type == RADEON_IS_PCIE)
  1260.         radeon_set_pciegart(info, 1);
  1261.     else
  1262.         radeon_set_pcigart(info, 1);
  1263.  
  1264.     dbgprintf("gart size 0x%x\n", info->gart_size);
  1265.     dbgprintf("gart base 0x%x\n", info->gart_vm_start);
  1266.     dbgprintf("gart table 0x%x\n", info->gart_table);
  1267.     dbgprintf("gart table dma 0x%x\n", info->gart_table_dma);
  1268.  
  1269. }
  1270.