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  1.  
  2. #include <types.h>
  3. #include <list.h>
  4. #include <pci_regs.h>
  5.  
  6. #ifndef __PCI_H__
  7. #define __PCI_H__
  8.  
  9.  
  10. /* pci_slot represents a physical slot */
  11. struct pci_slot {
  12.     struct pci_bus *bus;        /* The bus this slot is on */
  13.     struct list_head list;      /* node in list of slots on this bus */
  14. //    struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
  15.     unsigned char number;       /* PCI_SLOT(pci_dev->devfn) */
  16. //    struct kobject kobj;
  17. };
  18.  
  19.  
  20. #define PCI_ANY_ID (~0)
  21.  
  22.  
  23. #define PCI_CLASS_NOT_DEFINED           0x0000
  24. #define PCI_CLASS_NOT_DEFINED_VGA       0x0001
  25.  
  26. #define PCI_BASE_CLASS_STORAGE          0x01
  27. #define PCI_CLASS_STORAGE_SCSI          0x0100
  28. #define PCI_CLASS_STORAGE_IDE           0x0101
  29. #define PCI_CLASS_STORAGE_FLOPPY        0x0102
  30. #define PCI_CLASS_STORAGE_IPI           0x0103
  31. #define PCI_CLASS_STORAGE_RAID          0x0104
  32. #define PCI_CLASS_STORAGE_SATA          0x0106
  33. #define PCI_CLASS_STORAGE_SATA_AHCI     0x010601
  34. #define PCI_CLASS_STORAGE_SAS           0x0107
  35. #define PCI_CLASS_STORAGE_OTHER         0x0180
  36.  
  37. #define PCI_BASE_CLASS_NETWORK          0x02
  38. #define PCI_CLASS_NETWORK_ETHERNET      0x0200
  39. #define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
  40. #define PCI_CLASS_NETWORK_FDDI          0x0202
  41. #define PCI_CLASS_NETWORK_ATM           0x0203
  42. #define PCI_CLASS_NETWORK_OTHER         0x0280
  43.  
  44. #define PCI_BASE_CLASS_DISPLAY          0x03
  45. #define PCI_CLASS_DISPLAY_VGA           0x0300
  46. #define PCI_CLASS_DISPLAY_XGA           0x0301
  47. #define PCI_CLASS_DISPLAY_3D            0x0302
  48. #define PCI_CLASS_DISPLAY_OTHER         0x0380
  49.  
  50. #define PCI_BASE_CLASS_MULTIMEDIA       0x04
  51. #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
  52. #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
  53. #define PCI_CLASS_MULTIMEDIA_PHONE      0x0402
  54. #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
  55.  
  56. #define PCI_BASE_CLASS_MEMORY           0x05
  57. #define PCI_CLASS_MEMORY_RAM            0x0500
  58. #define PCI_CLASS_MEMORY_FLASH          0x0501
  59. #define PCI_CLASS_MEMORY_OTHER          0x0580
  60.  
  61. #define PCI_BASE_CLASS_BRIDGE           0x06
  62. #define PCI_CLASS_BRIDGE_HOST           0x0600
  63. #define PCI_CLASS_BRIDGE_ISA            0x0601
  64. #define PCI_CLASS_BRIDGE_EISA           0x0602
  65. #define PCI_CLASS_BRIDGE_MC             0x0603
  66. #define PCI_CLASS_BRIDGE_PCI            0x0604
  67. #define PCI_CLASS_BRIDGE_PCMCIA         0x0605
  68. #define PCI_CLASS_BRIDGE_NUBUS          0x0606
  69. #define PCI_CLASS_BRIDGE_CARDBUS        0x0607
  70. #define PCI_CLASS_BRIDGE_RACEWAY        0x0608
  71. #define PCI_CLASS_BRIDGE_OTHER          0x0680
  72.  
  73. #define PCI_BASE_CLASS_COMMUNICATION    0x07
  74. #define PCI_CLASS_COMMUNICATION_SERIAL  0x0700
  75. #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
  76. #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
  77. #define PCI_CLASS_COMMUNICATION_MODEM   0x0703
  78. #define PCI_CLASS_COMMUNICATION_OTHER   0x0780
  79.  
  80. #define PCI_BASE_CLASS_SYSTEM           0x08
  81. #define PCI_CLASS_SYSTEM_PIC            0x0800
  82. #define PCI_CLASS_SYSTEM_PIC_IOAPIC     0x080010
  83. #define PCI_CLASS_SYSTEM_PIC_IOXAPIC    0x080020
  84. #define PCI_CLASS_SYSTEM_DMA            0x0801
  85. #define PCI_CLASS_SYSTEM_TIMER          0x0802
  86. #define PCI_CLASS_SYSTEM_RTC            0x0803
  87. #define PCI_CLASS_SYSTEM_PCI_HOTPLUG    0x0804
  88. #define PCI_CLASS_SYSTEM_SDHCI          0x0805
  89. #define PCI_CLASS_SYSTEM_OTHER          0x0880
  90.  
  91. #define PCI_BASE_CLASS_INPUT            0x09
  92. #define PCI_CLASS_INPUT_KEYBOARD        0x0900
  93. #define PCI_CLASS_INPUT_PEN             0x0901
  94. #define PCI_CLASS_INPUT_MOUSE           0x0902
  95. #define PCI_CLASS_INPUT_SCANNER         0x0903
  96. #define PCI_CLASS_INPUT_GAMEPORT        0x0904
  97. #define PCI_CLASS_INPUT_OTHER           0x0980
  98.  
  99. #define PCI_BASE_CLASS_DOCKING          0x0a
  100. #define PCI_CLASS_DOCKING_GENERIC       0x0a00
  101. #define PCI_CLASS_DOCKING_OTHER         0x0a80
  102.  
  103. #define PCI_BASE_CLASS_PROCESSOR        0x0b
  104. #define PCI_CLASS_PROCESSOR_386         0x0b00
  105. #define PCI_CLASS_PROCESSOR_486         0x0b01
  106. #define PCI_CLASS_PROCESSOR_PENTIUM     0x0b02
  107. #define PCI_CLASS_PROCESSOR_ALPHA       0x0b10
  108. #define PCI_CLASS_PROCESSOR_POWERPC     0x0b20
  109. #define PCI_CLASS_PROCESSOR_MIPS        0x0b30
  110. #define PCI_CLASS_PROCESSOR_CO          0x0b40
  111.  
  112. #define PCI_BASE_CLASS_SERIAL           0x0c
  113. #define PCI_CLASS_SERIAL_FIREWIRE       0x0c00
  114. #define PCI_CLASS_SERIAL_FIREWIRE_OHCI  0x0c0010
  115. #define PCI_CLASS_SERIAL_ACCESS         0x0c01
  116. #define PCI_CLASS_SERIAL_SSA            0x0c02
  117. #define PCI_CLASS_SERIAL_USB            0x0c03
  118. #define PCI_CLASS_SERIAL_USB_UHCI       0x0c0300
  119. #define PCI_CLASS_SERIAL_USB_OHCI       0x0c0310
  120. #define PCI_CLASS_SERIAL_USB_EHCI       0x0c0320
  121. #define PCI_CLASS_SERIAL_FIBER          0x0c04
  122. #define PCI_CLASS_SERIAL_SMBUS          0x0c05
  123.  
  124. #define PCI_BASE_CLASS_WIRELESS                 0x0d
  125. #define PCI_CLASS_WIRELESS_RF_CONTROLLER        0x0d10
  126. #define PCI_CLASS_WIRELESS_WHCI                 0x0d1010
  127.  
  128. #define PCI_BASE_CLASS_INTELLIGENT      0x0e
  129. #define PCI_CLASS_INTELLIGENT_I2O       0x0e00
  130.  
  131. #define PCI_BASE_CLASS_SATELLITE        0x0f
  132. #define PCI_CLASS_SATELLITE_TV          0x0f00
  133. #define PCI_CLASS_SATELLITE_AUDIO       0x0f01
  134. #define PCI_CLASS_SATELLITE_VOICE       0x0f03
  135. #define PCI_CLASS_SATELLITE_DATA        0x0f04
  136.  
  137. #define PCI_BASE_CLASS_CRYPT            0x10
  138. #define PCI_CLASS_CRYPT_NETWORK         0x1000
  139. #define PCI_CLASS_CRYPT_ENTERTAINMENT   0x1001
  140. #define PCI_CLASS_CRYPT_OTHER           0x1080
  141.  
  142. #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
  143. #define PCI_CLASS_SP_DPIO               0x1100
  144. #define PCI_CLASS_SP_OTHER              0x1180
  145.  
  146. #define PCI_CLASS_OTHERS                0xff
  147.  
  148.  
  149.  
  150. #define PCI_MAP_REG_START                   0x10
  151. #define PCI_MAP_REG_END                     0x28
  152. #define PCI_MAP_ROM_REG                     0x30
  153.  
  154. #define PCI_MAP_MEMORY                0x00000000
  155. #define PCI_MAP_IO                    0x00000001
  156.  
  157. #define PCI_MAP_MEMORY_TYPE           0x00000007
  158. #define PCI_MAP_IO_TYPE               0x00000003
  159.  
  160. #define PCI_MAP_MEMORY_TYPE_32BIT     0x00000000
  161. #define PCI_MAP_MEMORY_TYPE_32BIT_1M  0x00000002
  162. #define PCI_MAP_MEMORY_TYPE_64BIT     0x00000004
  163. #define PCI_MAP_MEMORY_TYPE_MASK      0x00000006
  164. #define PCI_MAP_MEMORY_CACHABLE       0x00000008
  165. #define PCI_MAP_MEMORY_ATTR_MASK      0x0000000e
  166. #define PCI_MAP_MEMORY_ADDRESS_MASK   0xfffffff0
  167.  
  168. #define PCI_MAP_IO_ATTR_MASK          0x00000003
  169.  
  170.  
  171.  
  172. #define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
  173. #define PCI_MAP_IS_MEM(b)   (!PCI_MAP_IS_IO(b))
  174.  
  175. #define PCI_MAP_IS64BITMEM(b)   \
  176.     (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
  177.  
  178. #define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
  179. #define PCIGETMEMORY64HIGH(b)   (*((CARD32*)&b + 1))
  180. #define PCIGETMEMORY64(b)   \
  181.     (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
  182.  
  183. #define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc
  184.  
  185. #define PCIGETIO(b)     ((b) & PCI_MAP_IO_ADDRESS_MASK)
  186.  
  187. #define PCI_MAP_ROM_DECODE_ENABLE     0x00000001
  188. #define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800
  189.  
  190. #define PCIGETROM(b)        ((b) & PCI_MAP_ROM_ADDRESS_MASK)
  191.  
  192.  
  193. #ifndef PCI_DOM_MASK
  194. # define PCI_DOM_MASK 0x0ffu
  195. #endif
  196. #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
  197.  
  198. #define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
  199.                   (((d) & 0x00001fu) << 11) | \
  200.                   (((f) & 0x000007u) << 8))
  201.  
  202. #define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
  203. #define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
  204. #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
  205. #define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
  206.  
  207. #define PCI_DEVFN(slot, func)  ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  208. #define PCI_SLOT(devfn)        (((devfn) >> 3) & 0x1f)
  209. #define PCI_FUNC(devfn)        ((devfn) & 0x07)
  210.  
  211. /* Ioctls for /proc/bus/pci/X/Y nodes. */
  212. #define PCIIOC_BASE             ('P' << 24 | 'C' << 16 | 'I' << 8)
  213. #define PCIIOC_CONTROLLER       (PCIIOC_BASE | 0x00)    /* Get controller for PCI device. */
  214. #define PCIIOC_MMAP_IS_IO       (PCIIOC_BASE | 0x01)    /* Set mmap state to I/O space. */
  215. #define PCIIOC_MMAP_IS_MEM      (PCIIOC_BASE | 0x02)    /* Set mmap state to MEM space. */
  216. #define PCIIOC_WRITE_COMBINE    (PCIIOC_BASE | 0x03)    /* Enable/disable write-combining. */
  217.  
  218.  
  219. typedef unsigned int __bitwise pci_channel_state_t;
  220.  
  221. enum pci_channel_state {
  222.     /* I/O channel is in normal state */
  223.     pci_channel_io_normal = (__force pci_channel_state_t) 1,
  224.  
  225.     /* I/O to channel is blocked */
  226.     pci_channel_io_frozen = (__force pci_channel_state_t) 2,
  227.  
  228.     /* PCI card is dead */
  229.     pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
  230. };
  231.  
  232.  
  233. typedef unsigned int PCITAG;
  234.  
  235. extern inline PCITAG
  236. pciTag(int busnum, int devnum, int funcnum)
  237. {
  238.     return(PCI_MAKE_TAG(busnum,devnum,funcnum));
  239. }
  240.  
  241.  
  242. struct resource
  243. {
  244.          resource_size_t start;
  245.          resource_size_t end;
  246.          const char *name;
  247.          unsigned long flags;
  248.          struct resource *parent, *sibling, *child;
  249. };
  250.  
  251. /* This defines the direction arg to the DMA mapping routines. */
  252. #define PCI_DMA_BIDIRECTIONAL   0
  253. #define PCI_DMA_TODEVICE        1
  254. #define PCI_DMA_FROMDEVICE      2
  255. #define PCI_DMA_NONE            3
  256.  
  257. /*
  258.  *  For PCI devices, the region numbers are assigned this way:
  259.  */
  260. enum {
  261.     /* #0-5: standard PCI resources */
  262.     PCI_STD_RESOURCES,
  263.     PCI_STD_RESOURCE_END = 5,
  264.  
  265.     /* #6: expansion ROM resource */
  266.     PCI_ROM_RESOURCE,
  267.  
  268.     /* device specific resources */
  269. #ifdef CONFIG_PCI_IOV
  270.     PCI_IOV_RESOURCES,
  271.     PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
  272. #endif
  273.  
  274.     /* resources assigned to buses behind the bridge */
  275. #define PCI_BRIDGE_RESOURCE_NUM 4
  276.  
  277.     PCI_BRIDGE_RESOURCES,
  278.     PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
  279.                   PCI_BRIDGE_RESOURCE_NUM - 1,
  280.  
  281.     /* total resources associated with a PCI device */
  282.     PCI_NUM_RESOURCES,
  283.  
  284.     /* preserve this for compatibility */
  285.     DEVICE_COUNT_RESOURCE
  286. };
  287.  
  288.  
  289. /*
  290.  * IO resources have these defined flags.
  291.  */
  292. #define IORESOURCE_BITS         0x000000ff      /* Bus-specific bits */
  293.  
  294. #define IORESOURCE_IO           0x00000100      /* Resource type */
  295. #define IORESOURCE_MEM          0x00000200
  296. #define IORESOURCE_IRQ          0x00000400
  297. #define IORESOURCE_DMA          0x00000800
  298.  
  299. #define IORESOURCE_PREFETCH     0x00001000      /* No side effects */
  300. #define IORESOURCE_READONLY     0x00002000
  301. #define IORESOURCE_CACHEABLE    0x00004000
  302. #define IORESOURCE_RANGELENGTH  0x00008000
  303. #define IORESOURCE_SHADOWABLE   0x00010000
  304. #define IORESOURCE_BUS_HAS_VGA  0x00080000
  305.  
  306. #define IORESOURCE_DISABLED     0x10000000
  307. #define IORESOURCE_UNSET        0x20000000
  308. #define IORESOURCE_AUTO         0x40000000
  309. #define IORESOURCE_BUSY         0x80000000      /* Driver has marked this resource busy */
  310.  
  311. /* ISA PnP IRQ specific bits (IORESOURCE_BITS) */
  312. #define IORESOURCE_IRQ_HIGHEDGE         (1<<0)
  313. #define IORESOURCE_IRQ_LOWEDGE          (1<<1)
  314. #define IORESOURCE_IRQ_HIGHLEVEL        (1<<2)
  315. #define IORESOURCE_IRQ_LOWLEVEL         (1<<3)
  316. #define IORESOURCE_IRQ_SHAREABLE        (1<<4)
  317.  
  318. /* ISA PnP DMA specific bits (IORESOURCE_BITS) */
  319. #define IORESOURCE_DMA_TYPE_MASK        (3<<0)
  320. #define IORESOURCE_DMA_8BIT             (0<<0)
  321. #define IORESOURCE_DMA_8AND16BIT        (1<<0)
  322. #define IORESOURCE_DMA_16BIT            (2<<0)
  323.  
  324. #define IORESOURCE_DMA_MASTER           (1<<2)
  325. #define IORESOURCE_DMA_BYTE             (1<<3)
  326. #define IORESOURCE_DMA_WORD             (1<<4)
  327.  
  328. #define IORESOURCE_DMA_SPEED_MASK       (3<<6)
  329. #define IORESOURCE_DMA_COMPATIBLE       (0<<6)
  330. #define IORESOURCE_DMA_TYPEA            (1<<6)
  331. #define IORESOURCE_DMA_TYPEB            (2<<6)
  332. #define IORESOURCE_DMA_TYPEF            (3<<6)
  333.  
  334. /* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */
  335. #define IORESOURCE_MEM_WRITEABLE        (1<<0)  /* dup: IORESOURCE_READONLY */
  336. #define IORESOURCE_MEM_CACHEABLE        (1<<1)  /* dup: IORESOURCE_CACHEABLE */
  337. #define IORESOURCE_MEM_RANGELENGTH      (1<<2)  /* dup: IORESOURCE_RANGELENGTH */
  338. #define IORESOURCE_MEM_TYPE_MASK        (3<<3)
  339. #define IORESOURCE_MEM_8BIT             (0<<3)
  340. #define IORESOURCE_MEM_16BIT            (1<<3)
  341. #define IORESOURCE_MEM_8AND16BIT        (2<<3)
  342. #define IORESOURCE_MEM_32BIT            (3<<3)
  343. #define IORESOURCE_MEM_SHADOWABLE       (1<<5)  /* dup: IORESOURCE_SHADOWABLE */
  344. #define IORESOURCE_MEM_EXPANSIONROM     (1<<6)
  345.  
  346. /* PCI ROM control bits (IORESOURCE_BITS) */
  347. #define IORESOURCE_ROM_ENABLE           (1<<0)  /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
  348. #define IORESOURCE_ROM_SHADOW           (1<<1)  /* ROM is copy at C000:0 */
  349. #define IORESOURCE_ROM_COPY             (1<<2)  /* ROM is alloc'd copy, resource field overlaid */
  350. #define IORESOURCE_ROM_BIOS_COPY        (1<<3)  /* ROM is BIOS copy, resource field overlaid */
  351.  
  352. /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
  353. #define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
  354.  
  355.  
  356.  
  357.  
  358. /*
  359.  *  For PCI devices, the region numbers are assigned this way:
  360.  *
  361.  *      0-5     standard PCI regions
  362.  *      6       expansion ROM
  363.  *      7-10    bridges: address space assigned to buses behind the bridge
  364.  */
  365.  
  366. #define PCI_ROM_RESOURCE        6
  367. #define PCI_BRIDGE_RESOURCES    7
  368. #define PCI_NUM_RESOURCES       11
  369.  
  370. #ifndef PCI_BUS_NUM_RESOURCES
  371. #define PCI_BUS_NUM_RESOURCES   8
  372. #endif
  373.  
  374. #define DEVICE_COUNT_RESOURCE   12
  375.  
  376.  
  377. #define PCI_CFG_SPACE_SIZE      256
  378. #define PCI_CFG_SPACE_EXP_SIZE  4096
  379.  
  380.  
  381. typedef int __bitwise pci_power_t;
  382.  
  383. #define PCI_D0      ((pci_power_t __force) 0)
  384. #define PCI_D1      ((pci_power_t __force) 1)
  385. #define PCI_D2      ((pci_power_t __force) 2)
  386. #define PCI_D3hot   ((pci_power_t __force) 3)
  387. #define PCI_D3cold  ((pci_power_t __force) 4)
  388. #define PCI_UNKNOWN ((pci_power_t __force) 5)
  389. #define PCI_POWER_ERROR ((pci_power_t __force) -1)
  390.  
  391. /*
  392.  * The pci_dev structure is used to describe PCI devices.
  393.  */
  394. struct pci_dev {
  395.     struct list_head bus_list;  /* node in per-bus list */
  396.     struct pci_bus  *bus;       /* bus this device is on */
  397.     struct pci_bus  *subordinate;   /* bus this device bridges to */
  398.  
  399.     void        *sysdata;       /* hook for sys-specific extension */
  400. //    struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
  401.     struct pci_slot *slot;      /* Physical slot this device is in */
  402.     u32_t        busnr;
  403.         unsigned int    devfn;          /* encoded device & function index */
  404.         unsigned short  vendor;
  405.         unsigned short  device;
  406.         unsigned short  subsystem_vendor;
  407.         unsigned short  subsystem_device;
  408.         unsigned int    class;          /* 3 bytes: (base,sub,prog-if) */
  409.         u8              revision;       /* PCI revision, low byte of class word */
  410.         u8              hdr_type;       /* PCI header type (`multi' flag masked out) */
  411.         u8              pcie_cap;       /* PCI-E capability offset */
  412.     u8           pcie_type;     /* PCI-E device/port type */
  413.         u8              rom_base_reg;   /* which config register controls the ROM */
  414.         u8              pin;            /* which interrupt pin this device uses */
  415.  
  416.  //   struct pci_driver *driver;  /* which driver has allocated this device */
  417.         u64             dma_mask;       /* Mask of the bits of bus address this
  418.                        device implements.  Normally this is
  419.                        0xffffffff.  You only need to change
  420.                        this if your device has broken DMA
  421.                        or supports 64-bit transfers.  */
  422.  
  423.  //   struct device_dma_parameters dma_parms;
  424.  
  425.     pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
  426.                                        this is D0-D3, D0 being fully functional,
  427.                                        and D3 being off. */
  428.     int     pm_cap;     /* PM capability offset in the
  429.                            configuration space */
  430.     unsigned int    pme_support:5;  /* Bitmask of states from which PME#
  431.                        can be generated */
  432.         unsigned int    pme_interrupt:1;
  433.     unsigned int    d1_support:1;   /* Low power state D1 is supported */
  434.     unsigned int    d2_support:1;   /* Low power state D2 is supported */
  435.     unsigned int    no_d1d2:1;  /* Only allow D0 and D3 */
  436.         unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
  437.                                                    decoding during bar sizing */
  438.         unsigned int    wakeup_prepared:1;
  439.         unsigned int    d3_delay;       /* D3->D0 transition time in ms */
  440.  
  441.     pci_channel_state_t error_state;    /* current connectivity state */
  442.     struct  device  dev;        /* Generic device interface */
  443.  
  444.     int     cfg_size;   /* Size of configuration space */
  445.  
  446.     /*
  447.      * Instead of touching interrupt line and base address registers
  448.      * directly, use the values stored here. They might be different!
  449.      */
  450.     unsigned int    irq;
  451.     struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
  452.  
  453.     /* These fields are used by common fixups */
  454.     unsigned int    transparent:1;  /* Transparent PCI bridge */
  455.     unsigned int    multifunction:1;/* Part of multi-function device */
  456.     /* keep track of device state */
  457.     unsigned int    is_added:1;
  458.     unsigned int    is_busmaster:1; /* device is busmaster */
  459.     unsigned int    no_msi:1;   /* device may not use msi */
  460.     unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
  461.     unsigned int    broken_parity_status:1; /* Device generates false positive parity */
  462.     unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
  463.     unsigned int    msi_enabled:1;
  464.     unsigned int    msix_enabled:1;
  465.     unsigned int    ari_enabled:1;  /* ARI forwarding */
  466.     unsigned int    is_managed:1;
  467.         unsigned int    is_pcie:1;      /* Obsolete. Will be removed.
  468.                                            Use pci_is_pcie() instead */
  469.         unsigned int    needs_freset:1; /* Dev requires fundamental reset */
  470.     unsigned int    state_saved:1;
  471.     unsigned int    is_physfn:1;
  472.     unsigned int    is_virtfn:1;
  473.         unsigned int    reset_fn:1;
  474.         unsigned int    is_hotplug_bridge:1;
  475.         unsigned int    __aer_firmware_first_valid:1;
  476.         unsigned int    __aer_firmware_first:1;
  477.  
  478.  
  479. //    u32     saved_config_space[16]; /* config space saved at suspend time */
  480. //    struct hlist_head saved_cap_space;
  481. //    struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
  482. //    int rom_attr_enabled;       /* has display of the rom attribute been enabled? */
  483. //    struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
  484. //    struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
  485. };
  486.  
  487. #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
  488. #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
  489. #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
  490. #define pci_resource_len(dev,bar) \
  491.         ((pci_resource_start((dev), (bar)) == 0 &&      \
  492.           pci_resource_end((dev), (bar)) ==             \
  493.           pci_resource_start((dev), (bar))) ? 0 :       \
  494.                                                         \
  495.          (pci_resource_end((dev), (bar)) -              \
  496.           pci_resource_start((dev), (bar)) + 1))
  497.  
  498. struct pci_device_id
  499. {
  500.     u16_t vendor, device;           /* Vendor and device ID or PCI_ANY_ID*/
  501.     u16_t subvendor, subdevice;     /* Subsystem ID's or PCI_ANY_ID */
  502.     u32_t class, class_mask;        /* (class,subclass,prog-if) triplet */
  503.     u32_t driver_data;              /* Data private to the driver */
  504. };
  505.  
  506. typedef struct
  507. {
  508.     struct list_head    link;
  509.     struct pci_dev      pci_dev;
  510. }pci_dev_t;
  511.  
  512.  
  513. typedef unsigned short __bitwise pci_bus_flags_t;
  514. enum pci_bus_flags {
  515.     PCI_BUS_FLAGS_NO_MSI   = (__force pci_bus_flags_t) 1,
  516.     PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
  517. };
  518.  
  519. struct pci_sysdata
  520. {
  521.     int             domain;         /* PCI domain */
  522.     int             node;           /* NUMA node */
  523. #ifdef CONFIG_X86_64
  524.     void            *iommu;         /* IOMMU private data */
  525. #endif
  526. };
  527.  
  528. struct pci_bus;
  529.  
  530. struct pci_ops
  531. {
  532.     int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  533.     int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  534. };
  535.  
  536. /*
  537.  * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
  538.  * to P2P or CardBus bridge windows) go in a table.  Additional ones (for
  539.  * buses below host bridges or subtractive decode bridges) go in the list.
  540.  * Use pci_bus_for_each_resource() to iterate through all the resources.
  541.  */
  542.  
  543. /*
  544.  * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
  545.  * and there's no way to program the bridge with the details of the window.
  546.  * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
  547.  * decode bit set, because they are explicit and can be programmed with _SRS.
  548.  */
  549. #define PCI_SUBTRACTIVE_DECODE  0x1
  550.  
  551. struct pci_bus_resource {
  552.         struct list_head list;
  553.         struct resource *res;
  554.         unsigned int flags;
  555. };
  556.  
  557. #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
  558.  
  559. struct pci_bus {
  560.     struct list_head node;      /* node in list of buses */
  561.     struct pci_bus  *parent;    /* parent bus this bridge is on */
  562.     struct list_head children;  /* list of child buses */
  563.     struct list_head devices;   /* list of devices on this bus */
  564.     struct pci_dev  *self;      /* bridge device as seen by parent */
  565.     struct list_head slots;     /* list of slots on this bus */
  566.     struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
  567.     struct list_head resources; /* address space routed to this bus */
  568.  
  569.     struct pci_ops  *ops;       /* configuration access functions */
  570.     void        *sysdata;       /* hook for sys-specific extension */
  571.  
  572.     unsigned char   number;     /* bus number */
  573.     unsigned char   primary;    /* number of primary bridge */
  574.     unsigned char   secondary;  /* number of secondary bridge */
  575.     unsigned char   subordinate;    /* max number of subordinate buses */
  576.  
  577.     char        name[48];
  578.  
  579.     unsigned short  bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
  580.     pci_bus_flags_t bus_flags;  /* Inherited by child busses */
  581. //    struct device       *bridge;
  582. //    struct device       dev;
  583. //    struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
  584. //    struct bin_attribute    *legacy_mem; /* legacy mem */
  585.     unsigned int        is_added:1;
  586. };
  587.  
  588. #define pci_bus_b(n)    list_entry(n, struct pci_bus, node)
  589. #define to_pci_bus(n)   container_of(n, struct pci_bus, dev)
  590. #define pci_dev_b(n)    list_entry(n, struct pci_dev, bus_list)
  591. #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
  592. #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
  593.  
  594.  
  595. static inline int pci_domain_nr(struct pci_bus *bus)
  596. {
  597.     struct pci_sysdata *sd = bus->sysdata;
  598.     return sd->domain;
  599. }
  600. static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
  601.  
  602. /*
  603.  * Error values that may be returned by PCI functions.
  604.  */
  605. #define PCIBIOS_SUCCESSFUL              0x00
  606. #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
  607. #define PCIBIOS_BAD_VENDOR_ID           0x83
  608. #define PCIBIOS_DEVICE_NOT_FOUND        0x86
  609. #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
  610. #define PCIBIOS_SET_FAILED              0x88
  611. #define PCIBIOS_BUFFER_TOO_SMALL        0x89
  612.  
  613. /* Low-level architecture-dependent routines */
  614.  
  615. struct pci_bus_region {
  616.         resource_size_t start;
  617.         resource_size_t end;
  618. };
  619.  
  620.  
  621.  
  622.  
  623.  
  624.  
  625.  
  626.  
  627. int enum_pci_devices(void);
  628.  
  629. struct pci_device_id*
  630. find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist);
  631.  
  632. #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
  633.  
  634. int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
  635.  
  636. struct pci_bus * pci_create_bus(int bus, struct pci_ops *ops, void *sysdata);
  637. struct pci_bus * pci_find_bus(int domain, int busnr);
  638. int pci_find_capability(struct pci_dev *dev, int cap);
  639. int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
  640. int pci_find_ext_capability(struct pci_dev *dev, int cap);
  641. int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
  642.                                 int cap);
  643. int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
  644. struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
  645.  
  646. static inline bool pci_is_root_bus(struct pci_bus *pbus)
  647. {
  648.     return !(pbus->parent);
  649. }
  650.  
  651. /**
  652.  * pci_pcie_cap - get the saved PCIe capability offset
  653.  * @dev: PCI device
  654.  *
  655.  * PCIe capability offset is calculated at PCI device initialization
  656.  * time and saved in the data structure. This function returns saved
  657.  * PCIe capability offset. Using this instead of pci_find_capability()
  658.  * reduces unnecessary search in the PCI configuration space. If you
  659.  * need to calculate PCIe capability offset from raw device for some
  660.  * reasons, please use pci_find_capability() instead.
  661.  */
  662. static inline int pci_pcie_cap(struct pci_dev *dev)
  663. {
  664.     return dev->pcie_cap;
  665. }
  666.  
  667. /**
  668.  * pci_is_pcie - check if the PCI device is PCI Express capable
  669.  * @dev: PCI device
  670.  *
  671.  * Retrun true if the PCI device is PCI Express capable, false otherwise.
  672.  */
  673. static inline bool pci_is_pcie(struct pci_dev *dev)
  674. {
  675.     return !!pci_pcie_cap(dev);
  676. }
  677.  
  678. #define pci_name(x) "radeon"
  679.  
  680. #endif //__PCI__H__
  681.  
  682.  
  683.