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  1. /*
  2.  * Copyright © 2008 Keith Packard
  3.  *
  4.  * Permission to use, copy, modify, distribute, and sell this software and its
  5.  * documentation for any purpose is hereby granted without fee, provided that
  6.  * the above copyright notice appear in all copies and that both that copyright
  7.  * notice and this permission notice appear in supporting documentation, and
  8.  * that the name of the copyright holders not be used in advertising or
  9.  * publicity pertaining to distribution of the software without specific,
  10.  * written prior permission.  The copyright holders make no representations
  11.  * about the suitability of this software for any purpose.  It is provided "as
  12.  * is" without express or implied warranty.
  13.  *
  14.  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15.  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16.  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17.  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18.  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19.  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20.  * OF THIS SOFTWARE.
  21.  */
  22.  
  23. #ifndef _DRM_DP_HELPER_H_
  24. #define _DRM_DP_HELPER_H_
  25.  
  26. #include <linux/types.h>
  27. #include <linux/i2c.h>
  28. #include <linux/delay.h>
  29.  
  30. /*
  31.  * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
  32.  * DP and DPCD versions are independent.  Differences from 1.0 are not noted,
  33.  * 1.0 devices basically don't exist in the wild.
  34.  *
  35.  * Abbreviations, in chronological order:
  36.  *
  37.  * eDP: Embedded DisplayPort version 1
  38.  * DPI: DisplayPort Interoperability Guideline v1.1a
  39.  * 1.2: DisplayPort 1.2
  40.  *
  41.  * 1.2 formally includes both eDP and DPI definitions.
  42.  */
  43.  
  44. #define AUX_NATIVE_WRITE        0x8
  45. #define AUX_NATIVE_READ         0x9
  46. #define AUX_I2C_WRITE           0x0
  47. #define AUX_I2C_READ            0x1
  48. #define AUX_I2C_STATUS          0x2
  49. #define AUX_I2C_MOT             0x4
  50.  
  51. #define AUX_NATIVE_REPLY_ACK    (0x0 << 4)
  52. #define AUX_NATIVE_REPLY_NACK   (0x1 << 4)
  53. #define AUX_NATIVE_REPLY_DEFER  (0x2 << 4)
  54. #define AUX_NATIVE_REPLY_MASK   (0x3 << 4)
  55.  
  56. #define AUX_I2C_REPLY_ACK       (0x0 << 6)
  57. #define AUX_I2C_REPLY_NACK      (0x1 << 6)
  58. #define AUX_I2C_REPLY_DEFER     (0x2 << 6)
  59. #define AUX_I2C_REPLY_MASK      (0x3 << 6)
  60.  
  61. /* AUX CH addresses */
  62. /* DPCD */
  63. #define DP_DPCD_REV                         0x000
  64.  
  65. #define DP_MAX_LINK_RATE                    0x001
  66.  
  67. #define DP_MAX_LANE_COUNT                   0x002
  68. # define DP_MAX_LANE_COUNT_MASK             0x1f
  69. # define DP_TPS3_SUPPORTED                  (1 << 6) /* 1.2 */
  70. # define DP_ENHANCED_FRAME_CAP              (1 << 7)
  71.  
  72. #define DP_MAX_DOWNSPREAD                   0x003
  73. # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING  (1 << 6)
  74.  
  75. #define DP_NORP                             0x004
  76.  
  77. #define DP_DOWNSTREAMPORT_PRESENT           0x005
  78. # define DP_DWN_STRM_PORT_PRESENT           (1 << 0)
  79. # define DP_DWN_STRM_PORT_TYPE_MASK         0x06
  80. /* 00b = DisplayPort */
  81. /* 01b = Analog */
  82. /* 10b = TMDS or HDMI */
  83. /* 11b = Other */
  84. # define DP_FORMAT_CONVERSION               (1 << 3)
  85. # define DP_DETAILED_CAP_INFO_AVAILABLE     (1 << 4) /* DPI */
  86.  
  87. #define DP_MAIN_LINK_CHANNEL_CODING         0x006
  88.  
  89. #define DP_DOWN_STREAM_PORT_COUNT           0x007
  90. # define DP_PORT_COUNT_MASK                 0x0f
  91. # define DP_MSA_TIMING_PAR_IGNORED          (1 << 6) /* eDP */
  92. # define DP_OUI_SUPPORT                     (1 << 7)
  93.  
  94. #define DP_I2C_SPEED_CAP                    0x00c    /* DPI */
  95. # define DP_I2C_SPEED_1K                    0x01
  96. # define DP_I2C_SPEED_5K                    0x02
  97. # define DP_I2C_SPEED_10K                   0x04
  98. # define DP_I2C_SPEED_100K                  0x08
  99. # define DP_I2C_SPEED_400K                  0x10
  100. # define DP_I2C_SPEED_1M                    0x20
  101.  
  102. #define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
  103. #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
  104.  
  105. /* Multiple stream transport */
  106. #define DP_MSTM_CAP                         0x021   /* 1.2 */
  107. # define DP_MST_CAP                         (1 << 0)
  108.  
  109. #define DP_PSR_SUPPORT                      0x070   /* XXX 1.2? */
  110. # define DP_PSR_IS_SUPPORTED                1
  111. #define DP_PSR_CAPS                         0x071   /* XXX 1.2? */
  112. # define DP_PSR_NO_TRAIN_ON_EXIT            1
  113. # define DP_PSR_SETUP_TIME_330              (0 << 1)
  114. # define DP_PSR_SETUP_TIME_275              (1 << 1)
  115. # define DP_PSR_SETUP_TIME_220              (2 << 1)
  116. # define DP_PSR_SETUP_TIME_165              (3 << 1)
  117. # define DP_PSR_SETUP_TIME_110              (4 << 1)
  118. # define DP_PSR_SETUP_TIME_55               (5 << 1)
  119. # define DP_PSR_SETUP_TIME_0                (6 << 1)
  120. # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
  121. # define DP_PSR_SETUP_TIME_SHIFT            1
  122.  
  123. /*
  124.  * 0x80-0x8f describe downstream port capabilities, but there are two layouts
  125.  * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
  126.  * each port's descriptor is one byte wide.  If it was set, each port's is
  127.  * four bytes wide, starting with the one byte from the base info.  As of
  128.  * DP interop v1.1a only VGA defines additional detail.
  129.  */
  130.  
  131. /* offset 0 */
  132. #define DP_DOWNSTREAM_PORT_0                0x80
  133. # define DP_DS_PORT_TYPE_MASK               (7 << 0)
  134. # define DP_DS_PORT_TYPE_DP                 0
  135. # define DP_DS_PORT_TYPE_VGA                1
  136. # define DP_DS_PORT_TYPE_DVI                2
  137. # define DP_DS_PORT_TYPE_HDMI               3
  138. # define DP_DS_PORT_TYPE_NON_EDID           4
  139. # define DP_DS_PORT_HPD                     (1 << 3)
  140. /* offset 1 for VGA is maximum megapixels per second / 8 */
  141. /* offset 2 */
  142. # define DP_DS_VGA_MAX_BPC_MASK             (3 << 0)
  143. # define DP_DS_VGA_8BPC                     0
  144. # define DP_DS_VGA_10BPC                    1
  145. # define DP_DS_VGA_12BPC                    2
  146. # define DP_DS_VGA_16BPC                    3
  147.  
  148. /* link configuration */
  149. #define DP_LINK_BW_SET                      0x100
  150. # define DP_LINK_BW_1_62                    0x06
  151. # define DP_LINK_BW_2_7                     0x0a
  152. # define DP_LINK_BW_5_4                     0x14    /* 1.2 */
  153.  
  154. #define DP_LANE_COUNT_SET                   0x101
  155. # define DP_LANE_COUNT_MASK                 0x0f
  156. # define DP_LANE_COUNT_ENHANCED_FRAME_EN    (1 << 7)
  157.  
  158. #define DP_TRAINING_PATTERN_SET             0x102
  159. # define DP_TRAINING_PATTERN_DISABLE        0
  160. # define DP_TRAINING_PATTERN_1              1
  161. # define DP_TRAINING_PATTERN_2              2
  162. # define DP_TRAINING_PATTERN_3              3       /* 1.2 */
  163. # define DP_TRAINING_PATTERN_MASK           0x3
  164.  
  165. # define DP_LINK_QUAL_PATTERN_DISABLE       (0 << 2)
  166. # define DP_LINK_QUAL_PATTERN_D10_2         (1 << 2)
  167. # define DP_LINK_QUAL_PATTERN_ERROR_RATE    (2 << 2)
  168. # define DP_LINK_QUAL_PATTERN_PRBS7         (3 << 2)
  169. # define DP_LINK_QUAL_PATTERN_MASK          (3 << 2)
  170.  
  171. # define DP_RECOVERED_CLOCK_OUT_EN          (1 << 4)
  172. # define DP_LINK_SCRAMBLING_DISABLE         (1 << 5)
  173.  
  174. # define DP_SYMBOL_ERROR_COUNT_BOTH         (0 << 6)
  175. # define DP_SYMBOL_ERROR_COUNT_DISPARITY    (1 << 6)
  176. # define DP_SYMBOL_ERROR_COUNT_SYMBOL       (2 << 6)
  177. # define DP_SYMBOL_ERROR_COUNT_MASK         (3 << 6)
  178.  
  179. #define DP_TRAINING_LANE0_SET               0x103
  180. #define DP_TRAINING_LANE1_SET               0x104
  181. #define DP_TRAINING_LANE2_SET               0x105
  182. #define DP_TRAINING_LANE3_SET               0x106
  183.  
  184. # define DP_TRAIN_VOLTAGE_SWING_MASK        0x3
  185. # define DP_TRAIN_VOLTAGE_SWING_SHIFT       0
  186. # define DP_TRAIN_MAX_SWING_REACHED         (1 << 2)
  187. # define DP_TRAIN_VOLTAGE_SWING_400         (0 << 0)
  188. # define DP_TRAIN_VOLTAGE_SWING_600         (1 << 0)
  189. # define DP_TRAIN_VOLTAGE_SWING_800         (2 << 0)
  190. # define DP_TRAIN_VOLTAGE_SWING_1200        (3 << 0)
  191.  
  192. # define DP_TRAIN_PRE_EMPHASIS_MASK         (3 << 3)
  193. # define DP_TRAIN_PRE_EMPHASIS_0            (0 << 3)
  194. # define DP_TRAIN_PRE_EMPHASIS_3_5          (1 << 3)
  195. # define DP_TRAIN_PRE_EMPHASIS_6            (2 << 3)
  196. # define DP_TRAIN_PRE_EMPHASIS_9_5          (3 << 3)
  197.  
  198. # define DP_TRAIN_PRE_EMPHASIS_SHIFT        3
  199. # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED  (1 << 5)
  200.  
  201. #define DP_DOWNSPREAD_CTRL                  0x107
  202. # define DP_SPREAD_AMP_0_5                  (1 << 4)
  203. # define DP_MSA_TIMING_PAR_IGNORE_EN        (1 << 7) /* eDP */
  204.  
  205. #define DP_MAIN_LINK_CHANNEL_CODING_SET     0x108
  206. # define DP_SET_ANSI_8B10B                  (1 << 0)
  207.  
  208. #define DP_I2C_SPEED_CONTROL_STATUS         0x109   /* DPI */
  209. /* bitmask as for DP_I2C_SPEED_CAP */
  210.  
  211. #define DP_EDP_CONFIGURATION_SET            0x10a   /* XXX 1.2? */
  212.  
  213. #define DP_MSTM_CTRL                        0x111   /* 1.2 */
  214. # define DP_MST_EN                          (1 << 0)
  215. # define DP_UP_REQ_EN                       (1 << 1)
  216. # define DP_UPSTREAM_IS_SRC                 (1 << 2)
  217.  
  218. #define DP_PSR_EN_CFG                       0x170   /* XXX 1.2? */
  219. # define DP_PSR_ENABLE                      (1 << 0)
  220. # define DP_PSR_MAIN_LINK_ACTIVE            (1 << 1)
  221. # define DP_PSR_CRC_VERIFICATION            (1 << 2)
  222. # define DP_PSR_FRAME_CAPTURE               (1 << 3)
  223.  
  224. #define DP_SINK_COUNT                       0x200
  225. /* prior to 1.2 bit 7 was reserved mbz */
  226. # define DP_GET_SINK_COUNT(x)               ((((x) & 0x80) >> 1) | ((x) & 0x3f))
  227. # define DP_SINK_CP_READY                   (1 << 6)
  228.  
  229. #define DP_DEVICE_SERVICE_IRQ_VECTOR        0x201
  230. # define DP_REMOTE_CONTROL_COMMAND_PENDING  (1 << 0)
  231. # define DP_AUTOMATED_TEST_REQUEST          (1 << 1)
  232. # define DP_CP_IRQ                          (1 << 2)
  233. # define DP_SINK_SPECIFIC_IRQ               (1 << 6)
  234.  
  235. #define DP_LANE0_1_STATUS                   0x202
  236. #define DP_LANE2_3_STATUS                   0x203
  237. # define DP_LANE_CR_DONE                    (1 << 0)
  238. # define DP_LANE_CHANNEL_EQ_DONE            (1 << 1)
  239. # define DP_LANE_SYMBOL_LOCKED              (1 << 2)
  240.  
  241. #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |           \
  242.                             DP_LANE_CHANNEL_EQ_DONE |   \
  243.                             DP_LANE_SYMBOL_LOCKED)
  244.  
  245. #define DP_LANE_ALIGN_STATUS_UPDATED        0x204
  246.  
  247. #define DP_INTERLANE_ALIGN_DONE             (1 << 0)
  248. #define DP_DOWNSTREAM_PORT_STATUS_CHANGED   (1 << 6)
  249. #define DP_LINK_STATUS_UPDATED              (1 << 7)
  250.  
  251. #define DP_SINK_STATUS                      0x205
  252.  
  253. #define DP_RECEIVE_PORT_0_STATUS            (1 << 0)
  254. #define DP_RECEIVE_PORT_1_STATUS            (1 << 1)
  255.  
  256. #define DP_ADJUST_REQUEST_LANE0_1           0x206
  257. #define DP_ADJUST_REQUEST_LANE2_3           0x207
  258. # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK  0x03
  259. # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
  260. # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK   0x0c
  261. # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT  2
  262. # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK  0x30
  263. # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
  264. # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK   0xc0
  265. # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
  266.  
  267. #define DP_TEST_REQUEST                     0x218
  268. # define DP_TEST_LINK_TRAINING              (1 << 0)
  269. # define DP_TEST_LINK_PATTERN               (1 << 1)
  270. # define DP_TEST_LINK_EDID_READ             (1 << 2)
  271. # define DP_TEST_LINK_PHY_TEST_PATTERN      (1 << 3) /* DPCD >= 1.1 */
  272.  
  273. #define DP_TEST_LINK_RATE                   0x219
  274. # define DP_LINK_RATE_162                   (0x6)
  275. # define DP_LINK_RATE_27                    (0xa)
  276.  
  277. #define DP_TEST_LANE_COUNT                  0x220
  278.  
  279. #define DP_TEST_PATTERN                     0x221
  280.  
  281. #define DP_TEST_RESPONSE                    0x260
  282. # define DP_TEST_ACK                        (1 << 0)
  283. # define DP_TEST_NAK                        (1 << 1)
  284. # define DP_TEST_EDID_CHECKSUM_WRITE        (1 << 2)
  285.  
  286. #define DP_SOURCE_OUI                       0x300
  287. #define DP_SINK_OUI                         0x400
  288. #define DP_BRANCH_OUI                       0x500
  289.  
  290. #define DP_SET_POWER                        0x600
  291. # define DP_SET_POWER_D0                    0x1
  292. # define DP_SET_POWER_D3                    0x2
  293.  
  294. #define DP_PSR_ERROR_STATUS                 0x2006  /* XXX 1.2? */
  295. # define DP_PSR_LINK_CRC_ERROR              (1 << 0)
  296. # define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)
  297.  
  298. #define DP_PSR_ESI                          0x2007  /* XXX 1.2? */
  299. # define DP_PSR_CAPS_CHANGE                 (1 << 0)
  300.  
  301. #define DP_PSR_STATUS                       0x2008  /* XXX 1.2? */
  302. # define DP_PSR_SINK_INACTIVE               0
  303. # define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1
  304. # define DP_PSR_SINK_ACTIVE_RFB             2
  305. # define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3
  306. # define DP_PSR_SINK_ACTIVE_RESYNC          4
  307. # define DP_PSR_SINK_INTERNAL_ERROR         7
  308. # define DP_PSR_SINK_STATE_MASK             0x07
  309.  
  310. #define MODE_I2C_START  1
  311. #define MODE_I2C_WRITE  2
  312. #define MODE_I2C_READ   4
  313. #define MODE_I2C_STOP   8
  314.  
  315. /**
  316.  * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
  317.  *                               aux algorithm
  318.  * @running: set by the algo indicating whether an i2c is ongoing or whether
  319.  *           the i2c bus is quiescent
  320.  * @address: i2c target address for the currently ongoing transfer
  321.  * @aux_ch: driver callback to transfer a single byte of the i2c payload
  322.  */
  323. struct i2c_algo_dp_aux_data {
  324.         bool running;
  325.         u16 address;
  326.         int (*aux_ch) (struct i2c_adapter *adapter,
  327.                        int mode, uint8_t write_byte,
  328.                        uint8_t *read_byte);
  329. };
  330.  
  331. int
  332. i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
  333.  
  334.  
  335. #define DP_LINK_STATUS_SIZE        6
  336. bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
  337.                           int lane_count);
  338. bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
  339.                               int lane_count);
  340. u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
  341.                                      int lane);
  342. u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
  343.                                           int lane);
  344.  
  345. #define DP_RECEIVER_CAP_SIZE    0xf
  346. #define EDP_PSR_RECEIVER_CAP_SIZE       2
  347.  
  348. void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  349. void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
  350.  
  351. u8 drm_dp_link_rate_to_bw_code(int link_rate);
  352. int drm_dp_bw_code_to_link_rate(u8 link_bw);
  353.  
  354. struct edp_sdp_header {
  355.         u8 HB0; /* Secondary Data Packet ID */
  356.         u8 HB1; /* Secondary Data Packet Type */
  357.         u8 HB2; /* 7:5 reserved, 4:0 revision number */
  358.         u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */
  359. } __packed;
  360.  
  361. #define EDP_SDP_HEADER_REVISION_MASK            0x1F
  362. #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES      0x1F
  363.  
  364. struct edp_vsc_psr {
  365.         struct edp_sdp_header sdp_header;
  366.         u8 DB0; /* Stereo Interface */
  367.         u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
  368.         u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
  369.         u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
  370.         u8 DB4; /* CRC value bits 7:0 of the G or Y component */
  371.         u8 DB5; /* CRC value bits 15:8 of the G or Y component */
  372.         u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
  373.         u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
  374.         u8 DB8_31[24]; /* Reserved */
  375. } __packed;
  376.  
  377. #define EDP_VSC_PSR_STATE_ACTIVE        (1<<0)
  378. #define EDP_VSC_PSR_UPDATE_RFB          (1<<1)
  379. #define EDP_VSC_PSR_CRC_VALUES_VALID    (1<<2)
  380.  
  381. static inline int
  382. drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
  383. {
  384.         return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
  385. }
  386.  
  387. static inline u8
  388. drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
  389. {
  390.         return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
  391. }
  392.  
  393. #endif /* _DRM_DP_HELPER_H_ */
  394.