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  1.  
  2. typedef int Bool;
  3.  
  4. #define TRUE   1
  5. #define FALSE  0
  6.  
  7. #pragma pack(push, 1)
  8. typedef struct
  9. {
  10.      u16_t device;
  11.      u16_t ChipSet;
  12. }PciChipset_t;
  13. #pragma pack(pop)
  14.  
  15. #define VENDOR_ATI 0x1002
  16.  
  17.  
  18. #define PCI_CLASS_DISPLAY_VGA      0x0300
  19. /*
  20.  * Under PCI, each device has 256 bytes of configuration address space,
  21.  * of which the first 64 bytes are standardized as follows:
  22.  */
  23. #define PCI_VENDOR_ID                0x00    /* 16 bits */
  24. #define PCI_DEVICE_ID                0x02    /* 16 bits */
  25. #define PCI_COMMAND                  0x04    /* 16 bits */
  26. #define  PCI_COMMAND_IO              0x01    /* Enable response in I/O space */
  27. #define  PCI_COMMAND_MEMORY          0x02    /* Enable response in Memory space */
  28. #define  PCI_COMMAND_MASTER          0x04    /* Enable bus mastering */
  29. #define  PCI_COMMAND_SPECIAL         0x08    /* Enable response to special cycles */
  30. #define  PCI_COMMAND_INVALIDATE      0x10    /* Use memory write and invalidate */
  31. #define  PCI_COMMAND_VGA_PALETTE     0x20    /* Enable palette snooping */
  32. #define  PCI_COMMAND_PARITY          0x40    /* Enable parity checking */
  33. #define  PCI_COMMAND_WAIT            0x80    /* Enable address/data stepping */
  34. #define  PCI_COMMAND_SERR           0x100    /* Enable SERR */
  35. #define  PCI_COMMAND_FAST_BACK      0x200    /* Enable back-to-back writes */
  36. #define  PCI_COMMAND_INTX_DISABLE   0x400    /* INTx Emulation Disable */
  37.  
  38. #define PCI_STATUS                  0x06    /* 16 bits */
  39. #define  PCI_STATUS_CAP_LIST        0x10    /* Support Capability List */
  40. #define  PCI_STATUS_66MHZ           0x20    /* Support 66 Mhz PCI 2.1 bus */
  41. #define  PCI_STATUS_UDF             0x40    /* Support User Definable Features [obsolete] */
  42. #define  PCI_STATUS_FAST_BACK       0x80    /* Accept fast-back to back */
  43. #define  PCI_STATUS_PARITY          0x100   /* Detected parity error */
  44. #define  PCI_STATUS_DEVSEL_MASK     0x600   /* DEVSEL timing */
  45. #define  PCI_STATUS_DEVSEL_FAST         0x000
  46. #define  PCI_STATUS_DEVSEL_MEDIUM       0x200
  47. #define  PCI_STATUS_DEVSEL_SLOW         0x400
  48. #define  PCI_STATUS_SIG_TARGET_ABORT    0x800 /* Set on target abort */
  49. #define  PCI_STATUS_REC_TARGET_ABORT    0x1000 /* Master ack of " */
  50. #define  PCI_STATUS_REC_MASTER_ABORT    0x2000 /* Set on master abort */
  51. #define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000 /* Set when we drive SERR */
  52. #define  PCI_STATUS_DETECTED_PARITY     0x8000 /* Set on parity error */
  53.  
  54. #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8 revision */
  55. #define PCI_REVISION_ID         0x08    /* Revision ID */
  56. #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  57. #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  58.  
  59. #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  60. #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  61. #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  62. #define  PCI_HEADER_TYPE_NORMAL         0
  63. #define  PCI_HEADER_TYPE_BRIDGE         1
  64. #define  PCI_HEADER_TYPE_CARDBUS        2
  65.  
  66. #define PCI_BIST            0x0f    /* 8 bits */
  67. #define  PCI_BIST_CODE_MASK     0x0f    /* Return result */
  68. #define  PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
  69. #define  PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
  70.  
  71. #define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
  72. #define PCI_CB_CAPABILITY_LIST  0x14
  73. /* Capability lists */
  74.  
  75. #define PCI_CAP_LIST_ID     0       /* Capability ID */
  76. #define  PCI_CAP_ID_PM          0x01    /* Power Management */
  77. #define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
  78. #define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
  79. #define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
  80. #define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
  81. #define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
  82. #define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
  83. #define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
  84. #define  PCI_CAP_ID_VNDR        0x09    /* Vendor specific capability */
  85. #define  PCI_CAP_ID_SHPC        0x0C    /* PCI Standard Hot-Plug Controller */
  86. #define  PCI_CAP_ID_EXP         0x10    /* PCI Express */
  87. #define  PCI_CAP_ID_MSIX        0x11    /* MSI-X */
  88. #define PCI_CAP_LIST_NEXT   1       /* Next capability in the list */
  89. #define PCI_CAP_FLAGS       2       /* Capability defined flags (16 bits) */
  90. #define PCI_CAP_SIZEOF          4
  91.  
  92.  
  93. /* AGP registers */
  94.  
  95. #define PCI_AGP_VERSION          2   /* BCD version number */
  96. #define PCI_AGP_RFU              3   /* Rest of capability flags */
  97. #define PCI_AGP_STATUS           4   /* Status register */
  98. #define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
  99. #define  PCI_AGP_STATUS_SBA     0x0200   /* Sideband addressing supported */
  100. #define  PCI_AGP_STATUS_64BIT   0x0020   /* 64-bit addressing supported */
  101. #define  PCI_AGP_STATUS_FW      0x0010   /* FW transfers supported */
  102. #define  PCI_AGP_STATUS_RATE4   0x0004   /* 4x transfer rate supported */
  103. #define  PCI_AGP_STATUS_RATE2   0x0002   /* 2x transfer rate supported */
  104. #define  PCI_AGP_STATUS_RATE1   0x0001   /* 1x transfer rate supported */
  105. #define PCI_AGP_COMMAND              8   /* Control register */
  106. #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
  107. #define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
  108. #define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
  109. #define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
  110. #define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
  111. #define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
  112. #define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 2x rate */
  113. #define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 1x rate */
  114. #define PCI_AGP_SIZEOF          12
  115.  
  116.  
  117. #define PCI_MAP_REG_START             0x10
  118. #define PCI_MAP_REG_END               0x28
  119. #define PCI_MAP_ROM_REG               0x30
  120.  
  121. #define PCI_MAP_MEMORY                0x00000000
  122. #define PCI_MAP_IO                    0x00000001
  123.  
  124. #define PCI_MAP_MEMORY_TYPE           0x00000007
  125. #define PCI_MAP_IO_TYPE               0x00000003
  126.  
  127. #define PCI_MAP_MEMORY_TYPE_32BIT     0x00000000
  128. #define PCI_MAP_MEMORY_TYPE_32BIT_1M    0x00000002
  129. #define PCI_MAP_MEMORY_TYPE_64BIT     0x00000004
  130. #define PCI_MAP_MEMORY_TYPE_MASK      0x00000006
  131. #define PCI_MAP_MEMORY_CACHABLE       0x00000008
  132. #define PCI_MAP_MEMORY_ATTR_MASK      0x0000000e
  133. #define PCI_MAP_MEMORY_ADDRESS_MASK   0xfffffff0
  134.  
  135. #define PCI_MAP_IO_ATTR_MASK          0x00000003
  136.  
  137. #define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
  138. #define PCI_MAP_IS_MEM(b)       (!PCI_MAP_IS_IO(b))
  139.  
  140. #define PCI_MAP_IS64BITMEM(b)   \
  141.         (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
  142.  
  143. #define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
  144. #define PCIGETMEMORY64HIGH(b)   (*((CARD32*)&b + 1))
  145. #define PCIGETMEMORY64(b)       \
  146.         (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
  147.  
  148. #define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc
  149.  
  150. #define PCIGETIO(b)             ((b) & PCI_MAP_IO_ADDRESS_MASK)
  151.  
  152. #define PCI_MAP_ROM_DECODE_ENABLE     0x00000001
  153. #define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800
  154.  
  155. #define PCIGETROM(b)            ((b) & PCI_MAP_ROM_ADDRESS_MASK)
  156.  
  157.  
  158. #ifndef PCI_DOM_MASK
  159. # define PCI_DOM_MASK 0x0ffu
  160. #endif
  161. #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
  162.  
  163. #define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
  164.                               (((d) & 0x00001fu) << 11) | \
  165.                               (((f) & 0x000007u) << 8))
  166.  
  167. #define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
  168. #define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
  169. #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
  170. #define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
  171.  
  172.  
  173. typedef unsigned int PCITAG;
  174.  
  175. extern inline PCITAG
  176. pciTag(int busnum, int devnum, int funcnum)
  177. {
  178.         return(PCI_MAKE_TAG(busnum,devnum,funcnum));
  179. }
  180.  
  181. const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list);
  182. u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);
  183.  
  184. #define PCI_ANY_ID (~0)
  185.  
  186. #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1)
  187.