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  1.  
  2.  
  3. //
  4. //  Device and Vendor IDs - Needed like this for OSS only
  5. //
  6. #define CYRIX_VENDOR_ID     0x1078
  7. #define NATIONAL_VENDOR_ID  0x100B
  8.  
  9. //
  10. //       Audio  Device IDs
  11. //
  12. #define CX5530_DEV_ID    0x0103
  13. #define SC1200_DEV_ID    0x0503
  14. #define CS5535_DEV_ID    0x002E
  15.  
  16. //
  17. // Function 3 of 5530 PCI dev is Audio (ISA idx).
  18. //
  19. #define  PCI_FUNC3_AUDIO     0x300
  20. #define  PCI_AUDIO_CMD_REG   0x04
  21.  
  22. typedef unsigned char AUDIO_STATE;
  23.  
  24. #define AUDIO_STATE_IGNORE          0
  25. #define AUDIO_STATE_IN_RECORDING    0x01
  26. #define AUDIO_STATE_IN_OVERFLOW     0x02
  27. #define AUDIO_STATE_IN_STOPPED      0x03
  28. #define AUDIO_STATE_IN_MASK         0x0F
  29. #define AUDIO_STATE_OUT_PLAYING     0x10
  30. #define AUDIO_STATE_OUT_UNDERFLOW   0x20
  31. #define AUDIO_STATE_OUT_STOPPED     0x30
  32. #define AUDIO_STATE_OUT_MASK        0xF0
  33.  
  34. #define RECORD_RUNNING          0x01
  35. #define RECORD_OVERFLOW         0x02
  36. #define RECORD_STOPPED          0x03
  37.  
  38. #define PLAYBACK_RUNNING    0x10
  39. #define PLAYBACK_UNDERFLOW  0x20
  40. #define PLAYBACK_STOPPED    0x30
  41.  
  42. //
  43. // The CODEC commands are actually 16-bit words, into which is inserted
  44. // the codec "target" register, identified by a byte. The 5530 Codec
  45. // controller writes a command unsigned short of 32-bits, that includes the codec
  46. // command unsigned short.
  47. //
  48. #define CODEC_COMMAND_MASK       0xFF00FFFF
  49.  
  50. //
  51. //  The Interaction with the CODEC is a bit cumbersome
  52. //  because of the serial interface.
  53. //
  54. #define CODEC_STATUS_REG    0x08        // In Audio mem-map.
  55. #define CODEC_CMD_REG       0x0c        // In audio mem-map.
  56. #define CODEC_CMD_VALID     0x00010000
  57. #define CODEC_STATUS_VALID  0x00020000
  58. #define CODEC_STATUS_NEW    0x00010000
  59. #define BIT_CODEC_READY     0x00800000
  60.  
  61. //
  62. //   Registers for the 5535
  63. //
  64. #define CODEC_STATUS_REG_5535           0x08
  65. #define CODEC_CONTROL_REG_5535      0x0c
  66.  
  67. //
  68. //   5535 Bits
  69. //
  70. #define BIT_5535_CODEC_COMMAND_NEW   0x00010000
  71. #define BIT_5535_CODEC_STATUS_NEW        0x00020000
  72. #define BIT_5535_ACLINK_SHUTDOWN         0x00040000
  73. #define BIT_5535_ACLINK_WARM_RESET       0x00020000
  74. #define BIT_5535_CODEC_READY_PRIM        0x00800000
  75.  
  76. //
  77. // Codec register indexes. Note these are all shifted left by 16 bits.
  78. //
  79. #define RESET                0x00
  80. #define MASTER_VOLUME        0x02
  81. #define LINE_LEV_OUT_VOL     0x04
  82. #define MASTER_VOLUME_MONO   0x06
  83. #define MASTER_TONE_RL       0x08
  84. #define PC_BEEP_VOLUME       0x0a
  85. #define PHONE_VOLUME         0x0c
  86. #define MIC_VOLUME           0x0e
  87. #define LINE_IN_VOLUME       0x10
  88. #define CD_VOLUME            0x12
  89. #define VIDEO_VOLUME         0x14
  90. #define TV_VOLUME            0x16
  91. #define PCM_OUT_VOL          0x18
  92. #define RECORD_SELECT        0x1a
  93. #define RECORD_GAIN          0x1c
  94. #define RECORD_MIC_GAIN      0x1e
  95. #define GENERAL_PURPOSE      0x20
  96. #define CONTROL_3D           0x22
  97. #define MODEM_RATE           0x24
  98. #define POWERDOWN_CTRL_STAT  0x26
  99. #define EXTENDED_AUDIO_ID        0x28
  100. #define EXT_AUDIO_CTRL_STAT  0x2A
  101. #define PCM_FRONT_DAC_RATE   0x2C
  102. #define PCM_LR_ADC_RATE      0x32
  103. #define VENDOR_ID1           0x7c
  104. #define VENDOR_ID2           0x7e
  105.  
  106. #define MUTE_MASK                        0x8000
  107. #define HEADHONE_AVAIL       0x0010
  108. #define LINE_LEV_RESET_VOL       0x0000 // the reset without the mask
  109.  
  110. #ifdef AC97_2DOT1_6BIT_COMPLIANT
  111. #       define MASTER_ATTEN_CTL_BITS             6
  112. #else
  113. #       define MASTER_ATTEN_CTL_BITS             5
  114. #endif
  115.  
  116. #define MASTER_VOLUME_MAX    ( ( 1 << MASTER_ATTEN_CTL_BITS ) - 1 )
  117. #define LINE_LEV_OUT_MAX     ( ( 1 << MASTER_ATTEN_CTL_BITS ) - 1 )
  118.  
  119. //
  120. // AD1819A registers
  121. //
  122. #define AD1819A_SER_CONF                        0x74
  123. #define AD1819A_SER_CONF_DRQEN          0x08
  124. #define AD1819A_MISC                            0x76
  125. #define AD1819A_PCM_SR0                         0x78
  126. #define AD1819A_PCM_SR1                         0x7A
  127. #define AD1819A_VENDORID1                       0x7C
  128. #define AD1819A_VENDORID2                       0x7E
  129.  
  130. //
  131. //      Power Management bits
  132. //
  133. #define GEODEAUDIO_PWR_PR0      0x0100      // PCM in ADC's & input Mux Powerdown
  134. #define GEODEAUDIO_PWR_PR1    0x0200      // PCM out DACs Powerdown
  135. #define GEODEAUDIO_PWR_PR2    0x0400      // Analog Mixer powerdown (Vref still on)
  136. #define GEODEAUDIO_PWR_PR3    0x0800      // Analog Mxer powerdown (Vref off)
  137. #define GEODEAUDIO_PWR_PR4    0x1000      // Digital interface (AC-link) powerdown (external clk off)
  138. #define GEODEAUDIO_PWR_PR5    0x2000      // Internal Clk disable
  139. #define GEODEAUDIO_PWR_PR6    0x4000      // HP amp powerdown
  140. #define GEODEAUDIO_PWR_PR7    0x8000      // External Amplifier Power Down
  141.  
  142. #define GEODEAUDIO_PWR_D0              0x0000
  143. #define GEODEAUDIO_PWR_D1              GEODEAUDIO_PWR_EXTOFF
  144. #define GEODEAUDIO_PWR_D2              GEODEAUDIO_PWR_PR0|GEODEAUDIO_PWR_PR1|GEODEAUDIO_PWR_PR2|GEODEAUDIO_PWR_PR6|GEODEAUDIO_PWR_PR7
  145. #define GEODEAUDIO_PWR_D3              GEODEAUDIO_PWR_PR0|GEODEAUDIO_PWR_PR1|GEODEAUDIO_PWR_PR2|GEODEAUDIO_PWR_PR6|GEODEAUDIO_PWR_PR7
  146. #define GEODEAUDIO_PWR_D4              GEODEAUDIO_PWR_PR0|GEODEAUDIO_PWR_PR1|GEODEAUDIO_PWR_PR2|GEODEAUDIO_PWR_PR3|GEODEAUDIO_PWR_PR4|GEODEAUDIO_PWR_PR5|GEODEAUDIO_PWR_PR6|GEODEAUDIO_PWR_PR7
  147. #define GEODEAUDIO_PWR_ANLOFF          GEODEAUDIO_PWR_PR2|GEODEAUDIO_PWR_PR3  // Analog section OFF
  148. #define GEODEAUDIO_PWR_EXTOFF          GEODEAUDIO_PWR_PR6|GEODEAUDIO_PWR_PR7  // HP amp and External Amplifier OFF
  149. #define GEODEAUDIO_PWR_D1_HAWK         GEODEAUDIO_PWR_PR0|GEODEAUDIO_PWR_PR1|GEODEAUDIO_PWR_PR2|GEODEAUDIO_PWR_PR3|GEODEAUDIO_PWR_PR4
  150. #define GEODEAUDIO_PWR_DIGOFF                    GEODEAUDIO_PWR_PR0|GEODEAUDIO_PWR_PR1  // Digital section OFF
  151.  
  152. #define GEODEAUDIO_PWRUP_STEP1           0x0F00 // Clear EAPD,PR6 and AC-link to power up external and HP amp and Digital interface
  153. #define GEODEAUDIO_PWRUP_STEP2           0x0700 // Clear PR3 to power up Analog (Vref off)
  154. #define GEODEAUDIO_PWRUP_STEP3           0x0300 // Clear PR2 to power up Analog (Vref on)
  155. #define GEODEAUDIO_PWRUP_STEP4           0x0100 // Clear PR1 to power up DAC
  156. #define GEODEAUDIO_PWRUP_STEP5           0x0000 // Clear PR0 to power up ADC
  157.  
  158. #define GEODEAUDIO_CODEC_POWER_ADC       0x0001
  159. #define GEODEAUDIO_CODEC_POWER_DAC       0x0002
  160. #define GEODEAUDIO_CODEC_POWER_ANL       0x0004
  161. #define GEODEAUDIO_CODEC_POWER_REF   0x0008
  162.  
  163. //
  164. // Device Power States
  165. //
  166. typedef enum _GEODEAUDIO_POWER_STATE
  167. {
  168.     GEODEAUDIO_D0 = 0, // Full On: full power,  full functionality
  169.     GEODEAUDIO_D1,     // Low Power On: fully functional at low power/performance
  170.     GEODEAUDIO_D2,     // Standby: partially powered with automatic wake
  171.     GEODEAUDIO_D3,     // Sleep: partially powered with device initiated wake
  172.     GEODEAUDIO_D4,     // Off: unpowered
  173. } GEODEAUDIO_POWER_STATE, *PGEODEAUDIO_POWER_STATE;
  174.  
  175. // PRD table flags
  176. #define PRD_JMP_BIT                     0x20000000
  177. #define PRD_EOP_BIT                     0x40000000
  178. #define PRD_EOT_BIT                     0x80000000
  179.  
  180. typedef struct tagPRDEntry
  181. {
  182.     unsigned long  ulPhysAddr;
  183.     unsigned long  SizeFlags;
  184. } PRD_ENTRY, *PPRD_ENTRY;
  185.  
  186.  
  187. //
  188. //   Command register bits
  189. //
  190. #define  PCI_READS                      0x00
  191. #define  PCI_WRITES                     0x08
  192.  
  193. #define  ENABLE_BUSMASTER       0x01
  194. #define  PAUSE_BUSMASTER        0x03
  195. #define  STOP_BUSMASTER         0x00
  196.  
  197. #define CHANNEL0_PLAYBACK   0
  198. #define CHANNEL1_RECORD         1
  199. #define MAX_CHANNELS            2
  200.  
  201.