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  1. ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
  2. ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny15.xml ************
  3. ;*************************************************************************
  4. ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
  5. ;*
  6. ;* Number            : AVR000
  7. ;* File Name         : "tn15def.inc"
  8. ;* Title             : Register/Bit Definitions for the ATtiny15
  9. ;* Date              : 2005-01-11
  10. ;* Version           : 2.14
  11. ;* Support E-mail    : avr@atmel.com
  12. ;* Target MCU        : ATtiny15
  13. ;*
  14. ;* DESCRIPTION
  15. ;* When including this file in the assembly program file, all I/O register
  16. ;* names and I/O register bit names appearing in the data book can be used.
  17. ;* In addition, the six registers forming the three data pointers X, Y and
  18. ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
  19. ;* SRAM is also defined
  20. ;*
  21. ;* The Register names are represented by their hexadecimal address.
  22. ;*
  23. ;* The Register Bit names are represented by their bit number (0-7).
  24. ;*
  25. ;* Please observe the difference in using the bit names with instructions
  26. ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
  27. ;* (skip if bit in register set/cleared). The following example illustrates
  28. ;* this:
  29. ;*
  30. ;* in    r16,PORTB             ;read PORTB latch
  31. ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
  32. ;* out   PORTB,r16             ;output to PORTB
  33. ;*
  34. ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
  35. ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
  36. ;* rjmp  TOV0_is_set           ;jump if set
  37. ;* ...                         ;otherwise do something else
  38. ;*************************************************************************
  39.  
  40. #ifndef _TN15DEF_INC_
  41. #define _TN15DEF_INC_
  42.  
  43.  
  44. #pragma partinc 0
  45.  
  46. ; ***** SPECIFY DEVICE ***************************************************
  47. .device ATtiny15
  48. #pragma AVRPART ADMIN PART_NAME ATtiny15
  49. .equ    SIGNATURE_000   = 0x1e
  50. .equ    SIGNATURE_001   = 0x90
  51. .equ    SIGNATURE_002   = 0x06
  52.  
  53. #pragma AVRPART CORE CORE_VERSION V0E
  54.  
  55.  
  56. ; ***** I/O REGISTER DEFINITIONS *****************************************
  57. ; NOTE:
  58. ; Definitions marked "MEMORY MAPPED"are extended I/O ports
  59. ; and cannot be used with IN/OUT instructions
  60. .equ    SREG    = 0x3f
  61. .equ    GIMSK   = 0x3b
  62. .equ    GIFR    = 0x3a
  63. .equ    TIMSK   = 0x39
  64. .equ    TIFR    = 0x38
  65. .equ    MCUCR   = 0x35
  66. .equ    MCUSR   = 0x34
  67. .equ    TCCR0   = 0x33
  68. .equ    TCNT0   = 0x32
  69. .equ    OSCCAL  = 0x31
  70. .equ    TCCR1   = 0x30
  71. .equ    TCNT1   = 0x2f
  72. .equ    OCR1A   = 0x2e
  73. .equ    OCR1B   = 0x2d
  74. .equ    SFIOR   = 0x2c
  75. .equ    WDTCR   = 0x21
  76. .equ    EEAR    = 0x1e
  77. .equ    EEDR    = 0x1d
  78. .equ    EECR    = 0x1c
  79. .equ    PORTB   = 0x18
  80. .equ    DDRB    = 0x17
  81. .equ    PINB    = 0x16
  82. .equ    ACSR    = 0x08
  83. .equ    ADMUX   = 0x07
  84. .equ    ADCSR   = 0x06
  85. .equ    ADCH    = 0x05
  86. .equ    ADCL    = 0x04
  87.  
  88.  
  89. ; ***** BIT DEFINITIONS **************************************************
  90.  
  91. ; ***** AD_CONVERTER *****************
  92. ; ADMUX - The ADC multiplexer Selection Register
  93. .equ    MUX0    = 0     ; Analog Channel and Gain Selection Bits
  94. .equ    MUX1    = 1     ; Analog Channel and Gain Selection Bits
  95. .equ    MUX2    = 2     ; Analog Channel and Gain Selection Bits
  96. .equ    ADLAR   = 5     ; Left Adjust Result
  97. .equ    REFS0   = 6     ; Reference Selection Bit 0
  98. .equ    REFS1   = 7     ; Reference Selection Bit 1
  99.  
  100. ; ADCSR - The ADC Control and Status register
  101. .equ    ADPS0   = 0     ; ADC  Prescaler Select Bits
  102. .equ    ADPS1   = 1     ; ADC  Prescaler Select Bits
  103. .equ    ADPS2   = 2     ; ADC  Prescaler Select Bits
  104. .equ    ADIE    = 3     ; ADC Interrupt Enable
  105. .equ    ADIF    = 4     ; ADC Interrupt Flag
  106. .equ    ADFR    = 5     ; ADC  Free Running Select
  107. .equ    ADSC    = 6     ; ADC Start Conversion
  108. .equ    ADEN    = 7     ; ADC Enable
  109.  
  110. ; ADCH - ADC Data Register High Byte
  111. .equ    ADCH0   = 0     ; ADC Data Register High Byte Bit 0
  112. .equ    ADCH1   = 1     ; ADC Data Register High Byte Bit 1
  113. .equ    ADCH2   = 2     ; ADC Data Register High Byte Bit 2
  114. .equ    ADCH3   = 3     ; ADC Data Register High Byte Bit 3
  115. .equ    ADCH4   = 4     ; ADC Data Register High Byte Bit 4
  116. .equ    ADCH5   = 5     ; ADC Data Register High Byte Bit 5
  117. .equ    ADCH6   = 6     ; ADC Data Register High Byte Bit 6
  118. .equ    ADCH7   = 7     ; ADC Data Register High Byte Bit 7
  119.  
  120. ; ADCL - ADC Data Register Low Byte
  121. .equ    ADCL0   = 0     ; ADC Data Register Low Byte Bit 0
  122. .equ    ADCL1   = 1     ; ADC Data Register Low Byte Bit 1
  123. .equ    ADCL2   = 2     ; ADC Data Register Low Byte Bit 2
  124. .equ    ADCL3   = 3     ; ADC Data Register Low Byte Bit 3
  125. .equ    ADCL4   = 4     ; ADC Data Register Low Byte Bit 4
  126. .equ    ADCL5   = 5     ; ADC Data Register Low Byte Bit 5
  127. .equ    ADCL6   = 6     ; ADC Data Register Low Byte Bit 6
  128. .equ    ADCL7   = 7     ; ADC Data Register Low Byte Bit 7
  129.  
  130.  
  131. ; ***** ANALOG_COMPARATOR ************
  132. ; ACSR - Analog Comparator Control And Status Register
  133. .equ    ACIS0   = 0     ; Analog Comparator Interrupt Mode Select bit 0
  134. .equ    ACIS1   = 1     ; Analog Comparator Interrupt Mode Select bit 1
  135. .equ    ACIE    = 3     ; Analog Comparator Interrupt Enable
  136. .equ    ACI     = 4     ; Analog Comparator Interrupt Flag
  137. .equ    ACO     = 5     ; Analog Compare Output
  138. .equ    ACBG    = 6     ; Analog Comparator Bandgap Select
  139. .equ    AINBG6  = ACBG  ; For compatibility
  140. .equ    ACD     = 7     ; Analog Comparator Disable
  141.  
  142.  
  143. ; ***** EEPROM ***********************
  144. ; EEAR - EEPROM Read/Write Access
  145. .equ    EEAR0   = 0     ; EEPROM Read/Write Access bit 0
  146. .equ    EEAR1   = 1     ; EEPROM Read/Write Access bit 1
  147. .equ    EEAR2   = 2     ; EEPROM Read/Write Access bit 2
  148. .equ    EEAR3   = 3     ; EEPROM Read/Write Access bit 3
  149. .equ    EEAR4   = 4     ; EEPROM Read/Write Access bit 4
  150. .equ    EEAR5   = 5     ; EEPROM Read/Write Access bit 5
  151.  
  152. ; EEDR - EEPROM Data Register
  153. .equ    EEDR0   = 0     ; EEPROM Data Register bit 0
  154. .equ    EEDR1   = 1     ; EEPROM Data Register bit 1
  155. .equ    EEDR2   = 2     ; EEPROM Data Register bit 2
  156. .equ    EEDR3   = 3     ; EEPROM Data Register bit 3
  157. .equ    EEDR4   = 4     ; EEPROM Data Register bit 4
  158. .equ    EEDR5   = 5     ; EEPROM Data Register bit 5
  159. .equ    EEDR6   = 6     ; EEPROM Data Register bit 6
  160. .equ    EEDR7   = 7     ; EEPROM Data Register bit 7
  161.  
  162. ; EECR - EEPROM Control Register
  163. .equ    EERE    = 0     ; EEPROM Read Enable
  164. .equ    EEWE    = 1     ; EEPROM Write Enable
  165. .equ    EEMWE   = 2     ; EEPROM Master Write Enable
  166. .equ    EERIE   = 3     ; EEProm Ready Interrupt Enable
  167.  
  168.  
  169. ; ***** PORTB ************************
  170. ; PORTB - Data Register, Port B
  171. .equ    PORTB0  = 0     ;
  172. .equ    PB0     = 0     ; For compatibility
  173. .equ    PORTB1  = 1     ;
  174. .equ    PB1     = 1     ; For compatibility
  175. .equ    PORTB2  = 2     ;
  176. .equ    PB2     = 2     ; For compatibility
  177. .equ    PORTB3  = 3     ;
  178. .equ    PB3     = 3     ; For compatibility
  179. .equ    PORTB4  = 4     ;
  180. .equ    PB4     = 4     ; For compatibility
  181.  
  182. ; DDRB - Data Direction Register, Port B
  183. .equ    DDB0    = 0     ;
  184. .equ    DDB1    = 1     ;
  185. .equ    DDB2    = 2     ;
  186. .equ    DDB3    = 3     ;
  187. .equ    DDB4    = 4     ;
  188. .equ    DDB5    = 5     ;
  189.  
  190. ; PINB - Input Pins, Port B
  191. .equ    PINB0   = 0     ;
  192. .equ    PINB1   = 1     ;
  193. .equ    PINB2   = 2     ;
  194. .equ    PINB3   = 3     ;
  195. .equ    PINB4   = 4     ;
  196. .equ    PINB5   = 5     ;
  197.  
  198.  
  199. ; ***** TIMER_COUNTER_0 **************
  200. ; TIMSK - Timer/Counter Interrupt Mask Register
  201. .equ    TOIE0   = 1     ; Timer/Counter0 Overflow Interrupt Enable
  202.  
  203. ; TIFR - Timer/Counter Interrupt Flag register
  204. .equ    TOV0    = 1     ; Timer/Counter0 Overflow Flag
  205.  
  206. ; TCCR0 - Timer/Counter0 Control Register
  207. .equ    CS00    = 0     ; Clock Select0 bit 0
  208. .equ    CS01    = 1     ; Clock Select0 bit 1
  209. .equ    CS02    = 2     ; Clock Select0 bit 2
  210.  
  211. ; TCNT0 - Timer Counter 0
  212. .equ    TCNT00  = 0     ; Timer Counter 0 bit 0
  213. .equ    TCNT01  = 1     ; Timer Counter 0 bit 1
  214. .equ    TCNT02  = 2     ; Timer Counter 0 bit 2
  215. .equ    TCNT03  = 3     ; Timer Counter 0 bit 3
  216. .equ    TCNT04  = 4     ; Timer Counter 0 bit 4
  217. .equ    TCNT05  = 5     ; Timer Counter 0 bit 5
  218. .equ    TCNT06  = 6     ; Timer Counter 0 bit 6
  219. .equ    TCNT07  = 7     ; Timer Counter 0 bit 7
  220.  
  221.  
  222. ; ***** WATCHDOG *********************
  223. ; WDTCR - Watchdog Timer Control Register
  224. .equ    WDP0    = 0     ; Watch Dog Timer Prescaler bit 0
  225. .equ    WDP1    = 1     ; Watch Dog Timer Prescaler bit 1
  226. .equ    WDP2    = 2     ; Watch Dog Timer Prescaler bit 2
  227. .equ    WDE     = 3     ; Watch Dog Enable
  228. .equ    WDTOE   = 4     ; RW
  229. .equ    WDDE    = WDTOE ; For compatibility
  230.  
  231.  
  232. ; ***** CPU **************************
  233. ; SREG - Status Register
  234. .equ    SREG_C  = 0     ; Carry Flag
  235. .equ    SREG_Z  = 1     ; Zero Flag
  236. .equ    SREG_N  = 2     ; Negative Flag
  237. .equ    SREG_V  = 3     ; Two's Complement Overflow Flag
  238. .equ    SREG_S  = 4     ; Sign Bit
  239. .equ    SREG_H  = 5     ; Half Carry Flag
  240. .equ    SREG_T  = 6     ; Bit Copy Storage
  241. .equ    SREG_I  = 7     ; Global Interrupt Enable
  242.  
  243. ; MCUCR - MCU Control Register
  244. .equ    ISC00   = 0     ; Interrupt Sense Control 0 bit 0
  245. .equ    ISC01   = 1     ; Interrupt Sense Control 0 bit 1
  246. .equ    SM0     = 3     ; Sleep Mode Select Bit 0
  247. .equ    SM1     = 4     ; Sleep Mode Select Bit 1
  248. .equ    SE      = 5     ; Sleep Enable
  249. .equ    PUD     = 6     ; Pull-up Disable
  250.  
  251. ; MCUSR - MCU Status register
  252. .equ    PORF    = 0     ; Power-On Reset Flag
  253. .equ    EXTRF   = 1     ; External Reset Flag
  254. .equ    BORF    = 2     ; Brown-out Reset Flag
  255. .equ    WDRF    = 3     ; Watchdog Reset Flag
  256.  
  257. ; OSCCAL - Status Register
  258. .equ    CAL0    = 0     ; Oscillator Calibration Value Bit 0
  259. .equ    CAL1    = 1     ; Oscillator Calibration Value Bit 1
  260. .equ    CAL2    = 2     ; Oscillator Calibration Value Bit 2
  261. .equ    CAL3    = 3     ; Oscillator Calibration Value Bit 3
  262. .equ    CAL4    = 4
  263. .equ    CAL5    = 5     ; Oscillator Calibration Value Bit 5
  264. .equ    CAL6    = 6     ; Oscillator Calibration Value Bit 6
  265. .equ    CAL7    = 7     ; Oscillator Calibration Value Bit 7
  266.  
  267.  
  268. ; ***** EXTERNAL_INTERRUPT ***********
  269. ; GIMSK - General Interrupt Mask Register
  270. .equ    PCIE    = 5     ; Pin Change Interrupt Enable
  271. .equ    INT0    = 6     ; External Interrupt Request 0 Enable
  272.  
  273. ; GIFR - General Interrupt Flag register
  274. .equ    PCIF    = 5     ; Pin Change Interrupt Flag
  275. .equ    INTF0   = 6     ; External Interrupt Flag 0
  276.  
  277.  
  278. ; ***** TIMER_COUNTER_1 **************
  279. ; TCCR1 - Timer/Counter Control Register
  280. .equ    CS10    = 0     ; Clock Select Bits
  281. .equ    CS11    = 1     ; Clock Select Bits
  282. .equ    CS12    = 2     ; Clock Select Bits
  283. .equ    CS13    = 3     ; Clock Select Bits
  284. .equ    COM1A0  = 4     ; Compare Output Mode, Bit 1
  285. .equ    COM1A1  = 5     ; Compare Output Mode, Bit 0
  286. .equ    PWM1    = 6     ; Pulse Width Modulator Enable
  287. .equ    CTC1    = 7     ; Clear Timer/Counter on Compare Match
  288.  
  289. ; TCNT1 - Timer/Counter Register
  290. .equ    TCNT1_0 = 0     ; Timer/Counter Register Bit 0
  291. .equ    TCNT1_1 = 1     ; Timer/Counter Register Bit 1
  292. .equ    TCNT1_2 = 2     ; Timer/Counter Register Bit 2
  293. .equ    TCNT1_3 = 3     ; Timer/Counter Register Bit 3
  294. .equ    TCNT1_4 = 4     ; Timer/Counter Register Bit 4
  295. .equ    TCNT1_5 = 5     ; Timer/Counter Register Bit 5
  296. .equ    TCNT1_6 = 6     ; Timer/Counter Register Bit 6
  297. .equ    TCNT1_7 = 7     ; Timer/Counter Register Bit 7
  298.  
  299. ; OCR1A - Output Compare Register
  300. .equ    OCR1A0  = 0     ; Output Compare Register A Bit 0
  301. .equ    OCR1A1  = 1     ; Output Compare Register A Bit 1
  302. .equ    OCR1A2  = 2     ; Output Compare Register A Bit 2
  303. .equ    OCR1A3  = 3     ; Output Compare Register A Bit 3
  304. .equ    OCR1A4  = 4     ; Output Compare Register A Bit 4
  305. .equ    OCR1A5  = 5     ; Output Compare Register A Bit 5
  306. .equ    OCR1A6  = 6     ; Output Compare Register A Bit 6
  307. .equ    OCR1A7  = 7     ; Output Compare Register A Bit 7
  308.  
  309. ; OCR1B - Output Compare Register
  310. .equ    OCR1B0  = 0     ; Output Compare Register B Bit 0
  311. .equ    OCR1B1  = 1     ; Output Compare Register B Bit 1
  312. .equ    OCR1B2  = 2     ; Output Compare Register B Bit 2
  313. .equ    OCR1B3  = 3     ; Output Compare Register B Bit 3
  314. .equ    OCR1B4  = 4     ; Output Compare Register B Bit 4
  315. .equ    OCR1B5  = 5     ; Output Compare Register B Bit 5
  316. .equ    OCR1B6  = 6     ; Output Compare Register B Bit 6
  317. .equ    OCR1B7  = 7     ; Output Compare Register B Bit 7
  318.  
  319. ; TIMSK - Timer/Counter Interrupt Mask Register
  320. .equ    TOIE1   = 2     ; Timer/Counter1 Overflow Interrupt Enable
  321. .equ    OCIE1A  = 6     ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
  322.  
  323. ; TIFR - Timer/Counter Interrupt Flag Register
  324. .equ    TOV1    = 2     ; Timer/Counter1 Overflow Flag
  325. .equ    OCF1A   = 6     ; Timer/Counter1 Output Compare Flag 1A
  326.  
  327. ; SFIOR - Special Function IO Register
  328. .equ    PSR0    = 0     ; Prescaler Reset Timer/Counter0
  329. .equ    PSR1    = 1     ; Prescaler Reset Timer/Counter1
  330. .equ    FOC1A   = 2     ; Force Output Compare 1A
  331.  
  332.  
  333.  
  334. ; ***** LOCKSBITS ********************************************************
  335. .equ    LB1     = 0     ; Lockbit
  336. .equ    LB2     = 1     ; Lockbit
  337.  
  338.  
  339. ; ***** FUSES ************************************************************
  340. ; LOW fuse bits
  341.  
  342.  
  343.  
  344. ; ***** CPU REGISTER DEFINITIONS *****************************************
  345. .def    XH      = r27
  346. .def    XL      = r26
  347. .def    YH      = r29
  348. .def    YL      = r28
  349. .def    ZH      = r31
  350. .def    ZL      = r30
  351.  
  352.  
  353.  
  354. ; ***** DATA MEMORY DECLARATIONS *****************************************
  355. .equ    FLASHEND        = 0x01ff        ; Note: Word address
  356. .equ    IOEND   = 0x003f
  357. .equ    SRAM_SIZE       = 0
  358. .equ    RAMEND  = 0x0000
  359. .equ    XRAMEND = 0x0000
  360. .equ    E2END   = 0x003f
  361. .equ    EEPROMEND       = 0x003f
  362. .equ    EEADRBITS       = 6
  363. #pragma AVRPART MEMORY PROG_FLASH 1024
  364. #pragma AVRPART MEMORY EEPROM 64
  365. #pragma AVRPART MEMORY INT_SRAM SIZE 0
  366. #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0
  367.  
  368.  
  369.  
  370.  
  371.  
  372. ; ***** INTERRUPT VECTORS ************************************************
  373. .equ    INT0addr        = 0x0001        ; External Interrupt 0
  374. .equ    PCI0addr        = 0x0002        ; External Interrupt Request 0
  375. .equ    OC1addr = 0x0003        ; Timer/Counter1 Compare Match
  376. .equ    OVF1addr        = 0x0004        ; Timer/Counter1 Overflow
  377. .equ    OVF0addr        = 0x0005        ; Timer/Counter0 Overflow
  378. .equ    ERDYaddr        = 0x0006        ; EEPROM Ready
  379. .equ    ACIaddr = 0x0007        ; Analog Comparator
  380. .equ    ADCCaddr        = 0x0008        ; ADC Conversion Ready
  381.  
  382. .equ    INT_VECTORS_SIZE        = 9     ; size in words
  383.  
  384. #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
  385.  
  386. #endif  /* _TN15DEF_INC_ */
  387.  
  388. ; ***** END OF FILE ******************************************************
  389.