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  1. ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
  2. ;***** Created: 2005-01-11 10:31 ******* Source: ATtiny11.xml ************
  3. ;*************************************************************************
  4. ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
  5. ;*
  6. ;* Number            : AVR000
  7. ;* File Name         : "tn11def.inc"
  8. ;* Title             : Register/Bit Definitions for the ATtiny11
  9. ;* Date              : 2005-01-11
  10. ;* Version           : 2.14
  11. ;* Support E-mail    : avr@atmel.com
  12. ;* Target MCU        : ATtiny11
  13. ;*
  14. ;* DESCRIPTION
  15. ;* When including this file in the assembly program file, all I/O register
  16. ;* names and I/O register bit names appearing in the data book can be used.
  17. ;* In addition, the six registers forming the three data pointers X, Y and
  18. ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
  19. ;* SRAM is also defined
  20. ;*
  21. ;* The Register names are represented by their hexadecimal address.
  22. ;*
  23. ;* The Register Bit names are represented by their bit number (0-7).
  24. ;*
  25. ;* Please observe the difference in using the bit names with instructions
  26. ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
  27. ;* (skip if bit in register set/cleared). The following example illustrates
  28. ;* this:
  29. ;*
  30. ;* in    r16,PORTB             ;read PORTB latch
  31. ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
  32. ;* out   PORTB,r16             ;output to PORTB
  33. ;*
  34. ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
  35. ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
  36. ;* rjmp  TOV0_is_set           ;jump if set
  37. ;* ...                         ;otherwise do something else
  38. ;*************************************************************************
  39.  
  40. #ifndef _TN11DEF_INC_
  41. #define _TN11DEF_INC_
  42.  
  43.  
  44. #pragma partinc 0
  45.  
  46. ; ***** SPECIFY DEVICE ***************************************************
  47. .device ATtiny11
  48. #pragma AVRPART ADMIN PART_NAME ATtiny11
  49. .equ    SIGNATURE_000   = 0x1e
  50. .equ    SIGNATURE_001   = 0x90
  51. .equ    SIGNATURE_002   = 0x04
  52.  
  53. #pragma AVRPART CORE CORE_VERSION V0E
  54.  
  55.  
  56. ; ***** I/O REGISTER DEFINITIONS *****************************************
  57. ; NOTE:
  58. ; Definitions marked "MEMORY MAPPED"are extended I/O ports
  59. ; and cannot be used with IN/OUT instructions
  60. .equ    SREG    = 0x3f
  61. .equ    GIMSK   = 0x3b
  62. .equ    GIFR    = 0x3a
  63. .equ    TIMSK   = 0x39
  64. .equ    TIFR    = 0x38
  65. .equ    MCUCR   = 0x35
  66. .equ    MCUSR   = 0x34
  67. .equ    TCCR0   = 0x33
  68. .equ    TCNT0   = 0x32
  69. .equ    WDTCR   = 0x21
  70. .equ    PORTB   = 0x18
  71. .equ    DDRB    = 0x17
  72. .equ    PINB    = 0x16
  73. .equ    ACSR    = 0x08
  74.  
  75.  
  76. ; ***** BIT DEFINITIONS **************************************************
  77.  
  78. ; ***** ANALOG_COMPARATOR ************
  79. ; ACSR - Analog Comparator Control And Status Register
  80. .equ    ACIS0   = 0     ; Analog Comparator Interrupt Mode Select bit 0
  81. .equ    ACIS1   = 1     ; Analog Comparator Interrupt Mode Select bit 1
  82. .equ    ACIE    = 3     ; Analog Comparator Interrupt Enable
  83. .equ    ACI     = 4     ; Analog Comparator Interrupt Flag
  84. .equ    ACO     = 5     ; Analog Comparator Output
  85. .equ    ACD     = 7     ; Analog Comparator Disable
  86.  
  87.  
  88. ; ***** EXTERNAL_INTERRUPT ***********
  89. ; GIMSK - General Interrupt Mask Register
  90. .equ    PCIE    = 5     ; Pin Change Interrupt Enable
  91. .equ    INT0    = 6     ; External Interrupt Request 0 Enable
  92.  
  93. ; GIFR - General Interrupt Flag register
  94. .equ    PCIF    = 5     ; Pin Change Interrupt Flag
  95. .equ    INTF0   = 6     ; External Interrupt Flag 0
  96.  
  97.  
  98. ; ***** PORTB ************************
  99. ; PORTB - Data Register, Port B
  100. .equ    PORTB0  = 0     ;
  101. .equ    PB0     = 0     ; For compatibility
  102. .equ    PORTB1  = 1     ;
  103. .equ    PB1     = 1     ; For compatibility
  104. .equ    PORTB2  = 2     ;
  105. .equ    PB2     = 2     ; For compatibility
  106. .equ    PORTB3  = 3     ;
  107. .equ    PB3     = 3     ; For compatibility
  108. .equ    PORTB4  = 4     ;
  109. .equ    PB4     = 4     ; For compatibility
  110.  
  111. ; DDRB - Data Direction Register, Port B
  112. .equ    DDB0    = 0     ;
  113. .equ    DDB1    = 1     ;
  114. .equ    DDB2    = 2     ;
  115. .equ    DDB3    = 3     ;
  116. .equ    DDB4    = 4     ;
  117.  
  118. ; PINB - Input Pins, Port B
  119. .equ    PINB0   = 0     ;
  120. .equ    PINB1   = 1     ;
  121. .equ    PINB2   = 2     ;
  122. .equ    PINB3   = 3     ;
  123. .equ    PINB4   = 4     ;
  124. .equ    PINB5   = 5     ;
  125.  
  126.  
  127. ; ***** TIMER_COUNTER_0 **************
  128. ; TIMSK - Timer/Counter Interrupt Mask Register
  129. .equ    TOIE0   = 1     ; Timer/Counter0 Overflow Interrupt Enable
  130.  
  131. ; TIFR - Timer/Counter Interrupt Flag register
  132. .equ    TOV0    = 1     ; Timer/Counter0 Overflow Flag
  133.  
  134. ; TCCR0 - Timer/Counter0 Control Register
  135. .equ    CS00    = 0     ; Clock Select0 bit 0
  136. .equ    CS01    = 1     ; Clock Select0 bit 1
  137. .equ    CS02    = 2     ; Clock Select0 bit 2
  138.  
  139. ; TCNT0 - Timer Counter 0
  140. .equ    TCNT00  = 0     ; Timer Counter 0 bit 0
  141. .equ    TCNT01  = 1     ; Timer Counter 0 bit 1
  142. .equ    TCNT02  = 2     ; Timer Counter 0 bit 2
  143. .equ    TCNT03  = 3     ; Timer Counter 0 bit 3
  144. .equ    TCNT04  = 4     ; Timer Counter 0 bit 4
  145. .equ    TCNT05  = 5     ; Timer Counter 0 bit 5
  146. .equ    TCNT06  = 6     ; Timer Counter 0 bit 6
  147. .equ    TCNT07  = 7     ; Timer Counter 0 bit 7
  148.  
  149.  
  150. ; ***** WATCHDOG *********************
  151. ; WDTCR - Watchdog Timer Control Register
  152. .equ    WDP0    = 0     ; Watch Dog Timer Prescaler bit 0
  153. .equ    WDP1    = 1     ; Watch Dog Timer Prescaler bit 1
  154. .equ    WDP2    = 2     ; Watch Dog Timer Prescaler bit 2
  155. .equ    WDE     = 3     ; Watch Dog Enable
  156. .equ    WDTOE   = 4     ; RW
  157. .equ    WDDE    = WDTOE ; For compatibility
  158.  
  159.  
  160. ; ***** CPU **************************
  161. ; SREG - Status Register
  162. .equ    SREG_C  = 0     ; Carry Flag
  163. .equ    SREG_Z  = 1     ; Zero Flag
  164. .equ    SREG_N  = 2     ; Negative Flag
  165. .equ    SREG_V  = 3     ; Two's Complement Overflow Flag
  166. .equ    SREG_S  = 4     ; Sign Bit
  167. .equ    SREG_H  = 5     ; Half Carry Flag
  168. .equ    SREG_T  = 6     ; Bit Copy Storage
  169. .equ    SREG_I  = 7     ; Global Interrupt Enable
  170.  
  171. ; MCUCR - MCU Control Register
  172. .equ    ISC00   = 0     ; Interrupt Sense Control 0 bit 0
  173. .equ    ISC01   = 1     ; Interrupt Sense Control 0 bit 1
  174. .equ    SM      = 4     ; Sleep Mode
  175. .equ    SE      = 5     ; Sleep Enable
  176.  
  177. ; MCUSR - MCU Status register
  178. .equ    PORF    = 0     ; Power-On Reset Flag
  179. .equ    EXTRF   = 1     ; External Reset Flag
  180.  
  181.  
  182.  
  183. ; ***** LOCKSBITS ********************************************************
  184. .equ    LB1     = 0     ; Lockbit
  185. .equ    LB2     = 1     ; Lockbit
  186.  
  187.  
  188. ; ***** FUSES ************************************************************
  189. ; LOW fuse bits
  190.  
  191.  
  192.  
  193. ; ***** CPU REGISTER DEFINITIONS *****************************************
  194. .def    XH      = r27
  195. .def    XL      = r26
  196. .def    YH      = r29
  197. .def    YL      = r28
  198. .def    ZH      = r31
  199. .def    ZL      = r30
  200.  
  201.  
  202.  
  203. ; ***** DATA MEMORY DECLARATIONS *****************************************
  204. .equ    FLASHEND        = 0x01ff        ; Note: Word address
  205. .equ    IOEND   = 0x003f
  206. .equ    SRAM_SIZE       = 0
  207. .equ    RAMEND  = 0x0000
  208. .equ    XRAMEND = 0x0000
  209. .equ    E2END   = 0x0000
  210. .equ    EEPROMEND       = 0x0000
  211. .equ    EEADRBITS       = 4294967295
  212. #pragma AVRPART MEMORY PROG_FLASH 1024
  213. #pragma AVRPART MEMORY EEPROM 0
  214. #pragma AVRPART MEMORY INT_SRAM SIZE 0
  215. #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0
  216.  
  217.  
  218.  
  219.  
  220.  
  221. ; ***** INTERRUPT VECTORS ************************************************
  222. .equ    INT0addr        = 0x0001        ; External Interrupt 0
  223. .equ    PCI0addr        = 0x0002        ; External Interrupt Request 0
  224. .equ    OVF0addr        = 0x0003        ; Timer/Counter0 Overflow
  225. .equ    ACIaddr = 0x0004        ; Analog Comparator
  226.  
  227. .equ    INT_VECTORS_SIZE        = 5     ; size in words
  228.  
  229. #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
  230.  
  231. #endif  /* _TN11DEF_INC_ */
  232.  
  233. ; ***** END OF FILE ******************************************************
  234.