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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Zhao Yakui <yakui.zhao@intel.com>
  26.  *    Xiang Haihao <haihao.xiang@intel.com>
  27.  *    Li Zhong <zhong.li@intel.com>
  28.  *
  29.  */
  30.  
  31. /*
  32.  * __START
  33.  */
  34. __INTRA_START:
  35. mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
  36. mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
  37. mov  (16) tmp_reg4.0<1>:UD      0x0:UD {align1} ;
  38. mov  (16) tmp_reg6.0<1>:UD      0x0:UD {align1} ;
  39.  
  40. shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  41. add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
  42. add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */
  43. mov  (1) read0_header.8<1>:UD   BLOCK_32X1 {align1};
  44. mov  (1) read0_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
  45.  
  46. shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  47. add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
  48. mov  (1) read1_header.8<1>:UD   BLOCK_4X16 {align1};
  49. mov  (1) read1_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
  50.        
  51. shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  52. mov  (1) vme_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
  53.  
  54. mul  (1) obw_m0.8<1>:UD         w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
  55. add  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
  56. mul  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD 0x02:UD {align1};
  57. mov  (1) obw_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
  58.        
  59. /*
  60.  * Media Read Message -- fetch Luma neighbor edge pixels
  61.  */
  62. /* ROW */
  63. mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
  64. send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
  65.  
  66. /* COL */
  67. mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
  68. send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
  69.        
  70. /*
  71.  * Media Read Message -- fetch Chroma neighbor edge pixels
  72.  */
  73. /* ROW */
  74. shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 3:UW {align1};    /* x * 16 , y * 8 */
  75. mul  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D  2:W {align1};
  76. add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
  77. add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */
  78. mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
  79. send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
  80.  
  81. /* COL */
  82. shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 3:UW {align1};    /* x * 16, y * 8 */
  83. mul  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D  2:W {align1};
  84. add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
  85. mov  (1) read1_header.8<1>:UD   BLOCK_8X4 {align1};
  86. mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
  87. send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
  88.  
  89. /* m2, get the MV/Mb cost passed by constant buffer
  90. when creating EU thread by MEDIA_OBJECT */      
  91. mov (8) vme_msg_2<1>:UD         r1.0<8,8,1>:UD {align1};
  92.  
  93. /* m3. This is changed for FWD/BWD cost center */
  94. mov (8) vme_msg_3<1>:UD         0x0:UD {align1};               
  95.  
  96. /* m4.*/
  97. mov (8) vme_msg_4<1>:ud         0x0:ud  {align1};
  98.  
  99. /* m5 */
  100. mov  (1) INEP_ROW.0<1>:UD       0x0:UD {align1};
  101. and  (1) INEP_ROW.4<1>:UD       INEP_ROW.4<0,1,0>:UD            0xFF000000:UD {align1};
  102. mov  (8) vme_msg_5<1>:UD        INEP_ROW.0<8,8,1>:UD {align1};
  103.  
  104. mov  (1) tmp_reg0.0<1>:UB       INTRA_PLANAR_MODE_MASK {align1}; /* vp8 don't support planar intra mode */
  105. mov  (1) tmp_reg0.1<1>:UB       LUMA_CHROMA_MODE {align1}; /* Intra type: Luma + Chroma */
  106.  
  107. /* Intra mode mask && Intra compute type */
  108. mov  (1) vme_msg_5.4<1>:UW      tmp_reg0.0<0,1,0>:UW {align1};
  109.  
  110. /* m6 */        
  111. mov  (8) vme_msg_6<1>:UD         0x0:UD {align1};
  112. mov (16) vme_msg_6.0<1>:UB       INEP_COL0.3<32,8,4>:UB {align1};
  113. mov  (1) vme_msg_6.16<1>:UD      INTRA_PREDICTORE_MODE {align1};
  114.  
  115. /* the penalty for Intra mode */
  116. mov  (1) vme_msg_6.28<1>:UD     0x010101:UD {align1};
  117. mov  (1) vme_msg_6.20<1>:UW      CHROMA_ROW.6<0,1,0>:UW {align1};
  118.  
  119.  
  120. /* m7 */
  121.  
  122. mov  (4) vme_msg_7.16<1>:UD      CHROMA_ROW.8<4,4,1>:UD {align1};
  123. mov  (8) vme_msg_7.0<1>:UW       CHROMA_COL.2<16,8,2>:UW {align1};
  124.  
  125. /*
  126.  * VME message
  127.  */
  128.  
  129. /* m1 */
  130. mov  (1) intra_flag<1>:UW       0x0:UW {align1};
  131. mov  (1) intra_part_mask_ub<1>:UB  LUMA_INTRA_8x8_DISABLE {align1}; /* vp8 don't support intra_8x8 mode*/
  132.  
  133. /* assign MB intra struct from the thread payload*/
  134. mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1};
  135.                            
  136. /* Disable DC HAAR component when calculating HARR SATD block */
  137. mov  (1) tmp_reg0.0<1>:UW       DC_HARR_DISABLE:UW              {align1};
  138. mov  (1) vme_m1.30<1>:UB        tmp_reg0.0<0,1,0>:UB  {align1};
  139.  
  140. mov  (8) vme_msg_1<1>:UD        vme_m1.0<8,8,1>:UD {align1};
  141.  
  142. /* m0 */        
  143. add  (1) vme_m0.12<1>:UD        vme_m0.12<0,1,0>:ud     INTRA_SAD_HAAR:UD {align1};/* 16x16 Source, Intra_harr */
  144. mov  (1) vme_m0.15<1>:UB        SUB_PART_8x4_DISABLE + SUB_PART_4x8_DISABLE {align1}; /* vp8 don't support 8x4 and 4x8 partion */
  145. mov  (8) vme_msg_0<1>:UD        vme_m0.0<8,8,1>:UD {align1};
  146.  
  147. /* after verification it will be passed by using payload */
  148. send (8)
  149.         vme_msg_ind
  150.         vme_wb<1>:UD
  151.         null
  152.         cre(
  153.                 BIND_IDX_VME,
  154.                 VME_SIC_MESSAGE_TYPE
  155.         )
  156.         mlen sic_vme_msg_length
  157.         rlen vme_wb_length
  158.         {align1};
  159. /*
  160.  * Oword Block Write message
  161.  */
  162. mov  (8) msg_reg0.0<1>:UD       obw_m0<8,8,1>:UD {align1};
  163.        
  164. mov  (1) msg_reg1.0<1>:UD       vme_wb.0<0,1,0>:UD      {align1};
  165. mov  (1) msg_reg1.4<1>:UD       vme_wb.16<0,1,0>:UD     {align1};
  166. mov  (1) msg_reg1.8<1>:UD       vme_wb.20<0,1,0>:UD     {align1};
  167. mov  (1) msg_reg1.12<1>:UD      vme_wb.24<0,1,0>:UD     {align1};
  168.  
  169. /* Distortion, Intra (17-16), */
  170. mov  (1) msg_reg1.16<1>:UW      vme_wb.12<0,1,0>:UW     {align1};
  171.  
  172. mov  (1) msg_reg1.20<1>:UD      vme_wb.8<0,1,0>:UD     {align1};
  173. /* VME clock counts */
  174. mov  (1) msg_reg1.24<1>:UD      vme_wb.28<0,1,0>:UD     {align1};
  175.  
  176. mov  (1) msg_reg1.28<1>:UD      obw_m0.8<0,1,0>:UD     {align1};
  177.  
  178. /* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
  179. send (16)
  180.         msg_ind
  181.         obw_wb
  182.         null
  183.         data_port(
  184.                 OBW_CACHE_TYPE,
  185.                 OBW_MESSAGE_TYPE,
  186.                 OBW_CONTROL_2,
  187.                 OBW_BIND_IDX,
  188.                 OBW_WRITE_COMMIT_CATEGORY,
  189.                 OBW_HEADER_PRESENT
  190.         )
  191.         mlen 2
  192.         rlen obw_wb_length
  193.         {align1};
  194.  
  195. __EXIT:
  196. /*
  197.  * kill thread
  198.  */        
  199. mov  (8) ts_msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
  200. send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
  201.