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  1. /*
  2.  * Copyright © <2010>, Intel Corporation.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  */
  25. // Modual name: IntraFrame.asm
  26. //
  27. // Make intra predition estimation for Intra frame
  28. //
  29.  
  30. //
  31. //  Now, begin source code....
  32. //
  33.  
  34. /*
  35.  * __START
  36.  */
  37. __INTER_START:
  38. mov  (16) tmp_reg0.0<1>:UD      0x0:UD {align1};
  39. mov  (16) tmp_reg2.0<1>:UD      0x0:UD {align1};
  40. mov  (16) tmp_reg3.0<1>:UD      0x0:UD {align1};
  41.  
  42. shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  43. add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
  44. add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */
  45. mov  (1) read0_header.8<1>:UD   BLOCK_32X1 {align1};
  46. mov  (1) read0_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
  47.  
  48. shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  49. add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
  50. mov  (1) read1_header.8<1>:UD   BLOCK_4X16 {align1};
  51. mov  (1) read1_header.20<1>:UB  thread_id_ub {align1};                  /* dispatch id */
  52.        
  53. shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* Source =  (x, y) * 16 */
  54.  
  55. cmp.z.f0.0 (1)  null<1>:uw      quality_level_ub<0,1,0>:ub              LOW_QUALITY_LEVEL:uw   {align1};
  56. (f0.0) jmpi (1) __low_quality_search;
  57.  
  58. __high_quality_search:
  59. #ifdef DEV_SNB
  60. shl  (2) vme_m0.0<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    
  61. add  (1) vme_m0.0<1>:W          vme_m0.0<0,1,0>:W -16:W {align1};               /* Reference = (x-16,y-12)-(x+32,y+24) */
  62. add  (1) vme_m0.2<1>:W          vme_m0.2<0,1,0>:W -12:W {align1};
  63. #else
  64. mov  (1) vme_m0.0<1>:W          -16:W {align1} ;                /* Reference = (x-16,y-12)-(x+32,y+24) */
  65. mov  (1) vme_m0.2<1>:W          -12:W {align1} ;
  66. #endif
  67.        
  68. mov  (1) vme_m0.12<1>:UD        SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER:UD {align1};    /* 16x16 Source, 1/4 pixel, harr */
  69. mov  (1) vme_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
  70. mov  (1) vme_m0.22<1>:UW        REF_REGION_SIZE {align1};               /* Reference Width&Height, 48x40 */
  71. jmpi __vme_msg1;
  72.  
  73.  
  74. __low_quality_search:
  75. #ifdef DEV_SNB
  76. shl  (2) vme_m0.0<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    
  77. add  (1) vme_m0.0<1>:W          vme_m0.0<0,1,0>:W -8:W {align1};
  78. add  (1) vme_m0.2<1>:W          vme_m0.2<0,1,0>:W -8:W {align1};
  79. #else
  80. mov  (1) vme_m0.0<1>:W          -8:W {align1} ;
  81. mov  (1) vme_m0.2<1>:W          -8:W {align1} ;
  82. #endif
  83.        
  84. mov  (1) vme_m0.12<1>:UD        SEARCH_CTRL_SINGLE + INTER_PART_MASK + INTER_SAD_HAAR + SUB_PEL_MODE_HALF:UD {align1};    /* 16x16 Source, 1/2 pixel, harr */
  85. mov  (1) vme_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
  86. mov  (1) vme_m0.22<1>:UW        MIN_REF_REGION_SIZE {align1};               /* Reference Width&Height, 32x32 */
  87.  
  88. __vme_msg1:
  89. mov  (1) vme_m1.0<1>:UD         ADAPTIVE_SEARCH_ENABLE:ud {align1} ;
  90. mov  (1) vme_m1.4<1>:UD         FB_PRUNING_ENABLE:UD {align1};
  91. /* MV num is passed by constant buffer. R4.28 */
  92. mov  (1) vme_m1.4<1>:UB         r4.28<0,1,0>:UB {align1};
  93. mov  (1) vme_m1.8<1>:UD         START_CENTER + SEARCH_PATH_LEN:UD {align1};
  94.  
  95. mul  (1) obw_m0.8<1>:UD         w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
  96. add  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
  97. mul  (1) obw_m0.8<1>:UD         obw_m0.8<0,1,0>:UD INTER_VME_OUTPUT_IN_OWS:UD {align1};
  98. mov  (1) obw_m0.20<1>:UB        thread_id_ub {align1};                  /* dispatch id */
  99.  
  100. __VME_LOOP:    
  101.  
  102. /*
  103.  * Media Read Message -- fetch neighbor edge pixels
  104.  */
  105. /* ROW */
  106. mov  (8) msg_reg0.0<1>:UD       read0_header.0<8,8,1>:UD {align1};        
  107. send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
  108.  
  109. /* COL */
  110. mov  (8) msg_reg0.0<1>:UD       read1_header.0<8,8,1>:UD {align1};                
  111. send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
  112.        
  113. /*
  114.  * VME message
  115.  */
  116. /* m0 */
  117. mov  (8) vme_msg_0.0<1>:UD      vme_m0.0<8,8,1>:UD {align1};
  118.        
  119. /* m1 */
  120. mov  (1) intra_flag<1>:UW       0x0:UW {align1}                     ;
  121. and.z.f0.0 (1) null<1>:UW transform_8x8_ub<0,1,0>:UB 1:UW {align1};
  122. (f0.0) mov  (1) intra_part_mask_ub<1>:UB  LUMA_INTRA_8x8_DISABLE {align1};
  123.  
  124. cmp.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB 0:UW {align1};                                                   /* X != 0 */
  125. (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_AE {align1};         /* A */
  126.  
  127. cmp.nz.f0.0 (1) null<1>:UW orig_y_ub<0,1,0>:UB 0:UW {align1};                                                   /* Y != 0 */
  128. (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_B {align1};          /* B */
  129.  
  130. mul.nz.f0.0 (1) null<1>:UW orig_x_ub<0,1,0>:UB orig_y_ub<0,1,0>:UB {align1};                                    /* X * Y != 0 */
  131. (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_D {align1};          /* D */
  132.  
  133. add  (1) tmp_x_w<1>:W orig_x_ub<0,1,0>:UB 1:UW {align1};                                                        /* X + 1 */
  134. add  (1) tmp_x_w<1>:W w_in_mb_uw<0,1,0>:UW -tmp_x_w<0,1,0>:W {align1};                                          /* width - (X + 1) */
  135. mul.nz.f0.0 (1) null<1>:UD tmp_x_w<0,1,0>:W orig_y_ub<0,1,0>:UB {align1};                                       /* (width - (X + 1)) * Y != 0 */
  136. (f0.0) add (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB INTRA_PRED_AVAIL_FLAG_C {align1};          /* C */
  137.  
  138. and.nz.f0.0 (1) null<1>:UW slice_edge_ub<0,1,0>:UB 2:UW {align1};
  139. (f0.0) and (1) mb_intra_struct_ub<1>:UB mb_intra_struct_ub<0,1,0>:UB  0xE0 {align1};                            /* slice edge disable B,C,D*/
  140.        
  141. mov  (8) vme_msg_1<1>:UD        vme_m1.0<8,8,1>:UD {align1};
  142.        
  143. /* m2 */        
  144. mov  (8) vme_msg_2<1>:UD        0x0:UD {align1};
  145.  
  146. /* m3 */
  147. mov  (1) INEP_ROW.0<1>:UD       0x0:UD {align1};
  148. and  (1) INEP_ROW.4<1>:UD       INEP_ROW.4<0,1,0>:UD            0xFF000000:UD {align1};
  149. mov  (8) vme_msg_3<1>:UD        INEP_ROW.0<8,8,1>:UD {align1};        
  150.  
  151. /* m4 */
  152. mov  (8) vme_msg_4<1>:UD        0x0 {align1};
  153. mov (16) vme_msg_4.0<1>:UB      INEP_COL0.3<32,8,4>:UB {align1};
  154. mov  (1) vme_msg_4.16<1>:UD     INTRA_PREDICTORE_MODE {align1};
  155.  
  156. send (8)
  157.         vme_msg_ind
  158.         vme_wb
  159.         null
  160.         vme(
  161.                 BIND_IDX_VME,
  162.                 0,
  163.                 0,
  164.                 VME_MESSAGE_TYPE_MIXED
  165.         )
  166.         mlen vme_msg_length
  167.         rlen vme_inter_wb_length
  168.         {align1};
  169. /*
  170.  * Oword Block Write message
  171.  */
  172.  
  173. /* MV pairs */        
  174. mov  (8) msg_reg0.0<1>:UD       obw_m0.0<8,8,1>:UD {align1};
  175.  
  176. #ifdef DEV_SNB        
  177. mov  (16) obw_m1.0<1>:UW        vme_wb1.0<16,16,1>:UB  {align1};
  178. add  (8) obw_m1.0<2>:W          obw_m1.0<16,8,2>:W -64:W {align1};
  179. add  (8) obw_m1.2<2>:W          obw_m1.2<16,8,2>:W -48:W {align1};
  180. mov  (16) obw_m2.0<1>:UW        vme_wb1.16<16,16,1>:UB  {align1};
  181. add  (8) obw_m2.0<2>:W          obw_m2.0<16,8,2>:W -64:W {align1};
  182. add  (8) obw_m2.2<2>:W          obw_m2.2<16,8,2>:W -48:W {align1};
  183. mov  (16) obw_m3.0<1>:UW        vme_wb2.0<16,16,1>:UB  {align1};
  184. add  (8) obw_m3.0<2>:W          obw_m3.0<16,8,2>:W -64:W {align1};
  185. add  (8) obw_m3.2<2>:W          obw_m3.2<16,8,2>:W -48:W {align1};
  186. mov  (16) obw_m4.0<1>:UW        vme_wb2.16<16,16,1>:UB  {align1};
  187. add  (8) obw_m4.0<2>:W          obw_m4.0<16,8,2>:W -64:W {align1};
  188. add  (8) obw_m4.2<2>:W          obw_m4.2<16,8,2>:W -48:W {align1};
  189. #else
  190. mov  (8) obw_m1.0<1>:ud         vme_wb1.0<8,8,1>:ud {align1};
  191. mov  (8) obw_m2.0<1>:ud         vme_wb2.0<8,8,1>:ud {align1};
  192. mov  (8) obw_m3.0<1>:ud         vme_wb3.0<8,8,1>:ud {align1};
  193. mov  (8) obw_m4.0<1>:ud         vme_wb4.0<8,8,1>:ud {align1};                
  194. #endif      
  195.        
  196. mov  (8) msg_reg1.0<1>:UD       obw_m1.0<8,8,1>:UD   {align1};
  197.  
  198. mov  (8) msg_reg2.0<1>:UD       obw_m2.0<8,8,1>:UD   {align1};
  199.  
  200. mov  (8) msg_reg3.0<1>:UD       obw_m3.0<8,8,1>:UD   {align1};
  201.  
  202. mov  (8) msg_reg4.0<1>:UD       obw_m4.0<8,8,1>:UD   {align1};                
  203.  
  204. /* bind index 3, write 8 oword, msg type: 8(OWord Block Write) */
  205. send (16)
  206.         msg_ind
  207.         obw_wb
  208.         null
  209.         data_port(
  210.                 OBW_CACHE_TYPE,
  211.                 OBW_MESSAGE_TYPE,
  212.                 OBW_CONTROL_4,
  213.                 OBW_BIND_IDX,
  214.                 OBW_WRITE_COMMIT_CATEGORY,
  215.                 OBW_HEADER_PRESENT
  216.         )
  217.         mlen 5
  218.         rlen obw_wb_length
  219.         {align1};
  220.  
  221. /* other info */        
  222. add             (1)     msg_reg0.8<1>:UD        obw_m0.8<0,1,0>:UD      INTER_VME_OUTPUT_MV_IN_OWS:UD {align1} ;
  223.  
  224. and.z.f0.0      (1)     null<1>:ud              vme_wb0.0<0,1,0>:ud     INTRAMBFLAG_MASK:ud {align1} ;
  225.  
  226. (-f0.0)jmpi     (1)     __INTRA_INFO ;
  227.  
  228. __INTER_INFO:  
  229. mov             (1)     tmp_uw1<1>:uw           0:uw {align1} ;
  230. mov             (1)     tmp_ud1<1>:ud           0:ud {align1} ;
  231. (f0.0)and       (1)     tmp_uw1<1>:uw           vme_wb0.2<0,1,0>:uw     MV32_BIT_MASK:uw {align1} ;
  232. (f0.0)shr       (1)     tmp_uw1<1>:uw           tmp_uw1<1>:uw           MV32_BIT_SHIFT:uw {align1} ;
  233. (f0.0)mul       (1)     tmp_ud1<1>:ud           tmp_uw1<0,1,0>:uw       96:uw {align1} ;
  234. (f0.0)add       (1)     tmp_ud1<1>:ud           tmp_ud1<0,1,0>:ud       32:uw {align1} ;
  235. (f0.0)shl       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MFC_MV32_BIT_SHIFT:uw {align1} ;
  236. (f0.0)add       (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       MVSIZE_UW_BASE:uw {align1} ;
  237. add             (1)     tmp_uw1<1>:uw           tmp_uw1<0,1,0>:uw       CBP_DC_YUV_UW:uw {align1} ;
  238.  
  239. mov             (1)     msg_reg1.0<1>:uw        vme_wb0.0<0,1,0>:uw     {align1} ;
  240. mov             (1)     msg_reg1.2<1>:uw        tmp_uw1<0,1,0>:uw       {align1} ;
  241. mov             (1)     msg_reg1.4<1>:UD        vme_wb0.28<0,1,0>:UD    {align1};
  242. mov             (1)     msg_reg1.8<1>:ud        tmp_ud1<0,1,0>:ud       {align1} ;
  243.  
  244. jmpi            (1)     __OUTPUT_INFO ;
  245.        
  246. __INTRA_INFO:
  247. mov             (1)     msg_reg1.0<1>:UD        vme_wb.0<0,1,0>:UD      {align1};
  248. mov             (1)     msg_reg1.4<1>:UD        vme_wb.16<0,1,0>:UD     {align1};
  249. mov             (1)     msg_reg1.8<1>:UD        vme_wb.20<0,1,0>:UD     {align1};
  250. mov             (1)     msg_reg1.12<1>:UD       vme_wb.24<0,1,0>:UD     {align1};
  251.  
  252. __OUTPUT_INFO:  
  253. /* bind index 3, write 1 oword, msg type: 8(OWord Block Write) */
  254. send (16)
  255.         msg_ind
  256.         obw_wb
  257.         null
  258.         data_port(
  259.                 OBW_CACHE_TYPE,
  260.                 OBW_MESSAGE_TYPE,
  261.                 OBW_CONTROL_0,
  262.                 OBW_BIND_IDX,
  263.                 OBW_WRITE_COMMIT_CATEGORY,
  264.                 OBW_HEADER_PRESENT
  265.         )
  266.         mlen 2
  267.         rlen obw_wb_length
  268.         {align1};
  269.  
  270. add             (1)     orig_x_ub<1>:ub         orig_x_ub<0,1,0>:ub             1:uw {align1} ;
  271. add             (1)     vme_m0.8<1>:UW          vme_m0.8<0,1,0>:UW              16:UW {align1};    /* X += 16 */
  272. #ifdef DEV_SNB        
  273. add             (1)     vme_m0.0<1>:W           vme_m0.0<0,1,0>:W               16:W {align1};     /* X += 16 */
  274. #endif
  275.  
  276. cmp.e.f0.0      (1)     null<1>:uw              w_in_mb_uw<0,1,0>:uw            orig_x_ub<0,1,0>:ub {align1};
  277. /* (0, y + 1) */        
  278. (f0.0)mov       (1)     orig_x_ub<1>:ub         0:uw {align1} ;
  279. (f0.0)add       (1)     orig_y_ub<1>:ub orig_y_ub<0,1,0>:ub             1:uw {align1} ;
  280. (f0.0)mov       (1)     vme_m0.8<1>:uw          0:uw {align1} ;
  281. (f0.0)add       (1)     vme_m0.10<1>:uw         vme_m0.10<0,1,0>:uw             16:uw {align1} ;
  282. #ifdef DEV_SNB        
  283. (f0.0)mov       (1)     vme_m0.0<1>:w           -16:W {align1};                 /* Reference = (x-16,y-12)-(x+32,y+24) */
  284. (f0.0)add       (1)     vme_m0.2<1>:w           vme_m0.2<0,1,0>:w               16:w {align1};
  285. #endif
  286.  
  287. shl  (2) read0_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  288. add  (1) read0_header.0<1>:D    read0_header.0<0,1,0>:D -8:W {align1};     /* X offset */
  289. add  (1) read0_header.4<1>:D    read0_header.4<0,1,0>:D -1:W {align1};     /* Y offset */
  290.  
  291. shl  (2) read1_header.0<1>:D    orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* (x, y) * 16 */
  292. add  (1) read1_header.0<1>:D    read1_header.0<0,1,0>:D -4:W {align1};     /* X offset */
  293.  
  294. shl  (2) vme_m0.8<1>:UW         orig_xy_ub<2,2,1>:UB 4:UW {align1};    /* Source =  (x, y) * 16 */
  295.  
  296. add             (1)     obw_m0.8<1>:UD          obw_m0.8<0,1,0>:UD              INTER_VME_OUTPUT_IN_OWS:UW {align1} ;
  297.        
  298. add.z.f0.1      (1)     num_macroblocks<1>:w    num_macroblocks<0,1,0>:w        -1:w {align1} ;
  299. (-f0.1)jmpi     (1)     __VME_LOOP ;
  300.        
  301. __EXIT:
  302.        
  303. /*
  304.  * kill thread
  305.  */        
  306. mov  (8) msg_reg0<1>:UD         r0<8,8,1>:UD {align1};
  307. send (16) msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
  308.