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  1. /*
  2.  * All Video Processing kernels
  3.  * Copyright © <2010>, Intel Corporation.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the
  7.  * "Software"), to deal in the Software without restriction, including
  8.  * without limitation the rights to use, copy, modify, merge, publish,
  9.  * distribute, sub license, and/or sell copies of the Software, and to
  10.  * permit persons to whom the Software is furnished to do so, subject to
  11.  * the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice (including the
  14.  * next paragraph) shall be included in all copies or substantial portions
  15.  * of the Software.
  16.  *
  17.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  21.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24.  *
  25.  * This file was originally licensed under the following license
  26.  *
  27.  *  Licensed under the Apache License, Version 2.0 (the "License");
  28.  *  you may not use this file except in compliance with the License.
  29.  *  You may obtain a copy of the License at
  30.  *
  31.  *      http://www.apache.org/licenses/LICENSE-2.0
  32.  *
  33.  *  Unless required by applicable law or agreed to in writing, software
  34.  *  distributed under the License is distributed on an "AS IS" BASIS,
  35.  *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  36.  *  See the License for the specific language governing permissions and
  37.  *  limitations under the License.
  38.  *
  39.  */
  40.  
  41. // Module name: IMC3_Load_9x5.asm
  42. //
  43. //----------------------------------------------------------------
  44. //  This module loads 16x8 Y, 9x5 U and 9x5 V planar data blocks for CSC module
  45. //      and stores it in byte-aligned format.
  46. //----------------------------------------------------------------
  47.  
  48. #define  IMC3_LOAD_9x5
  49. #include "PL3_Load.inc"
  50.  
  51. // Load 16x8 planar Y ----------------------------------------------------------
  52.     add  (2) rMSGSRC.0<1>:d     wORIX<2;2,1>:w    wSRC_H_ORI_OFFSET<2;2,1>:w       // Source Y Block origin
  53. #if !defined(LOAD_UV_ONLY)
  54.     mov  (1) rMSGSRC.2<1>:ud    nDPR_BLOCK_SIZE_Y:ud                               // Block width and height (16x8)
  55.  
  56.     mov  (8) mMSGHDRY<1>:ud     rMSGSRC<8;8,1>:ud
  57.     send (8) udSRC_Y(0)<1>      mMSGHDRY    udDUMMY_NULL    nDATAPORT_READ    nDPMR_MSGDSC+nDPR_MSG_SIZE_Y+nBI_CURRENT_SRC_Y:ud
  58. #endif
  59.  
  60. // Load 9x5 planar U and V -----------------------------------------------------
  61.     asr (2)  rMSGSRC.0<1>:d     rMSGSRC.0<2;2,1>:d       1:w   // U/V block origin should be half of Y's
  62.     mov (1)  rMSGSRC.2<1>:ud    nDPR_BLOCK_SIZE_UV:ud          // U/V block width and height (12x5)
  63.  
  64.     mov  (8) mMSGHDRU<1>:ud     rMSGSRC<8;8,1>:ud
  65.     send (8) udSRC_U(0)<1>      mMSGHDRU    udDUMMY_NULL    nDATAPORT_READ    nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_U:ud
  66.     mov  (8) mMSGHDRV<1>:ud     rMSGSRC<8;8,1>:ud
  67.     send (8) udSRC_V(0)<1>      mMSGHDRU    udDUMMY_NULL    nDATAPORT_READ    nDPMR_MSGDSC+nDPR_MSG_SIZE_UV+nBI_CURRENT_SRC_V:ud
  68.  
  69. // Convert to word-aligned format ----------------------------------------------
  70. #if !defined(LOAD_UV_ONLY)
  71.     $for (nY_NUM_OF_ROWS-1; >-1; -1) {
  72.         mov (16)  uwDEST_Y(0,%1*16)<1>         ubSRC_Y(0,%1*16)
  73.     }
  74. #endif
  75.     $for(nUV_NUM_OF_ROWS-2; >-1; -1) {
  76.         mov (16)  uwDEST_U(0, %1*16)<1>        ubSRC_U(0, %1*16)
  77.         mov (16)  uwDEST_V(0, %1*16)<1>        ubSRC_V(0, %1*16)
  78.     }
  79.  
  80. // End of IMC3_Load_9x5
  81.