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  1. /*
  2.  * Copyright © 2014 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Qu Pengfei <Pengfei.Qu@intel.com>
  26.  *
  27.  */
  28.  
  29. #ifndef GEN9_MFC_H
  30. #define GEN9_MFC_H
  31.  
  32. #include <drm.h>
  33. #include <i915_drm.h>
  34. #include <intel_bufmgr.h>
  35.  
  36. #include "i965_gpe_utils.h"
  37.  
  38. struct encode_state;
  39.  
  40. #define MAX_HCP_REFERENCE_SURFACES      8
  41. #define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS             9
  42.  
  43. #define INTRA_MB_FLAG_MASK              0x00002000
  44.  
  45. /* The space required for slice header SLICE_STATE + header.
  46.  * Is it enough? */
  47. #define SLICE_HEADER            80
  48.  
  49. /* the space required for slice tail. */
  50. #define SLICE_TAIL          16
  51.  
  52. #define __SOFTWARE__    0
  53.  
  54. #define HCP_BATCHBUFFER_HEVC_INTRA       0
  55. #define HCP_BATCHBUFFER_HEVC_INTER       1
  56. #define NUM_HCP_KERNEL                   2
  57.  
  58. #define BIND_IDX_VME_OUTPUT             0
  59. #define BIND_IDX_HCP_SLICE_HEADER       1
  60. #define BIND_IDX_HCP_BATCHBUFFER        2
  61.  
  62. #define CMD_LEN_IN_OWORD        4
  63.  
  64. struct gen9_hcpe_context {
  65.     struct {
  66.         unsigned int width;
  67.         unsigned int height;
  68.         unsigned int w_pitch;
  69.         unsigned int h_pitch;
  70.     } surface_state;
  71.  
  72.     //HCP_PIPE_BUF_ADDR_STATE
  73.  
  74.     struct {
  75.         dri_bo *bo;
  76.     } deblocking_filter_line_buffer;            //OUTPUT: reconstructed picture with deblocked
  77.  
  78.     struct {
  79.         dri_bo *bo;
  80.     } deblocking_filter_tile_line_buffer;       //OUTPUT: reconstructed picture with deblocked
  81.  
  82.     struct {
  83.         dri_bo *bo;
  84.     } deblocking_filter_tile_column_buffer;     //OUTPUT: reconstructed picture with deblocked
  85.  
  86.     struct {
  87.         dri_bo *bo;
  88.     } uncompressed_picture_source;              //INPUT: original compressed image
  89.  
  90.     struct {
  91.         dri_bo *bo;
  92.     } metadata_line_buffer;                     //INTERNAL:metadata
  93.  
  94.     struct {
  95.         dri_bo *bo;
  96.     } metadata_tile_line_buffer;                //INTERNAL:metadata
  97.  
  98.     struct {
  99.         dri_bo *bo;
  100.     } metadata_tile_column_buffer;              //INTERNAL:metadata
  101.  
  102.     struct {
  103.         dri_bo *bo;
  104.     } sao_line_buffer;                     //INTERNAL:SAO not used in skylake
  105.  
  106.     struct {
  107.         dri_bo *bo;
  108.     } sao_tile_line_buffer;                //INTERNAL:SAO not used in skylake
  109.  
  110.     struct {
  111.         dri_bo *bo;
  112.     } sao_tile_column_buffer;              //INTERNAL:SAO not used in skylake
  113.  
  114.     struct {
  115.         dri_bo *bo;
  116.     } current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];       //
  117.  
  118.     struct {
  119.         dri_bo *bo;
  120.     } reference_surfaces[MAX_HCP_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
  121.  
  122.     //HCP_IND_OBJ_BASE_ADDR_STATE
  123.     struct {
  124.         dri_bo *bo;
  125.     } hcp_indirect_cu_object;           //INPUT: the cu' mv info
  126.  
  127.     struct {
  128.         dri_bo *bo;
  129.         int offset;
  130.         int end_offset;
  131.     } hcp_indirect_pak_bse_object;      //OUTPUT: the compressed bitstream
  132.  
  133.     //Bit rate tracking context
  134.     struct {
  135.         unsigned int QpPrimeY;
  136.         unsigned int MaxQpNegModifier;
  137.         unsigned int MaxQpPosModifier;
  138.         unsigned char MaxSizeInWord;
  139.         unsigned char TargetSizeInWord;
  140.         unsigned char Correct[6];
  141.         unsigned char GrowInit;
  142.         unsigned char GrowResistance;
  143.         unsigned char ShrinkInit;
  144.         unsigned char ShrinkResistance;
  145.  
  146.         unsigned int target_mb_size;
  147.         unsigned int target_frame_size;
  148.     } bit_rate_control_context[3];      //INTERNAL: for I, P, B frames
  149.  
  150.     struct {
  151.         int mode;
  152.         int gop_nums[3];
  153.         int target_frame_size[3]; // I,P,B
  154.         double bits_per_frame;
  155.         double qpf_rounding_accumulator;
  156.  
  157.         double saved_bps;
  158.         double saved_fps;
  159.         int saved_intra_period;
  160.         int saved_ip_period;
  161.         int saved_idr_period;
  162.     } brc;
  163.  
  164.     struct {
  165.         double current_buffer_fullness;
  166.         double target_buffer_fullness;
  167.         double buffer_capacity;
  168.         unsigned int buffer_size;
  169.         unsigned int violation_noted;
  170.     } hrd;
  171.  
  172.     //HRD control context
  173.     struct {
  174.         int i_bit_rate_value; // scale?
  175.         int i_cpb_size_value; // scale?
  176.  
  177.         int i_initial_cpb_removal_delay;
  178.         int i_cpb_removal_delay;
  179.  
  180.         int i_frame_number;
  181.  
  182.         int i_initial_cpb_removal_delay_length;
  183.         int i_cpb_removal_delay_length;
  184.         int i_dpb_output_delay_length;
  185.     } vui_hrd;
  186.  
  187.     // picture width and height
  188.     struct {
  189.         uint16_t picture_width_in_samples;
  190.         uint16_t picture_height_in_samples;
  191.         uint16_t picture_width_in_ctbs;
  192.         uint16_t picture_height_in_ctbs;
  193.         uint16_t picture_width_in_min_cb_minus1;
  194.         uint16_t picture_height_in_min_cb_minus1;
  195.         uint16_t picture_width_in_mbs; /* to use on skylake */
  196.         uint16_t picture_height_in_mbs;/* to sue on skylake */
  197.         uint8_t ctb_size;
  198.         uint8_t min_cb_size;
  199.     } pic_size;
  200.  
  201.     VAQMatrixBufferHEVC  iq_matrix_hevc;
  202.  
  203.     struct i965_gpe_context gpe_context;
  204.     struct i965_buffer_surface hcp_batchbuffer_surface;
  205.     struct intel_batchbuffer *aux_batchbuffer;
  206.     struct i965_buffer_surface aux_batchbuffer_surface;
  207.  
  208.     void (*pipe_mode_select)(VADriverContextP ctx,
  209.                              int standard_select,
  210.                              struct intel_encoder_context *encoder_context);
  211.     void (*set_surface_state)(VADriverContextP ctx, struct encode_state *encode_state,
  212.                               struct intel_encoder_context *encoder_context);
  213.     void (*ind_obj_base_addr_state)(VADriverContextP ctx,
  214.                                     struct intel_encoder_context *encoder_context);
  215.     void (*fqm_state)(VADriverContextP ctx,
  216.                       struct intel_encoder_context *encoder_context);
  217.     void (*qm_state)(VADriverContextP ctx,
  218.                      struct intel_encoder_context *encoder_context);
  219.     void (*pic_state)(VADriverContextP ctx,
  220.                       struct encode_state *encode_state,
  221.                       struct intel_encoder_context *encoder_context);
  222.     void (*insert_object)(VADriverContextP ctx,
  223.                           struct intel_encoder_context *encoder_context,
  224.                           unsigned int *insert_data,
  225.                           int lenght_in_dws, int data_bits_in_last_dw,
  226.                           int skip_emul_byte_count,
  227.                           int is_last_header, int is_end_of_slice,
  228.                           int emulation_flag,
  229.                           struct intel_batchbuffer *batch);
  230.     void (*buffer_suface_setup)(VADriverContextP ctx,
  231.                                 struct i965_gpe_context *gpe_context,
  232.                                 struct i965_buffer_surface *buffer_surface,
  233.                                 unsigned long binding_table_offset,
  234.                                 unsigned long surface_state_offset);
  235. };
  236.  
  237. VAStatus gen9_hcpe_pipeline(VADriverContextP ctx,
  238.                             VAProfile profile,
  239.                             struct encode_state *encode_state,
  240.                             struct intel_encoder_context *encoder_context);
  241.  
  242. /* HEVC BRC */
  243. extern int intel_hcpe_update_hrd(struct encode_state *encode_state,
  244.                                  struct gen9_hcpe_context *hcpe_context,
  245.                                  int frame_bits);
  246.  
  247. extern int intel_hcpe_brc_postpack(struct encode_state *encode_state,
  248.                                    struct gen9_hcpe_context *hcpe_context,
  249.                                    int frame_bits);
  250.  
  251. extern void intel_hcpe_hrd_context_update(struct encode_state *encode_state,
  252.         struct gen9_hcpe_context *hcpe_context);
  253.  
  254. extern int intel_hcpe_interlace_check(VADriverContextP ctx,
  255.                                       struct encode_state *encode_state,
  256.                                       struct intel_encoder_context *encoder_context);
  257.  
  258. extern void intel_hcpe_brc_prepare(struct encode_state *encode_state,
  259.                                    struct intel_encoder_context *encoder_context);
  260.  
  261. /* HEVC HCP pipeline */
  262. extern void intel_hcpe_hevc_pipeline_header_programing(VADriverContextP ctx,
  263.         struct encode_state *encode_state,
  264.         struct intel_encoder_context *encoder_context,
  265.         struct intel_batchbuffer *slice_batch);
  266.  
  267. extern VAStatus intel_hcpe_hevc_prepare(VADriverContextP ctx,
  268.                                         struct encode_state *encode_state,
  269.                                         struct intel_encoder_context *encoder_context);
  270.  
  271. extern void
  272. intel_hcpe_hevc_ref_idx_state(VADriverContextP ctx,
  273.                               struct encode_state *encode_state,
  274.                               struct intel_encoder_context *encoder_context);
  275.  
  276. extern void
  277. intel_hevc_slice_insert_packed_data(VADriverContextP ctx,
  278.                                     struct encode_state *encode_state,
  279.                                     struct intel_encoder_context *encoder_context,
  280.                                     int slice_index,
  281.                                     struct intel_batchbuffer *slice_batch);
  282.  
  283. extern
  284. Bool gen9_hcpe_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
  285.  
  286. void gen9_hcpe_context_destroy(void *context);
  287.  
  288. #endif  /* GEN9_MFC_H */
  289.