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  1. /*
  2.  * Copyright © 2010 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Zhou Chang <chang.zhou@intel.com>
  26.  *
  27.  */
  28.  
  29. #ifndef _GEN6_MFC_H_
  30. #define _GEN6_MFC_H_
  31.  
  32. #include <drm.h>
  33. #include <i915_drm.h>
  34. #include <intel_bufmgr.h>
  35.  
  36. #include "i965_gpe_utils.h"
  37. #include "i965_encoder.h"
  38.  
  39. struct encode_state;
  40.  
  41. #define MAX_MFC_REFERENCE_SURFACES      16
  42. #define NUM_MFC_DMV_BUFFERS             34
  43.  
  44. #define INTRA_MB_FLAG_MASK              0x00002000
  45.  
  46. /* The space required for slice header SLICE_STATE + header.
  47.  * Is it enough? */
  48. #define SLICE_HEADER                    80
  49.  
  50. /* the space required for slice tail. */
  51. #define SLICE_TAIL                      16
  52.  
  53. #define __SOFTWARE__    0
  54.  
  55. #define MFC_BATCHBUFFER_AVC_INTRA       0
  56. #define MFC_BATCHBUFFER_AVC_INTER       1
  57. #define NUM_MFC_KERNEL                  2
  58.  
  59. #define BIND_IDX_VME_OUTPUT             0
  60. #define BIND_IDX_MFC_SLICE_HEADER       1
  61. #define BIND_IDX_MFC_BATCHBUFFER        2
  62.  
  63. #define CMD_LEN_IN_OWORD        4
  64.  
  65. #define BRC_CLIP(x, min, max)                                   \
  66.     {                                                           \
  67.         x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x));  \
  68.     }
  69.  
  70. #define BRC_P_B_QP_DIFF 4
  71. #define BRC_I_P_QP_DIFF 2
  72. #define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
  73.  
  74. #define BRC_PWEIGHT 0.6  /* weight if P slice with comparison to I slice */
  75. #define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
  76.  
  77. #define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
  78. #define BRC_CY 0.1 /* weight for */
  79. #define BRC_CX_UNDERFLOW 5.
  80. #define BRC_CX_OVERFLOW -4.
  81.  
  82. #define BRC_PI_0_5 1.5707963267948966192313216916398
  83.  
  84. typedef enum {
  85.    VME_V_PRED = 0,
  86.    VME_H_PRED = 1,
  87.    VME_DC_PRED = 2,
  88.    VME_PL_PRED = 3,
  89.  
  90.    VME_MB_INTRA_MODE_COUNT
  91. } VME_MB_INTRA_PRED_MODE;
  92.  
  93. typedef enum {
  94.    PAK_DC_PRED = 0,
  95.    PAK_V_PRED = 1,
  96.    PAK_H_PRED = 2,
  97.    PAK_TM_PRED = 3,
  98.  
  99.    PAK_MB_INTRA_MODE_COUNT
  100. } VP8_PAK_MB_INTRA_PRED_MODE;
  101.  
  102. typedef enum
  103. {
  104.     VME_B_V_PRED = 0,
  105.     VME_B_H_PRED = 1,
  106.     VME_B_DC_PRED = 2,
  107.     VME_B_DL_PRED = 3,
  108.     VME_B_DR_PRED = 4,
  109.     VME_B_VR_PRED = 5,
  110.     VME_B_HD_PRED = 6,
  111.     VME_B_VL_PRED = 7,
  112.     VME_B_HU_PRED = 8,
  113.  
  114.     VME_B_INTRA_MODE_COUNT
  115. } VME_BLOCK_INTRA_PRED_MODE;
  116.  
  117. typedef enum
  118. {
  119.     PAK_B_DC_PRED = 0,
  120.     PAK_B_TM_PRED = 1,
  121.     PAK_B_VE_PRED = 2,
  122.     PAK_B_HE_PRED = 3,
  123.     PAK_B_LD_PRED = 4,
  124.     PAK_B_RD_PRED = 5,
  125.     PAK_B_VR_PRED = 6,
  126.     PAK_B_VL_PRED = 7,
  127.     PAK_B_HD_PRED = 8,
  128.     PAK_B_HU_PRED = 9,
  129.  
  130.     PAK_B_INTRA_MODE_COUNT
  131. } VP8_PAK_BLOCK_INTRA_PRED_MODE;
  132.  
  133. typedef struct
  134. {
  135.   int vme_intra_mb_mode;
  136.   int vp8_pak_intra_mb_mode;
  137. } vp8_intra_mb_mode_map_t;
  138.  
  139. typedef struct
  140. {
  141.   int vme_intra_block_mode;
  142.   int vp8_pak_intra_block_mode;
  143. } vp8_intra_block_mode_map_t;
  144.  
  145. typedef enum _gen6_brc_status
  146. {
  147.     BRC_NO_HRD_VIOLATION = 0,
  148.     BRC_UNDERFLOW = 1,
  149.     BRC_OVERFLOW = 2,
  150.     BRC_UNDERFLOW_WITH_MAX_QP = 3,
  151.     BRC_OVERFLOW_WITH_MIN_QP = 4,
  152. } gen6_brc_status;
  153.  
  154. struct gen6_mfc_avc_surface_aux
  155. {
  156.     dri_bo *dmv_top;
  157.     dri_bo *dmv_bottom;
  158. };
  159.  
  160. struct gen6_mfc_context
  161. {
  162.     struct {
  163.         unsigned int width;
  164.         unsigned int height;
  165.         unsigned int w_pitch;
  166.         unsigned int h_pitch;
  167.     } surface_state;
  168.  
  169.     //MFX_PIPE_BUF_ADDR_STATE
  170.     struct {
  171.         dri_bo *bo;                            
  172.     } post_deblocking_output;           //OUTPUT: reconstructed picture                          
  173.    
  174.     struct {  
  175.         dri_bo *bo;                                                            
  176.     } pre_deblocking_output;            //OUTPUT: reconstructed picture with deblocked                          
  177.  
  178.     struct {
  179.         dri_bo *bo;
  180.     } uncompressed_picture_source;      //INPUT: original compressed image
  181.  
  182.     struct {
  183.         dri_bo *bo;                                                            
  184.     } intra_row_store_scratch_buffer;   //INTERNAL:
  185.  
  186.     struct {
  187.         dri_bo *bo;
  188.     } macroblock_status_buffer;         //INTERNAL:
  189.  
  190.     struct {
  191.         dri_bo *bo;                                                            
  192.     } deblocking_filter_row_store_scratch_buffer;       //INTERNAL:
  193.  
  194.     struct {                                    
  195.         dri_bo *bo;
  196.     } reference_surfaces[MAX_MFC_REFERENCE_SURFACES];   //INTERNAL: refrence surfaces
  197.  
  198.     //MFX_IND_OBJ_BASE_ADDR_STATE
  199.     struct{
  200.         dri_bo *bo;
  201.     } mfc_indirect_mv_object;           //INPUT: the blocks' mv info
  202.  
  203.     struct {
  204.         dri_bo *bo;
  205.         int offset;
  206.         int end_offset;
  207.     } mfc_indirect_pak_bse_object;      //OUTPUT: the compressed bitstream
  208.  
  209.     //MFX_BSP_BUF_BASE_ADDR_STATE
  210.     struct {
  211.         dri_bo *bo;
  212.     } bsd_mpc_row_store_scratch_buffer; //INTERNAL:
  213.        
  214.     //MFX_AVC_DIRECTMODE_STATE
  215.     struct {
  216.         dri_bo *bo;
  217.     } direct_mv_buffers[NUM_MFC_DMV_BUFFERS];   //INTERNAL: 0-31 as input,32 and 33 as output
  218.  
  219.     //Bit rate tracking context
  220.     struct {
  221.         unsigned int QpPrimeY;
  222.         unsigned int MaxQpNegModifier;
  223.         unsigned int MaxQpPosModifier;
  224.         unsigned char MaxSizeInWord;
  225.         unsigned char TargetSizeInWord;
  226.         unsigned char Correct[6];
  227.         unsigned char GrowInit;
  228.         unsigned char GrowResistance;
  229.         unsigned char ShrinkInit;
  230.         unsigned char ShrinkResistance;
  231.  
  232.         unsigned int target_mb_size;
  233.         unsigned int target_frame_size;
  234.     } bit_rate_control_context[3];      //INTERNAL: for I, P, B frames
  235.  
  236.     struct {
  237.         int mode;
  238.         int gop_nums[3];
  239.         int target_frame_size[3]; // I,P,B
  240.         double bits_per_frame;
  241.         double qpf_rounding_accumulator;
  242.  
  243.         double saved_bps;
  244.         double saved_fps;
  245.         int saved_intra_period;
  246.         int saved_ip_period;
  247.         int saved_idr_period;
  248.     } brc;
  249.  
  250.     struct {
  251.         double current_buffer_fullness;
  252.         double target_buffer_fullness;
  253.         double buffer_capacity;
  254.         unsigned int buffer_size;
  255.         unsigned int violation_noted;
  256.     } hrd;
  257.  
  258.     //HRD control context
  259.     struct {
  260.         int i_bit_rate_value;
  261.         int i_cpb_size_value;
  262.  
  263.         int i_initial_cpb_removal_delay;
  264.         int i_cpb_removal_delay;
  265.  
  266.         int i_frame_number;
  267.  
  268.         int i_initial_cpb_removal_delay_length;
  269.         int i_cpb_removal_delay_length;
  270.         int i_dpb_output_delay_length;
  271.     }vui_hrd;
  272.  
  273.     struct {
  274.         unsigned char *vp8_frame_header;
  275.         unsigned int frame_header_bit_count;
  276.         unsigned int frame_header_qindex_update_pos;
  277.         unsigned int frame_header_lf_update_pos;
  278.         unsigned int frame_header_token_update_pos;
  279.         unsigned int frame_header_bin_mv_upate_pos;
  280.  
  281.         unsigned int intermediate_partition_offset[8];
  282.         unsigned int intermediate_buffer_max_size;
  283.         unsigned int final_frame_byte_offset;
  284.  
  285.         unsigned char mb_segment_tree_probs[3];
  286.         unsigned char y_mode_probs[4];
  287.         unsigned char uv_mode_probs[3];
  288.         unsigned char mv_probs[2][19];
  289.  
  290.         unsigned char prob_skip_false;
  291.         unsigned char prob_intra;
  292.         unsigned char prob_last;
  293.         unsigned char prob_gf;
  294.        
  295.         dri_bo *frame_header_bo;
  296.         dri_bo *intermediate_bo;
  297.         dri_bo *final_frame_bo;
  298.         dri_bo *stream_out_bo;
  299.         dri_bo *coeff_probs_stream_in_bo;
  300.         dri_bo *token_statistics_bo;
  301.         dri_bo *mpc_row_store_bo;
  302.     }vp8_state;
  303.  
  304.     //"buffered_QMatrix" will be used to buffer the QMatrix if the app sends one.
  305.     // Or else, we will load a default QMatrix from the driver for JPEG encode.
  306.     VAQMatrixBufferJPEG buffered_qmatrix;
  307.     struct i965_gpe_context gpe_context;
  308.     struct i965_buffer_surface mfc_batchbuffer_surface;
  309.     struct intel_batchbuffer *aux_batchbuffer;
  310.     struct i965_buffer_surface aux_batchbuffer_surface;
  311.  
  312.     void (*pipe_mode_select)(VADriverContextP ctx,
  313.                              int standard_select,
  314.                              struct intel_encoder_context *encoder_context);
  315.     void (*set_surface_state)(VADriverContextP ctx,
  316.                               struct intel_encoder_context *encoder_context);
  317.     void (*ind_obj_base_addr_state)(VADriverContextP ctx,
  318.                                     struct intel_encoder_context *encoder_context);
  319.     void (*avc_img_state)(VADriverContextP ctx,
  320.                           struct encode_state *encode_state,
  321.                           struct intel_encoder_context *encoder_context);
  322.     void (*avc_qm_state)(VADriverContextP ctx,
  323.                          struct intel_encoder_context *encoder_context);
  324.     void (*avc_fqm_state)(VADriverContextP ctx,
  325.                           struct intel_encoder_context *encoder_context);
  326.     void (*insert_object)(VADriverContextP ctx,
  327.                           struct intel_encoder_context *encoder_context,
  328.                           unsigned int *insert_data,
  329.                           int lenght_in_dws, int data_bits_in_last_dw,
  330.                           int skip_emul_byte_count,
  331.                           int is_last_header, int is_end_of_slice,
  332.                           int emulation_flag,
  333.                           struct intel_batchbuffer *batch);
  334.     void (*buffer_suface_setup)(VADriverContextP ctx,
  335.                                 struct i965_gpe_context *gpe_context,
  336.                                 struct i965_buffer_surface *buffer_surface,
  337.                                 unsigned long binding_table_offset,
  338.                                 unsigned long surface_state_offset);
  339. };
  340.  
  341. VAStatus gen6_mfc_pipeline(VADriverContextP ctx,
  342.                            VAProfile profile,
  343.                            struct encode_state *encode_state,
  344.                            struct intel_encoder_context *encoder_context);
  345. void gen6_mfc_context_destroy(void *context);
  346.  
  347. extern
  348. Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
  349.  
  350.  
  351. extern int intel_mfc_update_hrd(struct encode_state *encode_state,
  352.                                 struct gen6_mfc_context *mfc_context,
  353.                                 int frame_bits);
  354.  
  355. extern int intel_mfc_brc_postpack(struct encode_state *encode_state,
  356.                                   struct gen6_mfc_context *mfc_context,
  357.                                   int frame_bits);
  358.  
  359. extern void intel_mfc_hrd_context_update(struct encode_state *encode_state,
  360.                                          struct gen6_mfc_context *mfc_context);
  361.  
  362. extern int intel_mfc_interlace_check(VADriverContextP ctx,
  363.                                      struct encode_state *encode_state,
  364.                                      struct intel_encoder_context *encoder_context);
  365.  
  366. extern void intel_mfc_brc_prepare(struct encode_state *encode_state,
  367.                                   struct intel_encoder_context *encoder_context);
  368.  
  369. extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
  370.                                                      struct encode_state *encode_state,
  371.                                                      struct intel_encoder_context *encoder_context,
  372.                                                      struct intel_batchbuffer *slice_batch);
  373.  
  374. extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
  375.                                       struct encode_state *encode_state,
  376.                                       struct intel_encoder_context *encoder_context);
  377.  
  378. extern int intel_avc_enc_slice_type_fixup(int type);
  379.  
  380. extern void
  381. intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
  382.                             struct encode_state *encode_state,
  383.                             struct intel_encoder_context *encoder_context);
  384.  
  385. extern
  386. Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
  387.  
  388. extern void
  389. intel_avc_slice_insert_packed_data(VADriverContextP ctx,
  390.                              struct encode_state *encode_state,
  391.                              struct intel_encoder_context *encoder_context,
  392.                              int slice_index,
  393.                              struct intel_batchbuffer *slice_batch);
  394.  
  395. extern
  396. Bool gen9_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
  397.  
  398. #endif  /* _GEN6_MFC_BCS_H_ */
  399.