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  1. /*
  2.  * Copyright © <2010>, Intel Corporation.
  3.  *
  4.  * This program is licensed under the terms and conditions of the
  5.  * Eclipse Public License (EPL), version 1.0.  The full text of the EPL is at
  6.  * http://www.opensource.org/licenses/eclipse-1.0.php.
  7.  *
  8.  */
  9. /////////////////////////////////////////////////////////////////////////////////////
  10. // Kernel name: AVC_ILDB_Root_Mbaff.asm
  11. //
  12. //  Root kernel serves as a scheduler for child threads.
  13. //
  14. //
  15. //      ***** Note *****
  16. //      Initial design bundle MB pair for each thread, and share AVC_ILDB_MB_Dep_Check.asm
  17. //      with non mbaff kernels.
  18. //
  19. //      Optimization will be done later, putting top and bottom MBs on separate threads.
  20. //
  21. //
  22. /////////////////////////////////////////////////////////////////////////////////////
  23. //
  24. //  $Revision: 1 $
  25. //  $Date: 10/19/06 5:06p $
  26. //
  27.  
  28. // ----------------------------------------------------
  29. //  AVC_ILDB_ROOT_MBAFF_UV
  30. // ----------------------------------------------------
  31. #define AVC_ILDB
  32.  
  33. .kernel AVC_ILDB_ROOT_MBAFF_UV
  34. #if defined(COMBINED_KERNEL)
  35. ILDB_LABEL(AVC_ILDB_ROOT_UV):
  36. #endif
  37.  
  38. #include "SetupVPKernel.asm"
  39. #include "AVC_ILDB.inc"
  40.  
  41.  
  42. #if defined(_DEBUG)
  43.  
  44. /////////////////////////////////////////////////////////////////////////////////////
  45. // Init URB space for running on RTL.  It satisfies reading an unwritten URB entries.  
  46. // Will remove it for production release.
  47.  
  48.  
  49. //mov (8) m1:ud                 0x11111111:ud
  50. //mov (8) m2:ud                 0x22222222:ud
  51. //mov (8) m3:ud                 0x33333333:ud
  52. //mov (8) m4:ud                 0x44444444:ud
  53.  
  54. //mov (1)       Temp1_W:w       0:w
  55.  
  56. //ILDB_INIT_URB:
  57. //mul (1)       URBOffset:w                             Temp1_W:w               4:w
  58. //shl (1) URBWriteMsgDescLow:uw         URBOffset:w             4:w             // Msg descriptor: URB write dest offset (9:4)
  59. //mov (1) URBWriteMsgDescHigh:uw        0x0650:uw                               // Msg descriptor: URB write 5 MRFs (m0 - m4)
  60. //#include "writeURB.asm"
  61.  
  62. //add           (1)             Temp1_W:w       Temp1_W:w       1:w                             // Increase block count
  63. //cmp.l.f0.0 (1)        null            Temp1_W:w       MBsCntY:w               // Check the block count limit
  64. //(f0.0) jmpi           ILDB_INIT_URB                                                   // Loop back
  65.  
  66.  
  67. /////////////////////////////////////////////////////////////////////////////////////
  68.  
  69.  
  70. mov             (1)             EntrySignature:w                        0xEFF0:w
  71.  
  72. #endif
  73. //----------------------------------------------------------------------------------------------------------------
  74.  
  75. // Set global variable
  76. mov (32)        ChildParam:uw                   0:uw                                                            // Reset local variables
  77. //mul   (1)             TotalBlocks:w                   MBsCntX:w               MBsCntY:w                       // Total # of MB pairs
  78. //add   (1)             GatewayApertureE:w              MBsCntY:w               GatewayApertureB:w      // Aperture End = aperture Head + BlockCntY
  79.  
  80.  
  81. // 2 URB entries for Y:
  82. // Entry 0 - Child thread R0Hdr
  83. // Entry 1 - input parameter to child kernel (child r1)
  84.  
  85. #define         URB_ENTRIES_PER_MB      2
  86.  
  87. // URB_ENTRIES_PER_MB in differnt form, the final desired format is (URB_ENTRIES_PER_MB-1) << 10
  88. mov (1) URB_EntriesPerMB_2:w            URB_ENTRIES_PER_MB-1:w
  89. shl (1) URB_EntriesPerMB_2:w            URB_EntriesPerMB_2:w    10:w
  90.  
  91. #define         CHROMA_ROOT                                                                                                             // Compiling flag for chroma only
  92. //mul (1)               URBOffsetUVBase:w               MBsCntY:w               URB_ENTRIES_PER_MB:w    // Right after Y entries
  93.  
  94. // URB base for UV kernels
  95. #if defined(DEV_CL)    
  96.         mov (1)         URBOffsetUVBase:w               240:w
  97. #else
  98.         mov (1)         URBOffsetUVBase:w               320:w
  99. #endif
  100.  
  101.  
  102. mov     (1)             ChildThreadsID:uw               3:uw
  103.  
  104. shr (1)         ThreadLimit:w           MaxThreads:w            1:w             // Initial luma thread limit to 50%
  105. mul     (1)             TotalBlocks:w           MBsCntX:w               MBsCntY:w       // MBs to be processed count down from TotalBlocks
  106.  
  107. //***** Init CT_R0Hdr fields that are common to all threads *************************
  108. mov (8) CT_R0Hdr.0:ud                   r0.0<8;8,1>:ud                          // Init to root R0 header
  109. mov (1) CT_R0Hdr.7:ud                   r0.6:ud                                         // Copy Parent Thread Cnt; JJ did the change on 06/20/2006
  110. mov (1) CT_R0Hdr.31:ub                  0:w                                                     // Reset the highest byte
  111. mov (1) CT_R0Hdr.3:ud                   0x00000000       
  112. mov (1) CT_R0Hdr.6:uw                   sr0.0:uw                                        // sr0.0: state reg contains general thread states, e.g. EUID/TID.
  113.  
  114. //***** Init ChildParam fields that are common to all threads ***********************
  115. mov (8)         ChildParam<1>:ud        RootParam<8;8,1>:ud             // Copy all root parameters
  116. mov (4)         CurCol<1>:w                     0:w                                             // Reset CurCol, CurRow
  117. add     (2)             LastCol<1>:w            MBsCntX<2;2,1>:w                -1:w    // Get LastCol and LastRow
  118.  
  119. mov (1) URBWriteMsgDesc:ud              MSG_LEN(2)+URBWMSGDSC:ud
  120.  
  121. //===================================================================================
  122.  
  123. #include "AVC_ILDB_OpenGateway.asm"             // Open root thread gateway for receiving notification
  124.  
  125. #include "AVC_ILDB_Dep_Check.asm"       // Check dependency and spawn all MBs
  126.  
  127. //#include "AVC_ILDB_UpdateThrdLimit.asm"       // Update thread limit in luma root thread via gateway
  128.  
  129. #include "AVC_ILDB_CloseGateway.asm"    // Close root thread gateway
  130.  
  131. // Chroma root EOT = child send EOT : Request type = 1
  132.         END_CHILD_THREAD
  133.  
  134. #undef  CHROMA_ROOT
  135.  
  136. #if !defined(COMBINED_KERNEL)           // For standalone kernel only
  137. .end_code
  138.  
  139. .end_kernel
  140. #endif
  141.